JP2014203874A - Flip-chip semiconductor light-emitting element, semiconductor device and manufacturing method of the same - Google Patents

Flip-chip semiconductor light-emitting element, semiconductor device and manufacturing method of the same Download PDF

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JP2014203874A
JP2014203874A JP2013076700A JP2013076700A JP2014203874A JP 2014203874 A JP2014203874 A JP 2014203874A JP 2013076700 A JP2013076700 A JP 2013076700A JP 2013076700 A JP2013076700 A JP 2013076700A JP 2014203874 A JP2014203874 A JP 2014203874A
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semiconductor light
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JP6147061B2 (en
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拓也 風間
Takuya Kazama
拓也 風間
和之 吉水
Kazuyuki Yoshimizu
和之 吉水
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Stanley Electric Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a flip-chip semiconductor light-emitting element which is useful in improvement in mounting reliability.SOLUTION: A flip-chip semiconductor light-emitting element comprises: an n-type GaN layer 2, an InGaN/GaN multiquantum well active layer 3 and a p-type GaN layer 4 which are formed on a sapphire substrate 1; a p-side electrode and an n-side electrode 6 which are formed on the p-type GaN layer 4 and the n-type GaN layer 2; an insulation layer 7 which is composed of silicon oxide and formed so as to cover a region other than Au bump adhesion regions of the p-side electrode 5 and the n-side electrode 6; and an uneven surface 1a having large light scattering ability and a flat surface 1b having small light scattering ability, which serve as a light extraction surface and are provided on a top face of the sapphire substrate 1. The flat surface 1b is opposite to at least two boundaries with the p-side electrode 5 and the n-side electrode 6. Boundaries of a conductor pattern of a mounting substrate corresponding to the boundaries with the p-side electrode 5 and the n-side electrode 6 can be checked from above through the flat surface 1b, and as a result, alignment inspection of a semiconductor light-emitting element after face-down mounting with the mounting substrate in an alignment inspection process can be performed promptly and successfully.

Description

本発明はフリップチップ型半導体発光素子、フリップチップ型半導体発光素子を実装した半導体装置、及びその製造方法に関する。   The present invention relates to a flip chip type semiconductor light emitting device, a semiconductor device mounted with the flip chip type semiconductor light emitting device, and a method for manufacturing the same.

一般に、半導体素子を実装基板に実装する半導体装置の製造方法としては、半導体素子の表面電極と実装基板の電極とをワイヤによって電気的に接続するワイヤボンディング実装方法を用いていたが、最近は、フリップチップ半導体素子をバンプと呼ばれる突起状端子をアレイ状にボンディングした実装基板にフェイスダウン実装するフリップチップ実装方法が用いられている（参照：特許文献１、２）。   In general, as a method of manufacturing a semiconductor device for mounting a semiconductor element on a mounting substrate, a wire bonding mounting method in which the surface electrode of the semiconductor element and the electrode of the mounting substrate are electrically connected by a wire has been used. A flip-chip mounting method is used in which a flip-chip semiconductor element is face-down mounted on a mounting substrate in which protruding terminals called bumps are bonded in an array (refer to Patent Documents 1 and 2).

ワイヤボンディング実装方法に比較して、フリップチップ実装方法は、配線長が短いために電気的特性がよいので、高周波回路素子の実装に適している。また、小型化、薄型化の点で有利であるので、携帯機器の実装に適している。さらに、放熱性に優れているので、発光ダイオード（LED）素子、レーザダイオード（LD）素子等の半導体発光素子の実装にも適している。   Compared with the wire bonding mounting method, the flip chip mounting method is suitable for mounting high-frequency circuit elements because the wiring length is short and the electrical characteristics are good. Further, it is advantageous in terms of downsizing and thinning, and is suitable for mounting on portable devices. Furthermore, since it has excellent heat dissipation, it is suitable for mounting semiconductor light emitting devices such as light emitting diode (LED) devices and laser diode (LD) devices.

上述のフリップチップ実装方法において、フリップチップ型半導体発光素子の電極と実装基板のバンプとの接合を行う工法として、導電性接着剤（ペースト）を用いる導電性ペースト接合工法、共晶はんだ及び高温はんだを用いるはんだ接合工法、バンプに荷重を印加する圧接工法、バンプに超音波を印加する超音波接合工法等がある。このうち、超音波接合工法は、コスト、接合信頼性、接合荷重、接合ピッチ精度等において総合的に優れている。   In the flip chip mounting method described above, as a method of bonding the electrodes of the flip chip type semiconductor light emitting element and the bumps of the mounting substrate, a conductive paste bonding method using a conductive adhesive (paste), eutectic solder and high temperature solder. There are a solder bonding method using, a pressure welding method for applying a load to the bump, an ultrasonic bonding method for applying an ultrasonic wave to the bump, and the like. Among these, the ultrasonic bonding method is generally excellent in cost, bonding reliability, bonding load, bonding pitch accuracy, and the like.

他方、フリップチップ型半導体発光素子においては、光取り出し効率を向上させるために、光散乱用光取り出し凹凸面が上面全体に形成されている。   On the other hand, in the flip-chip type semiconductor light emitting device, in order to improve the light extraction efficiency, a light extraction uneven surface for light scattering is formed on the entire upper surface.

特開平１１−３４０５１４号公報（特許第３５３１４７５号公報）JP 11-340514 A (Patent No. 3531475) 特開２００３−１１０１４４号公報JP 2003-110144 A

しかしながら、上述のフリップチップ型半導体発光素子を実装基板にフリップチップ実装した場合、加熱超音波圧着後に、たとえフリップチップ型半導体発光素子と実装基板との位置関係がずれても、全面に形成された光取り出し凹凸面の光散乱のために、フリップチップ型半導体発光素子の電極と実装基板のバンプとの位置関係のずれ、つまり、フリップチップ型半導体発光素子と実装基板とのアライメント精度をフリップチップ型半導体発光素子の上面から確認できない。従って、フリップチップ型半導体発光素子の電極が実装基板のバンプからずれることがある。この結果、リーク電流の発生、電流集中による破壊を招き、実装後の信頼性が低下するという課題がある。   However, when the above-described flip-chip type semiconductor light-emitting device is flip-chip mounted on a mounting substrate, it is formed on the entire surface even if the positional relationship between the flip-chip type semiconductor light-emitting device and the mounting substrate is shifted after heating ultrasonic pressure bonding. Due to the light scattering on the light extraction uneven surface, the positional deviation between the flip chip type semiconductor light emitting device electrode and the bump of the mounting substrate, that is, the alignment accuracy between the flip chip type semiconductor light emitting device and the mounting substrate is flip chip type. It cannot be confirmed from the upper surface of the semiconductor light emitting device. Accordingly, the electrodes of the flip-chip type semiconductor light emitting device may be displaced from the bumps of the mounting substrate. As a result, there is a problem in that leakage current is generated and destruction due to current concentration is caused, and reliability after mounting is lowered.

上述の課題を解決するために、本発明に係るフリップチップ型半導体発光素子は、実装基板にフェイスダウン実装されるべきフリップチップ型半導体発光素子であって、このフリップチップ型半導体発光素子の実装基板に対向しない側の光取り出し面を光散乱が大きい凹凸面及び光散乱が小さい平坦面により構成したものである。これにより、フェイスダウン実装後に、フリップチップ型半導体発光素子と実装基板とのアライメント精度をフリップチップ型半導体発光素子の上面の光取り出し面の光散乱が小さい平坦面を介して確認するようになる。   In order to solve the above-mentioned problems, a flip chip type semiconductor light emitting device according to the present invention is a flip chip type semiconductor light emitting device to be face-down mounted on a mounting substrate, and the mounting substrate of this flip chip type semiconductor light emitting device The light extraction surface on the side not facing the surface is constituted by an uneven surface with large light scattering and a flat surface with small light scattering. Accordingly, after the face-down mounting, the alignment accuracy between the flip chip type semiconductor light emitting device and the mounting substrate is confirmed through a flat surface with a small light scattering of the light extraction surface on the upper surface of the flip chip type semiconductor light emitting device.

また、本発明に係る半導体装置は、上述のフリップチップ型半導体発光素子と、実装基板とを具備し、フリップチップ型半導体発光素子は実装基板にフェイスダウン実装されたものである。   A semiconductor device according to the present invention includes the above-described flip chip type semiconductor light emitting element and a mounting substrate, and the flip chip type semiconductor light emitting element is mounted on the mounting substrate face down.

さらに、本発明に係る半導体装置の製造方法は、フリップチップ型半導体発光素子の上側に光取り出し面として光散乱が大きい凹凸面及び光散乱が小さい平坦面を形成する光取り出し面形成工程と、フリップチップ型半導体発光素子の下側をp側導体パターン及びn側導体パターンが形成された実装基板にフェイスダウン実装するフェイスダウン工程と、平坦面を介して実装基板のp側導体パターンとn側導体パターンとの境界を観測することによりフリップチップ型半導体発光素子と実装基板とのアライメント検査を行うアライメント検査工程とを具備し、フリップチップ型半導体発光素子の上記平坦面がフリップチップ型半導体発光素子のp側電極とn側電極との少なくとも2つの境界に対向するようにしたものである。   Furthermore, the method of manufacturing a semiconductor device according to the present invention includes a light extraction surface forming step of forming an uneven surface having a large light scattering and a flat surface having a small light scattering as a light extraction surface above the flip chip type semiconductor light emitting element, A face-down process in which the lower side of the chip-type semiconductor light-emitting element is face-down mounted on a mounting substrate on which a p-side conductor pattern and an n-side conductor pattern are formed, and the p-side conductor pattern and the n-side conductor of the mounting substrate through a flat surface An alignment inspection process for performing an alignment inspection between the flip chip type semiconductor light emitting element and the mounting substrate by observing the boundary with the pattern, and the flat surface of the flip chip type semiconductor light emitting element is the flip chip type semiconductor light emitting element. It is intended to face at least two boundaries between the p-side electrode and the n-side electrode.

本発明によれば、フリップチップ型半導体発光素子と実装基板とのアライメント精度を迅速かつ正確に確認でき、実装後の信頼性を向上できる。   According to the present invention, the alignment accuracy between the flip-chip type semiconductor light emitting element and the mounting substrate can be confirmed quickly and accurately, and the reliability after mounting can be improved.

本発明に係るフリップチップ型半導体発光素子の実施の形態を示す断面図である。It is sectional drawing which shows embodiment of the flip-chip-type semiconductor light-emitting device based on this invention. 図１のフリップチップ型半導体発光素子の最上面の光取り出し面の平面図である。FIG. 2 is a plan view of an uppermost light extraction surface of the flip chip type semiconductor light emitting device of FIG. 1. 図１のフリップチップ型半導体発光素子の最下面のp側電極、n側電極の平面図である。FIG. 2 is a plan view of a p-side electrode and an n-side electrode on the lowermost surface of the flip-chip type semiconductor light emitting device of FIG. 1. 図１のフリップチップ型半導体発光素子がフェイスダウン実装されるべき実装基板の断面図である。FIG. 2 is a cross-sectional view of a mounting substrate on which the flip chip type semiconductor light emitting device of FIG. 1 is to be face-down mounted. 図４の実装基板の導体パターンの平面図である。It is a top view of the conductor pattern of the mounting substrate of FIG. 本発明に係る半導体装置の製造方法を説明するためのフローチャートである。4 is a flowchart for explaining a method for manufacturing a semiconductor device according to the present invention. 図６のバンプ形成工程を説明するための断面図である。It is sectional drawing for demonstrating the bump formation process of FIG. 図６のフェイスダウン実装工程を説明するための断面図である。It is sectional drawing for demonstrating the face-down mounting process of FIG. 図６のアライメント検査工程を説明するための上面図である。It is a top view for demonstrating the alignment test process of FIG.

図１は本発明に係るフリップチップ型半導体発光素子の実施の形態を示す断面図、図２及び図３は図１のフリップチップ型半導体発光素子の光取り出し面の平面図及びp側電極及びn側電極の平面図である。尚、図１、図２、図３のフリップチップ型半導体発光素子はたとえばサイズ1.0mm×1.2mm、厚さ0.1mmの発光ダイオード（LED）素子である。また、図１は図２、図３のI-I線断面図である。   FIG. 1 is a cross-sectional view showing an embodiment of a flip chip type semiconductor light emitting device according to the present invention, and FIGS. 2 and 3 are plan views, p-side electrodes and n of a light extraction surface of the flip chip type semiconductor light emitting device of FIG. It is a top view of a side electrode. 1, 2, and 3 are light emitting diode (LED) elements having a size of 1.0 mm × 1.2 mm and a thickness of 0.1 mm, for example. 1 is a cross-sectional view taken along the line II of FIG. 2 and FIG.

図１において、サファイア基板１上にSiドープn型GaN層２、InGaN/GaN多重井戸（MQW）活性層３、Mgドープp型GaN層４が形成されている。また、p型GaN層４及びn型GaN層２上に、AgNiTiPtAuよりなるp側電極５及びn側電極６が形成されている。p側電極５及びn側電極６のAuバンプ接着領域BR1、BR2（図３に図示）以外の領域を覆うように酸化シリコン（SiO２）よりなる絶縁層７が形成されている。 In FIG. 1, a Si-doped n-type GaN layer 2, an InGaN / GaN multiple well (MQW) active layer 3, and an Mg-doped p-type GaN layer 4 are formed on a sapphire substrate 1. A p-side electrode 5 and an n-side electrode 6 made of AgNiTiPtAu are formed on the p-type GaN layer 4 and the n-type GaN layer 2. An insulating layer 7 made of silicon oxide (SiO 2 ) is formed so as to cover regions other than the Au bump adhesion regions BR1 and BR2 (shown in FIG. 3) of the p-side electrode 5 and the n-side electrode 6.

図２、図３をも参照すると、サファイア基板１の上面には、光取り出し面の作用をする光散乱が大きい凹凸面１ａ及び光散乱が小さい平坦面１ｂが設けられている。この平坦面１ｂを介してp側電極５とn側電極６との境界８に対応する実装基板の導体パターンの境界を上から確認でき、この結果、後述のアライメント検査工程においてフェイスダウン実装後の半導体発光素子と実装基板とのアライメント検査を迅速かつ正確に実行できる。   Referring also to FIGS. 2 and 3, the upper surface of the sapphire substrate 1 is provided with a concavo-convex surface 1 a having a large light scattering functioning as a light extraction surface and a flat surface 1 b having a small light scattering. Through this flat surface 1b, the boundary of the conductor pattern of the mounting substrate corresponding to the boundary 8 between the p-side electrode 5 and the n-side electrode 6 can be confirmed from above. As a result, in the alignment inspection process described later, The alignment inspection between the semiconductor light emitting element and the mounting substrate can be performed quickly and accurately.

尚、平坦面１ｂは、形状によっては少なくとも１つのn側電極６またはp側電極５の境界に対向して設ければよい。より望ましくは、少なくとも２つのn側電極６またはp側電極５の境界に対向して設けるとよい。半導体発光素子の上面視形状を対角線または中心線で４つの象限に分けた際に、平坦面１ｂが異なる象限に属するようにすると、x方向、y方向、θ角方向のアライメントを合わせやすく、好ましい。たとえば、図２に示すごとく、半導体発光素子の重心Oから距離Dが等しい２つのn側電極６に対向して設ければよい。   The flat surface 1b may be provided to face the boundary of at least one n-side electrode 6 or p-side electrode 5 depending on the shape. More desirably, it may be provided opposite to the boundary between at least two n-side electrode 6 or p-side electrode 5. When the top view shape of the semiconductor light emitting device is divided into four quadrants by a diagonal line or a center line, it is preferable that the flat surface 1b belongs to different quadrants because the alignment in the x direction, the y direction, and the θ angle direction can be easily aligned. . For example, as shown in FIG. 2, it may be provided to face two n-side electrodes 6 having the same distance D from the center of gravity O of the semiconductor light emitting element.

また、平坦面１ｂの面積は、上面視したときの半導体発光素子全体の面積に対して１０％以下とすることが好ましい。これを上回ると、半導体発光素子の光取り出し効率を高めることができないからである。   The area of the flat surface 1b is preferably 10% or less with respect to the entire area of the semiconductor light emitting device when viewed from above. This is because the light extraction efficiency of the semiconductor light emitting device cannot be increased if the value exceeds this.

図４は図１〜図３の半導体発光素子がフェイスダウン実装される実装基板の断面図、図５は図４の実装基板の上面図である。尚、図４は図５のIV-IV線断面図である。   4 is a cross-sectional view of a mounting substrate on which the semiconductor light emitting device of FIGS. 1 to 3 is mounted face down, and FIG. 5 is a top view of the mounting substrate of FIG. 4 is a cross-sectional view taken along line IV-IV in FIG.

図４、図５に示すように、実装基板１１上には、半導体発光素子のp側電極５、n側電極６のそれぞれに接続されるp側導体パターン１２、n側導体パターン１３が形成されている。この場合、p側導体パターン１２とn側導体パターン１３とは電気的に分離されている。図３のp側電極５とn側電極６との境界８はp側導体パターン１２とn側導体パターン１３との境界１４に対向している。また、p側導体パターン１２には、後述のAuバンプB1がボンディングされるバンプボンディング領域R1が設けられ、他方、n側導体パターン１３には、後述のAuバンプB2がボンディングされるバンプボンディング領域R2が設けられている。   As shown in FIGS. 4 and 5, a p-side conductor pattern 12 and an n-side conductor pattern 13 connected to the p-side electrode 5 and the n-side electrode 6 of the semiconductor light emitting element are formed on the mounting substrate 11. ing. In this case, the p-side conductor pattern 12 and the n-side conductor pattern 13 are electrically separated. The boundary 8 between the p-side electrode 5 and the n-side electrode 6 in FIG. 3 faces the boundary 14 between the p-side conductor pattern 12 and the n-side conductor pattern 13. The p-side conductor pattern 12 is provided with a bump bonding region R1 to which an after-mentioned Au bump B1 is bonded, while the n-side conductor pattern 13 is provided with a bump bonding region R2 to which an after-mentioned Au bump B2 is bonded. Is provided.

次に、図１、図２、図３のフリップチップ型半導体発光素子及び図４、図５の実装基板を含む半導体装置の製造方法を図６を参照して説明する。   Next, a method of manufacturing a semiconductor device including the flip-chip type semiconductor light emitting device of FIGS. 1, 2, and 3 and the mounting substrate of FIGS. 4 and 5 will be described with reference to FIG.

始めに、ステップ６０１にて、光取り出し面としての光散乱が大きい凹凸面１ａ、光散乱が小さい平坦面１ｂの形成前の図１、図２、図３のフリップチップ型半導体発光素子を通常の方法で形成する。つまり、サファイア基板１上にn型GaN層２、InGaN/GaN MQW活性層３及びp型GaN層４をエピタキシャル成長法によって形成させ、次いで、p側電極５及びn側電極６を形成する。   First, in step 601, the flip chip type semiconductor light emitting device of FIGS. 1, 2, and 3 before the formation of the uneven surface 1a having a large light scattering as the light extraction surface and the flat surface 1b having a small light scattering is used as a normal one. Form by the method. That is, the n-type GaN layer 2, the InGaN / GaN MQW active layer 3 and the p-type GaN layer 4 are formed on the sapphire substrate 1 by the epitaxial growth method, and then the p-side electrode 5 and the n-side electrode 6 are formed.

次に、ステップ６０２にて、サファイア基板１上に酸化シリコンパターンをCVD法／エッチング法によって形成する。この酸化シリコンパターンは平坦面１ｂに対応する２つのn側電極６の中心に対して直径120μmの円及び140μmの円の差異である幅20μmの環状をなしている。次いで、この酸化シリコンパターンをマスクとしてバッファードフッ酸によるウェットエッチングにより凹凸面１ａを形成する。次いで、酸化シリコンパターンを除去して平坦面１ｂを露出させる。尚、凹凸面１ａは、リフトオフ法、インプリント等のプレス法、あるいはウェットブラスト法等によっても形成できる。   Next, in step 602, a silicon oxide pattern is formed on the sapphire substrate 1 by a CVD method / etching method. This silicon oxide pattern has an annular shape with a width of 20 μm, which is the difference between a circle with a diameter of 120 μm and a circle with a diameter of 140 μm with respect to the center of the two n-side electrodes 6 corresponding to the flat surface 1b. Next, the uneven surface 1a is formed by wet etching with buffered hydrofluoric acid using this silicon oxide pattern as a mask. Next, the silicon oxide pattern is removed to expose the flat surface 1b. The uneven surface 1a can also be formed by a lift-off method, a press method such as imprint, or a wet blast method.

他方、ステップ６０３にて、図７に示すごとく、実装基板１１のp側導体パターン１２のバンプボンディング領域R1及びn側導体パターン１３のバンプボンディング領域R2上にAuバンプB1、B2（図７にB2のみ図示）を加圧超音波法によってボンディングする。この場合、p側導体パターン１２に対して10個のAuバンプB1、n側導体パターン１３に対しては6個のAuバンプB2が設けられる。半導体発光素子の実装後のAuバンプB1、B2の直径は約80μm、高さは約20μmである。尚、AuバンプB1、B2の直径及び高さは半導体発光素子実装時のつぶし量により変化するものの、20μmより高い高さたとえば30μm程度であってもよい。   On the other hand, at step 603, as shown in FIG. 7, Au bumps B1 and B2 (B2 in FIG. 7) are formed on the bump bonding region R1 of the p-side conductor pattern 12 and the bump bonding region R2 of the n-side conductor pattern 13 of the mounting substrate 11. (Only shown) is bonded by a pressure ultrasonic method. In this case, ten Au bumps B1 are provided for the p-side conductor pattern 12, and six Au bumps B2 are provided for the n-side conductor pattern 13. The Au bumps B1 and B2 after mounting the semiconductor light emitting element have a diameter of about 80 μm and a height of about 20 μm. The diameters and heights of the Au bumps B1 and B2 vary depending on the crushing amount when the semiconductor light emitting device is mounted, but may be higher than 20 μm, for example, about 30 μm.

次に、ステップ６０４〜６０６を参照すると、図８に示すごとく、図７のAuバンプB1、B2が形成された実装基板１１に凹凸面１ａ、平坦面１ｂが形成されたフリップチップ型半導体発光素子をフェイスダウン実装する。以下、ステップ６０４〜６０７について詳細に説明する。   Next, referring to Steps 604 to 606, as shown in FIG. 8, a flip-chip type semiconductor light emitting device in which the uneven surface 1a and the flat surface 1b are formed on the mounting substrate 11 on which the Au bumps B1 and B2 of FIG. 7 are formed. Implement face down. Hereinafter, steps 604 to 607 will be described in detail.

ステップ６０４にて、フリップチップ型半導体発光素子のn側電極６及び実装基板のAuバンプB2及びn側導体パターン１３を画像認識する。   In step 604, the n-side electrode 6 of the flip-chip type semiconductor light emitting element, the Au bump B2 of the mounting substrate, and the n-side conductor pattern 13 are recognized.

次に、ステップ６０５にて、ステップ６０４において画像認識された結果に基づいて、図８に示すごとく、フリップチップ型半導体発光素子を実装基板に重ね合わせる。   Next, in step 605, based on the result of image recognition in step 604, as shown in FIG. 8, the flip chip type semiconductor light emitting element is superimposed on the mounting substrate.

次に、ステップ６０６にて、加熱すると共に超音波によって圧着させ、フェイスダウン実装工程が終了する。尚、このとき、フリップチップ型半導体発光素子と実装基板との位置関係がずれることがある。   Next, in step 606, heating and pressure bonding are performed with ultrasonic waves, and the face-down mounting process is completed. At this time, the positional relationship between the flip chip type semiconductor light emitting element and the mounting substrate may be shifted.

最後に、ステップ６０７にて、フリップチップ型半導体発光素子と実装基板とのアライメント検査をする。すなわち、光取り出し面の平坦面１ｂから顕微鏡にてフリップチップ型半導体発光素子のn側電極６と実装基板１１上のAuバンプB2とのX方向、Y方向、θ角方向のアライメントを検査する。このとき、実際には、フリップチップ型半導体発光素子の平坦面１ｂに関して実装基板１１の導体パターン１２、１３の境界が正しい位置で観察できるか否かで上記アライメント検査が行われる。この結果、図９の（Ａ）に示すごとく、平坦面１ｂに関して導体パターン１２、１３の境界１４が正しい位置で観察されれば、AuバンプB2はフリップチップ型半導体発光素子のn側電極６に対して正しく対向しているとみなす。この結果、アライメント検査は合格したとしてステップ６０８にて後工程に進む。他方、図９の（Ｂ）、（Ｃ）に示すごとく、平坦面１ｂに関して導体パターン１２、１３の境界１４がずれて正しくない位置で観察されれば、AuバンプB2はフリップチップ型半導体発光素子のn側電極６に対して正しく対向していないとみなす。この結果、アライメント検査は不合格としてステップ６０９にて当該フリップチップ型半導体発光素子と実装基板との圧着体は廃棄される。   Finally, in step 607, alignment inspection between the flip chip type semiconductor light emitting element and the mounting substrate is performed. That is, the alignment in the X direction, the Y direction, and the θ angle direction between the n-side electrode 6 of the flip chip type semiconductor light emitting element and the Au bump B2 on the mounting substrate 11 is inspected with a microscope from the flat surface 1b of the light extraction surface. At this time, the alignment inspection is actually performed based on whether or not the boundary between the conductor patterns 12 and 13 of the mounting substrate 11 can be observed at the correct position with respect to the flat surface 1b of the flip-chip type semiconductor light emitting device. As a result, as shown in FIG. 9A, if the boundary 14 of the conductor patterns 12 and 13 is observed at the correct position with respect to the flat surface 1b, the Au bump B2 is formed on the n-side electrode 6 of the flip-chip type semiconductor light emitting device. It is considered that they are correctly facing each other. As a result, it is determined that the alignment inspection has passed, and the process proceeds to a subsequent process in step 608. On the other hand, as shown in FIGS. 9B and 9C, if the boundary 14 of the conductor patterns 12 and 13 is shifted from the flat surface 1b and observed at an incorrect position, the Au bump B2 is flip-chip type semiconductor light emitting device. The n-side electrode 6 is considered not to be correctly opposed. As a result, the alignment inspection is rejected, and in step 609, the crimped body between the flip chip type semiconductor light emitting element and the mounting substrate is discarded.

尚、上述の実施の形態においては、サファイア基板上に光取り出し面の凹凸面及び平坦面を形成したが、サファイア基板を除去した場合には、n型GaN層に光取り出し面の凹凸面及び平坦面を形成する。また、成長基板をサファイア基板の代わりにGaN基板とすることもできる。   In the above embodiment, the uneven surface and the flat surface of the light extraction surface are formed on the sapphire substrate. However, when the sapphire substrate is removed, the uneven surface and the flat surface of the light extraction surface are formed on the n-type GaN layer. Form a surface. Further, the growth substrate can be a GaN substrate instead of the sapphire substrate.

また、本発明は、上述の実施の形態の自明の範囲の種々の変更例に適用し得る。   Further, the present invention can be applied to various modifications within the obvious range of the above-described embodiment.

１：サファイア基板
２：n型GaN層
３：InGaN/GaN多重井戸（MQW）活性層
４：p型GaN層
５：p側電極
６：n側電極
７：絶縁層
８：境界
１１：実装基板
１２：p側導体パターン
１３：n側導体パターン
１４：境界
B1、B2：バンプ
BR1、BR2：バンプ接着領域
R1、R2：バンプボンディング領域

1: Sapphire substrate 2: n-type GaN layer 3: InGaN / GaN multiple well (MQW) active layer 4: p-type GaN layer 5: p-side electrode 6: n-side electrode 7: insulating layer 8: boundary 11: mounting substrate 12 : P-side conductor pattern 13: n-side conductor pattern 14: boundary
B1, B2: Bump
BR1, BR2: Bump adhesion area
R1, R2: Bump bonding area

Claims (7)

実装基板にフェイスダウン実装されるべきフリップチップ型半導体発光素子であって、
該フリップチップ型半導体発光素子の前記実装基板に対向しない側の光取り出し面を光散乱が大きい凹凸面及び光散乱が小さい平坦面により構成したフリップチップ型半導体発光素子。 A flip chip type semiconductor light emitting device to be mounted face down on a mounting substrate,
A flip chip type semiconductor light emitting device comprising a light extraction surface on the side not facing the mounting substrate of the flip chip type semiconductor light emitting device, having an uneven surface with large light scattering and a flat surface with small light scattering. 前記平坦面は前記フリップチップ型半導体発光素子のp側電極又はn側電極の少なくとも一箇所の境界に対向して形成された請求項１に記載のフリップチップ型半導体発光素子。   2. The flip chip type semiconductor light emitting device according to claim 1, wherein the flat surface is formed to face at least one boundary of the p side electrode or the n side electrode of the flip chip type semiconductor light emitting device. 前記平坦面は前記フリップチップ型半導体発光素子のp側電極及びn側電極の少なくとも2箇所の境界に対向して形成された請求項２に記載のフリップチップ型半導体発光素子。   3. The flip-chip type semiconductor light emitting device according to claim 2, wherein the flat surface is formed to face at least two boundaries of the p-side electrode and the n-side electrode of the flip-chip type semiconductor light emitting device. 前記半導体発光素子は、実装基板の法線方向から見たときに四角形であり、その対角線又は中心線によって４つの象限に分けたとき、前記2箇所の境界はそれぞれ異なる象限に属している請求項３に記載のフリップチップ型半導体発光素子。   The semiconductor light-emitting element is a quadrangle when viewed from the normal direction of the mounting substrate, and when divided into four quadrants by its diagonal or center line, the boundary between the two locations belongs to different quadrants. 4. The flip-chip type semiconductor light emitting device according to 3. 前記平坦面の面積は実装基板の法線方向から見たときの半導体発光素子の面積に対して１０％以下である請求項１に記載のフリップチップ型半導体発光素子。   2. The flip-chip type semiconductor light emitting device according to claim 1, wherein an area of the flat surface is 10% or less with respect to an area of the semiconductor light emitting device when viewed from a normal direction of the mounting substrate. 請求項１〜５のいずれかに記載のフリップチップ型半導体発光素子と、
実装基板と
を具備し、
前記フリップチップ型半導体発光素子は前記実装基板にフェイスダウン実装された半導体装置。 The flip-chip type semiconductor light emitting device according to any one of claims 1 to 5,
A mounting substrate, and
The flip chip type semiconductor light emitting element is a semiconductor device mounted face down on the mounting substrate. フリップチップ型半導体発光素子の上側に光取り出し面として光散乱が大きい凹凸面及び光散乱が小さい平坦面を形成する光取り出し面形成工程と、
前記フリップチップ型半導体発光素子をp側導体パターン及びn側導体パターンが形成された実装基板にフェイスダウン実装するフェイスダウン工程と、
前記平坦面を介して前記実装基板の前記p側導体パターンと前記n側導体パターンとの境界を観測することにより前記フリップチップ型半導体発光素子と前記実装基板とのアライメント検査を行うアライメント検査工程と
を具備し、
前記フリップチップ型半導体発光素子の前記平坦面が前記フリップチップ型半導体発光素子のp側電極とn側電極との少なくとも2つの境界に対向するようにした半導体装置の製造方法。


A light extraction surface forming step of forming an uneven surface having a large light scattering and a flat surface having a small light scattering on the upper side of the flip-chip type semiconductor light emitting element;
A face-down process of face-down mounting the flip-chip type semiconductor light emitting device on a mounting substrate on which a p-side conductor pattern and an n-side conductor pattern are formed;
An alignment inspection step of performing an alignment inspection between the flip-chip type semiconductor light emitting element and the mounting substrate by observing a boundary between the p-side conductor pattern and the n-side conductor pattern of the mounting substrate through the flat surface; Comprising
A method of manufacturing a semiconductor device, wherein the flat surface of the flip-chip type semiconductor light-emitting element faces at least two boundaries between a p-side electrode and an n-side electrode of the flip-chip type semiconductor light-emitting element.


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