JP2014157906A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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JP2014157906A
JP2014157906A JP2013027472A JP2013027472A JP2014157906A JP 2014157906 A JP2014157906 A JP 2014157906A JP 2013027472 A JP2013027472 A JP 2013027472A JP 2013027472 A JP2013027472 A JP 2013027472A JP 2014157906 A JP2014157906 A JP 2014157906A
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conductive layer
layer
semiconductor device
resist film
electrode
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Isao Kojima
功 小島
Yasuhito Akutagawa
泰人 芥川
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Fujitsu Semiconductor Ltd
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    • H01L2224/03—Manufacturing methods
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    • H01L2224/03914—Methods of manufacturing bonding areas involving a specific sequence of method steps the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts
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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method and a semiconductor device, which can avoid decrease in intensity of a connection part such as a micro bump by side etching and a Cu pillar.SOLUTION: A semiconductor device manufacturing method comprises: first forming an electrode 12 and an insulation film 13 on a semiconductor substrate 11; subsequently forming a conductive layer 15 on the insulation film 13 of the semiconductor substrate 11; forming on the conductive layer 15, a resist film having an opening at a part corresponding to the electrode 12; and subsequently forming a metal plating layer 18 on an inner side of the opening of the resist film by electrolytic plating. In this plating process, a plating solution enters between the resist film around the resist opening and the conductive layer to form a flange. The semiconductor device manufacturing method comprises: removing the resist film; subsequently forming an oxide film 15a by oxidizing a surface of the conductive layer 15 at an exposed part; and subsequently removing the oxide film 15a and the conductive layer 15 under the oxide film 15a by etching.

Description

本発明は、半導体装置の製造方法及び半導体装置に関する。   The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

近年、半導体装置のより一層の高密度化及び高性能化が促進されており、それにともなって複数の半導体チップを積層するスタックタイプの半導体装置も増えている。スタックタイプの半導体装置では、チップ間の接合に、従来のバンプよりも小型のマイクロバンプやＣｕピラーが使用される。   In recent years, higher density and higher performance of semiconductor devices have been promoted, and accordingly, a stack type semiconductor device in which a plurality of semiconductor chips are stacked is also increasing. In a stack type semiconductor device, micro bumps and Cu pillars smaller than conventional bumps are used for bonding between chips.

本願では、ＵＢＭ（Under Bump Metal）径が８５μｍ以上のバンプを通常バンプ、それよりも小さいものをマイクロバンプと呼んでいる。現状、マイクロバンプやＣｕピラーのＵＢＭ径は、３０μｍ程度である。   In the present application, a bump having a UBM (Under Bump Metal) diameter of 85 μm or more is called a normal bump, and a bump smaller than that is called a micro bump. At present, the UBM diameter of micro bumps and Cu pillars is about 30 μm.

特開２００９−３０２３４０号公報JP 2009-302340 A

サイドエッチングによるマイクロバンプやＣｕピラー等の接続部の強度の低下を回避できる半導体装置の製造方法及び半導体装置を提供することを目的とする。   It is an object of the present invention to provide a method for manufacturing a semiconductor device and a semiconductor device capable of avoiding a decrease in the strength of connection portions such as micro bumps and Cu pillars due to side etching.

開示の技術の一観点によれば、半導体基板上に電極を形成する工程と、前記半導体基板上に、前記電極に対応する部分に開口部が設けられた絶縁膜を形成する工程と、前記半導体基板の前記絶縁膜上に導電層を形成する工程と、前記導電層の上に、前記電極に対応する部分に開口部が設けられたレジスト膜を形成する工程と、電解めっき法により、前記レジスト膜の前記開口部の内側の前記導電層上に金属めっき層を形成するとともに、前記レジスト膜の前記開口部の周囲の前記レジスト膜と前記導電層との間に前記金属めっき層と同じ金属からなる鍔部を形成する工程と、前記レジスト膜を除去して前記導電層を露出させる工程と、前記レジスト膜を除去することにより露出した部分の前記導電層の表面を酸化させて酸化膜を形成する工程と、前記酸化膜及びその下の前記導電層をエッチングにより除去する工程とを有する半導体装置の製造方法が提供される。   According to one aspect of the disclosed technology, a step of forming an electrode on a semiconductor substrate, a step of forming an insulating film on a portion corresponding to the electrode on the semiconductor substrate, and the semiconductor A step of forming a conductive layer on the insulating film of the substrate; a step of forming a resist film on the conductive layer with an opening corresponding to the electrode; and an electrolytic plating method to form the resist. A metal plating layer is formed on the conductive layer inside the opening of the film, and the same metal as the metal plating layer is formed between the resist film and the conductive layer around the opening of the resist film. Forming a flange portion, removing the resist film to expose the conductive layer, and oxidizing the surface of the conductive layer exposed by removing the resist film to form an oxide film Process A method of manufacturing a semiconductor device and a step of removing by etching the oxide layer and the conductive layer thereunder are provided.

開示の技術の他の一観点によれば、半導体基板と、前記半導体基板の上方に形成された電極と、前記電極の上に形成された導電層と、前記導電層の上を覆う金属めっき層と、前記金属めっき層の上に形成されて前記金属めっき層よりも小径の金属層とを有する半導体装置が提供される。   According to another aspect of the disclosed technology, a semiconductor substrate, an electrode formed above the semiconductor substrate, a conductive layer formed on the electrode, and a metal plating layer covering the conductive layer And a semiconductor device formed on the metal plating layer and having a metal layer having a smaller diameter than the metal plating layer.

上記一観点に係る半導体装置の製造方法によれば、鍔部の分だけ金属層よりも導電層のほうが大きくなる。これにより、接続部の強度が高い半導体装置が得られる。   According to the method for manufacturing a semiconductor device according to the above aspect, the conductive layer is larger than the metal layer by the amount of the flange portion. As a result, a semiconductor device having a high strength of the connection portion can be obtained.

図１は、第１の実施形態に係る半導体装置の製造方法を示す断面図（その１）である。FIG. 1 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 図２は、第１の実施形態に係る半導体装置の製造方法を示す断面図（その２）である。FIG. 2 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 図３は、第１の実施形態に係る半導体装置の製造方法を示す断面図（その３）である。FIG. 3 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 図４は、第１の実施形態に係る半導体装置の製造方法を示す断面図（その４）である。FIG. 4 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 図５は、第１の実施形態に係る半導体装置の製造方法を示す断面図（その５）である。FIG. 5 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 図６は、レジスト膜と導電層との間の隙間にめっき液が入り込んで形成された鍔部を示す模式図である。FIG. 6 is a schematic view showing a collar portion formed by the plating solution entering the gap between the resist film and the conductive layer. 図７は、導電層の酸化に使用するプラズマアッシング装置を示す模式図である。FIG. 7 is a schematic view showing a plasma ashing apparatus used for oxidizing the conductive layer. 図８は、第１の実施形態に係る方法により形成した半導体チップを、他の半導体チップ上に積層（スタック）して半導体装置を完成させた状態を示す図である。FIG. 8 is a view showing a state where a semiconductor device is completed by stacking (stacking) semiconductor chips formed by the method according to the first embodiment on other semiconductor chips. 図９は、第１の実施形態に係る方法により形成した半導体チップを、パッケージ基板上に搭載して半導体装置を完成させた状態を示す図である。FIG. 9 is a view showing a state where a semiconductor device is completed by mounting a semiconductor chip formed by the method according to the first embodiment on a package substrate. 図１０は、導電層の表面を酸化させなることなく導電層をエッチングした場合の不具合を示す図である。FIG. 10 is a diagram showing a problem when the conductive layer is etched without oxidizing the surface of the conductive layer. 図１１は、第２の実施形態に係る半導体装置の製造方法を示す断面図（その１）である。FIG. 11 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 図１２は、第２の実施形態に係る半導体装置の製造方法を示す断面図（その２）である。FIG. 12 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 図１３は、第２の実施形態に係る半導体装置の製造方法を示す断面図（その３）である。FIG. 13 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 図１４は、第２の実施形態に係る半導体装置の製造方法を示す断面図（その４）である。FIG. 14 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 図１５は、第２の実施形態に係る半導体装置の製造方法を示す断面図（その５）である。FIG. 15 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 図１６は、第２の実施形態に係る方法により形成した半導体チップを、他の半導体チップ上に積層（スタック）して半導体装置を完成させた状態を示す図である。FIG. 16 is a view showing a state where a semiconductor device is completed by stacking (stacking) semiconductor chips formed by the method according to the second embodiment on other semiconductor chips. 図１７は、第２の実施形態に係る方法により形成した半導体チップを、パッケージ基板上に搭載して半導体装置を完成させた状態を示す図である。FIG. 17 is a view showing a state where a semiconductor device is completed by mounting a semiconductor chip formed by the method according to the second embodiment on a package substrate.

前述したように、スタックタイプの半導体装置では、通常バンプよりも小型のマイクロバンプやＣｕピラーが使用される。これらのマイクロバンプやＣｕピラーの形成には、成膜工程、フォトリソグラフィ工程、及びエッチング工程が使用されるが、エッチング工程においてＵＢＭがサイドエッチングされると、元々小さいＵＢＭ径が更に縮小して、強度が著しく低下してしまう。これにより、半導体装置の信頼性が損なわれる。   As described above, in the stack type semiconductor device, micro bumps and Cu pillars smaller than normal bumps are used. For the formation of these micro bumps and Cu pillars, a film forming process, a photolithography process, and an etching process are used, but when the UBM is side-etched in the etching process, the originally small UBM diameter is further reduced, Strength will fall remarkably. This impairs the reliability of the semiconductor device.

以下の実施形態では、サイドエッチングによるマイクロバンプやＣｕピラー等の接続部の強度の低下を回避できる半導体装置の製造方法について説明する。   In the following embodiments, a method for manufacturing a semiconductor device capable of avoiding a decrease in strength of connection portions such as micro bumps and Cu pillars due to side etching will be described.

（第１の実施形態）
図１〜図５は、第１の実施形態に係る半導体装置の製造方法を工程順に示す断面図である。ここでは、接続部にＣｕピラーを備えた半導体装置の製造方法について説明している。 (First embodiment)
1 to 5 are cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. Here, a method for manufacturing a semiconductor device provided with a Cu pillar in the connection portion is described.

まず、公知の方法により、半導体基板（ウェハ）にトランジスタ等の素子を形成し、その上に絶縁層及び配線層を形成する。図１（ａ）中の符号１１は、素子、絶縁層及び配線層が形成された半導体基板を示している。   First, an element such as a transistor is formed on a semiconductor substrate (wafer) by a known method, and an insulating layer and a wiring layer are formed thereon. Reference numeral 11 in FIG. 1A denotes a semiconductor substrate on which an element, an insulating layer, and a wiring layer are formed.

この半導体基板１１上の所定の位置に、例えばＡｌ（アルミニウム）等の金属により、電極１２を形成する。電極１２の直径は例えば５０μｍ〜１００μｍ程度、電極１２の厚さは例えば数μｍ程度とする。   An electrode 12 is formed at a predetermined position on the semiconductor substrate 11 by using a metal such as Al (aluminum). The diameter of the electrode 12 is about 50 μm to 100 μm, for example, and the thickness of the electrode 12 is about several μm, for example.

次に、ＣＶＤ（Chemical Vapor Deposition）法等により、半導体基板１１の上側全面に酸化シリコン又は窒化シリコン等の絶縁材料を堆積させて、パッシベーション膜１３を形成する。   Next, an insulating material such as silicon oxide or silicon nitride is deposited on the entire upper surface of the semiconductor substrate 11 by a CVD (Chemical Vapor Deposition) method or the like to form a passivation film 13.

その後、フォトリソグラフィ法を使用して、パッシベーション膜１３のうち電極１２に対応する部分を除去して、電極１２の表面を露出させる。   Thereafter, a portion corresponding to the electrode 12 in the passivation film 13 is removed by using a photolithography method to expose the surface of the electrode 12.

次に、図１（ｂ）に示すように、半導体基板１１の上側全面に、ＵＢＭとなるバリア層１４及び導電層１５を形成する。本実施形態では、スパッタリング法によりＴｉ（チタン）を１００μｍ程度の厚さに堆積させてバリア層１４とし、その上にＣｕ（銅）を２５０μｍ程度の厚さに堆積させて導電層１５とする。但し、バリア層１４及び導電層１５の材質及び厚さは、適宜変更してもよい。   Next, as shown in FIG. 1B, a barrier layer 14 and a conductive layer 15 to be UBM are formed on the entire upper surface of the semiconductor substrate 11. In this embodiment, Ti (titanium) is deposited to a thickness of about 100 μm by sputtering to form the barrier layer 14, and Cu (copper) is deposited to a thickness of about 250 μm thereon to form the conductive layer 15. However, the material and thickness of the barrier layer 14 and the conductive layer 15 may be changed as appropriate.

次に、図１（ｃ）に示すように、導電層１５の上にフォトレジストを例えば４０μｍ〜８０μｍの厚さに塗布して、レジスト膜１６を形成する。レジスト膜１６の厚さは、後述するＣｕピラー１９及びはんだ層２０の厚さに応じて適宜設定する。   Next, as shown in FIG. 1C, a photoresist is applied on the conductive layer 15 to a thickness of, for example, 40 μm to 80 μm to form a resist film 16. The thickness of the resist film 16 is appropriately set according to the thickness of a Cu pillar 19 and a solder layer 20 described later.

次に、レジスト膜１６を乾燥させた後、図２（ａ）に示すように、所定のパターンが設けられた露光マスク１７を使用して、レジスト膜１６のうち電極１２の上方の部分を選択的に露光する。   Next, after drying the resist film 16, as shown in FIG. 2A, a portion of the resist film 16 above the electrode 12 is selected using an exposure mask 17 provided with a predetermined pattern. Exposure.

その後、現像処理を実施して、図２（ｂ）に示すように、導電層１５のうち電極１２の上方の部分が露出する開口部１６ａを形成する。開口部１６ａの直径は、例えば２５μｍ〜３５μｍ程度とする。   Thereafter, development processing is performed to form an opening 16a in which a portion of the conductive layer 15 above the electrode 12 is exposed, as shown in FIG. The diameter of the opening 16a is, for example, about 25 μm to 35 μm.

次に、アッシング装置を使用して、図２（ｃ）に示すようにレジスト膜１６をアッシングする。このアッシングは、後述の工程で行う電解めっき時にレジスト膜１６の濡れ性を確保して、開口部１６ａ内にめっき液が進入しやすくするために行うものである。   Next, the resist film 16 is ashed using an ashing device as shown in FIG. This ashing is performed in order to ensure the wettability of the resist film 16 and facilitate the penetration of the plating solution into the opening 16a during the electrolytic plating performed in the process described later.

次に、図３（ａ）に示すように、導電層１５を電極としてＮｉ（ニッケル）めっきを行い、開口部１６ａの導電層１５上に、Ｎｉめっき層１８を形成する。Ｎｉめっき層１８の厚さは、例えば５μｍ〜１０μｍ程度とする。   Next, as shown in FIG. 3A, Ni (nickel) plating is performed using the conductive layer 15 as an electrode to form a Ni plating layer 18 on the conductive layer 15 in the opening 16a. The thickness of the Ni plating layer 18 is, for example, about 5 μm to 10 μm.

このとき、開口部１６ａの内側のエッジ部分では、レジスト膜１６と導電層１５との間のわずかな隙間にめっき液が入り込んで導電層１５上にめっき金属（Ｎｉ）が析出し、図６に模式的に示すように、鍔部１８ａが形成される。鍔部１８ａの幅ａは、例えば２μｍ〜３μｍ程度である。   At this time, at the inner edge portion of the opening 16a, the plating solution enters a slight gap between the resist film 16 and the conductive layer 15, and the plating metal (Ni) is deposited on the conductive layer 15. FIG. As schematically shown, a flange 18a is formed. The width a of the flange portion 18a is, for example, about 2 μm to 3 μm.

本実施形態では、上述の如く導電層１５とレジスト膜１６との界面にめっき液が入り込んで鍔部１８ａが形成されることが重要である。導電層１５とレジスト膜１６との界面にどの程度めっき液が入り込むかは、導電層１５とレジスト膜１６との密着度に関係する。   In the present embodiment, as described above, it is important that the plating solution enters the interface between the conductive layer 15 and the resist film 16 to form the flange portion 18a. The extent to which the plating solution enters the interface between the conductive layer 15 and the resist film 16 is related to the degree of adhesion between the conductive layer 15 and the resist film 16.

市販されている一般的なフォトレジスト（例えば、東京応化工業製フォトレジストPMER P-LA900 PM）を使用した場合、開口部１６ａのエッジ部分の導電層１５とレジスト膜１６との界面にめっき液が若干進入して、鍔部１８ａが必然的に形成される。   When a general photoresist that is commercially available (for example, a photoresist PMER P-LA900 PM manufactured by Tokyo Ohka Kogyo Co., Ltd.) is used, a plating solution is present at the interface between the conductive layer 15 and the resist film 16 at the edge of the opening 16a. Slightly entering, the flange 18a is inevitably formed.

なお、本実施形態では導電層１５をＣｕにより形成し、めっき層１８をＮｉにより形成している。しかし、導電層１５及びめっき層１８は、それぞれＣｕ、Ｎｉ、Ａｕ、Ａｇ、Ｃｒ及びＳｎのうちから選択された金属、又はその金属を主成分とする合金により形成してもよい。   In the present embodiment, the conductive layer 15 is made of Cu, and the plating layer 18 is made of Ni. However, the conductive layer 15 and the plating layer 18 may be formed of a metal selected from Cu, Ni, Au, Ag, Cr, and Sn, or an alloy containing the metal as a main component.

次に、図３（ｂ）に示すように、電解めっきにより、Ｎｉめっき層１８の上にＣｕを例えば３０μｍ〜６０μｍの厚さに堆積させて、Ｃｕピラー１９を形成する。Ｃｕピラー１９の直径は開口部１６ａの直径と同じになり、めっき層１８の直径よりも小径となる。   Next, as shown in FIG. 3B, Cu is deposited on the Ni plating layer 18 to a thickness of, for example, 30 μm to 60 μm by electrolytic plating to form a Cu pillar 19. The diameter of the Cu pillar 19 is the same as the diameter of the opening 16 a and is smaller than the diameter of the plating layer 18.

更に、図３（ｃ）に示すように、Ｃｕピラー１９の上にはんだを例えば１０μｍ〜１５μｍの厚さに電解めっきして、はんだ層２０を形成する。   Further, as shown in FIG. 3C, solder is electroplated on the Cu pillar 19 to a thickness of, for example, 10 μm to 15 μm to form a solder layer 20.

次に、レジスト剥離液を使用して、図４（ａ）に示すようにレジスト膜１６を除去する。レジスト膜１６を除去した後には、導電層１５の上にＮｉめっき層１８（鍔部１８ａを含む）が残留する。   Next, the resist film 16 is removed using a resist stripper as shown in FIG. After removing the resist film 16, the Ni plating layer 18 (including the flange portion 18 a) remains on the conductive layer 15.

次に、図４（ｂ）に示すように、導電層１５のうち露出している部分の表面を酸化させて、酸化層１５ａを形成する。具体的には、図７に模式的に示すように、プラズマアッシング装置３０のチャンバ３１内に半導体基板１１を配置する。そして、チャンバ３１内に例えば酸素（Ｏ2）とＣＦ4との混合ガスを供給しながら、真空ポンプ（図示せず）によりチャンバ３１内を排気して、チャンバ３１内を一定の圧力に維持する。また、上部電極３２ａと下部電極３２ｂとの間に高周波（ＲＦ）電源３３から高周波電圧を印加する。これにより、チャンバ３１内にプラズマが発生し、Ｃｕにより形成された導電層１５の表面が酸化（プラズマアッシング）されて、酸化層１５ａが形成される。 Next, as shown in FIG. 4B, the surface of the exposed portion of the conductive layer 15 is oxidized to form an oxide layer 15a. Specifically, as schematically shown in FIG. 7, the semiconductor substrate 11 is disposed in the chamber 31 of the plasma ashing apparatus 30. Then, while supplying, for example, a mixed gas of oxygen (O 2 ) and CF 4 into the chamber 31, the inside of the chamber 31 is evacuated by a vacuum pump (not shown) to maintain the inside of the chamber 31 at a constant pressure. . A high frequency voltage is applied from a high frequency (RF) power source 33 between the upper electrode 32a and the lower electrode 32b. As a result, plasma is generated in the chamber 31, the surface of the conductive layer 15 formed of Cu is oxidized (plasma ashing), and the oxide layer 15a is formed.

この場合、酸化層１５ａの厚さはアッシング時間により決まる。導電層１５は、その厚さ方向の半分程度まで酸化すればよい。それよりも多く酸化しようとすると、アッシング時間が長くなり、スループットが低下する。本実施形態のように、Ｏ2ガスにＣＦ4を添加することにより、Ｃｕが酸化するときのアッシングレートが上昇する。 In this case, the thickness of the oxide layer 15a is determined by the ashing time. The conductive layer 15 may be oxidized to about half of its thickness direction. If more oxidation is attempted, the ashing time becomes longer and the throughput decreases. As in this embodiment, the addition of CF 4 to O 2 gas increases the ashing rate when Cu is oxidized.

なお、導電層１５を酸化するときのアッシングは、等方性アッシングでもよく、異方性アッシングでもよい。   The ashing when oxidizing the conductive layer 15 may be isotropic ashing or anisotropic ashing.

次に、図４（ｃ）に示すように、バリア層１４が露出するまで酸化層１５ａ及びその下の導電層１５をエッチングする。導電層１５及び酸化層１５ａのエッチングには、エッチング液として例えば過水酢酸（過酸化水素水と酢酸と純水とを混合した液）や過水硫酸（過酸化水素水と硫酸と純水とを混合した液）を使用することができる。   Next, as shown in FIG. 4C, the oxide layer 15a and the underlying conductive layer 15 are etched until the barrier layer 14 is exposed. For etching the conductive layer 15 and the oxide layer 15a, for example, perhydroacetic acid (a mixture of hydrogen peroxide, acetic acid, and pure water) or perhydrosulfuric acid (hydrogen peroxide, sulfuric acid, and pure water) is used as an etchant. Can be used.

本実施形態では、導電層１５の表面を酸化させているため、短時間で導電層１５をエッチング除去することができる。エッチング終了後は、Ｎｉめっき層１８（鍔部１８ａを含む）の下に導電層１５が残留する。   In this embodiment, since the surface of the conductive layer 15 is oxidized, the conductive layer 15 can be etched away in a short time. After the etching is completed, the conductive layer 15 remains under the Ni plating layer 18 (including the flange 18a).

一般的な半導体装置の製造工程では、めっき工程においてレジスト開口部の内側のエッジ部分に鍔部が形成されても、その後のエッチング工程等において鍔部が容易に脱落してしまう。しかし、本実施形態では、鍔部１８ａを残すために、上述したようにエッチング工程の前に導電層１５に対し酸化処理（アッシング処理）を行って、エッチング時間の短縮を図っている。   In a general semiconductor device manufacturing process, even if a flange is formed at the edge portion inside the resist opening in the plating process, the flange is easily dropped in the subsequent etching process or the like. However, in the present embodiment, in order to leave the flange portion 18a, as described above, the conductive layer 15 is oxidized (ashed) before the etching process to shorten the etching time.

上述の如く、導電層１５及び酸化層１５ａをエッチングしてバリア層１４を露出させた後、図５（ａ）に示すように、パッシベーション膜１３が露出するまでバリア層１４をエッチングする。Ｔｉからなるバリア層１４のエッチングには、例えばアルカリ性チタンエッチング液（例えば、過酸化水素水に純水と水酸化カリウム等を混合した液）を使用することができる。   As described above, after the conductive layer 15 and the oxide layer 15a are etched to expose the barrier layer 14, the barrier layer 14 is etched until the passivation film 13 is exposed as shown in FIG. For the etching of the barrier layer 14 made of Ti, for example, an alkaline titanium etching solution (for example, a solution obtained by mixing pure water and potassium hydroxide in hydrogen peroxide solution) can be used.

次いで、図５（ｂ）に示すようにはんだ層２０を例えば２３０℃〜２４０℃程度の低温でリフローして、はんだ層２０の表面を滑らかにする。本実施形態では、はんだ層２０の厚さが前述の如く１０μｍ〜１５μｍと薄いので、リフロー後のはんだ層２０のＣｕピラー１９から横方向に張り出し量が少ない。従って、狭ピッチの半導体装置に適用できる。   Next, as shown in FIG. 5B, the solder layer 20 is reflowed at a low temperature of about 230 ° C. to 240 ° C., for example, to smooth the surface of the solder layer 20. In the present embodiment, since the thickness of the solder layer 20 is as thin as 10 μm to 15 μm as described above, the amount of lateral protrusion from the Cu pillar 19 of the solder layer 20 after reflow is small. Therefore, it can be applied to a narrow pitch semiconductor device.

次いで、ダイシング装置により半導体基板１１を切断して、個々の半導体チップに分離する。そして、その半導体チップを、他の半導体チップ又はパッケージ基板上に実装して、半導体装置を完成する。   Next, the semiconductor substrate 11 is cut by a dicing apparatus and separated into individual semiconductor chips. Then, the semiconductor chip is mounted on another semiconductor chip or a package substrate to complete the semiconductor device.

図８は、上述した方法により形成した半導体チップを、他の半導体チップ上に積層（スタック）して半導体装置を完成させた状態を示す図である。   FIG. 8 is a view showing a state in which the semiconductor device is completed by stacking (stacking) the semiconductor chip formed by the above-described method on another semiconductor chip.

図８に示す半導体装置４０は、パッケージ基板４１と、半導体チップ４４と、半導体チップ４５とを有する。   A semiconductor device 40 illustrated in FIG. 8 includes a package substrate 41, a semiconductor chip 44, and a semiconductor chip 45.

半導体チップ４４にはロジック回路が形成されており、この半導体チップ４４はパッケージ基板４１上に搭載されている。パッケージ基板４１の下面側には回路基板（図示せず）に形成された電極と接続する通常バンプ４２が形成されており、上面側には電極４３が形成されている。電極４４と半導体チップ４４の上面周縁部に形成された電極とは、金属細線（ボンディングワイヤ）４７により電気的に接続されている。   A logic circuit is formed on the semiconductor chip 44, and the semiconductor chip 44 is mounted on the package substrate 41. A normal bump 42 connected to an electrode formed on a circuit board (not shown) is formed on the lower surface side of the package substrate 41, and an electrode 43 is formed on the upper surface side. The electrode 44 and the electrode formed on the periphery of the upper surface of the semiconductor chip 44 are electrically connected by a metal thin wire (bonding wire) 47.

半導体チップ４５には例えばＤＲＡＭ（Dynamic Random Access Memory）が形成されており、上述の実施形態に記載した方法により形成されたＣｕピラー１９を介して半導体チップ４４の電極に接続されている。   For example, a DRAM (Dynamic Random Access Memory) is formed in the semiconductor chip 45 and is connected to the electrode of the semiconductor chip 44 through the Cu pillar 19 formed by the method described in the above-described embodiment.

図９は、上述した方法により形成した半導体チップを、パッケージ基板上に搭載して半導体装置を完成させた状態を示す図である。   FIG. 9 is a diagram showing a state where the semiconductor chip is completed by mounting the semiconductor chip formed by the above-described method on the package substrate.

図９に示す半導体装置５０は、パッケージ基板５１と、半導体チップ５５とを有する。   A semiconductor device 50 shown in FIG. 9 includes a package substrate 51 and a semiconductor chip 55.

パッケージ基板５１の下側には通常バンプ５２が形成されている。また、パッケージ基板５１の上側には、電極５３が形成されている。   A normal bump 52 is formed on the lower side of the package substrate 51. Further, an electrode 53 is formed on the upper side of the package substrate 51.

半導体チップ５５は、上述の実施形態に記載した方法により形成されたＣｕピラー１９を介して、パッケージ基板５１の電極５３に接続されている。   The semiconductor chip 55 is connected to the electrode 53 of the package substrate 51 via the Cu pillar 19 formed by the method described in the above embodiment.

本実施形態では、前述したように、導電層１５をエッチングする前に導電層１５の表面を酸化させて、導電層１５のエッチング時間を短縮している。これにより、エッチング終了時には、鍔部１８ａと、鍔部１８ａの下方の導電層１５及びバリア層１４とが残る。   In the present embodiment, as described above, the etching time of the conductive layer 15 is shortened by oxidizing the surface of the conductive layer 15 before etching the conductive layer 15. Thereby, at the end of etching, the flange portion 18a, and the conductive layer 15 and the barrier layer 14 below the flange portion 18a remain.

そして、鍔部１８ａの下方に導電層１５及びバリア層１４が残ることにより、ＵＢＭ径の縮小が回避され、Ｃｕピラー１９の強度が高くなる。その結果、半導体装置の信頼性が向上する。   And since the conductive layer 15 and the barrier layer 14 remain below the flange portion 18a, the reduction of the UBM diameter is avoided, and the strength of the Cu pillar 19 is increased. As a result, the reliability of the semiconductor device is improved.

仮に、導電層１５の表面を酸化させなることなく導電層１５をエッチングした場合は、エッチング時間が長くなり、鍔部１８ａが除去されてしまう。そのため、例えば図１０に示すように導電層１５の径が縮小し、更にバリア層１４がサイドエッチングされてしまう。これにより、Ｃｕピラー１９の強度が減少し、半導体装置の信頼性が低下してしまう。   If the conductive layer 15 is etched without oxidizing the surface of the conductive layer 15, the etching time becomes long and the collar portion 18a is removed. Therefore, for example, as shown in FIG. 10, the diameter of the conductive layer 15 is reduced, and the barrier layer 14 is further side-etched. Thereby, the intensity | strength of Cu pillar 19 reduces and the reliability of a semiconductor device will fall.

（第２の実施形態）
図１１〜図１５は、第２の実施形態に係る半導体装置の製造方法を工程順に示す断面図である。ここでは、接続部にマイクロバンプを備えた半導体装置の製造方法について説明している。 (Second Embodiment)
11 to 15 are cross-sectional views showing the method of manufacturing the semiconductor device according to the second embodiment in the order of steps. Here, a manufacturing method of a semiconductor device provided with a micro bump in the connection portion is described.

まず、公知の方法により、半導体基板（ウェハ）にトランジスタ等の素子を形成し、その上に絶縁層及び配線層を形成する。図１１（ａ）中の符号６１は、素子、絶縁層及び配線層が形成された半導体基板を示している。   First, an element such as a transistor is formed on a semiconductor substrate (wafer) by a known method, and an insulating layer and a wiring layer are formed thereon. Reference numeral 61 in FIG. 11A denotes a semiconductor substrate on which an element, an insulating layer, and a wiring layer are formed.

この半導体基板６１上の所定の位置に、例えばＡｌ等の金属により、電極６２を形成する。   An electrode 62 is formed at a predetermined position on the semiconductor substrate 61 by using a metal such as Al.

次に、ＣＶＤ法等により、半導体基板６１の上側全面に酸化シリコン又は窒化シリコン等の絶縁材料を堆積させて、パッシベーション膜６３を形成する。   Next, a passivation film 63 is formed by depositing an insulating material such as silicon oxide or silicon nitride on the entire upper surface of the semiconductor substrate 61 by a CVD method or the like.

その後、フォトリソグラフィ法を使用して、パッシベーション膜６３のうち電極６２に対応する部分を除去して、電極６２の表面を露出させる。   Thereafter, a portion of the passivation film 63 corresponding to the electrode 62 is removed by using a photolithography method to expose the surface of the electrode 62.

次に、図１１（ｂ）に示すように、半導体基板６１の上側全面に、ＵＢＭとなるバリア層６４及び導電層６５を形成する。本実施形態では、スパッタリング法によりＴｉ（チタン）を１００μｍ程度の厚さに堆積させてバリア層６４とし、その上にＣｕ（銅）を２５０μｍ程度の厚さに堆積させて導電層６５とする。   Next, as illustrated in FIG. 11B, a barrier layer 64 and a conductive layer 65 to be UBM are formed on the entire upper surface of the semiconductor substrate 61. In this embodiment, Ti (titanium) is deposited to a thickness of about 100 μm by sputtering to form the barrier layer 64, and Cu (copper) is deposited to a thickness of about 250 μm thereon to form the conductive layer 65.

次に、図１１（ｃ）に示すように、導電層６５の上にフォトレジストを例えば１０μｍ〜２０μｍの厚さに塗布して、レジスト膜６６を形成する。レジスト膜６６の厚さは、後述するはんだ層６９の厚さに応じて適宜設定する。   Next, as shown in FIG. 11C, a photoresist is applied on the conductive layer 65 to a thickness of, for example, 10 μm to 20 μm to form a resist film 66. The thickness of the resist film 66 is appropriately set according to the thickness of a solder layer 69 described later.

次に、レジスト膜６６を乾燥させた後、図１２（ａ）に示すように、所定のパターンが設けられた露光マスク６７を使用して、レジスト膜６６のうち電極６２の上方の部分を選択的に露光する。   Next, after drying the resist film 66, as shown in FIG. 12A, a portion of the resist film 66 above the electrode 62 is selected using an exposure mask 67 provided with a predetermined pattern. Exposure.

その後、現像処理を実施して、図１２（ｂ）に示すように、導電層６５のうち電極６２の上方の部分が露出する開口部６６ａを形成する。開口部６６ａの直径は、例えば２５μｍ〜３５μｍ程度とする。   Thereafter, development processing is performed to form an opening 66a in which a portion of the conductive layer 65 above the electrode 62 is exposed, as shown in FIG. The diameter of the opening 66a is, for example, about 25 μm to 35 μm.

次に、アッシング装置を使用して、図１２（ｃ）に示すようにレジスト膜６６をアッシングする。   Next, using an ashing apparatus, the resist film 66 is ashed as shown in FIG.

次に、図１３（ａ）に示すように、導電層６５を電極としてＮｉ（ニッケル）めっきを行い、開口部６６ａ内の導電層６５上に、Ｎｉめっき層６８を形成する。Ｎｉめっき層６８の厚さは、例えば５μｍ程度とする。   Next, as shown in FIG. 13A, Ni (nickel) plating is performed using the conductive layer 65 as an electrode to form a Ni plating layer 68 on the conductive layer 65 in the opening 66a. The thickness of the Ni plating layer 68 is, for example, about 5 μm.

このとき、開口部６６ａの内側のエッジ部分では、レジスト膜６６と導電層６５との間のわずかな隙間にめっき液が入り込んで導電層６５上にめっき金属（Ｎｉ）が析出し、鍔部６８ａが形成される。   At this time, at the inner edge portion of the opening 66a, the plating solution enters a slight gap between the resist film 66 and the conductive layer 65, and the plating metal (Ni) is deposited on the conductive layer 65, so that the flange 68a. Is formed.

次に、図１３（ｂ）に示すように、Ｎｉめっき層６８の上にはんだを例えば１０μｍ〜１５μｍの厚さに電解めっきして、はんだ層６９を形成する。本実施形態では、図１３（ｂ）のように、はんだ層６９が開口部６６ａの外側に若干突出するまでＮｉめっきを行うものとする。   Next, as shown in FIG. 13 (b), a solder layer 69 is formed by electroplating solder on the Ni plating layer 68 to a thickness of 10 μm to 15 μm, for example. In this embodiment, as shown in FIG. 13B, Ni plating is performed until the solder layer 69 slightly protrudes outside the opening 66a.

次に、レジスト剥離液を使用して、図１３（ｃ）に示すようにレジスト膜６６を除去する。レジスト膜６６を除去した後には、導電層６５の上にＮｉめっき層６８（鍔部６８ａを含む）が残留する。   Next, using a resist stripper, the resist film 66 is removed as shown in FIG. After removing the resist film 66, the Ni plating layer 68 (including the flange portion 68a) remains on the conductive layer 65.

次に、図７に例示するプラズマアッシング装置を使用して、図１４（ａ）に示すように導電層６５のうち露出している部分の表面を酸化させて、酸化層６５ａを形成する。   Next, using the plasma ashing apparatus illustrated in FIG. 7, the surface of the exposed portion of the conductive layer 65 is oxidized as shown in FIG. 14A to form an oxide layer 65a.

次に、図１４（ｂ）に示すように、バリア層６４が露出するまで酸化層６５ａ及びその下の導電層６５をエッチングする。導電層６５及び酸化層６５ａのエッチングには、エッチング液として例えば過水酢酸（過酸化水素水と酢酸と純水とを混合した液）や過水硫酸（過酸化水素水と硫酸と純水とを混合した液）を使用することができる。   Next, as shown in FIG. 14B, the oxide layer 65a and the underlying conductive layer 65 are etched until the barrier layer 64 is exposed. For etching the conductive layer 65 and the oxide layer 65a, for example, perhydroacetic acid (a mixture of hydrogen peroxide, acetic acid, and pure water) or perhydrosulfuric acid (hydrogen peroxide, sulfuric acid, and pure water) is used as an etchant. Can be used.

本実施形態では、導電層６５の表面を酸化させているため、短時間で導電層６５をエッチング除去することができる。エッチング終了後は、Ｎｉめっき層６８（鍔部６８ａを含む）の下に導電層６５が残留する。   In this embodiment, since the surface of the conductive layer 65 is oxidized, the conductive layer 65 can be removed by etching in a short time. After the etching is completed, the conductive layer 65 remains under the Ni plating layer 68 (including the flange portion 68a).

次に、図１４（ｃ）に示すように、パッシベーション膜６３が露出するまでバリア層６４をエッチングする。Ｔｉからなるバリア層６４のエッチングには、例えばアルカリ性チタンエッチング液（例えば、過酸化水素水に純水と水酸化カリウム等を混合した液）を使用することができる。   Next, as shown in FIG. 14C, the barrier layer 64 is etched until the passivation film 63 is exposed. For the etching of the barrier layer 64 made of Ti, for example, an alkaline titanium etching solution (for example, a solution obtained by mixing pure water and potassium hydroxide in hydrogen peroxide solution) can be used.

次いで、図１５に示すようにはんだ層６９を例えば２３０℃〜２４０℃程度の低温でリフローして、はんだからなる表面が滑らかな球状のマイクロバンプ７０を形成する。本実施形態では、はんだ層６９の厚さが前述の如く１０μｍ〜１５μｍ程度と薄いので、はんだ層６９から形成されるマイクロバンプ７０の横方向に張り出し量が少ない。従って、狭ピッチの半導体装置に適用できる。   Next, as shown in FIG. 15, the solder layer 69 is reflowed at a low temperature of about 230 ° C. to 240 ° C., for example, to form spherical microbumps 70 having a smooth surface made of solder. In this embodiment, since the thickness of the solder layer 69 is as thin as about 10 μm to 15 μm as described above, the amount of protrusion of the micro bumps 70 formed from the solder layer 69 in the lateral direction is small. Therefore, it can be applied to a narrow pitch semiconductor device.

次いで、ダイシング装置により半導体基板６１を切断して、個々の半導体チップに分離する。そして、その半導体チップを、他の半導体チップ又はパッケージ基板上に実装して、半導体装置を完成する。   Next, the semiconductor substrate 61 is cut by a dicing apparatus and separated into individual semiconductor chips. Then, the semiconductor chip is mounted on another semiconductor chip or a package substrate to complete the semiconductor device.

図１６は、上述した方法により形成した半導体チップを、他の半導体チップ上に積層（スタック）して半導体装置を完成させた状態を示す図である。   FIG. 16 is a diagram showing a state in which the semiconductor device is completed by stacking (stacking) the semiconductor chip formed by the above-described method on another semiconductor chip.

図１６に示す半導体装置８０は、パッケージ基板８１と、半導体チップ８４と、半導体チップ８５とを有する。   A semiconductor device 80 illustrated in FIG. 16 includes a package substrate 81, a semiconductor chip 84, and a semiconductor chip 85.

半導体チップ８４にはロジック回路が形成されており、この半導体チップ８４はパッケージ基板８１上に搭載されている。パッケージ基板８１の下面側には回路基板（図示せず）に形成された電極と接続する通常バンプ８２が形成されており、上面側には電極８３が形成されている。電極８４と半導体チップ８４の上面周縁部に形成された電極とは、金属細線（ボンディングワイヤ）８７により電気的に接続されている。   A logic circuit is formed on the semiconductor chip 84, and the semiconductor chip 84 is mounted on the package substrate 81. A normal bump 82 connected to an electrode formed on a circuit board (not shown) is formed on the lower surface side of the package substrate 81, and an electrode 83 is formed on the upper surface side. The electrode 84 and the electrode formed on the periphery of the upper surface of the semiconductor chip 84 are electrically connected by a metal thin wire (bonding wire) 87.

半導体チップ８５には例えばＤＲＡＭが形成されており、上述の実施形態に記載した方法により形成されたマイクロバンプ７０を介して半導体チップ８４の電極に接続されている。   For example, a DRAM is formed in the semiconductor chip 85 and is connected to the electrode of the semiconductor chip 84 via the micro bumps 70 formed by the method described in the above-described embodiment.

図１７は、上述した方法により形成した半導体チップを、パッケージ基板上に搭載して半導体装置を完成させた状態を示す図である。   FIG. 17 is a view showing a state where a semiconductor device is completed by mounting the semiconductor chip formed by the above-described method on a package substrate.

図１７に示す半導体装置９０は、パッケージ基板９１と、半導体チップ９５とを有する。   A semiconductor device 90 illustrated in FIG. 17 includes a package substrate 91 and a semiconductor chip 95.

パッケージ基板９１の下側には通常バンプ９２が形成されている。また、パッケージ基板９１の上側には、電極９３が形成されている。   A normal bump 92 is formed on the lower side of the package substrate 91. An electrode 93 is formed on the upper side of the package substrate 91.

半導体チップ９５は、上述の実施形態に記載した方法により形成されたマイクロバンプ７０を介して、パッケージ基板９１の電極９３に接続されている。   The semiconductor chip 95 is connected to the electrode 93 of the package substrate 91 through the micro bumps 70 formed by the method described in the above embodiment.

本実施形態においても、第１の実施形態と同様に、導電層６５をエッチングする前に導電層６５の表面を酸化させて、導電層６５のエッチング時間を短縮している。これにより、エッチング終了時には、鍔部６８ａと、鍔部６８ａの下方の導電層６５及びバリア層６４とが残る。   Also in this embodiment, the etching time of the conductive layer 65 is shortened by oxidizing the surface of the conductive layer 65 before the conductive layer 65 is etched, as in the first embodiment. As a result, when the etching is finished, the flange 68a, and the conductive layer 65 and the barrier layer 64 below the flange 68a remain.

そして、鍔部６８ａの下方に導電層６５及びバリア層６４が残ることにより、ＵＢＭ径の縮小が回避され、マイクロバンプ７０の強度が高くなる。その結果、半導体装置の信頼性が向上する。   Then, the conductive layer 65 and the barrier layer 64 remain below the flange portion 68a, so that the UBM diameter is prevented from being reduced and the strength of the microbump 70 is increased. As a result, the reliability of the semiconductor device is improved.

以上の諸実施形態に関し、更に以下の付記を開示する。   The following additional notes are disclosed with respect to the above embodiments.

（付記１）半導体基板上に電極を形成する工程と、
前記半導体基板上に、前記電極に対応する部分に開口部が設けられた絶縁膜を形成する工程と、
前記半導体基板の前記絶縁膜上に導電層を形成する工程と、
前記導電層の上に、前記電極に対応する部分に開口部が設けられたレジスト膜を形成する工程と、
電解めっき法により、前記レジスト膜の前記開口部の内側の前記導電層上に金属めっき層を形成するとともに、前記レジスト膜の前記開口部の周囲の前記レジスト膜と前記導電層との間に前記金属めっき層と同じ金属からなる鍔部を形成する工程と、
前記レジスト膜を除去して前記導電層を露出させる工程と、
前記レジスト膜を除去することにより露出した部分の前記導電層の表面を酸化させて酸化膜を形成する工程と、
前記酸化膜及びその下の前記導電層をエッチングにより除去する工程と
を有することを特徴とする半導体装置の製造方法。 (Appendix 1) forming an electrode on a semiconductor substrate;
Forming an insulating film provided with an opening in a portion corresponding to the electrode on the semiconductor substrate;
Forming a conductive layer on the insulating film of the semiconductor substrate;
Forming a resist film having an opening in a portion corresponding to the electrode on the conductive layer;
A metal plating layer is formed on the conductive layer inside the opening of the resist film by an electrolytic plating method, and the resist film and the conductive layer around the opening of the resist film are interposed between the resist film and the conductive layer. Forming a flange made of the same metal as the metal plating layer;
Removing the resist film to expose the conductive layer;
Oxidizing the surface of the conductive layer exposed by removing the resist film to form an oxide film;
And a step of removing the oxide film and the conductive layer therebelow by etching.

（付記２）前記絶縁膜を形成する工程と前記導電層を形成する工程との間に、前記絶縁膜上にバリア層を形成する工程を有することを特徴とする付記１に記載の半導体装置の製造方法。   (Appendix 2) The semiconductor device according to Appendix 1, further comprising a step of forming a barrier layer on the insulating film between the step of forming the insulating film and the step of forming the conductive layer. Production method.

（付記３）前記導電層を銅により形成することを特徴とする付記１又は２に記載の半導体装置の製造方法。   (Additional remark 3) The manufacturing method of the semiconductor device of Additional remark 1 or 2 characterized by forming the said conductive layer with copper.

（付記４）前記金属めっき層をニッケルにより形成することを特徴とする付記１乃至３のいずれか１項に記載の半導体装置の製造方法。   (Additional remark 4) The said metal plating layer is formed with nickel, The manufacturing method of the semiconductor device of any one of Additional remark 1 thru | or 3 characterized by the above-mentioned.

（付記５）前記酸化膜を形成する工程は、ＣＦ4を含む酸素雰囲気中で行うことを特徴とする付記１乃至４のいずれか１項に記載の半導体装置の製造方法。 (Supplementary note 5) The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 4, wherein the step of forming the oxide film is performed in an oxygen atmosphere containing CF 4 .

（付記６）前記金属めっき層を形成する工程と前記レジスト膜を除去する工程との間に、前記金属めっき層の上に金属層をめっきする工程を有することを特徴とする付記１乃至５のいずれか１項に記載の半導体装置の製造方法。   (Additional remark 6) It has the process of plating a metal layer on the said metal plating layer between the process of forming the said metal plating layer, and the process of removing the said resist film, The additional remark 1 thru | or 5 characterized by the above-mentioned A manufacturing method of a semiconductor device given in any 1 paragraph.

（付記７）前記金属層を銅により形成することを特徴とする付記６に記載の半導体装置の製造方法。   (Additional remark 7) The manufacturing method of the semiconductor device of Additional remark 6 characterized by forming the said metal layer with copper.

（付記８）前記金属層をはんだにより形成することを特徴とする付記６に記載の半導体装置の製造方法。   (Additional remark 8) The manufacturing method of the semiconductor device of Additional remark 6 characterized by forming the said metal layer with a solder.

（付記９）半導体基板と、
前記半導体基板の上方に形成された電極と、
前記電極の上に形成された導電層と、
前記導電層の上を覆う金属めっき層と、
前記金属めっき層の上に形成されて前記金属めっき層よりも小径の金属層と
を有することを特徴とする半導体装置。 (Appendix 9) a semiconductor substrate;
An electrode formed above the semiconductor substrate;
A conductive layer formed on the electrode;
A metal plating layer covering the conductive layer;
A semiconductor device comprising: a metal layer formed on the metal plating layer and having a smaller diameter than the metal plating layer.

（付記１０）前記導電層が銅により形成され、前記金属めっき層がニッケルにより形成されていることを特徴とする付記９に記載の半導体装置。   (Supplementary note 10) The semiconductor device according to supplementary note 9, wherein the conductive layer is made of copper and the metal plating layer is made of nickel.

（付記１１）前記金属層が銅により形成されたＣｕピラーであることを特徴とする付記９又は１０に記載の半導体装置。   (Supplementary note 11) The semiconductor device according to Supplementary note 9 or 10, wherein the metal layer is a Cu pillar formed of copper.

（付記１２）前記金属層がはんだにより形成されたマイクロバンプであることを特徴とする付記９又は１０に記載の半導体装置。   (Supplementary note 12) The semiconductor device according to Supplementary note 9 or 10, wherein the metal layer is a micro bump formed of solder.

１１，６１…半導体基板、１２，６２…電極、１３，６３…パッシベーション膜、１４，６４…バリア層、１５，６５…導電層、１５ａ，６５ａ…酸化層、１６，６６…レジスト膜、１７，６７…露光マスク、１８，６８…めっき層、１８ａ，６８ａ…鍔部、１９…Ｃｕピラー、２０、６９…はんだ層、３０…プラズマアッシング装置、３１…チャンバ、３２ａ…上部電極、３２ｂ…下部電極、３３…高周波電源、４０，５０．８０，９０…半導体装置、４１，５１，８１，９１…パッケージ基板、４２，５２，８２，９２…通常バンプ、４３，５３，８３，９３…電極、４４，４５，５５，８４，８５，９５…半導体チップ、４７，８７…金属細線、７０…マイクロバンプ。   DESCRIPTION OF SYMBOLS 11, 61 ... Semiconductor substrate, 12, 62 ... Electrode, 13, 63 ... Passivation film, 14, 64 ... Barrier layer, 15, 65 ... Conductive layer, 15a, 65a ... Oxidation layer, 16, 66 ... Resist film, 17, 67 ... Exposure mask, 18, 68 ... Plating layer, 18a, 68a ... Hut, 19 ... Cu pillar, 20, 69 ... Solder layer, 30 ... Plasma ashing device, 31 ... Chamber, 32a ... Upper electrode, 32b ... Lower electrode 33, high frequency power supply, 40, 50.80, 90 ... semiconductor device, 41, 51, 81, 91 ... package substrate, 42, 52, 82, 92 ... normal bump, 43, 53, 83, 93 ... electrode, 44 , 45, 55, 84, 85, 95... Semiconductor chip, 47, 87... Fine metal wire, 70.

Claims (6)

半導体基板上に電極を形成する工程と、
前記半導体基板上に、前記電極に対応する部分に開口部が設けられた絶縁膜を形成する工程と、
前記半導体基板の前記絶縁膜上に導電層を形成する工程と、
前記導電層の上に、前記電極に対応する部分に開口部が設けられたレジスト膜を形成する工程と、
電解めっき法により、前記レジスト膜の前記開口部の内側の前記導電層上に金属めっき層を形成するとともに、前記レジスト膜の前記開口部の周囲の前記レジスト膜と前記導電層との間に前記金属めっき層と同じ金属からなる鍔部を形成する工程と、
前記レジスト膜を除去して前記導電層を露出させる工程と、
前記レジスト膜を除去することにより露出した部分の前記導電層の表面を酸化させて酸化膜を形成する工程と、
前記酸化膜及びその下の前記導電層をエッチングにより除去する工程と
を有することを特徴とする半導体装置の製造方法。 Forming an electrode on a semiconductor substrate;
Forming an insulating film provided with an opening in a portion corresponding to the electrode on the semiconductor substrate;
Forming a conductive layer on the insulating film of the semiconductor substrate;
Forming a resist film having an opening in a portion corresponding to the electrode on the conductive layer;
A metal plating layer is formed on the conductive layer inside the opening of the resist film by an electrolytic plating method, and the resist film and the conductive layer around the opening of the resist film are interposed between the resist film and the conductive layer. Forming a flange made of the same metal as the metal plating layer;
Removing the resist film to expose the conductive layer;
Oxidizing the surface of the conductive layer exposed by removing the resist film to form an oxide film;
And a step of removing the oxide film and the conductive layer therebelow by etching. 前記絶縁膜を形成する工程と前記導電層を形成する工程との間に、前記絶縁膜上にバリア層を形成する工程を有することを特徴とする請求項１に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a barrier layer on the insulating film between the step of forming the insulating film and the step of forming the conductive layer. 前記導電層を銅により形成することを特徴とする請求項１又は２に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the conductive layer is formed of copper. 前記金属めっき層をニッケルにより形成することを特徴とする請求項１乃至３のいずれか１項に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the metal plating layer is formed of nickel. 前記金属めっき層を形成する工程と前記レジスト膜を除去する工程との間に、前記金属めっき層の上に金属層をめっきする工程を有することを特徴とする請求項１乃至４のいずれか１項に記載の半導体装置の製造方法。   5. The method according to claim 1, further comprising a step of plating a metal layer on the metal plating layer between the step of forming the metal plating layer and the step of removing the resist film. A method for manufacturing the semiconductor device according to the item. 半導体基板と、
前記半導体基板の上方に形成された電極と、
前記電極の上に形成された導電層と、
前記導電層の上を覆う金属めっき層と、
前記金属めっき層の上に形成されて前記金属めっき層よりも小径の金属層と
を有することを特徴とする半導体装置。 A semiconductor substrate;
An electrode formed above the semiconductor substrate;
A conductive layer formed on the electrode;
A metal plating layer covering the conductive layer;
A semiconductor device comprising: a metal layer formed on the metal plating layer and having a smaller diameter than the metal plating layer.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190013551A (en) 2017-07-28 2019-02-11 아스리트 에프에이 가부시키가이샤 Columnar member mounting device and columnar member mounting method
US10964658B2 (en) 2019-02-14 2021-03-30 Toshiba Memory Corporation Semiconductor device having a metallic oxide or metallic hydroxide barrier layer
US11145513B2 (en) 2018-09-25 2021-10-12 Nichia Corporation Method of manufacturing semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11274201A (en) * 1998-03-18 1999-10-08 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JP2008028112A (en) * 2006-07-20 2008-02-07 Toshiba Corp Manufacturing method for semiconductor device
JP2012204391A (en) * 2011-03-23 2012-10-22 Sony Corp Semiconductor device, semiconductor device manufacturing method, and circuit board manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11274201A (en) * 1998-03-18 1999-10-08 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JP2008028112A (en) * 2006-07-20 2008-02-07 Toshiba Corp Manufacturing method for semiconductor device
JP2012204391A (en) * 2011-03-23 2012-10-22 Sony Corp Semiconductor device, semiconductor device manufacturing method, and circuit board manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190013551A (en) 2017-07-28 2019-02-11 아스리트 에프에이 가부시키가이샤 Columnar member mounting device and columnar member mounting method
US11145513B2 (en) 2018-09-25 2021-10-12 Nichia Corporation Method of manufacturing semiconductor device
US10964658B2 (en) 2019-02-14 2021-03-30 Toshiba Memory Corporation Semiconductor device having a metallic oxide or metallic hydroxide barrier layer

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