JP2014132603A - Multilayer wiring board - Google Patents

Multilayer wiring board Download PDF

Info

Publication number
JP2014132603A
JP2014132603A JP2012249904A JP2012249904A JP2014132603A JP 2014132603 A JP2014132603 A JP 2014132603A JP 2012249904 A JP2012249904 A JP 2012249904A JP 2012249904 A JP2012249904 A JP 2012249904A JP 2014132603 A JP2014132603 A JP 2014132603A
Authority
JP
Japan
Prior art keywords
land
wiring
wiring board
multilayer wiring
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2012249904A
Other languages
Japanese (ja)
Other versions
JP5789872B2 (en
Inventor
Atsushi Itabashi
敦 板橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Original Assignee
Fujikura Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd filed Critical Fujikura Ltd
Priority to JP2012249904A priority Critical patent/JP5789872B2/en
Priority to US14/075,023 priority patent/US9265147B2/en
Publication of JP2014132603A publication Critical patent/JP2014132603A/en
Application granted granted Critical
Publication of JP5789872B2 publication Critical patent/JP5789872B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer wiring board which can inhibit increase in wiring resistance and the occurrence of defective wiring.SOLUTION: A multilayer wiring board has a resin base material, a wiring pattern and vias. The wiring pattern has lands provided on the resin base material. Each via has an end connected with the land. At least a part of lateral faces of the land has contact with the via. Accordingly even when the via and the land are misaligned, decrease in contact area between the via and the land can be inhibited.

Description

この発明は、ビアを介して層間接続される多層配線基板に関する。   The present invention relates to a multilayer wiring board that is interlayer-connected through vias.

近年、携帯機器の多機能化に伴い、半導体デバイスの更なる高機能化が求められている。そして、この要求を満たすため、半導体デバイスの配線技術は向上し、配線の微細化が進んでいる。高密度配線技術としては、多層配線基板が知られているが、例えば、引用文献１に記載されているように、一般的には層間を接続するビアの径に対してビアの端部に接続されるランドの径は大きく設定されている。   In recent years, with the increase in the number of functions of portable devices, further enhancement of functions of semiconductor devices has been demanded. In order to satisfy this requirement, the wiring technology of semiconductor devices has been improved and the miniaturization of wiring has been advanced. As a high-density wiring technology, a multilayer wiring board is known. For example, as described in the cited document 1, generally, the connection is made to the end of the via with respect to the diameter of the via connecting the layers. The diameter of the land to be set is set large.

特開２００４−３１５３１JP 2004-31531 A

しかしながら、上記引用文献１のようにビアの径に対してランドの径が大きい構造においては、ランド間のスペースが狭くなるため、ＷＬＣＳＰ（Ｗａｆｅｒ Ｌｅｖｅｌ Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）等の挟ピッチ化された電極パッドを有する半導体デバイスを内蔵するような場合には、電極パッドと接続されたビアからの配線の引き回しが困難であるという問題がある。そこで、ランドの径を極力小さくしてランド間のスペースを確保することも考えられるが、ランドの径を小さくすると、ビアとランドの接触面積が小さくなって配線抵抗が増加したり、ランドとビア間の僅かな位置ずれによって配線不良が生じる。   However, in the structure in which the land diameter is larger than the via diameter as in the above cited document 1, since the space between the lands is narrowed, electrode pads with a narrow pitch such as WLCSP (Wafer Level Chip Size Package) are used. In the case of incorporating a semiconductor device having, there is a problem that it is difficult to route wiring from vias connected to electrode pads. Therefore, it is conceivable to reduce the land diameter as much as possible to secure a space between the lands. However, if the land diameter is reduced, the contact area between the via and the land decreases, the wiring resistance increases, and the land and vias increase. Wiring defects occur due to slight misalignment.

この発明は、上述した従来技術による問題点を解消し、配線抵抗の増加や配線不良の発生を抑制できる多層配線基板を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer wiring board capable of solving the above-described problems caused by the prior art and suppressing an increase in wiring resistance and occurrence of wiring defects.

本発明に係る多層配線基板は、樹脂基材と、前記樹脂基材に設けられたランドを有する配線パターンと、端部が前記ランドと接続されるビアとを備えた多層配線基板において、前記ランドの側面の少なくとも一部が前記ビアと接していることを特徴とする。   The multilayer wiring board according to the present invention includes a resin base material, a wiring pattern having a land provided on the resin base material, and a via having an end connected to the land. At least a part of the side surface of this is in contact with the via.

本発明に係る多層配線基板において、ランドの側面の少なくとも一部はビアと接している。したがって、ビアとランドの合わせずれが生じても、ビアとランドの接触面積の低下を抑えることができる。このため、本発明は、配線抵抗の増加や配線不良の発生を抑制できる。   In the multilayer wiring board according to the present invention, at least a part of the side surface of the land is in contact with the via. Therefore, even if a misalignment between the via and the land occurs, a decrease in the contact area between the via and the land can be suppressed. For this reason, this invention can suppress the increase in wiring resistance and generation | occurrence | production of wiring defect.

多層配線基板の一つの実施の形態において、前記ランドは、前記ビアに埋め込まれている。これにより、ビアとランドの接触面積を増やすことができる。また、多層配線基板の一つの実施の形態において、前記ランドの径は、前記ビアの径よりも小さい。これにより、ランドの占有面積を小さくでき、信号用配線間のピッチも小さくできる。したがって、信号用配線を高密度にレイアウトできる。   In one embodiment of the multilayer wiring board, the land is embedded in the via. As a result, the contact area between the via and the land can be increased. In one embodiment of the multilayer wiring board, the diameter of the land is smaller than the diameter of the via. Thereby, the area occupied by the land can be reduced, and the pitch between the signal wirings can also be reduced. Therefore, the signal wiring can be laid out with high density.

また、多層配線基板の一つの実施の形態において、所定ピッチで配列された複数の電極パッドを有する電子部品を内蔵し、前記ビアの前記ランドを接続されていない端部は、前記電極パッドに接続されている。   In one embodiment of the multilayer wiring board, an electronic component having a plurality of electrode pads arranged at a predetermined pitch is incorporated, and an end of the via not connected to the land is connected to the electrode pad. Has been.

本発明によれば、多層配線基板の配線抵抗や配線不良を低減できる。   According to the present invention, wiring resistance and wiring defects of a multilayer wiring board can be reduced.

本発明の第１の実施の形態に係る部品内蔵基板の構造を示す断面図である。It is sectional drawing which shows the structure of the component built-in board | substrate which concerns on the 1st Embodiment of this invention. 第１の実施の形態に係るランド３４とビア７０との関係を示す上面図である。It is a top view which shows the relationship between the land 34 and the via | veer 70 which concern on 1st Embodiment. 比較例及び第１の実施の形態の一例に係る上面図及び断面図である。It is a top view and sectional view concerning an example of a comparative example and a 1st embodiment. 本発明の第１の実施の形態に係る部品内蔵基板の製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process of the component built-in board | substrate which concerns on the 1st Embodiment of this invention. 同部品内蔵基板を製造工程の概略を示す断面図である。It is sectional drawing which shows the outline of a manufacturing process of the said board | substrate with a built-in component. 同部品内蔵基板を製造工程の概略を示す断面図である。It is sectional drawing which shows the outline of a manufacturing process of the said board | substrate with a built-in component. 同部品内蔵基板を製造工程の概略を示す断面図である。It is sectional drawing which shows the outline of a manufacturing process of the said board | substrate with a built-in component. 同部品内蔵基板を製造工程の概略を示す断面図である。It is sectional drawing which shows the outline of a manufacturing process of the said board | substrate with a built-in component. 同部品内蔵基板を製造工程の概略を示す断面図である。It is sectional drawing which shows the outline of a manufacturing process of the said board | substrate with a built-in component. 本発明の第２の実施の形態に係る多層配線基板の構造を示す断面図である。It is sectional drawing which shows the structure of the multilayer wiring board based on the 2nd Embodiment of this invention. 本発明の他の実施の形態に係るランド３４とビア７０との関係を示す断面図である。It is sectional drawing which shows the relationship between the land 34 and via | veer 70 concerning other embodiment of this invention.

以下、添付の図面を参照して、この発明の実施の形態に係る多層配線基板を詳細に説明する。   Hereinafter, a multilayer wiring board according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

［第１の実施の形態］
図１は、本発明の第１の実施の形態に係る部品内蔵基板（多層配線基板）の構造を示す断面図である。第１の実施の形態に係る部品内蔵基板は、図１に示すように、第１プリント配線基材１０と、第２プリント配線基材２０と、保護層４０と、第３プリント配線基材３０とを熱圧着（接着層５１〜５３）により積層した構造を備える。 [First Embodiment]
FIG. 1 is a cross-sectional view showing the structure of a component built-in substrate (multilayer wiring substrate) according to the first embodiment of the present invention. As shown in FIG. 1, the component-embedded substrate according to the first embodiment includes a first printed wiring substrate 10, a second printed wiring substrate 20, a protective layer 40, and a third printed wiring substrate 30. Are laminated by thermocompression bonding (adhesive layers 51 to 53).

接着層５１は、第１プリント配線基材１０と第２プリント配線基材２０との間を接着する。接着層５２は、第２プリント配線基材２０と保護層４０との間を接着する。接着層５３は、保護層４０と第３プリント配線基材３０との間を接着する。保護層４０は、加熱圧着時の層間短絡を防止するため、絶縁フィルム（ＰＥＴ，ポリイミド，液晶ポリマー等）により構成される。接着層５１〜５３は、例えばエポキシ系やアクリル系の接着剤など、有機系接着剤などからなる。   The adhesive layer 51 adheres between the first printed wiring substrate 10 and the second printed wiring substrate 20. The adhesive layer 52 adheres between the second printed wiring board 20 and the protective layer 40. The adhesive layer 53 adheres between the protective layer 40 and the third printed wiring substrate 30. The protective layer 40 is made of an insulating film (PET, polyimide, liquid crystal polymer, etc.) in order to prevent an interlayer short circuit during thermocompression bonding. The adhesive layers 51 to 53 are made of, for example, an organic adhesive such as an epoxy adhesive or an acrylic adhesive.

更に、部品内蔵基板は、図１に示すように、電子部品６０、及びビア７０を有する。電子部品６０は、第２プリント配線基材２０に形成された開口部２９内に、第１及び第３プリント配線基材１０，３０に挟まれた状態で内蔵される。ビア７０は、積層方向に延びて保護層４０を貫通して、電子部品６０と第３プリント配線基材３０との間に設けられる。ビア７０は、低融点の金属フィラーと高融点の金属フィラーを含む合金により構成され、その表面を熱硬化性樹脂により覆われている。ここで、金属フィラーは、例えばニッケル、金、銀、銅、アルミニウム、鉄、錫、ビスマス、インジウム、鉛などである。熱硬化性樹脂は、例えばエポキシ、アクリル、ウレタンなどを主成分とするペーストである。   Further, the component-embedded substrate has an electronic component 60 and a via 70 as shown in FIG. The electronic component 60 is housed inside the opening 29 formed in the second printed wiring substrate 20 in a state sandwiched between the first and third printed wiring substrates 10 and 30. The via 70 extends in the stacking direction and penetrates the protective layer 40 and is provided between the electronic component 60 and the third printed wiring substrate 30. The via 70 is made of an alloy including a low melting point metal filler and a high melting point metal filler, and the surface thereof is covered with a thermosetting resin. Here, the metal filler is, for example, nickel, gold, silver, copper, aluminum, iron, tin, bismuth, indium, lead or the like. The thermosetting resin is a paste mainly composed of epoxy, acrylic, urethane, or the like.

第１〜第３プリント配線基材１０〜３０は、各々、図１に示すように、第１〜第３樹脂基材１１〜３１、及び信号用配線１２〜３２を有する。信号用配線１２は、第１樹脂基材１１の下面（片面）に形成される。信号用配線２２は、第２樹脂基材２１の下面及び上面（両面）に形成される。信号用配線３２は、第３樹脂基材３１の下面及び上面（両面）に形成される。   As shown in FIG. 1, each of the first to third printed wiring base materials 10 to 30 includes first to third resin base materials 11 to 31 and signal wirings 12 to 32. The signal wiring 12 is formed on the lower surface (one surface) of the first resin base material 11. The signal wiring 22 is formed on the lower surface and the upper surface (both surfaces) of the second resin base material 21. The signal wiring 32 is formed on the lower surface and the upper surface (both surfaces) of the third resin base material 31.

第１〜第３樹脂基材１１〜３１は、樹脂フィルムにより構成される。ここで、樹脂フィルムは、例えばポリイミド、ポリオレフィン、液晶ポリマー、熱硬化性のエポキシ樹脂等である。信号用配線１２〜３２は、パターン形成された銅箔などの導電材により構成される。   The 1st-3rd resin base materials 11-31 are comprised with the resin film. Here, the resin film is, for example, polyimide, polyolefin, liquid crystal polymer, thermosetting epoxy resin, or the like. The signal wirings 12 to 32 are made of a conductive material such as a patterned copper foil.

また、第３プリント配線基材３０は、図１に示すように、第３樹脂基材３１を貫通するビアホールＨ内に充填された信号用ビア３３、及び信号用配線３２の先端に設けられたランド３４を有する。信号用ビア３３は、第３樹脂基材３１の両面に形成された信号用配線３２に電気的に接続される。信号用ビア３３は、めっきにより形成される。ランド３４は、第３樹脂基材３１の下面に設けられている。ここで、図２は第１の実施の形態に係るランド３４とビア７０との関係を示す上面図である。図２に示すように、ランド３４の径はビア７０の径よりも小さく、ランド３４はビア７０に埋め込まれている。したがって、ランド３４はその下面だけでなく、側面でもビア７０と接している。ランド３４は、パターン形成された銅箔などの導電材により構成され、ビア７０と合金を形成している。   Further, as shown in FIG. 1, the third printed wiring substrate 30 is provided at the tip of the signal via 33 and the signal wiring 32 filled in the via hole H penetrating the third resin substrate 31. It has a land 34. The signal via 33 is electrically connected to the signal wiring 32 formed on both surfaces of the third resin base material 31. The signal via 33 is formed by plating. The land 34 is provided on the lower surface of the third resin base material 31. Here, FIG. 2 is a top view showing the relationship between the land 34 and the via 70 according to the first embodiment. As shown in FIG. 2, the diameter of the land 34 is smaller than the diameter of the via 70, and the land 34 is embedded in the via 70. Therefore, the land 34 is in contact with the via 70 not only on the lower surface but also on the side surface. The land 34 is made of a conductive material such as a patterned copper foil, and forms an alloy with the via 70.

電子部品６０は、ＷＬＰ（Ｗａｆｅｒ Ｌｅｖｅｌ Ｐａｃｋａｇｅ）により構成される。電子部品６０の上面には、図１に示すように、電極６１、樹脂６２が設けられる。電極６１は、ビア７０の下端と電気的に接続される。電極６１は銅などの導電材により構成され、ビア７０と合金を形成している。樹脂６２は、電極６１を露出させるように電子部品６０の上面を覆う。   The electronic component 60 is configured by WLP (Wafer Level Package). As shown in FIG. 1, an electrode 61 and a resin 62 are provided on the upper surface of the electronic component 60. The electrode 61 is electrically connected to the lower end of the via 70. The electrode 61 is made of a conductive material such as copper, and forms an alloy with the via 70. The resin 62 covers the upper surface of the electronic component 60 so that the electrode 61 is exposed.

次に、図３を参照して、第１の実施の形態の効果を比較例と比較して説明する。図３（ａ）は、比較例のビア７０、信号用配線３２、及びランド３４を示す上面図、図３（ｂ）は、図３（ａ）のＡ−Ａ’断面図であり、図３（ｃ）は、第１の実施の形態のビア７０、信号用配線３２、及びランド３４の一例を示す上面図、図３（ｄ）は、図３（ｃ）のＢ−Ｂ’断面図である。   Next, the effect of the first embodiment will be described in comparison with a comparative example with reference to FIG. 3A is a top view showing the via 70, the signal wiring 32, and the land 34 of the comparative example, and FIG. 3B is a cross-sectional view taken along the line AA ′ of FIG. FIG. 3C is a top view illustrating an example of the via 70, the signal wiring 32, and the land 34 according to the first embodiment, and FIG. 3D is a cross-sectional view taken along the line BB ′ in FIG. is there.

図３（ａ）及び図３（ｂ）に示すように、比較例において、ビア７０はランド３４の下面に接し、ランド３４の径はビア７０の径よりも大きい。したがって、ランド３４間の間隔が狭くなって、配線可能な信号用配線３２の数が少なくなってしまう。   As shown in FIGS. 3A and 3B, in the comparative example, the via 70 is in contact with the lower surface of the land 34, and the diameter of the land 34 is larger than the diameter of the via 70. Therefore, the interval between the lands 34 is narrowed, and the number of signal wirings 32 that can be wired is reduced.

例えば、図３（ａ）に示す比較例において、ビア７０のピッチＰを３００μｍ、ランド３４の径Ｒ１を１７０μｍ、ビア７０の径Ｒ２を１００μｍとすると、隣接ランド３４間の配線可能幅Ｄ１は３００−１７０＝１３０μｍである。従って、信号用配線３２の幅Ｗ１を４０μｍ、配線間に最低必要な間隔を４０μｍとすると、ランド３４間には、１本の信号用配線３２しか形成することができない。
これに対して、図３（ｃ）及び図３（ｄ）に示すように、第１の実施の形態の一例においては、ランド３４の径Ｒ１′がビア７０の径Ｒ２よりも小さい。上述の例によれば、隣接ビア７０間の配線可能幅Ｄ２は、３００−１００＝２００μｍとなる。このため、信号用配線３２の幅Ｗ１を４０μｍ、配線間に最低必要な間隔を４０μｍとすると、ランド３４間には、２本の信号用配線３２を配置することができ、信号用配線３２を比較例よりも高密度にレイアウトすることができる。 For example, in the comparative example shown in FIG. 3A, if the pitch P of the vias 70 is 300 μm, the diameter R1 of the lands 34 is 170 μm, and the diameter R2 of the vias 70 is 100 μm, the wireable width D1 between the adjacent lands 34 is 300. −170 = 130 μm. Therefore, if the width W1 of the signal wiring 32 is 40 μm and the minimum necessary interval between the wirings is 40 μm, only one signal wiring 32 can be formed between the lands 34.
On the other hand, as shown in FIGS. 3C and 3D, in one example of the first embodiment, the diameter R1 ′ of the land 34 is smaller than the diameter R2 of the via 70. According to the above example, the routable width D2 between the adjacent vias 70 is 300−100 = 200 μm. For this reason, if the width W1 of the signal wiring 32 is 40 μm and the minimum necessary interval between the wirings is 40 μm, two signal wirings 32 can be arranged between the lands 34, and the signal wiring 32 The layout can be laid out more densely than the comparative example.

以上の相違点により、比較例よりも第１の実施の形態の方が、同一層に配置可能な配線数が多い。このため、図３（ｂ）及び図３（ｄ）に示すように、比較例では信号用配線３２の配置に３層必要であったのに対し、第１の実施の形態では、信号用配線３２の配置に２層あれば足りることになる。   Due to the above differences, the first embodiment has more wires that can be arranged in the same layer than the comparative example. For this reason, as shown in FIGS. 3B and 3D, in the comparative example, three layers are required for the arrangement of the signal wiring 32, whereas in the first embodiment, the signal wiring is used. Two layers are sufficient for the arrangement of 32.

一方、第１の実施の形態のように、ランド３４の径Ｒ１′がビア７０の径Ｒ２よりも小さくなると、ビア７０とランド３４の接触面積が小さくなると共に、ビア７０とランド３４との位置合わせズレが生じた場合には、配線不良になる可能性が高くなる。この点、第１の実施の形態では、ランド３４がビア７０の上端に埋め込まれており、ランド３４の下面のみならず、ランド３４の側面もＴ１の幅でビア７０と接している。このため、接触面積を大きくすることができ、且つビア７０とランド３４の合わせズレが生じたとしても、ビア７０とランド３４の接触面積の低下及び配線不良を抑えることができる。   On the other hand, when the diameter R1 ′ of the land 34 is smaller than the diameter R2 of the via 70 as in the first embodiment, the contact area between the via 70 and the land 34 is reduced, and the positions of the via 70 and the land 34 are reduced. When misalignment occurs, there is a high possibility of wiring failure. In this regard, in the first embodiment, the land 34 is embedded in the upper end of the via 70, and not only the lower surface of the land 34 but also the side surface of the land 34 is in contact with the via 70 with a width of T1. For this reason, the contact area can be increased, and even if a misalignment between the via 70 and the land 34 occurs, a decrease in the contact area between the via 70 and the land 34 and wiring defects can be suppressed.

次に、図４に沿って、図５〜図９を参照しながら第１の実施の形態に係る部品内蔵基板の製造方法について説明する。図４は、部品内蔵基板の製造工程を示すフローチャートである。図５〜図９は、部品内蔵基板を製造工程の概略を示す断面図である。   Next, a method for manufacturing the component-embedded substrate according to the first embodiment will be described along FIG. 4 with reference to FIGS. FIG. 4 is a flowchart showing manufacturing steps of the component built-in substrate. 5 to 9 are cross-sectional views showing an outline of the manufacturing process of the component-embedded substrate.

先ず、図５に示すように、第１〜第３プリント配線基材１０〜３０を準備する（図４のＳ１０１）。ここで、第１〜第３プリント配線基材１０〜３０の信号用配線１２〜３２は、サブトラクティブ法、又はセミアディティブ法により形成される。また、第２プリント配線基材２０の開口部２９は、レーザ加工、ドリル加工、金型加工により形成される。次に、図６に示すように、第１プリント配線基材１０の上面に接着層５１を積層させ、第２プリント配線基材２０の上面に接着層５２、保護層４０、及び接着層５３を積層させる（図４のＳ１０２）。   First, as shown in FIG. 5, the 1st-3rd printed wiring base materials 10-30 are prepared (S101 of FIG. 4). Here, the signal wirings 12 to 32 of the first to third printed wiring substrates 10 to 30 are formed by a subtractive method or a semi-additive method. In addition, the opening 29 of the second printed wiring board 20 is formed by laser processing, drilling, or die processing. Next, as shown in FIG. 6, the adhesive layer 51 is laminated on the upper surface of the first printed wiring substrate 10, and the adhesive layer 52, the protective layer 40, and the adhesive layer 53 are formed on the upper surface of the second printed wiring substrate 20. They are stacked (S102 in FIG. 4).

続いて、図７に示すように、接着層５１の上面に電子部品６０を実装する（図４のＳ１０３）。次に、図８に示すように、電子部品６０を開口部２９に収容するように、接着層５１の上面に第２プリント配線基材２０を積層させる（図４のＳ１０４）。   Subsequently, as shown in FIG. 7, the electronic component 60 is mounted on the upper surface of the adhesive layer 51 (S103 in FIG. 4). Next, as shown in FIG. 8, the second printed wiring substrate 20 is laminated on the upper surface of the adhesive layer 51 so that the electronic component 60 is accommodated in the opening 29 (S104 in FIG. 4).

続いて、レーザ加工により、保護層４０を貫通するホールＨ’を形成する。次に、図９に示すように、ホールＨ’を導電ペーストにて埋めることによってビア７０を形成する（図４のＳ１０５）。そして、第３プリント配線基材３０を接着層５３の上面に積層させ、第１〜第３プリント配線基材１０〜３０を加熱圧着させる（図４のＳ１０６）。これにより、ランド３４がビア７０の上端部に埋め込まれるように第１〜第３プリント配線基材１０〜３０が圧着され、図１に示す部品内蔵基板が製造される。このランド３４とビア７０を圧着させる際に、ビア７０内の低融点の金属フィラー及び熱硬化性樹脂は融解する。融解した低融点の金属フィラーは、ランド３４の銅と合金化する。   Subsequently, a hole H ′ penetrating the protective layer 40 is formed by laser processing. Next, as shown in FIG. 9, vias 70 are formed by filling the holes H 'with a conductive paste (S105 in FIG. 4). And the 3rd printed wiring base material 30 is laminated | stacked on the upper surface of the contact bonding layer 53, and the 1st-3rd printed wiring base materials 10-30 are heat-pressed (S106 of FIG. 4). Thereby, the first to third printed wiring bases 10 to 30 are pressure-bonded so that the land 34 is embedded in the upper end portion of the via 70, and the component built-in substrate shown in FIG. 1 is manufactured. When the land 34 and the via 70 are pressure-bonded, the low melting point metal filler and the thermosetting resin in the via 70 are melted. The molten low melting point metal filler is alloyed with the copper of the land 34.

［第２の実施の形態］
次に、図１０を参照して、本発明の第２の実施の形態に係る多層配線基板８０について説明する。第１の実施の形態は、電子部品６０を内蔵した部品内蔵基板であったが、本実施の形態の多層配線基板８０は、図１０に示すように、電子部品９０と実装基板１００と間に設けられ、それらを電気的に接続するインターポーザとして機能する。 [Second Embodiment]
Next, a multilayer wiring board 80 according to a second embodiment of the present invention will be described with reference to FIG. Although the first embodiment is a component built-in board in which the electronic component 60 is built, the multilayer wiring board 80 of the present embodiment is provided between the electronic component 90 and the mounting board 100 as shown in FIG. It is provided and functions as an interposer that electrically connects them.

多層配線基板８０は、図１０に示すように、第１プリント配線基材１１０と、保護層２００と、第２プリント配線基材１２０と、保護層２１０と、第３プリント配線基材１３０とを熱圧着（接着層１４１〜１４４）により積層した構造を備える。   As shown in FIG. 10, the multilayer wiring board 80 includes a first printed wiring base 110, a protective layer 200, a second printed wiring base 120, a protective layer 210, and a third printed wiring base 130. A structure laminated by thermocompression bonding (adhesive layers 141 to 144) is provided.

接着層１４１は、第１プリント配線基材１１０と保護層２００との間を接着する。接着層１４２は、保護層２００と第２プリント配線基材１２０との間を接着する。接着層１４３は、第２プリント配線基材１２０と保護層２１０との間を接着する。接着層１４４は、保護層２１０と第３プリント配線基材１３０との間を接着する。なお、保護層２００，２１０及び接着層１４１〜１４４は、第１の実施の形態の保護層４０及び接着層５１〜５３と同様の材料にて構成される。   The adhesive layer 141 adheres between the first printed wiring substrate 110 and the protective layer 200. The adhesive layer 142 adheres between the protective layer 200 and the second printed wiring substrate 120. The adhesive layer 143 adheres between the second printed wiring substrate 120 and the protective layer 210. The adhesive layer 144 adheres between the protective layer 210 and the third printed wiring substrate 130. The protective layers 200 and 210 and the adhesive layers 141 to 144 are made of the same material as the protective layer 40 and the adhesive layers 51 to 53 of the first embodiment.

更に、多層配線基板８０は、図１０に示すように、ビア１５０，１６０を有する。ビア１５０，１６０は、積層方向に延びる。ビア１５０は、保護層２００を貫通して、第１プリント配線基材１１０と第２プリント配線基材１２０との間に設けられる。ビア１６０は、保護層２１０を貫通して、第２プリント配線基材１２０と第３プリント配線基材１３０との間に設けられる。なお、ビア１５０，１６０は、第１の実施の形態のビア７０と同様の材料にて構成される。   Furthermore, the multilayer wiring board 80 has vias 150 and 160 as shown in FIG. The vias 150 and 160 extend in the stacking direction. The via 150 is provided between the first printed wiring base 110 and the second printed wiring base 120 through the protective layer 200. The via 160 is provided between the second printed wiring substrate 120 and the third printed wiring substrate 130 through the protective layer 210. The vias 150 and 160 are made of the same material as the via 70 of the first embodiment.

第１〜第３プリント配線基材１１０〜１３０は、各々、図１０に示すように、第１〜第３樹脂基材１１１〜１３１、信号用配線１１２〜１３２、及び信号用ビア１１３〜１３３を有する。信号用配線１１２は、第１樹脂基材１１１の下面及び上面（両面）に形成される。信号用配線１２２は、第２樹脂基材１２１の下面及び上面（両面）に形成される。信号用配線１３２は、第３樹脂基材１３１の下面及び上面（両面）に形成される。信号用ビア１１３〜１３３は、各々、第１〜第３樹脂基材１１１〜１３１を貫通するビアホールＨ１〜Ｈ３内に充填される。信号用ビア１１３〜１３３は、各々、第１〜第３樹脂基材１１１〜１３１の両面に形成された信号用配線１１２〜１３２に電気的に接続される。なお、第１〜第３樹脂基材１１１〜１３１、信号用配線１１２〜１３２、及び信号用ビア１１３〜１３３は、第１の実施の形態の第１〜第３樹脂基材１１〜３１、信号用配線１２〜３２、及び信号用ビア３３と同様の材料にて構成される。   As shown in FIG. 10, the first to third printed wiring substrates 110 to 130 include first to third resin substrates 111 to 131, signal wirings 112 to 132, and signal vias 113 to 133, respectively. Have. The signal wiring 112 is formed on the lower surface and the upper surface (both surfaces) of the first resin base material 111. The signal wiring 122 is formed on the lower surface and the upper surface (both surfaces) of the second resin base 121. The signal wiring 132 is formed on the lower surface and the upper surface (both surfaces) of the third resin base material 131. The signal vias 113 to 133 are filled in the via holes H1 to H3 penetrating the first to third resin base materials 111 to 131, respectively. The signal vias 113 to 133 are electrically connected to signal wirings 112 to 132 formed on both surfaces of the first to third resin base materials 111 to 131, respectively. The first to third resin base materials 111 to 131, the signal wirings 112 to 132, and the signal vias 113 to 133 are the first to third resin base materials 11 to 31 of the first embodiment. The wirings 12 to 32 and the signal vias 33 are made of the same material.

また、第２、第３プリント配線基材１２０、１３０は、各々、図１０に示すように、信号用配線１２２，１３２の先端に設けられたランド１２４，１３４を有する。ランド１２４，１３４は、第２，第３樹脂基材１２１，１３１の下面に設けられている。具体的に、ランド１２４，１３４の径は、各々ビア１５０，１６０の径よりも小さく、ランド１２４，１３４はビア１５０，１６０に埋め込まれている。したがって、ランド１２４，１３４はその下面だけでなく、側面でもビア１５０，１６０と接している。なお、ランド１２４，１３４は、第１の実施の形態のランド３４と同様の材料にて構成される。   The second and third printed wiring substrates 120 and 130 have lands 124 and 134 provided at the tips of the signal wirings 122 and 132, respectively, as shown in FIG. The lands 124 and 134 are provided on the lower surfaces of the second and third resin base materials 121 and 131. Specifically, the diameters of the lands 124 and 134 are smaller than the diameters of the vias 150 and 160, respectively, and the lands 124 and 134 are embedded in the vias 150 and 160. Therefore, the lands 124 and 134 are in contact with the vias 150 and 160 not only on the lower surface but also on the side surfaces. The lands 124 and 134 are made of the same material as that of the land 34 according to the first embodiment.

更に、第１、第３プリント配線基材１１０、１３０は、各々、図１０に示すように、バンプ１１５，１３５、及びソルダーレジスト１１６，１３６を有する。バンプ１１５は、信号用配線１１２の下面に設けられ、実装基板１００と電気的に接続される。バンプ１３５は、信号用配線１３２の上面に設けられ、電子部品９０の電極９１に電気的に接続される。ソルダーレジスト１１６は、第１樹脂基材１１１の下面及び信号用配線１１２の下面を覆う。ソルダーレジスト１３６は、第３樹脂基材１３１の上面及び信号用配線１３２の上面を覆う。   Further, the first and third printed wiring substrates 110 and 130 have bumps 115 and 135 and solder resists 116 and 136, respectively, as shown in FIG. The bump 115 is provided on the lower surface of the signal wiring 112 and is electrically connected to the mounting substrate 100. The bump 135 is provided on the upper surface of the signal wiring 132 and is electrically connected to the electrode 91 of the electronic component 90. The solder resist 116 covers the lower surface of the first resin substrate 111 and the lower surface of the signal wiring 112. The solder resist 136 covers the upper surface of the third resin base 131 and the upper surface of the signal wiring 132.

以上、第２の実施の形態に係る多層配線基板８０は、第１の実施の形態と同様の特徴を有するビア１５０，１６０及びランド１２４，１３４により、第１の実施の形態と同様の効果を奏する。   As described above, the multilayer wiring board 80 according to the second embodiment has the same effect as that of the first embodiment by the vias 150 and 160 and the lands 124 and 134 having the same characteristics as those of the first embodiment. Play.

以上、発明の実施の形態を説明したが、本発明はこれらに限定されるものではなく、発明の趣旨を逸脱しない範囲内において、種々の変更、追加等が可能である。例えば、図１１（ａ）〜（ｃ）に示すように、ランド３４の側面の一部のみがビア７０に接していてもよい。図１１（ａ）に示す例においては、ランド３４の側面の一部及び下面の一部のみがビア７０に接する。図１１（ｂ）に示す例においては、ランド３４の側面の一部及び下面全体のみがビア７０に接する。図１１（ｃ）に示す例においては、ランド３４の下面全体及び側面の下部のみがビア７０に接する。   Although the embodiments of the invention have been described above, the present invention is not limited to these embodiments, and various modifications and additions can be made without departing from the spirit of the invention. For example, as shown in FIGS. 11A to 11C, only a part of the side surface of the land 34 may be in contact with the via 70. In the example shown in FIG. 11A, only a part of the side surface and a part of the lower surface of the land 34 are in contact with the via 70. In the example shown in FIG. 11B, only a part of the side surface and the entire lower surface of the land 34 are in contact with the via 70. In the example shown in FIG. 11C, the entire lower surface of the land 34 and only the lower part of the side surface are in contact with the via 70.

１０〜３０…第１〜第３プリント配線基材、 １１〜３１…第１〜第３樹脂基材、 １２〜３２…信号用配線、 ２９…開口部、 ３３…信号用ビア、 ３４…ランド、 ４０…保護層、 ５１〜５３…接着層、 ６０…電子部品、 ６１…電極、 ７０…ビア、 ８０…多層配線基板、 ９０…電子部品、 ９１…電極、 １００…実装基板、 １１０〜１３０…第１〜第３プリント配線基材、 １１１〜１３１…第１〜第３樹脂基材、 １１２〜１３２…信号用配線、 １１３〜１３３…信号用ビア、 １２４，１３４…ランド、 １１５，１３５…バンプ、 １１６，１３６…ソルダーレジスト、 １４１〜１４４…接着層、 １５０，１６０…ビア、 ２００，２１０…保護層。   DESCRIPTION OF SYMBOLS 10-30 ... 1st-3rd printed wiring base material, 11-31 ... 1st-3rd resin base material, 12-32 ... Signal wiring, 29 ... Opening part, 33 ... Signal via, 34 ... Land, DESCRIPTION OF SYMBOLS 40 ... Protective layer, 51-53 ... Adhesion layer, 60 ... Electronic component, 61 ... Electrode, 70 ... Via, 80 ... Multi-layer wiring board, 90 ... Electronic component, 91 ... Electrode, 100 ... Mounting substrate, 110-130 ... No. 1st-3rd printed wiring base material, 111-131 ... 1st-3rd resin base material, 112-132 ... Signal wiring, 113-133 ... Signal via, 124, 134 ... Land, 115, 135 ... Bump, 116, 136 ... Solder resist, 141-144 ... Adhesive layer, 150, 160 ... Via, 200, 210 ... Protective layer.

Claims (4)

樹脂基材と、
前記樹脂基材に設けられたランドを有する配線パターンと、
端部が前記ランドと接続されるビアと
を備えた多層配線基板において、
前記ランドの側面の少なくとも一部が前記ビアと接している
ことを特徴とする多層配線基板。 A resin substrate;
A wiring pattern having lands provided on the resin substrate;
In a multilayer wiring board provided with vias whose ends are connected to the lands,
A multilayer wiring board, wherein at least a part of a side surface of the land is in contact with the via. 前記ランドは、前記ビアに埋め込まれている
ことを特徴とする請求項１記載の多層配線基板。 The multilayer wiring board according to claim 1, wherein the land is embedded in the via. 前記ランドの径は、前記ビアの径よりも小さい
ことを特徴とする請求項１又は請求項２記載の多層配線基板。 The multilayer wiring board according to claim 1, wherein a diameter of the land is smaller than a diameter of the via. 所定ピッチで配列された複数の電極パッドを有する電子部品を内蔵し、
前記ビアの前記ランドを接続されていない端部は、前記電極パッドに接続されている
ことを特徴とする請求項１乃至請求項３記載の多層配線基板。


Built-in electronic component having a plurality of electrode pads arranged at a predetermined pitch,
4. The multilayer wiring board according to claim 1, wherein an end of the via that is not connected to the land is connected to the electrode pad. 5.


JP2012249904A 2012-11-14 2012-11-14 Multilayer wiring board Active JP5789872B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012249904A JP5789872B2 (en) 2012-11-14 2012-11-14 Multilayer wiring board
US14/075,023 US9265147B2 (en) 2012-11-14 2013-11-08 Multi-layer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012249904A JP5789872B2 (en) 2012-11-14 2012-11-14 Multilayer wiring board

Publications (2)

Publication Number Publication Date
JP2014132603A true JP2014132603A (en) 2014-07-17
JP5789872B2 JP5789872B2 (en) 2015-10-07

Family

ID=51411544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012249904A Active JP5789872B2 (en) 2012-11-14 2012-11-14 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JP5789872B2 (en)

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1093242A (en) * 1996-09-18 1998-04-10 Toshiba Corp Printed wiring board
JPH10303561A (en) * 1997-04-30 1998-11-13 Hitachi Chem Co Ltd Multi-layer wiring board and its manufacture
JPH11251740A (en) * 1998-02-27 1999-09-17 Fuji Xerox Co Ltd Printed board and manufacture thereof
JP2002026520A (en) * 2000-07-06 2002-01-25 Matsushita Electric Ind Co Ltd Multilayer interconnection board and its manufacturing method
JP2005101935A (en) * 2003-09-25 2005-04-14 Canon Inc Image reading apparatus and image reading method
JP2005167094A (en) * 2003-12-04 2005-06-23 Matsushita Electric Ind Co Ltd Circuit board and manufacturing method therefor
JP2007069789A (en) * 2005-09-08 2007-03-22 Nissan Motor Co Ltd Engine start-controlling device for hybrid vehicle
JP2008131036A (en) * 2006-11-21 2008-06-05 Samsung Electro-Mechanics Co Ltd Printed circuit board and method of manufacturing the same
JP2009130203A (en) * 2007-11-26 2009-06-11 Sharp Corp Double-sided wiring board, method of manufacturing double-sided wiring board, and mounting double-sided wiring board
JP2009141305A (en) * 2007-12-03 2009-06-25 Samsung Electro Mech Co Ltd Printed circuit board and method of manufacturing the same
WO2009081853A1 (en) * 2007-12-25 2009-07-02 Murata Manufacturing Co., Ltd. Method for manufacturing multilayer wiring board
JP2009188146A (en) * 2008-02-06 2009-08-20 Murata Mfg Co Ltd Method for manufacturing wiring board
JP2009289900A (en) * 2008-05-28 2009-12-10 Kyocera Corp Wiring substrate, its method for manufacturing, and electronic device using it

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1093242A (en) * 1996-09-18 1998-04-10 Toshiba Corp Printed wiring board
JPH10303561A (en) * 1997-04-30 1998-11-13 Hitachi Chem Co Ltd Multi-layer wiring board and its manufacture
JPH11251740A (en) * 1998-02-27 1999-09-17 Fuji Xerox Co Ltd Printed board and manufacture thereof
JP2002026520A (en) * 2000-07-06 2002-01-25 Matsushita Electric Ind Co Ltd Multilayer interconnection board and its manufacturing method
JP2005101935A (en) * 2003-09-25 2005-04-14 Canon Inc Image reading apparatus and image reading method
JP2005167094A (en) * 2003-12-04 2005-06-23 Matsushita Electric Ind Co Ltd Circuit board and manufacturing method therefor
JP2007069789A (en) * 2005-09-08 2007-03-22 Nissan Motor Co Ltd Engine start-controlling device for hybrid vehicle
JP2008131036A (en) * 2006-11-21 2008-06-05 Samsung Electro-Mechanics Co Ltd Printed circuit board and method of manufacturing the same
JP2009130203A (en) * 2007-11-26 2009-06-11 Sharp Corp Double-sided wiring board, method of manufacturing double-sided wiring board, and mounting double-sided wiring board
JP2009141305A (en) * 2007-12-03 2009-06-25 Samsung Electro Mech Co Ltd Printed circuit board and method of manufacturing the same
WO2009081853A1 (en) * 2007-12-25 2009-07-02 Murata Manufacturing Co., Ltd. Method for manufacturing multilayer wiring board
JP2009188146A (en) * 2008-02-06 2009-08-20 Murata Mfg Co Ltd Method for manufacturing wiring board
JP2009289900A (en) * 2008-05-28 2009-12-10 Kyocera Corp Wiring substrate, its method for manufacturing, and electronic device using it

Also Published As

Publication number Publication date
JP5789872B2 (en) 2015-10-07

Similar Documents

Publication Publication Date Title
JP6158676B2 (en) WIRING BOARD, SEMICONDUCTOR DEVICE, AND WIRING BOARD MANUFACTURING METHOD
JP6462480B2 (en) Wiring board and method of manufacturing wiring board
JP5389770B2 (en) Printed circuit board with built-in electronic element and manufacturing method thereof
JP5547615B2 (en) WIRING BOARD, SEMICONDUCTOR DEVICE, AND WIRING BOARD MANUFACTURING METHOD
JP5795196B2 (en) Semiconductor package
CN105228341A (en) Printed circuit board (PCB), base plate for packaging and manufacture method thereof
JP2016207958A (en) Wiring board and manufacturing method for wiring board
JP2015115558A (en) Semiconductor device
JP6226167B2 (en) Multilayer wiring board
US9305895B2 (en) Substrates having ball lands, semiconductor packages including the same, and methods of fabricating semiconductor packages including the same
JP6550260B2 (en) Wiring board and method of manufacturing wiring board
JP2009141169A (en) Semiconductor device
JP2017152536A (en) Printed wiring board and manufacturing method thereof
JP2017034059A (en) Printed wiring board, semiconductor package and manufacturing method for printed wiring board
TW201519714A (en) Printed circuit board and method of manufacturing the same
JP2017084997A (en) Printed wiring board and method of manufacturing the same
US9265147B2 (en) Multi-layer wiring board
JP2011129729A (en) Wiring board and semiconductor device
TWI506758B (en) Package on package structure and method for manufacturing same
JP2009135147A (en) Connection structure of wiring board and electronic element, and electronic device
JP4934444B2 (en) Semiconductor device and manufacturing method thereof
KR20220046134A (en) Semiconductor package
JP2010232616A (en) Semiconductor device, and wiring board
JP2007214568A (en) Circuit board structure
JP2012174791A (en) Wiring board, manufacturing method of wiring board, and semiconductor device

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140604

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20140612

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20140627

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150326

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150612

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20150713

R150 Certificate of patent or registration of utility model

Ref document number: 5789872

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250