JP2014086477A - Semiconductor element manufacturing method - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
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Abstract
Description
本発明は、半導体素子の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor element.
従来、ダイシングによって切り出す前のウエハレベルで半導体素子を製造することが行われている。近年では、素子の小型化、高密度化等の観点から、複数の半導体素子が形成された半導体ウエハにおいて、能動面（素子が形成されている側の面）とその反対側の面（以後、「裏面」と称することもある）とを繋ぐ貫通導電路を形成し、該裏面に半田バンプを形成することが提案されている（例えば、特許文献１）。 Conventionally, a semiconductor element is manufactured at a wafer level before being cut out by dicing. In recent years, from the viewpoint of miniaturization, high density, etc., in a semiconductor wafer in which a plurality of semiconductor elements are formed, the active surface (the surface on which the element is formed) and the opposite surface (hereinafter referred to as the element) It has been proposed to form a through-conduction path that connects to a “back surface” and to form solder bumps on the back surface (for example, Patent Document 1).
上記貫通導電路を有する半導体素子の製造においては、半導体ウエハを薄く研削することによって貫通導電路の形成を容易にすることができる。しかしながら、半導体ウエハを薄くすると、強度が低下するので、その後の工程における取扱いが困難となり、生産効率の低下につながる場合がある。よって、本発明は、貫通導電路を有する半導体素子を優れた生産効率で製造することができる方法を提供することを目的とする。 In the manufacture of a semiconductor element having the above-described through-conductive path, the through-conductive path can be easily formed by grinding the semiconductor wafer thinly. However, when the semiconductor wafer is thinned, the strength is lowered, so that it is difficult to handle in subsequent processes, which may lead to a reduction in production efficiency. Therefore, an object of this invention is to provide the method which can manufacture the semiconductor element which has a penetration conductive path with the outstanding production efficiency.
本発明の製造方法は、
［工程Ａ］複数の半導体素子が形成された能動面と、該能動面と反対側の面に形成された所定のパターンの導電層と、該能動面とその反対側の面とを繋ぐ貫通導電路と、を有する半導体ウエハを準備すること、
［工程Ｂ］該導電層上に半田バンプを形成すること、および
［工程Ｃ］該半導体ウエハをダイシングすることを含み、
該［工程Ａ］が、複数の半導体素子が形成された能動面を有する半導体ウエハの該能動面側に保護テープを貼付した状態で、該能動面と反対側の面を研削することを含み、
該研削から[工程Ｃ]のダイシングまでを該保護テープを貼付したままで行う。
好ましい実施形態においては、上記［工程Ａ］が、
［工程ａ−１］複数の半導体素子が形成された能動面を有する半導体ウエハの該能動面側に保護テープを貼付した状態で、該能動面と反対側の面を研削すること、
［工程ａ−２］該半導体ウエハに能動面とその反対側の面とを繋ぐ貫通孔を形成すること、および
［工程ａ−３］該貫通孔内に貫通導電路を形成するとともに、該能動面と反対側の面に所定のパターンの導電層を形成すること、を含む。
好ましい実施形態においては、上記［工程Ａ］が、
［工程ａ’−１］複数の半導体素子が形成された能動面と該能動面側から厚み方向の途中まで形成された複数の導電路とを有する半導体ウエハの該能動面側に保護テープを貼付した状態で、該能動面と反対側の面を研削して、該反対側の面に該導電路を露出させること、および
［工程ａ’−２］該能動面と反対側の面に所定のパターンの導電層を形成すること、を含む。
好ましい実施形態においては、上記半導体素子が、固体撮像素子である。
The production method of the present invention comprises:
[Step A] Penetration conduction connecting the active surface on which a plurality of semiconductor elements are formed, a conductive layer of a predetermined pattern formed on the surface opposite to the active surface, and the active surface and the surface on the opposite side A semiconductor wafer having a path,
[Step B] forming solder bumps on the conductive layer, and [Step C] dicing the semiconductor wafer;
The [Step A] includes grinding a surface opposite to the active surface with a protective tape applied to the active surface side of a semiconductor wafer having an active surface on which a plurality of semiconductor elements are formed,
The process from the grinding to the dicing in [Step C] is performed with the protective tape applied.
In a preferred embodiment, the above [Step A] is
[Step a-1] Grinding a surface opposite to the active surface in a state where a protective tape is applied to the active surface of a semiconductor wafer having an active surface on which a plurality of semiconductor elements are formed,
[Step a-2] Forming a through hole connecting the active surface and the opposite surface to the semiconductor wafer, and [Step a-3] forming a through conductive path in the through hole and Forming a conductive layer having a predetermined pattern on a surface opposite to the surface.
In a preferred embodiment, the above [Step A] is
[Step a′-1] Affixing a protective tape on the active surface side of a semiconductor wafer having an active surface on which a plurality of semiconductor elements are formed and a plurality of conductive paths formed from the active surface side to the middle in the thickness direction In this state, the surface opposite to the active surface is ground to expose the conductive path on the opposite surface, and [Step a′-2] a predetermined surface is provided on the surface opposite to the active surface. Forming a conductive layer of a pattern.
In a preferred embodiment, the semiconductor element is a solid-state image sensor.
従来の製造方法によれば、半導体ウエハの支持および／または能動面の保護を目的として、裏面研削、貫通孔の形成、導電層の形成、ダイシング等の工程毎に異なる粘着テープを用いており、その都度貼り替える必要があった。これに対し、本発明においては、半導体ウエハの能動面側に同じ保護テープを貼付したままの状態で、裏面研削からダイシングまで一貫して行うので、生産効率を向上させることができる。 According to the conventional manufacturing method, for the purpose of supporting the semiconductor wafer and / or protecting the active surface, different adhesive tapes are used for each process such as back grinding, formation of a through hole, formation of a conductive layer, dicing, It was necessary to reapply each time. On the other hand, in the present invention, since the same protective tape is stuck on the active surface side of the semiconductor wafer, it is performed consistently from back grinding to dicing, so that the production efficiency can be improved.
本発明の半導体素子の製造方法は、
［工程Ａ］複数の半導体素子が形成された能動面と、該能動面と反対側の面に形成された所定のパターンの導電層と、該能動面とその反対側の面とを繋ぐ貫通導電路と、を有する半導体ウエハを準備すること、
［工程Ｂ］該導電層上に半田バンプを形成すること、および
［工程Ｃ］該半導体ウエハをダイシングすること、を含む。該製造方法において、［工程Ａ］は、複数の半導体素子が形成された能動面を有する半導体ウエハの該能動面側に保護テープを貼付した状態で、該能動面と反対側の面を研削することを含み、該研削から[工程Ｃ]のダイシングまでを該保護テープを貼付したままで行う。なお、本明細書において、半導体ウエハとは、表面に複数の半導体素子が形成された状態の、すなわち、ダイシングによって切り出される前のウエハを意味する。
The method for manufacturing a semiconductor device of the present invention includes:
[Step A] Penetration conduction connecting the active surface on which a plurality of semiconductor elements are formed, a conductive layer of a predetermined pattern formed on the surface opposite to the active surface, and the active surface and the surface on the opposite side A semiconductor wafer having a path,
[Step B] forming solder bumps on the conductive layer, and [Step C] dicing the semiconductor wafer. In the manufacturing method, in [Step A], a surface opposite to the active surface is ground with a protective tape attached to the active surface side of a semiconductor wafer having an active surface on which a plurality of semiconductor elements are formed. The process from the grinding to the dicing of [Step C] is carried out with the protective tape being applied. In the present specification, the semiconductor wafer means a wafer in which a plurality of semiconductor elements are formed on the surface, that is, before being cut out by dicing.
上記のとおり、本発明の半導体素子の製造方法においては、裏面研削時に半導体ウエハの能動面側に貼付した保護テープを剥離することなく、貼付したままの状態でダイシングまで行う。このように一枚の保護テープで裏面研削からダイシングまで行うことにより、貫通導電路の形成に起因して、薄く、取扱いに注意を要する半導体ウエハに対して工程毎に保護テープを貼り替える必要がないので、生産効率を著しく向上させることができる。 As described above, in the method for manufacturing a semiconductor element of the present invention, dicing is performed in a state of being attached without peeling off the protective tape attached to the active surface side of the semiconductor wafer during back grinding. By performing the process from backside grinding to dicing with a single protective tape in this way, it is necessary to reattach the protective tape for each process on a thin semiconductor wafer that requires careful handling due to the formation of through-conductive paths. Therefore, production efficiency can be remarkably improved.
上記保護テープは、裏面研削中に半導体ウエハが剥離しない程度、および、ダイシング中にチップが剥離したり、欠けたりしない程度の粘着力を有すること、貫通導電路や導電層形成時に用いる薬液（レジストの現像液、エッチング液等）やメッキ液に対する耐性を有すること、ならびに、半田バンプ形成時等の高温環境における耐熱性を有することが好ましい。 The protective tape has an adhesive strength that does not peel the semiconductor wafer during backside grinding and does not peel or chip during dicing. It is preferable to have resistance to a developing solution, an etching solution, etc.) and a plating solution, and to have heat resistance in a high temperature environment such as when a solder bump is formed.
上記保護テープは、代表的には、基材層とその片面上に積層された粘着剤層とを有する。該保護テープは、［工程Ｂ］の半田バンプ形成時に高温環境下（例えば、約３００℃）に曝される場合がある。したがって、保護テープの基材層は、このような高温条件に対して耐熱性を満足する材料から形成されることが好ましい。 The protective tape typically has a base material layer and an adhesive layer laminated on one surface thereof. The protective tape may be exposed to a high temperature environment (for example, about 300 ° C.) when forming the solder bump in [Step B]. Therefore, the base material layer of the protective tape is preferably formed from a material that satisfies heat resistance with respect to such a high temperature condition.
上記基材層の形成材料としては、例えば、ポリエチレンテレフタレート（ＰＥＴ）フィルム、ポリエチレンナフタレート（ＰＥＮ）フィルム、ポリエチレンサルフォン（ＰＥＳ）フィルム、ポリエーテルイミド（ＰＥＩ）フィルム、ポリサルフォン（ＰＳＦ）フィルム、ポリフェニレンサルファイド（ＰＰＳ）フィルム、ポリエーテルエーテルケトン（ＰＥＥＫ）フィルム、ポリアリレート（ＰＡＲ）フィルム、アラミドフィルム、液晶ポリマー（ＬＣＰ）フィルム等の樹脂フィルムが挙げられる。 Examples of the material for forming the base material layer include a polyethylene terephthalate (PET) film, a polyethylene naphthalate (PEN) film, a polyethylene sulfone (PES) film, a polyetherimide (PEI) film, a polysulfone (PSF) film, and a polyphenylene. Examples of the resin film include a sulfide (PPS) film, a polyether ether ketone (PEEK) film, a polyarylate (PAR) film, an aramid film, and a liquid crystal polymer (LCP) film.
上記基材層の厚みは、折れや裂けを防止する観点から、好ましくは５μｍ以上であり、好適なハンドリング性の観点から、より好ましくは１０μｍ〜１００μｍである。 The thickness of the base material layer is preferably 5 μm or more from the viewpoint of preventing breakage and tearing, and more preferably 10 μm to 100 μm from the viewpoint of suitable handling properties.
上記粘着剤層としては、耐熱性を有し、かつ、エッチング時に使用する薬液（レジストの現像液、エッチング液等）やメッキ液に対する耐性を有する粘着剤により形成されるものであれば特に制限されない。このような粘着剤としては、例えば、ゴム系粘着剤、アクリル系粘着剤、シリコーン系粘着剤等が挙げられる。 The pressure-sensitive adhesive layer is not particularly limited as long as it has heat resistance and is formed of a pressure-sensitive adhesive having resistance to chemicals (resist developer, etching solution, etc.) and plating solution used during etching. . Examples of such adhesives include rubber adhesives, acrylic adhesives, and silicone adhesives.
上記アクリル系粘着剤としては、粘着性を与える低Ｔｇのモノマーを主モノマーとし、接着性や凝集力を与える高Ｔｇのコモノマー、架橋や接着性改良のための官能基含有モノマー等のモノエチレン性不飽和モノマー等を共重合させて得られるアクリル系ポリマーが用いられる。主モノマーとしては、例えば、メチル（メタ）アクリレート、エチル（メタ）アクリレート、ブチル（メタ）アクリレート、イソアミル（メタ）アクリレート、ｎ−へキシル（メタ）アクリレート、２−エチルヘキシル（メタ）アクリレート、イソオクチル（メタ）アグノレート、イソノニル（メタ）アクリレート、デシシル（メタ）アクリレート、ドデシル（メタ）アクリレート等のアルキル（メタ）アクリレートが挙げられる。ここで、主モノマーとは、ポリマーを構成する全モノマーの総重量に基づき、５０重量％以上含まれるモノマーを意味する。 The acrylic pressure-sensitive adhesive is mainly composed of a low-Tg monomer that gives tackiness, a high-Tg comonomer that gives adhesiveness and cohesion, and a monoethylenic property such as a functional group-containing monomer for crosslinking and adhesion improvement. An acrylic polymer obtained by copolymerizing an unsaturated monomer or the like is used. Examples of the main monomer include methyl (meth) acrylate, ethyl (meth) acrylate, butyl (meth) acrylate, isoamyl (meth) acrylate, n-hexyl (meth) acrylate, 2-ethylhexyl (meth) acrylate, and isooctyl ( Examples include alkyl (meth) acrylates such as (meth) agnolate, isononyl (meth) acrylate, decyl (meth) acrylate, and dodecyl (meth) acrylate. Here, the main monomer means a monomer contained in an amount of 50% by weight or more based on the total weight of all monomers constituting the polymer.
上記コモノマーとしては、例えば、酢酸ビニル、プロピオン酸ビニル、ビニルエーテル、スチレン、アクリロニトリル、メタクリロニトリル等のビニル基含有化合物が挙げられる。官能基含有モノマーとしては、例えば、アクリル酸、メタクリル酸、クロトン酸、マレイン酸、フマル酸、イタコン酸等のカルボキシル基含有モノマー、２−ヒドロキシエチル（メタ）アクリレート、２−ヒドロキシプロピル（メタ）アクリレート、４−ヒドロキシブチル（メタ）アクリレート、Ｎ−メチロールアクリルアミド、アリルアルコール等のヒドロキシル基含有モノマー、ジメチルアミノエチル（メタ）アクリレート、ジエチルアミノエチル（メタ）アクリレート、ジメチルアミノプロピル（メタ）アクリレート等の三級アミノ基含有モノマー、アクリルアミド、メタクリルアミド等のアミド基含有モノマー、Ｎ−メチル（メタ）アクリルアミド、Ｎ−エチル（メタ）アクリルアミド、Ｎ−メトキシメチル（メタ）アクリルアミド、Ｎ−エトキシメチル（メタ）アクリルアミド、Ｎ−ｔ−ブチルアクリルアミド、Ｎ−オクチルアクリルアミド等のＮ−置換アミド基含有モノマー、グリシジルメタクリレート等のエポキシ基含有モノマーが挙げられる。 Examples of the comonomer include vinyl group-containing compounds such as vinyl acetate, vinyl propionate, vinyl ether, styrene, acrylonitrile, and methacrylonitrile. Examples of the functional group-containing monomer include carboxyl group-containing monomers such as acrylic acid, methacrylic acid, crotonic acid, maleic acid, fumaric acid, and itaconic acid, 2-hydroxyethyl (meth) acrylate, and 2-hydroxypropyl (meth) acrylate. , Tertiary groups such as 4-hydroxybutyl (meth) acrylate, N-methylolacrylamide, hydroxyl group-containing monomers such as allyl alcohol, dimethylaminoethyl (meth) acrylate, diethylaminoethyl (meth) acrylate, dimethylaminopropyl (meth) acrylate, etc. Amino group-containing monomers, amide group-containing monomers such as acrylamide and methacrylamide, N-methyl (meth) acrylamide, N-ethyl (meth) acrylamide, N-methoxymethyl (meth) acrylamide N- ethoxymethyl (meth) acrylamide, N-t-butyl acrylamide, N- substituted amide group-containing monomers such as N- octyl acrylamide, an epoxy group-containing monomers such as glycidyl methacrylate.
上記アクリル系粘着剤は、任意の適切な架橋剤を含有し得る。例えば、イソシアネート系架橋剤、エポキシ系架橋剤、アジリジン系化合物、キレート系架橋剤等が挙げられる。架橋剤の使用量は、例えば上記アクリル系ポリマー１００重量部に対して、０．１重量部〜１５重量部が好ましく、１．０重量部〜１０重量部がより好ましい。このようなアクリル系粘着剤は適切な粘着力や貯蔵弾性率を得やすいことから、本発明の製造方法に好適に用いられ得る。 The acrylic pressure-sensitive adhesive can contain any appropriate crosslinking agent. For example, an isocyanate type crosslinking agent, an epoxy type crosslinking agent, an aziridine type compound, a chelate type crosslinking agent and the like can be mentioned. The amount of the crosslinking agent used is preferably 0.1 to 15 parts by weight, and more preferably 1.0 to 10 parts by weight with respect to 100 parts by weight of the acrylic polymer. Such an acrylic pressure-sensitive adhesive can be suitably used in the production method of the present invention because it is easy to obtain appropriate adhesive strength and storage elastic modulus.
上記粘着剤層は、必要に応じて、例えば、紫外線吸収剤、粘着付与剤、軟化剤（可塑剤）、充填剤、老化防止剤、粘着付与剤、顔料、染料、シランカップリング剤、離型剤等の各種添加剤を含有することができる。 The above-mentioned pressure-sensitive adhesive layer is, for example, an ultraviolet absorber, a tackifier, a softener (plasticizer), a filler, an anti-aging agent, a tackifier, a pigment, a dye, a silane coupling agent, and a release agent. Various additives such as an agent can be contained.
上記粘着剤層の厚みは、特に限定されるものではないが、好ましくは１μｍ〜５０μｍ程度、より好ましくは５μｍ〜２５μｍである。 Although the thickness of the said adhesive layer is not specifically limited, Preferably it is about 1 micrometer-50 micrometers, More preferably, it is 5 micrometers-25 micrometers.
上記保護テープの粘着力としては、測定温度２３℃、引張速度０．３ｍ／分、剥離角度１８０度の条件下におけるステンレス鋼板（ＳＵＳ板）に対する粘着力が、好ましくは０．０１Ｎ／２０ｍｍ〜１０．０Ｎ／２０ｍｍであり、より好ましくは０．１Ｎ／２０ｍｍ〜８．０Ｎ／２０ｍｍである。このような粘着力であれば、裏面研削やダイシングを好適に行うことができる。該粘着力の測定は、例えば、ＪＩＳ−Ｚ−０２３７（２０００）に準拠して行うことができる。 As the adhesive strength of the protective tape, the adhesive strength to a stainless steel plate (SUS plate) under the conditions of a measurement temperature of 23 ° C., a tensile speed of 0.3 m / min, and a peeling angle of 180 degrees is preferably 0.01 N / 20 mm to 10 mm. 0.0 N / 20 mm, more preferably 0.1 N / 20 mm to 8.0 N / 20 mm. With such an adhesive force, back surface grinding and dicing can be suitably performed. The measurement of this adhesive force can be performed based on JIS-Z-0237 (2000), for example.
また、上記保護テープのステンレス板に貼り合わせた状態で２００℃にて１時間加熱した後に、ＪＩＳ−Ｚ−０２３７に準じて測定される粘着力は、好ましくは０．００１Ｎ／２０ｍｍ〜８．０Ｎ／２０ｍｍであり、より好ましくは０．００５Ｎ／２０ｍｍ〜５．０Ｎ／２０ｍｍである。このような粘着力であれば、半田バンプの形成等を好適に行うことができる。 Moreover, the adhesive force measured according to JIS-Z-0237 after heating for 1 hour at 200 ° C. in a state of being bonded to the stainless steel plate of the protective tape is preferably 0.001 N / 20 mm to 8.0 N. / 20 mm, more preferably 0.005 N / 20 mm to 5.0 N / 20 mm. With such adhesive strength, solder bumps can be suitably formed.
上記保護テープは、例えば、粘着剤および必要に応じて溶媒やその他の添加剤を含む混合物を、基材層上に塗布する方法、適当なセパレータ（剥離紙等）上に該混合物を塗布して粘着剤層を形成し、これを基材層上に転写（移着）する方法等により得ることができる。 For example, the protective tape may be formed by applying a mixture containing a pressure-sensitive adhesive and, if necessary, a solvent and other additives onto the base material layer, and applying the mixture onto an appropriate separator (such as a release paper). It can be obtained by a method of forming an adhesive layer and transferring (transferring) it onto the base material layer.
本発明によって製造される半導体素子としては、特に制限はなく、任意の適切な半導体素子であり得る。好ましくはＣＭＯＳ、ＣＣＤ等の固体撮像素子である。固体撮像素子の場合、通常、半導体ウエハの能動面側にガラス基板を介して保護テープを貼付するので、能動面に直接保護テープを貼付する場合に比べてウエハの強度がより一層補強され得る。その結果、取扱い性がより一層向上して、本発明の効果がより好適に得られ得る。 There is no restriction | limiting in particular as a semiconductor element manufactured by this invention, It can be arbitrary appropriate semiconductor elements. A solid-state imaging device such as a CMOS or CCD is preferable. In the case of a solid-state imaging device, since the protective tape is usually attached to the active surface side of the semiconductor wafer via a glass substrate, the strength of the wafer can be further reinforced compared to the case where the protective tape is directly attached to the active surface. As a result, the handleability is further improved, and the effects of the present invention can be obtained more suitably.
本発明の製造方法の１つの好ましい実施形態において、［工程Ａ］は、
［工程ａ−１］複数の半導体素子が形成された能動面を有する半導体ウエハの該能動面側に保護テープを貼付した状態で、該能動面と反対側の面を研削すること、
［工程ａ−２］該半導体ウエハに能動面とその反対側の面とを繋ぐ貫通孔を形成すること、および
［工程ａ−３］該貫通孔内に貫通導電路を形成するとともに、該能動面と反対側の面に所定のパターンの導電層を形成すること、を含む。以下、［工程Ａ］が［工程ａ−１］〜［工程ａ−３］を含む半導体素子の製造方法（以下、「第１の半導体素子の製造方法」と称する場合がある）について、図１を参照しながら説明する。
In one preferred embodiment of the production method of the present invention, [Step A] comprises:
[Step a-1] Grinding a surface opposite to the active surface in a state where a protective tape is applied to the active surface of a semiconductor wafer having an active surface on which a plurality of semiconductor elements are formed,
[Step a-2] Forming a through hole connecting the active surface and the opposite surface to the semiconductor wafer, and [Step a-3] forming a through conductive path in the through hole and Forming a conductive layer having a predetermined pattern on a surface opposite to the surface. Hereinafter, a method for manufacturing a semiconductor device in which [Step A] includes [Step a-1] to [Step a-3] (hereinafter may be referred to as “first method for manufacturing a semiconductor device”) is described with reference to FIG. Will be described with reference to FIG.
［工程ａ−１］
まず、複数の半導体素子１０が形成された能動面を有する半導体ウエハ２０の該能動面側に保護テープ３０を貼付し（図１（ａ））、その状態で裏面を研削する（図１（ｂ））。具体的には、予め半導体ウエハ２０の能動面側にスペーサー５０を介してガラス基板４０を貼り合わせておき、該ガラス基板４０の上に、保護テープ３０をその粘着剤層面がガラス基板４０側となるように重ね合わせ、押圧しながら貼付する。保護テープの貼付方法としては、例えば
（ｉ）テーブル上に能動面側にガラス基板を貼り合わせた半導体ウエハを該ガラス基板が上になるように載置し、その上に保護テープを粘着剤層がウエハ側になるように重ね、圧着ロール等の押圧手段により、押圧しながら貼付すること、
（ｉｉ）加圧可能な容器（例えば、オートクレーブ等）中で、半導体ウエハと保護テープとを上述したように重ね、容器内を加圧することで半導体ウエハに貼付すること（この際、押圧手段により押圧しながら貼り付けてもよい）、または
（ｉｉｉ）真空チャンバー内で、上記と同様に貼付することが挙げられる。これらの方法で貼付する際、３０℃〜１５０℃程度の加熱を行ってもよい。
[Step a-1]
First, a protective tape 30 is attached to the active surface side of the semiconductor wafer 20 having an active surface on which a plurality of semiconductor elements 10 are formed (FIG. 1A), and the back surface is ground in this state (FIG. 1B). )). Specifically, the glass substrate 40 is bonded to the active surface side of the semiconductor wafer 20 via the spacer 50 in advance, and the protective tape 30 is attached to the glass substrate 40 side on the protective tape 30 on the glass substrate 40. Overlap and paste while pressing. As a method for applying the protective tape, for example, (i) a semiconductor wafer in which a glass substrate is bonded to the active surface side is placed on a table so that the glass substrate is on top, and the protective tape is placed on the adhesive layer. Are stacked so as to be on the wafer side, and applied while pressing with a pressing means such as a pressure roll,
(Ii) In a pressurizable container (for example, an autoclave), the semiconductor wafer and the protective tape are stacked as described above, and the inside of the container is applied to the semiconductor wafer by pressurization (at this time, by pressing means) (Iii) It may be applied in the same manner as described above in a vacuum chamber. When pasting by these methods, you may heat about 30 to 150 degreeC.
その後、保護テープが貼付された状態で、半導体ウエハの裏面を研削する。研削量は目的等に応じて適切に設定され得る。研削後の半導体ウエハの厚みは、例えば、２５μｍ〜２５０μｍであり得る。 Then, the back surface of the semiconductor wafer is ground with the protective tape attached. The grinding amount can be appropriately set according to the purpose and the like. The thickness of the semiconductor wafer after grinding can be, for example, 25 μm to 250 μm.
なお、図示例では、ガラス基板４０を介して保護テープ３０を貼付しているが、これとは異なり、半導体ウエハの能動面に直接保護テープを貼付してもよい。 In the illustrated example, the protective tape 30 is affixed via the glass substrate 40. However, unlike this, the protective tape may be affixed directly to the active surface of the semiconductor wafer.
［工程ａ−２］
次いで、図１（ｃ）に示すとおり、裏面研削後の半導体ウエハ２０に能動面と裏面とを繋ぐ貫通孔６０を形成する。貫通孔の形成は、例えば、半導体ウエハの裏面に貫通孔形成部位に対応する開口部を有するレジスト膜を形成し、該開口部から露出した半導体ウエハを薬液を用いてエッチングまたはＲＩＥ等のドライエッチングし、次いで、該レジスト膜を裏面から除去することによって行われ得る。
[Step a-2]
Next, as illustrated in FIG. 1C, a through hole 60 that connects the active surface and the back surface is formed in the semiconductor wafer 20 after the back surface grinding. For example, the through hole is formed by forming a resist film having an opening corresponding to the through hole forming portion on the back surface of the semiconductor wafer and etching the semiconductor wafer exposed from the opening using a chemical solution or dry etching such as RIE. Then, the resist film can be removed from the back surface.
貫通孔は、例えば、半導体素子の電極パッド（図示せず）に対応する位置に形成され、該電極パッドに接続し得る。 The through hole is formed at a position corresponding to an electrode pad (not shown) of the semiconductor element, for example, and can be connected to the electrode pad.
［工程ａ−３］
次いで、図１（ｄ）に示すとおり、上記貫通孔６０内に貫通導電路７０を形成するとともに、半導体ウエハ２０の裏面に所定のパターンの導電層８０を形成する。貫通導電路および導電層の形成材料としては、一般的に銅が用いられる。貫通導電路および導電層の形成は、例えば、電解めっき等によって行われ得る。
[Step a-3]
Next, as shown in FIG. 1D, a through conductive path 70 is formed in the through hole 60 and a conductive layer 80 having a predetermined pattern is formed on the back surface of the semiconductor wafer 20. Generally, copper is used as a material for forming the through conductive path and the conductive layer. Formation of the through conductive path and the conductive layer can be performed, for example, by electrolytic plating.
貫通導電路は、貫通孔の内壁に沿って形成されてもよく、また、貫通孔内を充填するように形成されてもよい。また、上記所定のパターンの導電層の少なくとも一部は、貫通導電路と導通するように形成される。なお、本明細書において、所定のパターンの導電層は、半田バンプ搭載用端子、再配線パターン等を含む。 The through conductive path may be formed along the inner wall of the through hole, or may be formed to fill the through hole. Further, at least a part of the conductive layer having the predetermined pattern is formed so as to be electrically connected to the through conductive path. In the present specification, the conductive layer having a predetermined pattern includes a solder bump mounting terminal, a rewiring pattern, and the like.
［工程Ｂ］
次いで、図１（ｅ）に示すとおり、上記所定のパターンの導電層８０の半田バンプ搭載用端子上に半田バンプ９０を形成する。半田バンプの形成は、任意の適切な方法で行われ得る。例えば、半田ペーストを用いた印刷法、半田ボールの直接搭載法、電解めっき法等が適用され得る。
[Step B]
Next, as shown in FIG. 1E, solder bumps 90 are formed on the solder bump mounting terminals of the conductive layer 80 having the predetermined pattern. The formation of the solder bumps can be performed by any appropriate method. For example, a printing method using a solder paste, a direct mounting method of solder balls, an electrolytic plating method, or the like can be applied.
半田バンプの配列は、実装されるプリント基板等の接合パッドの位置に応じて適切に設定され得る。半田バンプは、半導体素子の外部接続端子として機能するものであり、例えば錫−鉛系金属材料、錫−銀系金属材料、錫−銀−銅系金属材料、錫−亜鉛系金属材料、錫−亜鉛−ビスマス系金属材料等から形成され得る。半田バンプは、例えば、上記導電層（半田バンプ搭載用端子および再配線パターン）を介して半導体素子の電極パッドと電気的に接続されている。 The arrangement of the solder bumps can be appropriately set according to the position of a bonding pad such as a printed board to be mounted. The solder bump functions as an external connection terminal of the semiconductor element. For example, tin-lead metal material, tin-silver metal material, tin-silver-copper metal material, tin-zinc metal material, tin- It can be formed from a zinc-bismuth metal material or the like. The solder bump is electrically connected to the electrode pad of the semiconductor element through the conductive layer (solder bump mounting terminal and rewiring pattern), for example.
［工程Ｃ］
次いで、図１（ｆ）に示すとおり、上記半導体ウエハ２０をダイシングする（図中の点線はダイシングラインを示す）。これにより、半導体素子毎に個片化された半導体チップが得られる。ダイシングは、例えば、任意の適切なダイシング装置を用いて、半導体ウエハの裏面側から常法に従って行われ得る。本発明では、例えば、保護テープまで切込みを行うフルカットと呼ばれる切断方式等を採用できる。
[Step C]
Next, as shown in FIG. 1F, the semiconductor wafer 20 is diced (a dotted line in the figure indicates a dicing line). Thereby, the semiconductor chip separated into pieces for each semiconductor element is obtained. Dicing can be performed in accordance with a conventional method from the back side of the semiconductor wafer, for example, using any appropriate dicing apparatus. In the present invention, for example, a cutting method called full cut for cutting up to the protective tape can be adopted.
本発明の製造方法の別の好ましい実施形態において、［工程Ａ］は、
［工程ａ’−１］複数の半導体素子が形成された能動面と該能動面側から厚み方向の途中まで形成された複数の導電路とを有する半導体ウエハの該能動面側に保護テープを貼付した状態で、該能動面と反対側の面を研削して、該反対側の面に該導電路を露出させること、および
［工程ａ’−２］該能動面と反対側の面に所定のパターンの導電層を形成すること、を含む。以下、［工程Ａ］が［工程ａ’−１］〜［工程ａ’−２］を含む半導体素子の製造方法（以下、「第２の半導体素子の製造方法」と称する場合がある）について、図２を参照しながら説明する。
In another preferred embodiment of the production method of the present invention, [Step A] comprises:
[Step a′-1] Affixing a protective tape on the active surface side of a semiconductor wafer having an active surface on which a plurality of semiconductor elements are formed and a plurality of conductive paths formed from the active surface side to the middle in the thickness direction In this state, the surface opposite to the active surface is ground to expose the conductive path on the opposite surface, and [Step a′-2] a predetermined surface is provided on the surface opposite to the active surface. Forming a conductive layer of a pattern. Hereinafter, a method for manufacturing a semiconductor element in which [Step A] includes [Step a′-1] to [Step a′-2] (hereinafter may be referred to as “second semiconductor element manufacturing method”). This will be described with reference to FIG.
［工程ａ’−１］
まず、複数の半導体素子１０が形成された能動面と該能動面側から厚み方向の途中まで形成された複数の導電路７０’とを有する半導体ウエハ２０を準備する。該半導体ウエハ２０の能動面側に保護テープ３０を貼付し（図２（ａ））、その状態で裏面を研削して、該裏面に該導電路を露出させる。これにより、貫通導電路７０を有する半導体ウエハ２０が得られる（図２（ｂ））。保護テープの貼付方法としては、[工程ａ−１]で記載した方法と同様の方法が適用される。なお、図示例では、ガラス基板４０を介して保護テープ３０を貼付しているが、これとは異なり、半導体ウエハ２０の能動面に直接保護テープ３０を貼付してもよい。
[Step a′-1]
First, a semiconductor wafer 20 having an active surface on which a plurality of semiconductor elements 10 are formed and a plurality of conductive paths 70 ′ formed from the active surface side to the middle in the thickness direction is prepared. A protective tape 30 is attached to the active surface side of the semiconductor wafer 20 (FIG. 2A), and the back surface is ground in this state to expose the conductive path on the back surface. Thereby, the semiconductor wafer 20 having the through conductive path 70 is obtained (FIG. 2B). As a method for applying the protective tape, the same method as that described in [Step a-1] is applied. In the illustrated example, the protective tape 30 is affixed via the glass substrate 40, but unlike this, the protective tape 30 may be affixed directly to the active surface of the semiconductor wafer 20.
上記能動面側から厚み方向の途中まで形成された導電路７０’は、半導体ウエハの能動面に形成された所定の深さの孔の内壁に沿って形成されたものであってもよく、該孔を充填するように形成されたものであってもよい。 The conductive path 70 ′ formed from the active surface side to the middle in the thickness direction may be formed along the inner wall of a hole having a predetermined depth formed in the active surface of the semiconductor wafer. It may be formed so as to fill the hole.
裏面研削後の半導体ウエハの厚みは、目的等に応じて適切に設定され得る。該厚みは、例えば、２５μｍ〜２５０μｍであり得る。 The thickness of the semiconductor wafer after the back surface grinding can be appropriately set according to the purpose or the like. The thickness can be, for example, 25 μm to 250 μm.
［工程ａ’−２］
次いで、図２（ｃ）に示すとおり、裏面研削後の半導体ウエハ２０の裏面に所定のパターンの導電層８０を形成する。導電層の形成材料としては、一般的に銅が用いられる。導電層の形成は、例えば、電解めっき等によって行われ得る。
[Step a′-2]
Next, as shown in FIG. 2C, a conductive layer 80 having a predetermined pattern is formed on the back surface of the semiconductor wafer 20 after the back surface grinding. As a material for forming the conductive layer, copper is generally used. The formation of the conductive layer can be performed by, for example, electrolytic plating.
導電層８０の少なくとも一部は、貫通導電路７０と導通するように形成される。 At least a part of the conductive layer 80 is formed so as to be electrically connected to the through conductive path 70.
図２（ｄ）および（ｅ）はそれぞれ、第２の半導体素子の製造方法における［工程Ｂ］および［工程Ｃ］を説明する概略図であるが、これらの工程は、上記第１の半導体素子の製造方法における［工程Ｂ］および［工程Ｃ］と同様の説明を適用することができるので、その詳細は省略する。 FIGS. 2D and 2E are schematic views for explaining [Step B] and [Step C] in the method for manufacturing the second semiconductor element, respectively. Since the same description as [Step B] and [Step C] in the manufacturing method can be applied, the details thereof are omitted.
上記第１の半導体素子の製造方法および第２の半導体素子の製造方法は、必要に応じて、任意の適切な工程をさらに含み得る。例えば、［工程ａ−３］と［工程Ｂ］との間または［工程ａ’−２］と［工程Ｂ］との間に封止樹脂層形成工程、電磁遮光シールド層形成工程等を含んでもよく、また、［工程Ｃ］の後に、半導体チップを保護テープから剥離および回収するピックアップ工程を含んでもよい。 The manufacturing method of the first semiconductor element and the manufacturing method of the second semiconductor element may further include any appropriate process as necessary. For example, a sealing resin layer forming step, an electromagnetic shielding layer forming step, or the like may be included between [Step a-3] and [Step B] or between [Step a′-2] and [Step B]. In addition, after [Step C], a pickup step of peeling and collecting the semiconductor chip from the protective tape may be included.
以下、実施例により本発明をさらに詳細に説明するが、本発明は該実施例には限定されない。 EXAMPLES Hereinafter, although an Example demonstrates this invention further in detail, this invention is not limited to this Example.
［製造例１］
２５μｍ厚のポリイミドフィルム（東レデュポン製：商品名「カプトン１００Ｈ」）を基材として用いた。一方、ブチルアクリレート１００重量部に対してアクリル酸５重量部を構成モノマーとするアクリル系共重合体を用いて、このポリマー１００重量部に対してエポキシ系架橋剤（三菱ガス化学製：商品名「Ｔｅｔｒａｄ−Ｃ」）を３重量部添加して、アクリル系粘着剤組成物を調製した。このアクリル系粘着剤組成物を基材上に塗布し、１２０℃で３分間、次いで、５０℃で４８時間加熱した。これにより、厚さ１０μｍの粘着剤層を基材上に設けた保護テープ１を作製した。
[Production Example 1]
A polyimide film having a thickness of 25 μm (manufactured by Toray DuPont: trade name “Kapton 100H”) was used as a substrate. On the other hand, using an acrylic copolymer having 5 parts by weight of acrylic acid as a constituent monomer for 100 parts by weight of butyl acrylate, 100 parts by weight of this polymer is an epoxy crosslinking agent (Mitsubishi Gas Chemical Co., Ltd .: trade name “ 3 parts by weight of Tetrad-C ") was added to prepare an acrylic pressure-sensitive adhesive composition. This acrylic pressure-sensitive adhesive composition was applied onto a substrate and heated at 120 ° C. for 3 minutes and then at 50 ° C. for 48 hours. Thereby, the protective tape 1 which provided the 10-micrometer-thick adhesive layer on the base material was produced.
［実施例１］
１００μｍ×１００μｍの半導体素子が２００μｍピッチで格子状に形成された能動面を有する半導体ウエハ（厚み：７５０μｍ）の該能動面側に接着層を介してガラス基板（厚み：３００μｍ）を貼り合わせた。次いで、該半導体ウエハの能動面側にガラス基板を介して上記保護テープ１を貼付し、この状態で、７０μｍの厚みになるまで裏面研削した。
[Example 1]
A glass substrate (thickness: 300 μm) was bonded to the active surface side of a semiconductor wafer (thickness: 750 μm) having an active surface on which 100 μm × 100 μm semiconductor elements were formed in a lattice shape at a pitch of 200 μm via an adhesive layer. Subsequently, the said protective tape 1 was affixed on the active surface side of this semiconductor wafer through the glass substrate, and the back surface grinding was carried out until it became a thickness of 70 micrometers in this state.
能動面側に保護テープ１を貼付したままの該半導体ウエハの裏面に、感光性レジスト材料を用いて貫通孔形成部位に対応する開口部を有するエッチングレジストを形成した。次いで、該開口部から露出したウエハをフッ硝酸でエッチングして、能動面と裏面とを繋ぐ貫通孔（φ３０μｍ）を形成した。その後、レジストを剥離した。 An etching resist having an opening corresponding to the through-hole forming portion was formed on the back surface of the semiconductor wafer with the protective tape 1 attached to the active surface side using a photosensitive resist material. Next, the wafer exposed from the opening was etched with hydrofluoric acid to form a through hole (φ30 μm) connecting the active surface and the back surface. Thereafter, the resist was peeled off.
次いで、能動面側に保護テープ１を貼付したままの状態でエッチングや電解銅めっきを行うことによって、上記貫通孔の内壁に沿って導電路を形成するとともに裏面に再配線パターンおよび半田バンプ搭載用端子を含む導電層を形成した。その後、該半田バンプ搭載用端子と接続するように半田バンプを形成し、半導体ウエハの各半導体素子間を裏面側からダイシングして、半導体チップを得た。 Next, a conductive path is formed along the inner wall of the through hole by performing etching or electrolytic copper plating while the protective tape 1 is still attached to the active surface side, and a rewiring pattern and solder bump are mounted on the back surface. A conductive layer including terminals was formed. Thereafter, solder bumps were formed so as to be connected to the solder bump mounting terminals, and each semiconductor element of the semiconductor wafer was diced from the back side to obtain a semiconductor chip.
［実施例２］
１００μｍ×１００μｍの半導体素子が２００μｍピッチで格子状に形成された能動面と該能動面側表面に半導体素子毎に７０μｍの厚みで形成された複数の導電路（φ３０μｍ）とを有する半導体ウエハ（厚み：７５０μｍ）の該能動面側に接着層を介してガラス基板（厚み：３００μｍ）を貼り合わせた。次いで、該半導体ウエハの能動面側にガラス基板を介して上記保護テープ１を貼付し、この状態で、７０μｍの厚みになるまで裏面研削して、裏面に該導電路を露出させた。
[Example 2]
A semiconductor wafer (thickness) having an active surface in which 100 μm × 100 μm semiconductor elements are formed in a lattice pattern at a pitch of 200 μm and a plurality of conductive paths (φ30 μm) formed on the active surface side surface with a thickness of 70 μm for each semiconductor element. : 750 μm), a glass substrate (thickness: 300 μm) was bonded to the active surface side through an adhesive layer. Next, the protective tape 1 was attached to the active surface side of the semiconductor wafer via a glass substrate, and in this state, the back surface was ground to a thickness of 70 μm to expose the conductive path on the back surface.
次いで、能動面側に保護テープ１を貼付したままの状態でエッチングや電解銅めっきを行うことによって、半導体ウエハの裏面に再配線パターンおよび半田バンプ搭載用端子を含む導電層を形成した。その後、該半田バンプ搭載用端子と接続するように半田バンプを形成し、半導体ウエハの各半導体素子間を裏面側からダイシングして、半導体チップを得た。 Next, etching or electrolytic copper plating was performed while the protective tape 1 was stuck on the active surface side, thereby forming a conductive layer including a rewiring pattern and solder bump mounting terminals on the back surface of the semiconductor wafer. Thereafter, solder bumps were formed so as to be connected to the solder bump mounting terminals, and each semiconductor element of the semiconductor wafer was diced from the back side to obtain a semiconductor chip.
本発明の製造方法は、ＣＭＯＳ、ＣＣＤ等の固体撮像素子の製造において好ましく適用され得る。 The production method of the present invention can be preferably applied to the production of solid-state imaging devices such as CMOS and CCD.
１０ 半導体素子
２０ 半導体ウエハ
３０ 保護テープ
４０ ガラス基板
５０ スペーサー
６０ 貫通孔
７０ 貫通導電路
８０ 導電層
９０ 半田バンプ
DESCRIPTION OF SYMBOLS 10 Semiconductor element 20 Semiconductor wafer 30 Protection tape 40 Glass substrate 50 Spacer 60 Through-hole 70 Through-conductive path 80 Conductive layer 90 Solder bump
Claims (4)
［工程Ｂ］該導電層上に半田バンプを形成すること、および
［工程Ｃ］該半導体ウエハをダイシングすることを含み、
該［工程Ａ］が、複数の半導体素子が形成された能動面を有する半導体ウエハの該能動面側に保護テープを貼付した状態で、該能動面と反対側の面を研削することを含み、
該研削から[工程Ｃ]のダイシングまでを該保護テープを貼付したままで行う、半導体素子の製造方法。 [Step A] Penetration conduction connecting the active surface on which a plurality of semiconductor elements are formed, a conductive layer of a predetermined pattern formed on the surface opposite to the active surface, and the active surface and the surface on the opposite side A semiconductor wafer having a path,
[Step B] forming solder bumps on the conductive layer, and [Step C] dicing the semiconductor wafer;
The [Step A] includes grinding a surface opposite to the active surface with a protective tape applied to the active surface side of a semiconductor wafer having an active surface on which a plurality of semiconductor elements are formed,
A method for manufacturing a semiconductor device, wherein the steps from the grinding to the dicing in [Step C] are performed with the protective tape still attached.
［工程ａ−１］複数の半導体素子が形成された能動面を有する半導体ウエハの該能動面側に保護テープを貼付した状態で、該能動面と反対側の面を研削すること、
［工程ａ−２］該半導体ウエハに能動面とその反対側の面とを繋ぐ貫通孔を形成すること、および
［工程ａ−３］該貫通孔内に貫通導電路を形成するとともに、該能動面と反対側の面に所定のパターンの導電層を形成すること、を含む、請求項１に記載の半導体素子の製造方法。 [Step A]
[Step a-1] Grinding a surface opposite to the active surface in a state where a protective tape is applied to the active surface of a semiconductor wafer having an active surface on which a plurality of semiconductor elements are formed,
[Step a-2] Forming a through hole connecting the active surface and the opposite surface to the semiconductor wafer, and [Step a-3] forming a through conductive path in the through hole and The method of manufacturing a semiconductor element according to claim 1, comprising forming a conductive layer having a predetermined pattern on a surface opposite to the surface.
［工程ａ’−１］複数の半導体素子が形成された能動面と該能動面側から厚み方向の途中まで形成された複数の導電路とを有する半導体ウエハの該能動面側に保護テープを貼付した状態で、該能動面と反対側の面を研削して、該反対側の面に該導電路を露出させること、および
［工程ａ’−２］該能動面と反対側の面に所定のパターンの導電層を形成すること、を含む、請求項１に記載の半導体素子の製造方法。 [Step A]
[Step a′-1] Affixing a protective tape on the active surface side of a semiconductor wafer having an active surface on which a plurality of semiconductor elements are formed and a plurality of conductive paths formed from the active surface side to the middle in the thickness direction In this state, the surface opposite to the active surface is ground to expose the conductive path on the opposite surface, and [Step a′-2] a predetermined surface is provided on the surface opposite to the active surface. The method of manufacturing a semiconductor device according to claim 1, comprising forming a conductive layer having a pattern.
The manufacturing method of the semiconductor element in any one of Claim 1 to 3 whose said semiconductor element is a solid-state image sensor.
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| JP2012232509A JP2014086477A (en) | 2012-10-22 | 2012-10-22 | Semiconductor element manufacturing method |
| TW102137342A TW201423856A (en) | 2012-10-22 | 2013-10-16 | Manufacture method for semiconductor element |
| KR1020130123916A KR20140051078A (en) | 2012-10-22 | 2013-10-17 | Method for producing the semiconductor device |
| CN201310499119.3A CN103779371A (en) | 2012-10-22 | 2013-10-22 | Method for manufacturing semiconductor component |
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| JP2005260144A (en) * | 2004-03-15 | 2005-09-22 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof |
| JP2007067429A (en) * | 2006-10-27 | 2007-03-15 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor device |
| JP2007227810A (en) * | 2006-02-24 | 2007-09-06 | Sharp Corp | Surface protection sheet, and method for manufacturing semiconductor device using surface protection sheet |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2005260144A (en) * | 2004-03-15 | 2005-09-22 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof |
| JP2007227810A (en) * | 2006-02-24 | 2007-09-06 | Sharp Corp | Surface protection sheet, and method for manufacturing semiconductor device using surface protection sheet |
| JP2007067429A (en) * | 2006-10-27 | 2007-03-15 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor device |
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| CN103779371A (en) | 2014-05-07 |
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