JP2014066522A - Semiconductor hall sensor - Google Patents

Semiconductor hall sensor Download PDF

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JP2014066522A
JP2014066522A JP2012209889A JP2012209889A JP2014066522A JP 2014066522 A JP2014066522 A JP 2014066522A JP 2012209889 A JP2012209889 A JP 2012209889A JP 2012209889 A JP2012209889 A JP 2012209889A JP 2014066522 A JP2014066522 A JP 2014066522A
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hall element
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JP6072482B2 (en
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Takaaki Tobioka
孝明 飛岡
Hirotane Hirose
嘉胤 廣瀬
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Seiko Instruments Inc
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor Hall sensor which can decrease an offset voltage at a high temperature.SOLUTION: A center line connecting a center of a first terminal 11A and a third terminal 11C to which an internal power supply voltage is applied and a center of a second terminal 11B and a fourth terminal 11D to which an earth voltage is applied is equal to a center line of a hall element 11. The hall element 11 and an output transistor 32 are laid out in a manner to be symmetric about the center line. Namely, the center line of the hall element 11 coincides with a center line of the output transistor 32.

Description

本発明は、スピニングカレント法によって動作する半導体ホールセンサに関する。   The present invention relates to a semiconductor Hall sensor that operates by a spinning current method.

半導体ホールセンサとして、特許文献１に開示される技術を例に説明する。
特許文献１に開示された半導体ホールセンサにおいては、ホール素子に発生するホール電圧は、ホール素子の固有のオフセット電圧を含んでいる。そこで、特許文献１に開示される技術は、そこの図３に示されるように、スピニングカレント法を用いることにより、オフセット電圧を少なくしている。 As a semiconductor Hall sensor, the technique disclosed in Patent Document 1 will be described as an example.
In the semiconductor Hall sensor disclosed in Patent Document 1, the Hall voltage generated in the Hall element includes a unique offset voltage of the Hall element. Therefore, the technique disclosed in Patent Document 1 reduces the offset voltage by using a spinning current method as shown in FIG.

特開２０１２−０３２３８３号公報JP 2012-032383 A

ここで、半導体ホールセンサがボルテージレギュレータを搭載することがある。この時、半導体ホールセンサの内部回路は、電源電圧でなく、ボルテージレギュレータが電源電圧を降圧して生成した内部電源電圧を使用する。この時、このボルテージレギュレータは発熱するので、この発熱の影響により、ホール素子が有するオフセット電圧が大きくなる可能性がある。   Here, the semiconductor Hall sensor may be equipped with a voltage regulator. At this time, the internal circuit of the semiconductor Hall sensor uses not the power supply voltage but the internal power supply voltage generated by the voltage regulator stepping down the power supply voltage. At this time, since this voltage regulator generates heat, the offset voltage of the Hall element may increase due to the influence of this heat generation.

本発明は、上記課題に鑑みてなされ、高温時においてもオフセット電圧が大きくならない半導体ホールセンサを提供する。   The present invention is made in view of the above problems, and provides a semiconductor Hall sensor in which an offset voltage does not increase even at high temperatures.

本発明は、上記課題を解決するため、スピニングカレント法によって動作する半導体ホールセンサにおいて、電源電圧から内部電源電圧を生成する出力トランジスタを備えるボルテージレギュレータと、平面図で正方形であり、前記内部電源電圧が前記スピニングカレント法によって順次印加される第一端子及び第三端子を備え、接地電圧が前記スピニングカレント法によって順次印加される第二端子及び第四端子を備えるホール素子と、を備え、前記第一ないし第四端子は前記ホール素子の四隅にそれぞれ設けられ、前記第一および第二端子は対向し、前記第三および第四端子は対向し、前記ホール素子及び前記出力トランジスタは、前記第一端子と前記第三端子との中心と、前記第二端子と前記第四端子との中心と、をつなぐ中心線で、対称になるようレイアウトされる、ことを特徴とする半導体ホールセンサを提供する。   In order to solve the above problems, the present invention provides a semiconductor Hall sensor that operates by a spinning current method, a voltage regulator including an output transistor that generates an internal power supply voltage from a power supply voltage, and a square in plan view, the internal power supply voltage Comprises a first terminal and a third terminal that are sequentially applied by the spinning current method, and a Hall element that includes a second terminal and a fourth terminal to which a ground voltage is sequentially applied by the spinning current method. First to fourth terminals are provided at four corners of the Hall element, the first and second terminals are opposed to each other, the third and fourth terminals are opposed to each other, and the Hall element and the output transistor are A center line connecting the center of the terminal and the third terminal and the center of the second terminal and the fourth terminal, It is laid so as to be referred, to provide a semiconductor Hall sensor, characterized in that.

本発明によれば、出力トランジスタが発する熱は、ホール素子の中心線を基準にして、対称にホール素子に伝播するので、この発熱によって温度上昇したホール素子において、ホール電圧に含まれるオフセット電圧が大きくならない。   According to the present invention, the heat generated by the output transistor propagates symmetrically to the Hall element with respect to the center line of the Hall element. Therefore, in the Hall element whose temperature has increased due to this heat generation, the offset voltage included in the Hall voltage is Does not grow.

半導体ホールセンサを示す回路図である。It is a circuit diagram which shows a semiconductor Hall sensor. 半導体ホールセンサを示すレイアウト図である。It is a layout figure which shows a semiconductor Hall sensor. 半導体ホールセンサを示すレイアウト図である。It is a layout figure which shows a semiconductor Hall sensor.

以下、本発明の実施形態について、図面を参照して説明する。
＜半導体ホールセンサの要素＞
図１に示すように、半導体ホールセンサ１０は、ホール素子１１、アンプ１２、容量１３〜１４、スイッチ１５〜１８、スイッチ２１〜２８、及び、ボルテージレギュレータ３０を備えている。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
<Elements of semiconductor Hall sensor>
As shown in FIG. 1, the semiconductor Hall sensor 10 includes a Hall element 11, an amplifier 12, capacitors 13 to 14, switches 15 to 18, switches 21 to 28, and a voltage regulator 30.

ホール素子１１は、平面図で正方形である。ホール素子１１は、内部電源電圧がスピニングカレント法によって順次印加される第一端子１１Ａおよび第三端子１１Ｃを備え、接地電圧がスピニングカレント法によって順次印加される第二端子１１Ｂおよび第四端子１１Ｄを備える。第一ないし第四端子１１Ａ〜１１Ｄはホール素子の四隅にそれぞれ設けられ、第一および第二端子１１Ａ〜１１Ｂは対向し、第三および第四端子１１Ｃ〜１１Ｄは対向する。   The Hall element 11 is square in plan view. The Hall element 11 includes a first terminal 11A and a third terminal 11C to which an internal power supply voltage is sequentially applied by a spinning current method, and a second terminal 11B and a fourth terminal 11D to which a ground voltage is sequentially applied by a spinning current method. Prepare. The first to fourth terminals 11A to 11D are provided at the four corners of the Hall element, respectively, the first and second terminals 11A to 11B are opposed, and the third and fourth terminals 11C to 11D are opposed.

＜半導体ホールセンサの接続関係＞
ホール素子１１の第一端子１１Ａは、スイッチ１５を介し、内部電源ノード１９に接続され、スイッチ２３を介し、アンプ１２の第一入力端子に接続される。ホール素子１１の第三端子１１Ｃは、スイッチ１７を介し、内部電源ノード１９に接続され、スイッチ２１を介し、アンプ１２の第一入力端子に接続される。 <Connections for semiconductor Hall sensors>
The first terminal 11 </ b> A of the Hall element 11 is connected to the internal power supply node 19 through the switch 15, and is connected to the first input terminal of the amplifier 12 through the switch 23. The third terminal 11 </ b> C of the Hall element 11 is connected to the internal power supply node 19 through the switch 17, and is connected to the first input terminal of the amplifier 12 through the switch 21.

ホール素子１１の第二端子１１Ｂは、スイッチ１６を介し、接地端子に接続され、スイッチ２４を介し、アンプ１２の第二入力端子に接続される。ホール素子１１の第二端子１１Ｄは、スイッチ１８を介し、接地端子に接続され、スイッチ２２を介し、アンプ１２の第二入力端子に接続される。   The second terminal 11B of the Hall element 11 is connected to the ground terminal via the switch 16 and is connected to the second input terminal of the amplifier 12 via the switch 24. The second terminal 11 </ b> D of the hall element 11 is connected to the ground terminal via the switch 18, and is connected to the second input terminal of the amplifier 12 via the switch 22.

ボルテージレギュレータ３０は、電源端子と接地端子との間の電圧で動作する。ボルテージレギュレータ３０の出力端子は、内部電源ノード１９に接続される。アンプ１２は、内部電源ノード１９と接地端子との間の電圧で動作する。   The voltage regulator 30 operates with a voltage between the power supply terminal and the ground terminal. The output terminal of the voltage regulator 30 is connected to the internal power supply node 19. Amplifier 12 operates with a voltage between internal power supply node 19 and the ground terminal.

容量１３の一端は、接地端子に接続される。容量１３の多端は、スイッチ２５を介し、アンプ１２の出力端子に接続され、スイッチ２７を介し、半導体ホールセンサ１０の出力端子に接続される。容量１４の一端は、接地端子に接続される。容量１４の多端は、スイッチ２６を介し、アンプ１２の出力端子に接続され、スイッチ２８を介し、半導体ホールセンサ１０の出力端子に接続される。   One end of the capacitor 13 is connected to the ground terminal. The multi-end of the capacitor 13 is connected to the output terminal of the amplifier 12 via the switch 25 and is connected to the output terminal of the semiconductor Hall sensor 10 via the switch 27. One end of the capacitor 14 is connected to the ground terminal. The multi-end of the capacitor 14 is connected to the output terminal of the amplifier 12 via the switch 26 and is connected to the output terminal of the semiconductor Hall sensor 10 via the switch 28.

＜ボルテージレギュレータの動作＞
ボルテージレギュレータ３０は、半導体ホールセンサ１０の電源端子の電源電圧を降圧することにより、電源電圧から一定の所望電圧（内部電源電圧）を生成し、ボルテージレギュレータ３０の出力端子（内部電源ノード１９）から出力する。この時、制御回路３１が出力トランジスタ３２のゲート電圧を適宜制御することにより、出力トランジスタ３２のドレイン電圧が一定の所望電圧（内部電源電圧）になる。つまり、ボルテージレギュレータ３０の出力端子の電圧が、一定の所望電圧（内部電源電圧）になる。ここで、出力トランジスタ３２には、出力電流が流れるので、降圧した電圧と出力電流の積である消費電力の分だけ発熱する。この発熱により、半導体ホールセンサ１０の温度は高くなる。 <Operation of voltage regulator>
The voltage regulator 30 generates a constant desired voltage (internal power supply voltage) from the power supply voltage by stepping down the power supply voltage at the power supply terminal of the semiconductor Hall sensor 10, and from the output terminal (internal power supply node 19) of the voltage regulator 30. Output. At this time, the control circuit 31 appropriately controls the gate voltage of the output transistor 32, whereby the drain voltage of the output transistor 32 becomes a constant desired voltage (internal power supply voltage). That is, the voltage at the output terminal of the voltage regulator 30 becomes a constant desired voltage (internal power supply voltage). Here, since an output current flows through the output transistor 32, heat is generated by the amount of power consumption that is the product of the stepped down voltage and the output current. Due to this heat generation, the temperature of the semiconductor Hall sensor 10 increases.

＜半導体ホールセンサの動作（期間Φ１）＞
スイッチ１５〜１６がオンし、スイッチ１７〜１８がオフし、スイッチ２１〜２２がオンし、スイッチ２３〜２４がオフし、スイッチ２５がオンし、スイッチ２６がオフし、スイッチ２７〜２８がオフする。 <Operation of semiconductor Hall sensor (period Φ1)>
Switches 15-16 are turned on, switches 17-18 are turned off, switches 21-22 are turned on, switches 23-24 are turned off, switch 25 is turned on, switch 26 is turned off, and switches 27-28 are turned off To do.

ボルテージレギュレータ３０の出力端子（内部電源ノード１９）により、内部電源電圧が、ホール素子１１の第一端子１１Ａと第二端子１１Ｂとの間に印加される。この内部電源電圧に基づき、第一端子１１Ａから第二端子１１Ｂに電流が流れる。この時、ホール素子１１の平面に対して垂直に磁界が印加されると、電流及び磁界の双方に対して垂直にホール電圧Ｖｈが発生する。つまり、第三端子１１Ｃと第四端子１１Ｄとの間に、ホール電圧Ｖｈが発生する。ホール電圧Ｖｈは、ホール素子１１の固有のオフセット電圧（＋Ｖｏ）を含んでいる。このホール電圧Ｖｈは、アンプ１２及びスイッチ２５を介し、容量１３にサンプルされる。   An internal power supply voltage is applied between the first terminal 11A and the second terminal 11B of the Hall element 11 by the output terminal (internal power supply node 19) of the voltage regulator 30. Based on this internal power supply voltage, a current flows from the first terminal 11A to the second terminal 11B. At this time, when a magnetic field is applied perpendicular to the plane of the Hall element 11, a Hall voltage Vh is generated perpendicular to both the current and the magnetic field. That is, the Hall voltage Vh is generated between the third terminal 11C and the fourth terminal 11D. The Hall voltage Vh includes the inherent offset voltage (+ Vo) of the Hall element 11. This Hall voltage Vh is sampled by the capacitor 13 via the amplifier 12 and the switch 25.

＜半導体ホールセンサの動作（期間Φ２）＞
スイッチ１５〜１６がオフし、スイッチ１７〜１８がオンし、スイッチ２１〜２２がオフし、スイッチ２３〜２４がオンし、スイッチ２５がオフし、スイッチ２６がオンし、スイッチ２７〜２８がオフする。 <Operation of semiconductor Hall sensor (period Φ2)>
Switches 15-16 are turned off, Switches 17-18 are turned on, Switches 21-22 are turned off, Switches 23-24 are turned on, Switch 25 is turned off, Switch 26 is turned on, and Switches 27-28 are turned off To do.

ボルテージレギュレータ３０の出力端子（内部電源ノード１９）により、内部電源電圧が、ホール素子１１の第三端子１１Ｃと第四端子１１Ｄとの間に印加される。この内部電源電圧に基づき、第三端子１１Ｃから第四端子１１Ｄに電流が流れる。この時、ホール素子１１の平面に対して垂直に磁界が印加されると、電流及び磁界の双方に対して垂直にホール電圧Ｖｈが発生する。つまり、第一端子１１Ａと第二端子１１Ｂとの間に、ホール電圧Ｖｈが発生する。ホール電圧Ｖｈは、ホール素子１１の固有のオフセット電圧（−Ｖｏ）を含んでいる。このホール電圧Ｖｈは、アンプ１２及びスイッチ２６を介し、容量１４にサンプルされる。   An internal power supply voltage is applied between the third terminal 11C and the fourth terminal 11D of the Hall element 11 by the output terminal (internal power supply node 19) of the voltage regulator 30. Based on the internal power supply voltage, a current flows from the third terminal 11C to the fourth terminal 11D. At this time, when a magnetic field is applied perpendicular to the plane of the Hall element 11, a Hall voltage Vh is generated perpendicular to both the current and the magnetic field. That is, the Hall voltage Vh is generated between the first terminal 11A and the second terminal 11B. The Hall voltage Vh includes the inherent offset voltage (−Vo) of the Hall element 11. This Hall voltage Vh is sampled by the capacitor 14 via the amplifier 12 and the switch 26.

＜半導体ホールセンサの動作（期間Φ３）＞
スイッチ２５〜２６がオフし、スイッチ２７〜２８がオンする。
半導体ホールセンサ１０の出力端子で、期間Φ１のホール電圧Ｖｈと期間Φ２のホール電圧Ｖｈとは平均化される。すると、期間Φ１のオフセット電圧（＋Ｖｏ）と期間Φ２のオフセット電圧（−Ｖｏ）とは相殺されるので、半導体ホールセンサ１０の出力端子でのホール電圧Ｖｈにオフセット成分は無い（スピニングカレント法）。 <Operation of semiconductor Hall sensor (period Φ3)>
Switches 25-26 are turned off and switches 27-28 are turned on.
At the output terminal of the semiconductor Hall sensor 10, the Hall voltage Vh in the period Φ1 and the Hall voltage Vh in the period Φ2 are averaged. Then, since the offset voltage (+ Vo) in the period Φ1 and the offset voltage (−Vo) in the period Φ2 cancel each other, there is no offset component in the Hall voltage Vh at the output terminal of the semiconductor Hall sensor 10 (spinning current method).

＜半導体ホールセンサのレイアウト＞
ボルテージレギュレータ３０の出力トランジスタ３２は、図２に示すように、第一端子１１Ａ及び第三端子１１Ｃの側にレイアウトされる。内部電源電圧が印加される第一端子１１Ａと第三端子１１Ｃとの中心と、接地電圧が印加される第二端子１１Ｂと第四端子１１Ｄとの中心と、をつなぐ中心線は、ホール素子１１の中心線であるとする。ホール素子１１及び出力トランジスタ３２は、その中心線で、対称になるようレイアウトされる。つまり、ホール素子１１の中心線は、出力トランジスタ３２の中心線と一致する。 <Semiconductor Hall sensor layout>
As shown in FIG. 2, the output transistor 32 of the voltage regulator 30 is laid out on the first terminal 11A and third terminal 11C sides. A center line connecting the center of the first terminal 11A and the third terminal 11C to which the internal power supply voltage is applied and the center of the second terminal 11B and the fourth terminal 11D to which the ground voltage is applied is the Hall element 11 Is the center line of. The Hall element 11 and the output transistor 32 are laid out symmetrically with respect to the center line. That is, the center line of the Hall element 11 coincides with the center line of the output transistor 32.

なお、出力トランジスタ３２は、図３に示すように、第二端子１１Ｂ及び第四端子１１Ｄの側にレイアウトしても良い。
このようにすると、出力トランジスタ３２から発生する熱は、ホール素子１１の中心線を基準にして、対称にホール素子１１に伝播する。熱の加わり方が対称で均等になるため、この発熱によって温度が上昇したホール素子１１においてはホール電圧Ｖｈに含まれるオフセット電圧は相殺し、温度が上昇してもオフセット電圧は大きくならない。 The output transistor 32 may be laid out on the second terminal 11B and fourth terminal 11D sides as shown in FIG.
In this way, the heat generated from the output transistor 32 propagates symmetrically to the Hall element 11 with respect to the center line of the Hall element 11. Since the method of applying heat is symmetrical and uniform, the offset voltage included in the Hall voltage Vh cancels out in the Hall element 11 whose temperature has increased due to this heat generation, and the offset voltage does not increase even if the temperature increases.

１０ 半導体ホールセンサ
１１ ホール素子
１２ アンプ
１３〜１４ 容量
１５〜１８、２１〜２８ スイッチ
１９ 内部電源ノード
３０ ボルテージレギュレータ
３１ 制御回路
３２ 出力トランジスタ DESCRIPTION OF SYMBOLS 10 Semiconductor Hall sensor 11 Hall element 12 Amplifier 13-14 Capacity | capacitance 15-18, 21-28 Switch 19 Internal power supply node 30 Voltage regulator 31 Control circuit 32 Output transistor

Claims (3)

電源電圧から内部電源電圧を生成する出力トランジスタを備えるボルテージレギュレータと、
平面図で正方形であり、前記内部電源電圧が順次印加される第一端子及び第三端子と、接地電圧が順次印加される第二端子及び第四端子と、を備えるホール素子と、
を備え、
前記第一ないし第四端子は前記ホール素子の四隅にそれぞれ設けられ、前記第一および第二端子は対向し、前記第三および第四端子は対向しており、
前記ホール素子及び前記出力トランジスタは、前記第一端子と前記第三端子との中心と、前記第二端子と前記第四端子との中心と、をつなぐ中心線で、対称になるようレイアウトされている、
ことを特徴とする半導体ホールセンサ。 A voltage regulator including an output transistor for generating an internal power supply voltage from the power supply voltage;
A hall element comprising a first terminal and a third terminal, which are square in plan view, to which the internal power supply voltage is sequentially applied, and a second terminal and a fourth terminal to which a ground voltage is sequentially applied;
With
The first to fourth terminals are respectively provided at the four corners of the Hall element, the first and second terminals are opposed, and the third and fourth terminals are opposed,
The Hall element and the output transistor are laid out symmetrically with a center line connecting the center of the first terminal and the third terminal and the center of the second terminal and the fourth terminal. Yes,
A semiconductor Hall sensor characterized by that. 前記出力トランジスタは、前記第一端子及び前記第三端子の側にレイアウトされていることを特徴とする請求項１記載の半導体ホールセンサ。   2. The semiconductor Hall sensor according to claim 1, wherein the output transistor is laid out on the first terminal and the third terminal side. 前記出力トランジスタは、前記第二端子及び前記第四端子の側にレイアウトされていることを特徴とする請求項１記載の半導体ホールセンサ。   2. The semiconductor Hall sensor according to claim 1, wherein the output transistor is laid out on the second terminal side and the fourth terminal side.
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