JP2014052262A - Magnetic sensor - Google Patents

Magnetic sensor Download PDF

Info

Publication number
JP2014052262A
JP2014052262A JP2012196352A JP2012196352A JP2014052262A JP 2014052262 A JP2014052262 A JP 2014052262A JP 2012196352 A JP2012196352 A JP 2012196352A JP 2012196352 A JP2012196352 A JP 2012196352A JP 2014052262 A JP2014052262 A JP 2014052262A
Authority
JP
Japan
Prior art keywords
voltage
amplifier circuit
output
circuit
magnetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2012196352A
Other languages
Japanese (ja)
Other versions
JP6257019B2 (en
Inventor
Nobuaki Otake
伸明 大竹
Masanori Tanaka
政範 田中
Kazuya Yano
一也 矢野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko NPC Corp
Original Assignee
Seiko NPC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko NPC Corp filed Critical Seiko NPC Corp
Priority to JP2012196352A priority Critical patent/JP6257019B2/en
Publication of JP2014052262A publication Critical patent/JP2014052262A/en
Application granted granted Critical
Publication of JP6257019B2 publication Critical patent/JP6257019B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Measuring Magnetic Variables (AREA)
  • Hall/Mr Elements (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a magnetic sensor that amplifies a magnetic detection signal containing a DC component.SOLUTION: A comparator 6 compares an output voltage of an amplifier circuit 2, in a state where magnetism is not detected, with a reference voltage. Based on an output of the comparator 6, a successive comparison type analog/digital converter 7 generates a signal Vdao for correcting an output offset voltage generated in the amplifier circuit 2. By input of the generated signal Vdao into a reference voltage input terminal 2b of an amplifier circuit 2, a magnetic detection signal containing a DC component from a magnetic detection circuit 1 is transmitted to the amplifier circuit 2 directly.

Description

本発明は、被検出体に含まれる磁性体などを磁気抵抗素子により検出した磁気信号を増幅するための増幅回路を具備した磁気センサに関するものである。   The present invention relates to a magnetic sensor including an amplifier circuit for amplifying a magnetic signal detected by a magnetoresistive element such as a magnetic material included in a detection object.

磁気抵抗素子により検出された磁気信号を増幅する方法として、磁気抵抗素子対の接続点と増幅回路との間にカップリング容量を介して、磁気検出信号を増幅する方法が広く知られている（例えば、特許文献1参照。）。また、磁気検出信号のＤＣ成分を増幅する場合は、可変抵抗器などを用いて増幅回路の基準電圧を調整し、磁気検出信号のみを増幅する方法が一般的である（例えば、特許文献２の図１３参照。）。   As a method of amplifying a magnetic signal detected by a magnetoresistive element, a method of amplifying a magnetic detection signal via a coupling capacitor between a connection point of a magnetoresistive element pair and an amplifier circuit is widely known ( For example, see Patent Document 1.) Further, when amplifying the DC component of the magnetic detection signal, a method of amplifying only the magnetic detection signal by adjusting the reference voltage of the amplifier circuit using a variable resistor or the like is generally used (for example, Patent Document 2). (See FIG. 13).

特開平６−２０１８０６号公報JP-A-6-201806 特開２００５−５６９５０号公報JP 2005-56950 A

従来のカップリング容量を介して磁気検出信号を増幅する場合、磁気抵抗素子に印加されたバイアス磁界成分（外部磁界によるＤＣ成分）が除去できる。しかし、同時に磁気検出信号に含まれるＤＣ成分も除去されてしまうため、増幅後の出力信号としては、磁性体が移動したときなどの微小変化量（ＡＣ成分）のみしか取り出すことができない。
また、磁気検出信号のＤＣ成分を増幅する場合は、磁気抵抗素子に印加したバイアス磁界に起因する電圧および増幅回路の入力オフセット電圧を打ち消すために、可変抵抗器などを用いて増幅回路の基準電圧入力端子の電圧値を調整して、磁気検出信号のみを増幅するようにしなければならない。
本発明は、このような問題を鑑みてなされたものであり、ＤＣ成分を含む磁気検出信号を増幅する磁気センサを提供する。 When a magnetic detection signal is amplified through a conventional coupling capacitor, a bias magnetic field component (DC component due to an external magnetic field) applied to the magnetoresistive element can be removed. However, since the DC component included in the magnetic detection signal is also removed at the same time, only a minute change amount (AC component) such as when the magnetic body moves can be taken out as an output signal after amplification.
In addition, when amplifying the DC component of the magnetic detection signal, a variable resistor or the like is used to cancel the voltage caused by the bias magnetic field applied to the magnetoresistive element and the input offset voltage of the amplifier circuit. The voltage value of the input terminal must be adjusted so that only the magnetic detection signal is amplified.
The present invention has been made in view of such problems, and provides a magnetic sensor that amplifies a magnetic detection signal including a DC component.

上記の問題を解決するために、本発明の磁気センサの一態様は、磁気抵抗素子を含む磁気検出回路と、前記磁気検出回路にて取り出されるＤＣ成分を含む磁気検出信号を増幅して出力する増幅回路と、磁気非検出の状態での前記増幅回路の出力信号に基づき、前記磁気抵抗素子に印加したバイアス磁界に起因する電圧および前記増幅回路の入力オフセット電圧により発生する前記増幅回路の出力オフセット電圧を補正する電圧を生成して、前記増幅回路の基準電圧入力端子に前記信号を入力するオフセット調整回路を具備したことを特徴としている。
また、本発明に用いるオフセット調整回路は、磁気非検出の状態での前記増幅回路の出力電圧と参照電圧を比較するコンパレータと、前記コンパレータの出力に基づいて前記出力オフセット電圧を補正する信号を生成する逐次比較型ＤＡコンバータを具備したことを特徴としている。 In order to solve the above problem, an aspect of the magnetic sensor of the present invention amplifies and outputs a magnetic detection circuit including a magnetoresistive element and a magnetic detection signal including a DC component extracted by the magnetic detection circuit. Based on an output signal of the amplifier circuit and the amplifier circuit in a magnetic non-detection state, an output offset of the amplifier circuit generated by a voltage caused by a bias magnetic field applied to the magnetoresistive element and an input offset voltage of the amplifier circuit An offset adjustment circuit that generates a voltage for correcting the voltage and inputs the signal to a reference voltage input terminal of the amplifier circuit is provided.
In addition, the offset adjustment circuit used in the present invention generates a signal for correcting the output offset voltage based on the output of the comparator that compares the output voltage of the amplifier circuit and the reference voltage in a magnetic non-detection state. The successive approximation type DA converter is provided.

本発明によれば、磁気抵抗素子により検出されたＤＣ成分を含む磁気検出信号をそのまま増幅回路に伝えられるようにしているため、磁気検出回路と増幅回路との間にカップリング容量を介さなくてもよい。
また、磁気抵抗素子に印加したバイアス磁界に起因する電圧および増幅回路の入力オフセット電圧により発生する増幅回路の出力オフセット電圧を補正するオフセット調整回路を具備しているため、可変抵抗器などを用いた増幅回路の基準電圧入力端子に対する電圧値調整が不必要となる。
なお、オフセット調整回路には、逐次比較型ＤＡコンバータを具備しており、電圧精度の良い補正信号を生成することができるため、確実に出力オフセット電圧を補正することができ、ＤＣ成分を含む磁気検出信号を安定して増幅することができる。 According to the present invention, since the magnetic detection signal including the DC component detected by the magnetoresistive element can be directly transmitted to the amplifier circuit, a coupling capacitor is not interposed between the magnetic detection circuit and the amplifier circuit. Also good.
In addition, since it has an offset adjustment circuit that corrects the voltage caused by the bias magnetic field applied to the magnetoresistive element and the output offset voltage of the amplifier circuit generated by the input offset voltage of the amplifier circuit, a variable resistor or the like was used. It is not necessary to adjust the voltage value with respect to the reference voltage input terminal of the amplifier circuit.
Note that the offset adjustment circuit includes a successive approximation DA converter, and can generate a correction signal with high voltage accuracy, so that the output offset voltage can be reliably corrected and a magnetic component including a DC component can be obtained. The detection signal can be amplified stably.

実施例１における磁気センサの構成ブロック図。1 is a configuration block diagram of a magnetic sensor in Embodiment 1. FIG. 実施例１における磁気非検出の状態での磁気抵抗素子からの信号波形図。FIG. 3 is a signal waveform diagram from the magnetoresistive element in a magnetic non-detected state in the first embodiment. 実施例１における図1の磁気センサで磁気非検出の状態としたときの回路図。FIG. 2 is a circuit diagram when the magnetic sensor of FIG. 実施例１で説明するＮビット逐次比較型ＤＡコンバータの回路図。1 is a circuit diagram of an N-bit successive approximation DA converter described in Embodiment 1. FIG. 実施例１で説明する４ビット逐次比較型ＤＡコンバータの回路図。1 is a circuit diagram of a 4-bit successive approximation DA converter described in Embodiment 1. FIG. 実施例１で説明する出力オフセット電圧を補正しているときの４ビット逐次比較型ＤＡコンバータの入出力波形図。FIG. 6 is an input / output waveform diagram of the 4-bit successive approximation DA converter when the output offset voltage described in the first embodiment is corrected. 実施例１で説明する出力オフセット電圧の補正信号を生成する際の手順を示したフロー図。FIG. 3 is a flowchart illustrating a procedure for generating a correction signal for an output offset voltage described in the first embodiment. 実施例２における磁気センサの構成ブロック図。FIG. 6 is a configuration block diagram of a magnetic sensor according to a second embodiment. 実施例２における磁気非検出の状態での磁気抵抗素子からの信号波形図。FIG. 6 is a signal waveform diagram from a magnetoresistive element in a magnetic non-detected state in the second embodiment. 実施例２における図８の磁気センサで磁気非検出の状態としたときの回路図。FIG. 9 is a circuit diagram when the magnetic sensor of FIG.

以下に添付図面に基づいて、本発明の実施形態を説明する。   Embodiments of the present invention will be described below with reference to the accompanying drawings.

本発明の実施例１を、図1乃至図７に基づいて説明する。   A first embodiment of the present invention will be described with reference to FIGS.

図１の磁気センサは、磁気抵抗素子のみからなる磁気検出回路を用いた場合の一実施形態であり、電源電圧端子とグランド端子の間に磁気抵抗素子ＭＲ１、ＭＲ２を直列にて接続された磁気抵抗素子対１と、磁気抵抗素子対１での磁気検出信号を増幅するための増幅回路２と、増幅回路２の出力でのオフセット電圧を補正するためのオフセット調整回路３を備えている。   The magnetic sensor shown in FIG. 1 is an embodiment in which a magnetic detection circuit consisting of only a magnetoresistive element is used, and a magnetic sensor in which magnetoresistive elements MR1 and MR2 are connected in series between a power supply voltage terminal and a ground terminal. A resistor element pair 1, an amplifier circuit 2 for amplifying a magnetic detection signal from the magnetoresistive element pair 1, and an offset adjustment circuit 3 for correcting an offset voltage at the output of the amplifier circuit 2 are provided.

磁気抵抗素子対１の接続点から取り出される信号は、磁気抵抗素子ＭＲ１、ＭＲ２の磁気抵抗値が同じであり、外部磁界が印加されていない場合、電源電圧端子とグランド端子との中点電圧Ｖdd/２となる。
ただし、磁気抵抗素子対１には、図示していないが、ネオジム磁石やサマリウムコバルト磁石などの永久磁石を備えており、その永久磁石を用いて外部からバイアス磁界を与えることで、磁気検出感度が好適になるようにしている。
そのため、磁気非検出のときの磁気抵抗素子対１の接続点から取り出される信号Ｖin0は、図２に示すような中点電圧Ｖdd/２に、バイアス磁界に起因した電圧Ｖibが加えられた信号となる。なお、磁性体等の磁気信号を検出した場合は、Ｖin0を基準として磁気検出信号が取り出される。 The signal taken out from the connection point of the magnetoresistive element pair 1 has the same magnetoresistance value of the magnetoresistive elements MR1 and MR2, and when no external magnetic field is applied, the midpoint voltage Vdd between the power supply voltage terminal and the ground terminal. / 2.
However, although not shown, the magnetoresistive element pair 1 includes a permanent magnet such as a neodymium magnet or a samarium cobalt magnet. By applying a bias magnetic field from the outside using the permanent magnet, the magnetic detection sensitivity is increased. To be suitable.
Therefore, the signal Vin0 taken out from the connection point of the magnetoresistive element pair 1 at the time of magnetic non-detection is a signal obtained by adding the voltage Vib resulting from the bias magnetic field to the midpoint voltage Vdd / 2 as shown in FIG. Become. When a magnetic signal from a magnetic material or the like is detected, the magnetic detection signal is extracted with Vin0 as a reference.

図３は、図1の磁気センサで磁気非検出の状態としたときの回路図であり、増幅回路２に前記信号Ｖin0を入力したとき、出力電圧Ｖout0が得られる。 FIG. 3 is a circuit diagram when the magnetic sensor of FIG. 1 is in a magnetic non-detection state. When the signal Vin0 is input to the amplifier circuit 2, an output voltage Vout0 is obtained.

増幅回路２は、抵抗Ｒ１、Ｒ２とＯＰアンプ４により構成される反転型増幅回路であり、図３に示すように、ＯＰアンプ４は理想ＯＰアンプ９のほか、入力オフセット電圧Ｖioを有している。
増幅回路２の信号入力端子２ａに、磁気非検出のときの信号Ｖin0を、基準電圧入力端子２ｂに参照電圧Ｖref=Ｖdd/２を入力したとき、増幅回路の出力電圧Ｖout0は第１式となる。
このとき、出力電圧Ｖout0には、バイアス磁界に起因した電圧Ｖibが増幅された電圧（第１式の右辺第２項）、ＯＰアンプ４の入力オフセット電圧Ｖioが増幅された電圧（第1式の右辺第3項）が出力オフセット電圧として現れる。 The amplifier circuit 2 is an inverting amplifier circuit composed of resistors R1 and R2 and an OP amplifier 4. As shown in FIG. 3, the OP amplifier 4 has an input offset voltage Vio in addition to the ideal OP amplifier 9. Yes.
When the signal Vin0 when no magnetism is detected is input to the signal input terminal 2a of the amplifier circuit 2 and the reference voltage Vref = Vdd / 2 is input to the reference voltage input terminal 2b, the output voltage Vout0 of the amplifier circuit is expressed by the first equation. .
At this time, the output voltage Vout0 includes a voltage obtained by amplifying the voltage Vib due to the bias magnetic field (second term on the right side of the first expression), and a voltage obtained by amplifying the input offset voltage Vio of the OP amplifier 4 (equation 1 The third term on the right side) appears as the output offset voltage.

（数１）
Ｖout0 ＝ Ｖdd/2
− (Ｒ２/Ｒ１)・Ｖib ＋ (１＋Ｒ２/Ｒ１)・Ｖio
・・・ (1) (Equation 1)
Vout0 = Vdd / 2
− (R2 / R1) ・ Vib + (1 + R2 / R1) ・ Vio
(1)

オフセット調整回路３は、磁気非検出のときの増幅回路２の出力電圧と参照電圧回路５から生成される参照電圧Ｖrefと比較するコンパレータ６と、出力オフセット電圧を補正する信号Ｖdaoを生成する逐次比較型ＤＡコンバータ７と、コンパレータ６の出力に基づいて逐次比較型ＤＡコンバータ７を制御する制御回路８からなり、生成された前記信号Ｖdaoを増幅回路２の基準電圧入力端子２ｂに入力することで、上記出力オフセット電圧を補正するための回路である。   The offset adjustment circuit 3 compares the output voltage of the amplifier circuit 2 when no magnetism is detected with the reference voltage Vref generated from the reference voltage circuit 5, and the successive approximation that generates the signal Vdao for correcting the output offset voltage. A DA converter 7 and a control circuit 8 that controls the successive approximation DA converter 7 based on the output of the comparator 6. By inputting the generated signal Vdao to the reference voltage input terminal 2b of the amplifier circuit 2, It is a circuit for correcting the output offset voltage.

逐次比較型ＤＡコンバータ７は、具体的には図４に示した回路であり、前記コンパレータ６の出力に基づいたＮビットのディジタル入力信号ＤＮ−１、ＤＮ−２、…、Ｄ０
にそれぞれ対応するスイッチＳＮ−１、ＳＮ−２、…、Ｓ０ とＲ−２Ｒ型抵抗回路網からなる。 The successive approximation type DA converter 7 is specifically the circuit shown in FIG. 4, and is an N-bit digital input signal D N−1 , D N−2 ,..., D 0 based on the output of the comparator 6.
, S 0 and an R-2R resistor network corresponding to the switches S N−1 , S N−2 ,.

ディジタル入力信号ＤＮ−１、ＤＮ−２、…、Ｄ０が「１」である場合は、それぞれに対応したスイッチＳＮ−１、ＳＮ−２、…、Ｓ０がＨｉｇｈ（Ｖｄｄと接続）となり、ディジタル入力信号ＤＮ−１、ＤＮ−２、…、Ｄ０が「０」である場合は、それぞれに対応したスイッチＳＮ−１、ＳＮ−２、…、Ｓ０がＬｏｗ（ＧＮＤと接続）となる。 When the digital input signals D N−1 , D N−2 ,..., D 0 are “1”, the corresponding switches S N−1 , S N−2 ,..., S 0 are High (Vdd and Vdd). When the digital input signals D N−1 , D N−2 ,..., D 0 are “0”, the corresponding switches S N−1 , S N−2 ,. Low (connected to GND).

ここで、オフセット調整回路３により、磁気非検出のときの増幅回路２の出力信号に基づいて、出力オフセット電圧を補正する信号Ｖdaoを生成する方法の一実施形態を説明する。なお、説明においては、逐次比較型ＤＡコンバータとして図５に示した４ビット（Ｎ＝４）とした場合について、図７のフロー図を参照して説明する。   Here, an embodiment of a method for generating the signal Vdao for correcting the output offset voltage based on the output signal of the amplifier circuit 2 when the magnetic field is not detected by the offset adjustment circuit 3 will be described. In the description, the case of 4 bits (N = 4) shown in FIG. 5 as the successive approximation type DA converter will be described with reference to the flowchart of FIG.

はじめに、初期状態（図6の区間Ｔ３のとき）として、対象とするビットＸを最上位ビットに設定し（ステップ１０１）、逐次比較型ＤＡコンバータ７の最上位ビットに対応するディジタル入力信号Ｄ３を「１」とし、スイッチＳ３をＨｉｇｈにする。また、それ以外のディジタル入力信号Ｄ２、Ｄ１、Ｄ０を「０」とし、スイッチＳ２、Ｓ１、Ｓ０をＬｏｗにする（ステップ１０２）。
そのとき、逐次比較型ＤＡコンバータ７の出力電圧Ｖdaoは、参照電圧Ｖref＝Ｖdd/２であり、その電圧を増幅回路２の基準電圧入力端子２ｂに入力するため、増幅回路の出力電圧は第１式に示したＶout0となり、出力オフセット電圧（第１式の右辺第２項および第３項）を含んだ信号が増幅回路２の出力に現れる。 First, as an initial state (when the period T 3 in FIG. 6), it sets the bit X of interest to the most significant bit (step 101), the digital input signal D corresponding to the most significant bit of the successive approximation type DA converter 7 3 is set to “1”, and the switch S 3 is set to High. The other digital input signals D 2 , D 1 , D 0 are set to “0”, and the switches S 2 , S 1 , S 0 are set low (step 102).
At this time, the output voltage Vdao of the successive approximation DA converter 7 is the reference voltage Vref = Vdd / 2, and the voltage is input to the reference voltage input terminal 2b of the amplifier circuit 2, so that the output voltage of the amplifier circuit is the first voltage Vout0 shown in the equation, and a signal including the output offset voltage (the second term and the third term on the right side of the first equation) appears at the output of the amplifier circuit 2.

それから、コンパレータ６により、出力電圧Ｖout0と参照電圧Ｖrefとの電圧比較を行い（ステップ１０３）、Ｖout0＞ＶrefであればスイッチＳ３をＬｏｗに変更（Ｄ３＝０）し（ステップ１０４）、Ｖout0＜ＶrefであればスイッチＳ３をＨｉｇｈのまま（Ｄ３＝１）にして（ステップ１０５）、スイッチＳ３の状態を確定させる。
図６に示したＶout0は、区間Ｔ３の初期状態のとき、Ｖrefよりも低いため、スイッチＳ３はＨｉｇｈのままとしている。 Then, the comparator 6 performs voltage comparison to a reference voltage Vref and the output voltage Vout0 (step 103), Vout0> change the switch S 3 to Low if Vref (D 3 = 0) (step 104), Vout0 <leave the switch S 3 of High if Vref (D 3 = 1) (step 105), thereby determining the state of the switch S 3.
Vout0 shown in FIG. 6, when the initial state of the period T 3, lower than Vref, the switch S 3 is a left High.

次に、下位ビットへ移動して（ステップ１０７）、そのビットに対応するディジタル入力信号Ｄ２を「１」とし、スイッチＳ２をＨｉｇｈにする（ステップ１０８）。そのとき、ＶdaoはＶrefの１/２（＝Ｖdd/４）の電圧が、以前のＶdaoの値に重畳される（図6の区間Ｔ２のとき）。 Then go to the lower bits (step 107), the digital input signal D 2 corresponding to the bit set to "1", the switch S 2 to High (Step 108). At that time, Vdao (in case of interval T 2 of the FIG. 6) the voltage of 1/2 (= Vdd / 4) of Vref is superimposed on the values of these Vdao.

そして、スイッチＳ３のときと同様、出力電圧Ｖout0と参照電圧Ｖrefをコンパレータ６により電圧比較を行い、Ｖout0＞ＶrefであればスイッチＳ２をＬｏｗに変更（Ｄ２＝０）し、Ｖout0＜ＶrefであればスイッチＳ２をＨｉｇｈのまま（Ｄ２＝１）にして、スイッチＳ２の状態を確定させる。
図６に示したＶout0は、区間Ｔ２のとき、Ｖrefよりも高いため、スイッチＳ２はＬｏｗに変更している。 Then, similarly to the case of the switch S 3, a reference voltage Vref and the output voltage Vout0 performs voltage comparison by the comparator 6, Vout0> change if Vref switch S 2 to the Low (D 2 = 0), Vout0 <Vref if the switch S 2 to remain (D 2 = 1) of the High, to determine the state of the switch S 2.
Vout0 shown in FIG. 6, when the interval T 2, higher than Vref, the switch S 2 is changed to Low.

このような処理をスイッチＳ１、スイッチＳ０に対しても同様に行い、対象となるスイッチを一旦、Ｈｉｇｈの状態にし、それぞれに対応したＶdaoを増幅回路２の基準電圧入力端子２ｂに入力し、そのときの出力電圧Ｖout0と参照電圧Ｖrefをコンパレータ６にて比較した出力結果より、それぞれのスイッチの状態を確定させていく。そして、最下位ビットに対応するスイッチＳ０の状態が確定した時点で上記処理を終了する（ステップ１０６）。
なお、Ｖdaoは、スイッチＳ１をＨｉｇｈにするとＶrefの１/４（＝Ｖdd/８）の電圧が、スイッチＳ0をＨｉｇｈにするとＶrefの１/８（＝Ｖdd/１６）の電圧が、以前のＶdaoの値に重畳される。
図６に示したＶout0は、区間Ｔ１のとき、Ｖrefよりも高いため、スイッチＳ１はＬｏｗに変更しており、また、区間Ｔ0のとき、Ｖrefよりも低いため、スイッチＳ0はＨｉｇｈのままとしている。 This process is similarly performed for the switches S 1 and S 0 , and the target switch is temporarily set to the High state, and the corresponding Vdao is input to the reference voltage input terminal 2 b of the amplifier circuit 2. Based on the output result obtained by comparing the output voltage Vout0 and the reference voltage Vref at that time by the comparator 6, the state of each switch is determined. Then, ends the processing when the state of the switch S 0 corresponding to the least significant bit is determined (step 106).
Incidentally, Vdao the voltage of the switch S 1 of when the High Vref 1/4 (= Vdd / 8 ) is the voltage of the switches S 0 of when the High Vref 1/8 (= Vdd / 16 ) is, before Is superimposed on the value of Vdao.
Vout0 shown in FIG. 6, when the interval T 1, higher than Vref, the switch S 1 is changed to Low, also when the interval T 0, is lower than Vref, the switch S 0 is High It remains.

このように、図７のフロー図に基づいて、最上位ビットから最下位ビットへと、それぞれのビットに対応するスイッチの状態を確定していくことで、出力電圧Ｖout0は、図６のように参照電圧Ｖref＝Ｖdd/２に近づき、最終的に出力オフセット電圧が略０になるように補正される。
このとき、Ｖdaoは第２式で表わされ、全てのスイッチの状態が確定した後のＶdaoが出力オフセット電圧を補正する信号となる。 As described above, by determining the state of the switch corresponding to each bit from the most significant bit to the least significant bit based on the flowchart of FIG. 7, the output voltage Vout0 is as shown in FIG. The reference voltage Vref = Vdd / 2 is approached, and the output offset voltage is finally corrected to be substantially zero.
At this time, Vdao is expressed by the second equation, and Vdao after the states of all the switches are determined becomes a signal for correcting the output offset voltage.

（数２）
Ｖdao ＝｛（Ｄ３×２３＋Ｄ２×２２＋Ｄ１×２１＋Ｄ０×２０）／２4 ｝・Ｖdd ・・・ (２) (Equation 2)
Vdao = {(D 3 × 2 3 + D 2 × 2 2 + D 1 × 2 1 + D 0 × 2 0 ) / 2 4 } · Vdd (2)

ここでは、４ビットの逐次比較型ＤＡコンバータを実施形態の一例としたが、Ｎビットの逐次比較型ＤＡコンバータを用いた場合のＶdaoは第３式となり、出力オフセット電圧をより高い電圧精度にて補正したい場合は、逐次比較型ＤＡコンバータのビット数をさらに増やせばよい。   Here, a 4-bit successive approximation type DA converter is taken as an example, but Vdao in the case of using an N-bit successive approximation type DA converter is expressed by the third equation, and the output offset voltage is set with higher voltage accuracy. If correction is desired, the number of bits of the successive approximation DA converter may be further increased.

（数３）
Ｖdao ＝｛（Ｄｎ−１×２ｎ−１＋Ｄｎ−２×２ｎ−２＋
… ＋Ｄ０×２０）／２ｎ｝・Ｖdd ・・・ (３) (Equation 3)
Vdao = {(Dn -1 * 2n-1 + Dn -2 * 2n-2 +
... + D 0 × 2 0 ) / 2 n } · Vdd (3)

本実施例によれば、磁気抵抗素子対１により検出されたＤＣ成分を含む磁気検出信号をそのまま増幅回路２に伝えられるようにしているため、磁気検出回路と増幅回路との間にカップリング容量を介さなくてもよく、また、増幅回路での出力オフセット電圧を補正するオフセット調整回路３を具備しているため、可変抵抗器などを用いて増幅回路の基準電圧を調整する必要がない。
さらに、オフセット調整回路３に、逐次比較型ＤＡコンバータ７を具備したことにより、電圧精度の良い補正信号Ｖdaoを生成することができるため、確実に出力オフセット電圧を補正することができ、ＤＣ成分を含む磁気検出信号を安定して増幅することができる。 According to the present embodiment, since the magnetic detection signal including the DC component detected by the magnetoresistive element pair 1 is transmitted to the amplifier circuit 2 as it is, a coupling capacitance is provided between the magnetic detection circuit and the amplifier circuit. Since the offset adjustment circuit 3 for correcting the output offset voltage in the amplifier circuit is provided, it is not necessary to adjust the reference voltage of the amplifier circuit using a variable resistor or the like.
Furthermore, since the offset adjustment circuit 3 includes the successive approximation DA converter 7, the correction signal Vdao with high voltage accuracy can be generated, so that the output offset voltage can be reliably corrected and the DC component can be reduced. The magnetic detection signal that is included can be stably amplified.

本発明の実施例２を図８乃至図１０に基づいて説明する。   A second embodiment of the present invention will be described with reference to FIGS.

図８の磁気センサは、磁気抵抗素子と差動入力型増幅回路からなる磁気検出回路を用いた場合の一実施形態であり、電源電圧端子とグランド端子の間に、磁気抵抗素子ＭＲ１、ＭＲ２を直列にて接続された第１の磁気抵抗素子対１１と、磁気抵抗素子ＭＲ３、ＭＲ４を直列にて接続された第２の磁気抵抗素子対１２と、それらの磁気抵抗素子対の接続点から取り出される磁気検出信号を差動増幅するための差動入力型増幅回路１３からなる磁気検出回路１０を備え、実施例１と同一である、差動入力型増幅回路１３の出力信号をさらに増幅するための増幅回路２と、前記増幅回路２の出力でのオフセット電圧を補正するためのオフセット調整回路３を備えている。 The magnetic sensor of FIG. 8 is an embodiment in which a magnetic detection circuit comprising a magnetoresistive element and a differential input type amplifier circuit is used, and magnetoresistive elements MR1 and MR2 are provided between a power supply voltage terminal and a ground terminal. The first magnetoresistive element pair 11 connected in series, the second magnetoresistive element pair 12 in which the magnetoresistive elements MR3 and MR4 are connected in series, and the connection point of these magnetoresistive element pairs are taken out. In order to further amplify the output signal of the differential input type amplifier circuit 13, which is the same as that of the first embodiment, including the magnetic detection circuit 10 including the differential input type amplifier circuit 13 for differentially amplifying the magnetic detection signal to be detected. And an offset adjustment circuit 3 for correcting an offset voltage at the output of the amplification circuit 2.

また、上記磁気抵抗素子対１１、１２は、実施例１と同様、永久磁石を用いて外部からバイアス磁界を与えることで、磁気検出感度が好適になるようにしている。
よって、磁気非検出のときの磁気抵抗素子対１１、１２の接続点から取り出される信号Ｖin10、Ｖin20は図９のようになり、Ｖin10は中点電圧Ｖdd/２にバイアス磁界に起因した電圧Ｖib1が加えられた信号、Ｖin20は中点電圧Ｖdd/２にバイアス磁界に起因した電圧Ｖib2が加えられた信号となる。 Further, the magnetoresistive element pairs 11 and 12 have a magnetic detection sensitivity suitable by applying a bias magnetic field from the outside using a permanent magnet, as in the first embodiment.
Therefore, the signals Vin10 and Vin20 taken out from the connection point of the magnetoresistive element pair 11 and 12 when no magnetism is detected are as shown in FIG. 9, and Vin10 is a voltage Vib1 due to the bias magnetic field to the midpoint voltage Vdd / 2. The added signal, Vin20, is a signal obtained by adding the voltage Vib2 resulting from the bias magnetic field to the midpoint voltage Vdd / 2.

図１０は、図８の磁気センサで磁気非検出の状態としたときの回路図であり、差動入力型増幅回路１３に前記信号Ｖin10およびＶin20を入力したとき、出力電圧Ｖdif0が得られ、そのＶdif0を増幅回路２によりさらに増幅した電圧Ｖout0が得られる。 FIG. 10 is a circuit diagram when the magnetic sensor of FIG. 8 is in a non-magnetic state. When the signals Vin10 and Vin20 are input to the differential input type amplifier circuit 13, an output voltage Vdif0 is obtained. A voltage Vout0 obtained by further amplifying Vdif0 by the amplifier circuit 2 is obtained.

差動入力型増幅回路１３は、抵抗Ｒ３乃至Ｒ６とＯＰアンプ１４乃至１６からなり、高入力インピーダンスでかつ高ＣＭＲＲ（同相信号除去比）を特徴とした計測アンプの構成としている。なお、ＯＰアンプ１４乃至１６は、図１０に示すように、理想ＯＰアンプ１７乃至１９のほか、入力オフセット電圧Ｖio1乃至Ｖio3を有している。   The differential input type amplifier circuit 13 includes resistors R3 to R6 and OP amplifiers 14 to 16, and has a configuration of a measurement amplifier characterized by a high input impedance and a high CMRR (common mode rejection ratio). As shown in FIG. 10, the OP amplifiers 14 to 16 have input offset voltages Vio1 to Vio3 in addition to the ideal OP amplifiers 17 to 19.

差動入力型増幅回路１３の信号入力端子１３ａ、１３ｂに、それぞれ磁気非検出のときの信号Ｖin10、Ｖin20を入力したとき、差動入力型増幅回路１３の出力電圧Ｖdif0は第４式となり、バイアス磁界に起因した電圧Ｖib1、Ｖib2が増幅された電圧（第４式の右辺第２項）、ＯＰアンプ１４乃至１６の入力オフセット電圧Ｖio1乃至Ｖio3が増幅された電圧（第４式の右辺第3項、第４項）が差動入力型増幅回路１３の出力に現れる。 When the signals Vin10 and Vin20 at the time of magnetic non-detection are inputted to the signal input terminals 13a and 13b of the differential input type amplifier circuit 13, respectively, the output voltage Vdif0 of the differential input type amplifier circuit 13 becomes the fourth formula, and the bias Voltages obtained by amplifying the voltages Vib1 and Vib2 due to the magnetic field (second term on the right side of the fourth equation), and voltages obtained by amplifying the input offset voltages Vio1 to Vio3 of the OP amplifiers 14 to 16 (third term on the right side of the fourth equation) , The fourth term) appears at the output of the differential input type amplifier circuit 13.

（数４）
Ｖdif0 ＝ Ｖdd/2
−(Ｒ６/Ｒ５)・{１＋２・(Ｒ４/Ｒ３)}・(Ｖib1−Ｖib2）
−(Ｒ６/Ｒ５)・{１＋２・(Ｒ４/Ｒ３)}・(Ｖio1−Ｖio2)
＋(１＋Ｒ６/Ｒ５)・Ｖio3 ・・・ (４) (Equation 4)
Vdif0 = Vdd / 2
-(R6 / R5) ・ {1 + 2 ・ (R4 / R3)} ・ (Vib1-Vib2)
-(R6 / R5) ・ {1 + 2 ・ (R4 / R3)} ・ (Vio1−Vio2)
+ (1 + R6 / R5) ・ Vio3 (4)

出力電圧Ｖdif0は、増幅回路２の信号入力端子２ａに入力されるため、増幅回路２の出力電圧Ｖout0には、バイアス磁界に起因した電圧Ｖib1、Ｖib2が増幅された電圧およびＯＰアンプ１４乃至１６の入力オフセット電圧Ｖio1乃至Ｖio3が増幅された電圧、さらにＯＰアンプ４の入力オフセット電圧Ｖioが増幅された電圧が出力オフセット電圧として現れる。
その出力オフセット電圧は、実施例１と同様、オフセット調整回路３より生成された信号Ｖdaoを、増幅回路２の基準電圧入力端子２ｂに入力することにより、略０になるよう補正される。 Since the output voltage Vdif0 is input to the signal input terminal 2a of the amplifier circuit 2, the output voltage Vout0 of the amplifier circuit 2 includes the voltages obtained by amplifying the voltages Vib1 and Vib2 due to the bias magnetic field and the OP amplifiers 14 to 16. A voltage obtained by amplifying the input offset voltages Vio1 to Vio3 and a voltage obtained by amplifying the input offset voltage Vio of the OP amplifier 4 appear as output offset voltages.
As in the first embodiment, the output offset voltage is corrected to substantially zero by inputting the signal Vdao generated by the offset adjustment circuit 3 to the reference voltage input terminal 2b of the amplifier circuit 2.

本実施例によれば、実施例１と同様の効果が得られ、さらに、２つの磁気抵抗素子対から取り出される磁気検出信号の差分信号が差動入力型増幅回路１３に入力されるため、実施例１よりもＳ／Ｎ比の向上が期待できる。   According to the present embodiment, the same effect as that of the first embodiment can be obtained, and further, since the differential signal of the magnetic detection signals extracted from the two magnetoresistive element pairs is input to the differential input type amplifier circuit 13, An improvement in the S / N ratio can be expected compared to Example 1.

１ 磁気抵抗素子対（差動入力型増幅回路を含まない磁気検出回路）
２ 増幅回路
２ａ 増幅回路２の信号入力端子
２ｂ 増幅回路２の基準電圧入力端子
３ オフセット調整回路
４、１４、１５、１６ ＯＰアンプ
５ 参照電圧回路
６ コンパレータ
７ 逐次比較型ＤＡコンバータ
８ 制御回路
９、１７、１８、１９ 理想ＯＰアンプ
１０ 差動入力型増幅回路を含む磁気検出回路
１１、１２ 磁気抵抗素子対
１３ 差動入力型増幅回路
１３ａ、１３ｂ 差動入力型増幅回路１３の信号入力端子
1 Magnetoresistive element pair (Magnetic detection circuit not including differential input type amplifier circuit)
2 amplifier circuit 2a signal input terminal 2b of amplifier circuit 2 reference voltage input terminal 3 of amplifier circuit 2 offset adjustment circuit 4, 14, 15, 16 OP amplifier 5 reference voltage circuit 6 comparator 7 successive approximation DA converter 8 control circuit 9, 17, 18, 19 Ideal OP amplifier 10 Magnetic detection circuit 11, 12 including differential input type amplifier circuit Magnetoresistive element pair 13 Differential input type amplifier circuit 13 a, 13 b Signal input terminal of differential input type amplifier circuit 13

Claims (2)

磁気抵抗素子を含む磁気検出回路と、前記磁気検出回路にて取り出されるＤＣ成分を含む磁気検出信号を増幅して出力する増幅回路と、磁気非検出の状態での前記増幅回路の出力信号に基づき、前記磁気抵抗素子に印加したバイアス磁界に起因する電圧および前記増幅回路の入力オフセット電圧により発生する前記増幅回路の出力オフセット電圧を補正する電圧を生成して、前記増幅回路の基準電圧入力端子に前記信号を入力するオフセット調整回路を具備したことを特徴とする磁気センサ。 Based on a magnetic detection circuit including a magnetoresistive element, an amplification circuit for amplifying and outputting a magnetic detection signal including a DC component extracted by the magnetic detection circuit, and an output signal of the amplification circuit in a magnetic non-detection state Generating a voltage for correcting an output offset voltage of the amplifier circuit generated by a voltage caused by a bias magnetic field applied to the magnetoresistive element and an input offset voltage of the amplifier circuit, and generating a voltage at a reference voltage input terminal of the amplifier circuit A magnetic sensor comprising an offset adjustment circuit for inputting the signal. 前記オフセット調整回路は、磁気非検出の状態での前記増幅回路の出力電圧と参照電圧を比較するコンパレータと、前記コンパレータの出力に基づいて前記出力オフセット電圧を補正する信号を生成する逐次比較型ＤＡコンバータを具備したことを特徴とする請求項1記載の磁気センサ。



The offset adjustment circuit includes a comparator that compares the output voltage of the amplifier circuit in a magnetic non-detection state with a reference voltage, and a successive approximation DA that generates a signal for correcting the output offset voltage based on the output of the comparator. 2. The magnetic sensor according to claim 1, further comprising a converter.



JP2012196352A 2012-09-06 2012-09-06 Magnetic sensor Active JP6257019B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012196352A JP6257019B2 (en) 2012-09-06 2012-09-06 Magnetic sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012196352A JP6257019B2 (en) 2012-09-06 2012-09-06 Magnetic sensor

Publications (2)

Publication Number Publication Date
JP2014052262A true JP2014052262A (en) 2014-03-20
JP6257019B2 JP6257019B2 (en) 2018-01-10

Family

ID=50610859

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012196352A Active JP6257019B2 (en) 2012-09-06 2012-09-06 Magnetic sensor

Country Status (1)

Country Link
JP (1) JP6257019B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020008568A (en) * 2018-07-02 2020-01-16 旭化成エレクトロニクス株式会社 Magnetic field measuring device, magnetic field measuring method, and magnetic field measuring program
US10983179B2 (en) 2018-07-02 2021-04-20 Asahi Kasei Microdevices Corporation Magnetic field measuring device, magnetic field measurement method, and recording medium having recorded thereon magnetic field measurement program

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3866338B1 (en) * 2020-02-12 2024-03-06 TE Connectivity Sensors Germany GmbH Amplifier circuit and method for offset compensation

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5927414U (en) * 1982-08-11 1984-02-20 株式会社島津製作所 automatic level adjustment device
JPH02213783A (en) * 1989-02-14 1990-08-24 Shimadzu Corp Automatic zero point adjusting circuit
JPH10160810A (en) * 1996-11-27 1998-06-19 Shimadzu Corp Magnetism measuring apparatus
JP2004069655A (en) * 2002-08-09 2004-03-04 Denso Corp Adjustment method for offset of magnetic sensor
JP2009033638A (en) * 2007-07-30 2009-02-12 Fujitsu Microelectronics Ltd Amplifier circuit
US20090295373A1 (en) * 2008-05-30 2009-12-03 Infineon Technologies Ag Integrated circuit with tracking logic

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5927414U (en) * 1982-08-11 1984-02-20 株式会社島津製作所 automatic level adjustment device
JPH02213783A (en) * 1989-02-14 1990-08-24 Shimadzu Corp Automatic zero point adjusting circuit
JPH10160810A (en) * 1996-11-27 1998-06-19 Shimadzu Corp Magnetism measuring apparatus
JP2004069655A (en) * 2002-08-09 2004-03-04 Denso Corp Adjustment method for offset of magnetic sensor
JP2009033638A (en) * 2007-07-30 2009-02-12 Fujitsu Microelectronics Ltd Amplifier circuit
US20090295373A1 (en) * 2008-05-30 2009-12-03 Infineon Technologies Ag Integrated circuit with tracking logic

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020008568A (en) * 2018-07-02 2020-01-16 旭化成エレクトロニクス株式会社 Magnetic field measuring device, magnetic field measuring method, and magnetic field measuring program
US10983179B2 (en) 2018-07-02 2021-04-20 Asahi Kasei Microdevices Corporation Magnetic field measuring device, magnetic field measurement method, and recording medium having recorded thereon magnetic field measurement program
JP7082590B2 (en) 2018-07-02 2022-06-08 旭化成エレクトロニクス株式会社 Magnetic field measuring device, magnetic field measuring method, and magnetic field measuring program
US11391792B2 (en) 2018-07-02 2022-07-19 Asahi Kasei Microdevices Corporation Magnetic field measuring device, magnetic field measurement method, and recording medium having recorded thereon magnetic field measurement program

Also Published As

Publication number Publication date
JP6257019B2 (en) 2018-01-10

Similar Documents

Publication Publication Date Title
KR101127891B1 (en) Output amplifier circuit and sensor device using the same
US7750737B2 (en) Common mode stabilization in a fully differential amplifier
US9128127B2 (en) Sensor device
CN101083451A (en) Digital auto-calibration operational amplification offset voltage circuit and method thereof
KR102262379B1 (en) Sensor device
US20170131333A1 (en) Sensor circuit
KR20150095060A (en) Fully differential signal system including common mode feedback circuit
KR20230133904A (en) current sensing circuit
JP6257019B2 (en) Magnetic sensor
CN104007400A (en) Magnetic sensor device
CN109743032B (en) Inverting pseudo-fully differential amplifier with common-mode feedback control circuit
US11374544B2 (en) Capacitive-coupled chopper instrumentation amplifiers and associated methods
WO2022209720A1 (en) Sensor output compensation circuit
WO2022209797A1 (en) Sensor output compensation circuit
TW201637361A (en) Comparison circuit and sensor device
JP5284875B2 (en) Offset voltage correction circuit
US20170097377A1 (en) Impedance measuring circuit
KR20230170901A (en) Linearization of magnetic sensor output based on continuous correction of high-order voltage output components
EP2878927B1 (en) Sensor circuit for measuring a physical quantity
WO2019097870A1 (en) Instrumentation amplifier
US9817034B2 (en) Measuring device
CN111587533A (en) Common mode sensing architecture
US20240097632A1 (en) Integrated circuit and semiconductor device
Dutta et al. Low offset, low noise, variable gain interfacing circuit with a novel scheme for sensor sensitivity and offset compensation for MEMS based, Wheatstone bridge type, resistive smart sensor
WO2022209719A1 (en) Sensor output compensation circuit

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20150907

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20151125

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160713

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160816

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161013

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170411

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170609

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20170609

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20171107

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20171201

R150 Certificate of patent or registration of utility model

Ref document number: 6257019

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250