JP2013222781A - Device-mounting structure in semiconductor device - Google Patents

Device-mounting structure in semiconductor device Download PDF

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JP2013222781A
JP2013222781A JP2012092575A JP2012092575A JP2013222781A JP 2013222781 A JP2013222781 A JP 2013222781A JP 2012092575 A JP2012092575 A JP 2012092575A JP 2012092575 A JP2012092575 A JP 2012092575A JP 2013222781 A JP2013222781 A JP 2013222781A
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drain
die pad
source
lead
gate
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JP2013222781A5 (en
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Makoto Ijiri
良 井尻
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Sharp Corp
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Sharp Corp
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Priority to JP2012092575A priority Critical patent/JP2013222781A/en
Priority to PCT/JP2013/054757 priority patent/WO2013157300A1/en
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Publication of JP2013222781A5 publication Critical patent/JP2013222781A5/ja
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Abstract

PROBLEM TO BE SOLVED: To achieve a device-mounting structure capable of exploiting the merits of low power consumption and fast response characteristics of a semiconductor device in which GaN is used.SOLUTION: A surface-mounting type device-mounting structure is employed, the rear surface of a GaN chip 30 is electrically connected to the front surface of a die pad 14, and the connection between the die pad 14 and a source terminal 11 of the chip 30 is established by wire bonding. The die pad 14 has the rear surface exposed and is configured so as to be capable of being electrically connected to an electrode pad (source pad) on a printed board. Consequently, leak current from the chip rear surface is reduced, on-resistance is decreased, loop current between a gate and a source is reduced, and parasitic inductance on a source wiring side is decreased, thereby suppressing gate voltage oscillation via a parasitic capacitance between the gate and the source.

Description

本発明は、半導体装置に関し、特に、ＧａＮを用いるパワーデバイスチップをフレームに搭載する場合のデバイスの実装構造に関する。   The present invention relates to a semiconductor device, and more particularly to a device mounting structure when a power device chip using GaN is mounted on a frame.

ＧａＮ（窒化ガリウム）に代表される、バンドギャップが２ｅＶを超えるワイドギャップ半導体を用いたデバイスは、従来のＳｉを用いるデバイスと比較して、低消費電力であり、高速スイッチングが可能という利点を備えている。これは、デバイスの絶縁破壊電界が大きいという理由による。   Devices using wide gap semiconductors with a band gap exceeding 2 eV, represented by GaN (gallium nitride), have the advantages of low power consumption and high-speed switching compared with devices using conventional Si. ing. This is because the breakdown electric field of the device is large.

一般に、デバイスの耐圧はドリフト層の長さ（ＷＤ）と絶縁破壊電界（Ｅｃ）の積により表される。従って、耐圧を同じとした場合、絶縁破壊電界が大きい方がドリフト層の長さを短くできる。ここで、ワイドギャップ半導体において、絶縁破壊電界はＳｉよりも１０倍程度高いため、ドリフト層の長さをおよそ１／１０にすることができる。また、不純物濃度は絶縁破壊電界の２乗に比例するため、Ｓｉと比べて１００倍に高くすることができる。以上より、耐圧を同じとした場合、ワイドギャップ半導体を用いたデバイスのオン抵抗（Ｒｏｎ）は、Ｓｉを用いるデバイスと比較して約１／１０００に低抵抗化が可能となる。   In general, the breakdown voltage of a device is represented by the product of the drift layer length (WD) and the breakdown electric field (Ec). Therefore, when the breakdown voltage is the same, the length of the drift layer can be shortened when the breakdown electric field is large. Here, in the wide gap semiconductor, since the dielectric breakdown electric field is about 10 times higher than Si, the length of the drift layer can be reduced to about 1/10. Further, since the impurity concentration is proportional to the square of the dielectric breakdown electric field, it can be made 100 times higher than Si. As described above, when the breakdown voltage is the same, the on-resistance (Ron) of the device using the wide gap semiconductor can be reduced to about 1/1000 compared to the device using Si.

一方、デバイスの高速応答性を表す指標として、遮断周波数（ｆＴ）という指標がある。当該遮断周波数はデバイスの電流利得が１となる周波数であり、ドリフト層の長さＷＤに反比例する。従って、ワイドギャップ半導体を用いるデバイスでは、ドリフト層の長さをＳｉと比べて１／１０に設定できることにより、Ｓｉよりも一桁高い周波数で使用することが可能となる。   On the other hand, there is an index called cutoff frequency (fT) as an index representing the high-speed response of the device. The cutoff frequency is a frequency at which the current gain of the device is 1, and is inversely proportional to the length WD of the drift layer. Therefore, in a device using a wide gap semiconductor, since the length of the drift layer can be set to 1/10 compared to Si, it can be used at a frequency one digit higher than Si.

このように、ワイドギャップ半導体を用いることで、Ｓｉと比較してオン抵抗が低く、結果低消費電力で、且つ、高速性に優れたデバイスが可能である。   As described above, by using a wide gap semiconductor, a device having a low on-resistance as compared with Si, resulting in low power consumption and excellent high-speed performance is possible.

上記のワイドギャップ半導体を用いるデバイスの実装方法として、下記特許文献１および２に示すように、ドレインリードとダイパッドを接続したリードフレームのダイパッド上にデバイスを固定し、デバイスとドレインリード、ソースリード、及び、ゲートリードとの接続をワイヤボンディングにより行う方法が、従来より用いられてきた。   As a device mounting method using the above wide gap semiconductor, as shown in Patent Documents 1 and 2, the device is fixed on the die pad of the lead frame in which the drain lead and the die pad are connected, and the device and the drain lead, the source lead, A method of connecting to the gate lead by wire bonding has been conventionally used.

図８に、かかる従来構成の方法でチップ実装を行う場合の樹脂封止（モールド）される前のリードフレームとＧａＮチップ３０とのワイヤボンディングの状態を示す平面図を示す。   FIG. 8 is a plan view showing a state of wire bonding between the lead frame and the GaN chip 30 before resin sealing (molding) when chip mounting is performed by the method of the conventional configuration.

従来例では、図８に示すように、ドレインリード１６とダイパッド１４が一体成形されたリードフレームを用いて、ドレイン端子１２とドレインリード１６の接続が、ドレイン端子１２とダイパッド１４をワイヤボンディングすることによりなされている。一方、ソースリード１５及びゲートリード１７は、夫々、ダイパッド１４と分離形成され、ソースリード１５とソース端子１１、ゲートリード１７とゲート端子１３との接続が、ワイヤボンディングによりなされている。   In the conventional example, as shown in FIG. 8, using a lead frame in which the drain lead 16 and the die pad 14 are integrally formed, the drain terminal 12 and the drain lead 16 are connected by wire bonding the drain terminal 12 and the die pad 14. It is made by. On the other hand, the source lead 15 and the gate lead 17 are formed separately from the die pad 14, and the source lead 15 and the source terminal 11 and the gate lead 17 and the gate terminal 13 are connected by wire bonding.

特開２００８−６６５５３号公報JP 2008-66553 A 特開２０１０−１６１０３号公報JP 2010-16103 A

従来のＳｉパワーデバイスでは、ゲート注入電荷量Ｑｇが大きいため、寄生発振が起こるような大きなインダクタンスは回路側で対応が可能であり、デバイス実装において、回路の寄生インダクタンスについて特別の注意を払う必要がなかった。   In the conventional Si power device, since the gate injection charge amount Qg is large, a large inductance that causes parasitic oscillation can be dealt with on the circuit side, and it is necessary to pay special attention to the parasitic inductance of the circuit when mounting the device. There wasn't.

ところが、ＧａＮを用いたデバイスでは、ゲート注入電荷量Ｑｇが非常に小さいため、単なる配線の寄生インダクタンスであってもゲート電圧が発振する虞がある。すなわち、一般に用いられるソースリード、ドレインリード、ゲートリードの長さにより生じる寄生インダクタンスであっても、ゲート電圧の発振が問題になる。   However, in a device using GaN, since the gate injection charge amount Qg is very small, there is a possibility that the gate voltage oscillates even if the parasitic inductance of the wiring is simple. That is, oscillation of the gate voltage becomes a problem even with the parasitic inductance caused by the length of the commonly used source lead, drain lead, and gate lead.

これに対し、ゲート抵抗として大きなものをゲート端子に接続することで発振は抑制できるが、ＧａＮの低消費電力、高速応答性の長所を生かすことができない結果となる。   On the other hand, oscillation can be suppressed by connecting a large gate resistance to the gate terminal, but the advantages of low power consumption and high-speed response of GaN cannot be utilized.

本発明は、上記の状況に鑑み、ＧａＮを用いたデバイスにおいて、大きなゲート抵抗を付加することなく寄生発振を抑制できるように、デバイス実装構造の面から寄生インダクタンスの低減を実現するものであり、これにより、ＧａＮの特徴である低消費電力、高速応答特性を生かしたパワーデバイスを実現することを目的とする。   In view of the above situation, the present invention realizes a reduction in parasitic inductance from the surface of a device mounting structure so that parasitic oscillation can be suppressed without adding a large gate resistance in a device using GaN. Accordingly, it is an object to realize a power device that takes advantage of the low power consumption and high-speed response characteristics that are characteristic of GaN.

上記目的を達成するための本発明に係る半導体装置は、
ソース端子、ドレイン端子、ゲート端子の少なくとも三端子が基板表面側に設けられた、ＧａＮを用いるパワーデバイスを搭載してなる半導体装置であって、
前記パワーデバイスが、表面実装タイプのリードフレームのダイパッド部の表面側に固定され、 前記パワーデバイスの前記ソース端子が前記ダイパッド部とワイヤ接続され、
前記パワーデバイスの前記ドレイン端子がドレインリードと、前記パワーデバイスの前記ゲート端子がゲートリードとワイヤ接続され、前記ダイパッド部の裏面がプリント基板上のソースパッドと接続するために露出したデバイス実装構造を有することを特徴とする。 In order to achieve the above object, a semiconductor device according to the present invention provides:
A semiconductor device comprising a power device using GaN, wherein at least three terminals of a source terminal, a drain terminal, and a gate terminal are provided on the substrate surface side,
The power device is fixed to a surface side of a die pad portion of a surface mount type lead frame, and the source terminal of the power device is wire-connected to the die pad portion,
A device mounting structure in which the drain terminal of the power device is connected to a drain lead, the gate terminal of the power device is connected to a gate lead, and the back surface of the die pad portion is exposed to connect to a source pad on a printed circuit board. It is characterized by having.

上記特徴の半導体装置は、更に、前記ソース端子と前記ダイパッド部とのワイヤ接続における前記ダイパッド部側のワイヤとの接続位置に対応する裏面側が露出していることが好ましい。   In the semiconductor device having the above characteristics, it is preferable that the back surface side corresponding to the connection position of the wire on the die pad portion side in the wire connection between the source terminal and the die pad portion is exposed.

上記特徴の半導体装置は、更に、前記ドレインリード内の樹脂封止されるインナーリード部分の面積が、前記ゲートリード内の樹脂封止されるインナーリード部分の面積よりも大きいことが好ましい。   In the semiconductor device having the above characteristics, it is preferable that the area of the inner lead portion to be resin-sealed in the drain lead is larger than the area of the inner lead portion to be resin-sealed in the gate lead.

上記特徴の半導体装置は、更に、前記ドレイン端子の長手方向に対して平行となるように前記ドレインリードが配置され、前記パワーデバイスの前記ダイパッド部上の位置が、前記ドレインリードが延伸する直線の延長線上に前記ドレイン端子があるように、且つ、前記ドレインリード側に片寄って配置されていることが好ましい。   In the semiconductor device having the above characteristics, the drain lead is arranged so as to be parallel to the longitudinal direction of the drain terminal, and the position on the die pad portion of the power device is a straight line extending the drain lead. It is preferable that the drain terminal is arranged on an extension line and is offset from the drain lead side.

上記特徴の半導体装置は、更に、前記パワーデバイスを構成するトランジスタが、
前記ソース端子と接続するソース電極、前記ドレイン端子と接続するドレイン電極、及び、前記ゲート端子と接続するゲート電極を備え、前記ゲート電極が前記ドレイン電極よりも前記ソース電極側に片寄って配置される非対称構造を有することが好ましい。 In the semiconductor device having the above characteristics, the transistor constituting the power device further includes:
A source electrode connected to the source terminal; a drain electrode connected to the drain terminal; and a gate electrode connected to the gate terminal, wherein the gate electrode is disposed closer to the source electrode side than the drain electrode. It preferably has an asymmetric structure.

上記特徴の半導体装置は、更に、前記ダイパッド部の裏面の露出部分には、前記ドレインリードよりも低電圧が供給されることが好ましい。   In the semiconductor device having the above characteristics, it is preferable that a lower voltage than the drain lead is supplied to the exposed portion of the back surface of the die pad portion.

本発明者等は、鋭意研究により、ソース側配線の寄生インダクタンスを小さくすることで、発振が抑制され、ゲート電圧のオンオフに対して安定なスイッチングが可能になることを見出した。   The inventors of the present invention have intensively researched and found that by reducing the parasitic inductance of the source-side wiring, oscillation is suppressed and stable switching can be performed with respect to on / off of the gate voltage.

図９にシミュレーションに用いた回路の構成を示す。Ｌｄ、Ｌｓ１、Ｌｓ２、Ｌｇｓは夫々配線の寄生インダクタンスであり、Ｃｇｄ，Ｃｇｓ，Ｃｄｓは夫々ＧａＮ−ＦＥＴの寄生容量である。図９において、ＦＥＴがオンからオフに、オフからオンに切り替わると、ＬｄからＣｏｓｓ、Ｌｓ１、及びＬｓ２を介したＬＣ直列回路が共振する。結果、Ｌｓ１の両端電圧が振動する。かかるＬｓ１の両端電圧の振動は、ゲートドライバにとって電圧ノイズ源となる。   FIG. 9 shows the configuration of the circuit used for the simulation. Ld, Ls1, Ls2, and Lgs are parasitic inductances of wirings, respectively, and Cgd, Cgs, and Cds are parasitic capacitances of GaN-FETs. In FIG. 9, when the FET is switched from on to off and from off to on, the LC series circuit from Ld to Coss, Ls1, and Ls2 resonates. As a result, the voltage across Ls1 vibrates. Such oscillation of the voltage across Ls1 becomes a voltage noise source for the gate driver.

更に、Ｌｓ１の両端電圧が振動することにより、ＣｇｓとＬｓ１を介したＬＣ直列回路が共振し、ゲート電圧Ｖｇが振動する。この結果、ＦＥＴの意図しないオンオフが繰り返され、これが更にＬｄからＣｏｓｓ、Ｌｓ１、及びＬｓ２を介したＬＣ直列回路の共振を引き起こす。   Furthermore, when the voltage across Ls1 vibrates, the LC series circuit via Cgs and Ls1 resonates, and the gate voltage Vg vibrates. As a result, unintended ON / OFF of the FET is repeated, which further causes resonance of the LC series circuit from Ld to Coss, Ls1, and Ls2.

このように、ＬｄからＣｏｓｓ、Ｌｓ１、及びＬｓ２を介したＬＣ直列回路の共振と、ＣｇｓとＬｓ１を介したＬＣ直列回路の共振が相互に誘起される結果、ゲート電圧Ｖｇの振動が増幅され、スイッチングノイズが増加し、最悪の場合ＦＥＴが発振して回路が破壊される虞がある。   As described above, the resonance of the LC series circuit via Loss and Coss, Ls1, and Ls2 and the resonance of the LC series circuit via Cgs and Ls1 are mutually induced. As a result, the oscillation of the gate voltage Vg is amplified. The switching noise increases, and in the worst case, the FET may oscillate and the circuit may be destroyed.

上記のＬＣ回路による共振を防ぐには、ＬｄとＬｓ１（及び、Ｌｓ２）をできる限り小さくすればよいことが推察される。   It can be inferred that Ld and Ls1 (and Ls2) should be as small as possible in order to prevent resonance by the LC circuit.

図１０は、ソース側配線の寄生インダクタンスＬｓ１、及び、ドレイン側配線の寄生インダクタンスＬｄを変えた場合の、スイッチング時のゲート電圧の立ち上がり、立ち下がりの電圧変化をシミュレーションした結果である。図１０より、ドレイン側配線の寄生インダクタンスＬｄを小さくする（図１０（ｂ））よりも、むしろソース側配線の寄生インダクタンスＬｓ１を小さくした（図１０（ａ））方が、ゲート電圧の振動防止に著しい効果があることが分かる。   FIG. 10 shows the result of simulating the rise and fall of the gate voltage during switching when the parasitic inductance Ls1 of the source side wiring and the parasitic inductance Ld of the drain side wiring are changed. From FIG. 10, the gate voltage oscillation is prevented by reducing the parasitic inductance Ls1 of the source wiring (FIG. 10A) rather than reducing the parasitic inductance Ld of the drain wiring (FIG. 10B). It can be seen that there is a remarkable effect.

図１１は、図１０においてＦＥＴに生じる電力損失（＝Ｉｆｅｔ＊Ｖｄ）を示す図であり、図１１より、ドレイン側配線の寄生インダクタンスＬｄを小さくする（図１１（ｂ））よりも、ソース側配線の寄生インダクタンスＬｓ１を小さくした（図１１（ａ））方が、損失も少ないことが分かる。   FIG. 11 is a diagram showing the power loss (= Ifet * Vd) generated in the FET in FIG. 10, and the parasitic inductance Ld of the drain side wiring is made smaller than that in FIG. 11 (FIG. 11 (b)). It can be seen that the loss is smaller when the parasitic inductance Ls1 of the wiring is reduced (FIG. 11A).

上記の知見に基づき、本発明では、デバイスの実装方法を変更し、表面実装型のデバイス実装構造において、ＧａＮチップ裏面をダイパッド部の表面と電気的に接続し、かかるダイパッド部とデバイスのソース端子との接続をワイヤボンディングにより行うこととした。ダイパッド部は、裏面が露出しており、プリント基板上の電極パッド（ソースパッド）と電気的に接続可能に構成されている。   Based on the above knowledge, in the present invention, the device mounting method is changed, and in the surface mounting type device mounting structure, the back surface of the GaN chip is electrically connected to the surface of the die pad portion, and the die pad portion and the source terminal of the device are connected. It was decided to make a connection with the wire bonding. The back surface of the die pad portion is exposed, and the die pad portion can be electrically connected to an electrode pad (source pad) on the printed circuit board.

このような構成とした場合、ダイパッド部の厚みが従来構成におけるソースリードの長さに相当するため、ソース側配線の寄生インダクタンスが大幅に低減され、ゲート電圧の発振を抑制できる。また、従来のソースリードがダイパッド厚みまで短くなるため、オン抵抗を小さくすることができる。   In such a configuration, since the thickness of the die pad portion corresponds to the length of the source lead in the conventional configuration, the parasitic inductance of the source side wiring is greatly reduced, and oscillation of the gate voltage can be suppressed. Further, since the conventional source lead is shortened to the die pad thickness, the on-resistance can be reduced.

さらに、従来のダイパッドとドレインリードを一体成形した構造と比較して、ＧａＮチップのソース端子とチップ裏面の電位差を小さくできるため、チップ裏面からのリーク電流を減らすことができる。また、ゲート−ソース間のループ電流が小さくなることでソース配線の寄生インダクタンスに起因した電圧変動（誘導電圧）が抑制され、Ｃｇｓを介したＬＣ直列回路の発振を抑えることができる。   Furthermore, since the potential difference between the source terminal of the GaN chip and the back surface of the chip can be reduced as compared with the structure in which the conventional die pad and drain lead are integrally formed, the leakage current from the back surface of the chip can be reduced. Further, since the loop current between the gate and the source is reduced, voltage fluctuation (induced voltage) due to the parasitic inductance of the source wiring is suppressed, and oscillation of the LC series circuit via Cgs can be suppressed.

従って、本発明に依れば、ＧａＮを用いたデバイスにおいて、大きなゲート抵抗を付加することなく寄生発振を抑制でき、ＧａＮの特徴である低消費電力、高速応答特性を生かしたパワーデバイスを実現することができる。   Therefore, according to the present invention, in a device using GaN, parasitic oscillation can be suppressed without adding a large gate resistance, and a power device utilizing the low power consumption and high-speed response characteristics of GaN is realized. be able to.

本発明に係る半導体装置のチップ実装例を示す樹脂封止前の平面図The top view before resin sealing which shows the chip mounting example of the semiconductor device which concerns on this invention 本発明に係る半導体装置のチップ実装例を示す樹脂封止後の鳥瞰図Bird's-eye view after resin sealing showing a chip mounting example of a semiconductor device according to the present invention 本発明に係る半導体装置のチップ実装例を示す樹脂封止後の断面図Sectional drawing after resin sealing showing a chip mounting example of a semiconductor device according to the present invention ＧａＮを用いるパワーデバイスのデバイス構造を示す断面図。Sectional drawing which shows the device structure of the power device using GaN. ＧａＮパワーデバイスにおいて、基板電位とソース電圧との電位差に対するリーク電流の依存性を示すグラフGraph showing the dependence of leakage current on the potential difference between the substrate potential and the source voltage in a GaN power device 本発明に係る半導体装置の他のチップ実装例を示す樹脂封止前の平面図The top view before resin sealing which shows the other chip mounting example of the semiconductor device which concerns on this invention 本発明に係る半導体装置の他のチップ実装例を示す樹脂封止前の平面図The top view before resin sealing which shows the other chip mounting example of the semiconductor device which concerns on this invention 従来技術に係る半導体装置のチップ実装例を示す樹脂封止前の平面図Plan view before resin sealing showing a chip mounting example of a semiconductor device according to the prior art 本発明の課題を説明するための回路図The circuit diagram for explaining the subject of the present invention 本発明の効果を説明するためのグラフであり、スイッチング時のゲート電圧の立ち上がり及び立ち下がりの、ゲート電圧の変化を示すグラフIt is a graph for demonstrating the effect of this invention, and is a graph which shows the change of the gate voltage of the rise and fall of the gate voltage at the time of switching 本発明の効果を説明するためのグラフであり、スイッチング時においてＦＥＴに生じる電力損失の時間変化を示すグラフIt is a graph for demonstrating the effect of this invention, and is a graph which shows the time change of the power loss which arises in FET at the time of switching

本発明のチップ実装構造を有する半導体装置１０の構成例を図１〜図３に示す。図１〜図３は、半導体装置１０の実装後の形態を示す模式図である。図１は、樹脂封止（モールド）される前のリードフレームとＧａＮチップとのワイヤボンディングの状態を示す平面図である。図２は、樹脂封止後の半導体装置１０をプリント基板上に実装した状態を示す鳥瞰図である。また、図３は図１及び図２のＡ−Ａ’方向（ドレイン端子１２及びドレインリード１６上で、ドレインリード１６に平行な方向）並びにＢ−Ｂ’方向（ソース端子１１上で、ドレインリード１６に平行な方向）のプリント基板３１に垂直な面における断面図である。なお、以降の実施形態の説明に用いる図面では、同一の構成要素には同一の符号を付すこととし、また、名称及び機能も同一であるので、同様の説明を繰り返すことはしない。   A configuration example of the semiconductor device 10 having the chip mounting structure of the present invention is shown in FIGS. 1 to 3 are schematic views showing a form after the semiconductor device 10 is mounted. FIG. 1 is a plan view showing a state of wire bonding between a lead frame and a GaN chip before resin sealing (molding). FIG. 2 is a bird's-eye view showing a state where the semiconductor device 10 after resin sealing is mounted on a printed board. 3 shows the direction of AA ′ (on the drain terminal 12 and the drain lead 16 and the direction parallel to the drain lead 16) and the direction of BB ′ (on the source terminal 11, the drain lead of FIG. 1 and FIG. 2). 16 is a cross-sectional view in a plane perpendicular to the printed circuit board 31 (in a direction parallel to 16). In the drawings used for the description of the following embodiments, the same components are denoted by the same reference numerals, and the names and functions are also the same, so the same description will not be repeated.

半導体装置１０は、ＧａＮを用いて構成されるパワーデバイスであり、基板表面側に、ソース端子１１、ドレイン端子１２、ゲート端子１３が形成されたチップ３０を備える。   The semiconductor device 10 is a power device configured using GaN, and includes a chip 30 on which a source terminal 11, a drain terminal 12, and a gate terminal 13 are formed on the substrate surface side.

一例として、ＧａＮを用いるパワーデバイスのデバイス構造の模式的な断面図を図４に示す。図４に示すデバイスは、ＨＥＭＴ(High Electron Mobility Transistor)構造のＦＥＴであり、Ｓｉ基板２０上に、ＡｌとＧａの組成比が異なるＡｌＧａＮの多層膜からなるバッファ層２１を介してＧａＮ層２２が積層され、ＧａＮ層２２の上にＡｌＧａＮの層２３が積層されている。ＧａＮ層２２上の所定の領域には、ＡｌＧａＮ層２３を貫通するようにソース電極２４とドレイン電極２５が形成され、ゲート電極２６が、ＡｌＧａＮ層２３上の所定の領域に、ソース電極２４とドレイン電極２５がゲート電極２６を挟んで互いに対向するように形成されている。ドレイン電極２５は、絶縁膜２７上に形成されたドレイン端子１２と、コンタクトホール２８を介して電気的に接続される。同様に、図示しないが、ソース電極２４は、別の断面において、絶縁膜２７上に形成されたソース端子１１と電気的に接続され、ゲート電極２５は、更に別の断面において、絶縁膜２７上に形成されたゲート端子１３と電気的に接続される。   As an example, FIG. 4 shows a schematic cross-sectional view of a device structure of a power device using GaN. The device shown in FIG. 4 is an FET having a HEMT (High Electron Mobility Transistor) structure, and a GaN layer 22 is formed on a Si substrate 20 via a buffer layer 21 made of an AlGaN multilayer film having different composition ratios of Al and Ga. The AlGaN layer 23 is laminated on the GaN layer 22. A source electrode 24 and a drain electrode 25 are formed in a predetermined region on the GaN layer 22 so as to penetrate the AlGaN layer 23, and a gate electrode 26 is formed in the predetermined region on the AlGaN layer 23. The electrodes 25 are formed so as to face each other with the gate electrode 26 interposed therebetween. The drain electrode 25 is electrically connected to the drain terminal 12 formed on the insulating film 27 through the contact hole 28. Similarly, although not shown, the source electrode 24 is electrically connected to the source terminal 11 formed on the insulating film 27 in another cross section, and the gate electrode 25 is formed on the insulating film 27 in another cross section. Are electrically connected to the gate terminal 13 formed in the circuit.

ＡｌＧａＮ層２３とＧａＮ層２２とのヘテロ接合界面近傍において、２次元電子ガス層２９が形成され、ゲート電極２６に電圧（ゲート電圧）を印加することで、かかるゲート電極２６の下方の２次元電子ガス層２９の濃度が変調され、ソース電極２４とドレイン電極２５間に流れる電流が制御される。通常の使用では、ドレイン電極２５には、ソース電極２４に対して２００Ｖ〜６００Ｖ程度の高電圧が印加される。また、図４に示すデバイスは、ドレイン電極２５に印加される電圧とゲート電圧との差が高電圧となるため、放電しないようにゲート電極２６とドレイン電極２５との距離を、ゲート電極２６とソース電極２４との距離よりも大きくとり、ゲート電極２６がドレイン電極２５よりもソース電極２４側に片寄って配置された非対称なデバイス構造を有している。   In the vicinity of the heterojunction interface between the AlGaN layer 23 and the GaN layer 22, a two-dimensional electron gas layer 29 is formed. By applying a voltage (gate voltage) to the gate electrode 26, two-dimensional electrons below the gate electrode 26 are formed. The concentration of the gas layer 29 is modulated, and the current flowing between the source electrode 24 and the drain electrode 25 is controlled. In normal use, a high voltage of about 200 V to 600 V is applied to the drain electrode 25 with respect to the source electrode 24. In the device shown in FIG. 4, since the difference between the voltage applied to the drain electrode 25 and the gate voltage becomes a high voltage, the distance between the gate electrode 26 and the drain electrode 25 is set so as not to discharge. The device has an asymmetric device structure in which the gate electrode 26 is arranged closer to the source electrode 24 side than the drain electrode 25 with a distance greater than the distance from the source electrode 24.

図１〜図３に戻って、チップ３０は、図３に示す導電性の接着材料３３によりダイパッド１４の表面に固定されている。図１に示すように、ダイパッド１４に隣接して、ドレインリード１６、及び、ゲートリード１７が配置され、ドレインリード１６はチップ３０のドレイン端子１２と、ゲートリード１７はチップ３０のゲート端子１３と、夫々ワイヤ接続（ワイヤボンディング）されている。さらに、ダイパッド１４の表面側で、ソース端子１１とダイパッド１４との接続がワイヤボンディングによりなされている。そして、図１の点線で示す領域１８内において、ワイヤ接続される部分を覆うように封止樹脂３４で封止がされ、半導体装置１０がパッケージされる。   1 to 3, the chip 30 is fixed to the surface of the die pad 14 by the conductive adhesive material 33 shown in FIG. 3. As shown in FIG. 1, a drain lead 16 and a gate lead 17 are disposed adjacent to the die pad 14. The drain lead 16 is connected to the drain terminal 12 of the chip 30, and the gate lead 17 is connected to the gate terminal 13 of the chip 30. These are respectively connected by wires (wire bonding). Further, the source terminal 11 and the die pad 14 are connected by wire bonding on the surface side of the die pad 14. Then, in a region 18 indicated by a dotted line in FIG. 1, the semiconductor device 10 is packaged by sealing with a sealing resin 34 so as to cover a wire-connected portion.

このようにしてパッケージされた半導体装置１０は、ダイパッド１４の裏面に露出部分１９を有している。本実施形態では、半導体装置１０は、ダイパッド１４の裏面がモールド材により覆わる領域を除いて、ダイパッド１４の裏面の金属部分が露出してプリント基板３１上の電極パッドと電気的に接続可能に構成されている。図２及び図３に示すように、ドレインリード１６、及び、ゲートリード１７を、夫々、プリント基板３１上に形成された配線（電極パッド）３２ａ、３２ｂと接続し、ダイパッド１４の裏面のかかる露出部分を、プリント基板３１上に形成された配線（ソースパッド）３２ｃと接続することで、プリント基板３１上に半導体装置１０が実装される。   The semiconductor device 10 packaged in this way has an exposed portion 19 on the back surface of the die pad 14. In the present embodiment, the semiconductor device 10 can be electrically connected to the electrode pad on the printed circuit board 31 by exposing the metal portion of the back surface of the die pad 14 except for the region where the back surface of the die pad 14 is covered with the molding material. It is configured. As shown in FIGS. 2 and 3, the drain lead 16 and the gate lead 17 are connected to wirings (electrode pads) 32 a and 32 b formed on the printed circuit board 31, respectively, and the back surface of the die pad 14 is exposed. The semiconductor device 10 is mounted on the printed circuit board 31 by connecting the portion with a wiring (source pad) 32 c formed on the printed circuit board 31.

半導体装置１０では、ソース端子１１とプリント基板３１上のソースパッド３２ｃとの接続が、ソース端子１１とダイパッド１４とをワイヤボンディングし、ダイパッド１４の裏面の露出部分をソースパッド３２ｃに接触することによりなされている。つまり、ダイパッド１４は、従来構成（図８）におけるソースリードに相当するものである。しかしながら、ダイパッド１４内において電流は平板内を主として膜厚方向に流れるため、ダイパッド１４で生じる寄生インダクタンスは非常に小さくなる。   In the semiconductor device 10, the source terminal 11 and the source pad 32 c on the printed circuit board 31 are connected by wire bonding the source terminal 11 and the die pad 14, and the exposed portion on the back surface of the die pad 14 is brought into contact with the source pad 32 c. Has been made. That is, the die pad 14 corresponds to the source lead in the conventional configuration (FIG. 8). However, since the current flows in the die pad 14 mainly in the film thickness direction in the flat plate, the parasitic inductance generated in the die pad 14 becomes very small.

このとき、ソース端子１１とダイパッド１４とのワイヤボンディングにおけるダイパッド１４側のワイヤとの接続位置（図３の位置Ｘ）は、その対応する裏面側が露出している位置に設定されている。これにより、ワイヤからソースパッド３２ｃに流れるダイパッド１４内の電流経路が最短となり、ダイパッド１４内における電流の殆どは膜厚方向に流れる。この結果、ダイパッド１４内において平板に平行に流れる電流成分を最低限にでき、平板に平行に流れる電流の寄生インダクタンスへの寄与を最小限にできる。   At this time, the connection position (position X in FIG. 3) of the wire on the die pad 14 side in wire bonding between the source terminal 11 and the die pad 14 is set to a position where the corresponding back surface side is exposed. As a result, the current path in the die pad 14 flowing from the wire to the source pad 32c becomes the shortest, and most of the current in the die pad 14 flows in the film thickness direction. As a result, the current component flowing parallel to the flat plate in the die pad 14 can be minimized, and the contribution of the current flowing parallel to the flat plate to the parasitic inductance can be minimized.

つまり、ダイパッド１４の厚みが従来構成におけるソースリードの長さに相当するため、ソース側配線の寄生インダクタンスが大幅に低減され、ゲート電圧の発振を抑制できる。   That is, since the thickness of the die pad 14 corresponds to the length of the source lead in the conventional configuration, the parasitic inductance of the source side wiring is greatly reduced, and the oscillation of the gate voltage can be suppressed.

具体的には、従来のソースリードの長さを１５ｍｍ、ダイパッドの厚みを１．５ｍｍとして、インダクダンスが電流経路の長さに比例するとした場合、寄生インダクタンスを１／１０に低減できる。   Specifically, when the length of the conventional source lead is 15 mm and the thickness of the die pad is 1.5 mm and the inductance is proportional to the length of the current path, the parasitic inductance can be reduced to 1/10.

さらに、半導体装置１０では、ソース端子１１とダイパッド１４がワイヤボンディングされて接続されているため、ダイパッド１４を介して基板２０の電位がソース電圧に固定され、これにより、チップ裏面とソース電極２４との間を、基板２０、バッファ層２１、及びＧａＮ層２２の端部側壁を経由して流れるリーク電流を低減できる。   Further, in the semiconductor device 10, since the source terminal 11 and the die pad 14 are connected by wire bonding, the potential of the substrate 20 is fixed to the source voltage via the die pad 14, whereby the chip back surface, the source electrode 24, Leakage current flowing between the substrate 20, the buffer layer 21, and the end side walls of the GaN layer 22 can be reduced.

図５に、ソース端子１１を介してソース電極２４に印加するソース電圧を基準として、基板２０に与える電圧Ｖｓｕｂを変化させたときの、ドレイン電圧Ｖｄとチップ裏面に流れるリーク電流Ｉｓｕｂとの依存性を示す。図５から、基板２０の電位とソース電圧に電位差があるとリーク電流が大きくなり、基板２０の電位をソース電圧と同電位とすることにより、リーク電流を大幅に抑制できることが分かる。   FIG. 5 shows the dependence of the drain voltage Vd and the leakage current Isub flowing on the back surface of the chip when the voltage Vsub applied to the substrate 20 is changed with reference to the source voltage applied to the source electrode 24 via the source terminal 11. Indicates. From FIG. 5, it can be seen that if there is a potential difference between the potential of the substrate 20 and the source voltage, the leakage current increases, and the leakage current can be significantly suppressed by making the potential of the substrate 20 the same as the source voltage.

なお、かかるリーク電流の防止の観点からは、ソース電極２４を、ドレイン電極２５の全周を囲むようにチップの周辺部に配置するとよい。これにより、チップ３０の端部側壁を経由してチップ裏面とドレイン電極間に流れるリーク電流のパスが存在しないため、リーク電流を効果的に抑制できる。   From the viewpoint of preventing such a leakage current, the source electrode 24 may be disposed in the peripheral portion of the chip so as to surround the entire circumference of the drain electrode 25. As a result, there is no leakage current path flowing between the chip back surface and the drain electrode via the end side wall of the chip 30, so that the leakage current can be effectively suppressed.

さらに、図１に示す半導体装置１０では、チップ３０をダイパッド１４の中央に配置せず、ドレイン端子１２とドレインリード１６の距離が最適化されるように、チップ３０のダイパッド１４上の位置を、ドレインリード１６側に片寄らせ、且つ、ドレインリード１６が延伸する直線の延長線上にドレイン端子１２があるように配置している。ドレイン端子１２の平面レイアウト形状が長方形である場合、ドレイン端子１２の長手方向に対して略平行となるようにドレインリード１５を配置し、チップをドレインリード１６に近づけて配置するとよい。これにより、ドレイン端子１２とドレインリード１６とをワイヤボンディングするワイヤの曲げ角を小さくでき、また、長さを短くできる。この結果、ソース配線側の寄生インダクタンスと併せて、ドレイン配線側の寄生インダクタンスを低減することが可能になる。   Further, in the semiconductor device 10 shown in FIG. 1, the position of the chip 30 on the die pad 14 is adjusted so that the distance between the drain terminal 12 and the drain lead 16 is optimized without arranging the chip 30 in the center of the die pad 14. The drain terminal 16 is shifted toward the drain lead 16 side, and the drain terminal 12 is arranged on a straight line extending from the drain lead 16. When the planar layout of the drain terminal 12 is rectangular, the drain lead 15 may be disposed so as to be substantially parallel to the longitudinal direction of the drain terminal 12 and the chip may be disposed close to the drain lead 16. Thereby, the bending angle of the wire for wire bonding the drain terminal 12 and the drain lead 16 can be reduced, and the length can be shortened. As a result, the parasitic inductance on the drain wiring side can be reduced together with the parasitic inductance on the source wiring side.

また、ゲート端子１３とゲートリード１７とをワイヤボンディングするワイヤの長さを短くするため、ゲート端子１３をゲートリード１７に近づけて配置することが好ましい。   Further, in order to shorten the length of the wire for wire bonding the gate terminal 13 and the gate lead 17, it is preferable to arrange the gate terminal 13 close to the gate lead 17.

なお、図１では、ソース端子１１がチップ中央部に配置され、ドレイン端子がチップ周辺領域（図１の右側）に配置されているため、ドレインリード１６を図１の右側に、ドレイン端子１２の長手方向と平行になるように配置しているが、ドレイン端子１２がチップ中央部に配置されるチップ構成の場合には、例えば図６に示すように、ドレインリード１６がダイパッド１４に対して中央に位置するようにダイパッド１４と分離形成されたリードフレームを採用し、チップ３０のダイパッド１４上の位置をドレインリード１６側に片寄らせ、且つ、ドレインリード１６が延伸する直線の延長線上にドレイン端子１２があるように配置するとよい。   In FIG. 1, since the source terminal 11 is disposed in the center of the chip and the drain terminal is disposed in the chip peripheral region (right side in FIG. 1), the drain lead 16 is disposed on the right side in FIG. Although arranged so as to be parallel to the longitudinal direction, in the case of a chip configuration in which the drain terminal 12 is arranged at the center of the chip, for example, as shown in FIG. A lead frame separated from the die pad 14 so as to be positioned at the position is adopted, the position on the die pad 14 of the chip 30 is shifted to the drain lead 16 side, and the drain terminal is on a linear extension line extending the drain lead 16 12 may be arranged.

さらに、半導体装置１０の他の実装例を図７の樹脂封止前の平面図に示す。図７では、ドレインリード１６の領域１８との重なり部分、即ちドレインリード１６内の樹脂封止される部分（インナーリード）の面積を、ゲートリード１７の領域１８との重なり部分、即ちゲートリード１７内の樹脂封止される部分の面積よりも大きくしている。上記ドレインリード１６（ゲートリード１７）の樹脂封止される部分は、ワイヤボンディングが可能な部分の面積に相当する。ドレインリード１６のワイヤボンディング可能な部分の面積を大きくすることで、ドレインリード１６とドレイン端子１２との接続を、複数のワイヤを介して行うことが可能になるため、ソース配線側の寄生インダクタンスと併せて、ドレイン配線側の寄生インダクタンスを低減することが可能になる。これにより、ゲート電圧の発振を防止できるとともに、オン抵抗を削減することができる。   Further, another mounting example of the semiconductor device 10 is shown in a plan view before resin sealing in FIG. In FIG. 7, the area of the portion of the drain lead 16 that overlaps the region 18, that is, the area of the drain lead 16 that is sealed with resin (inner lead) is the same as the portion of the gate lead 17 that overlaps the region 18, ie, the gate lead 17. The area is larger than the area of the resin-sealed portion. The resin-sealed portion of the drain lead 16 (gate lead 17) corresponds to the area of the portion where wire bonding is possible. By increasing the area of the portion of the drain lead 16 that can be wire bonded, the drain lead 16 and the drain terminal 12 can be connected via a plurality of wires. In addition, the parasitic inductance on the drain wiring side can be reduced. As a result, oscillation of the gate voltage can be prevented and on-resistance can be reduced.

ところで、本発明では、ドレインリード１６はドレイン端子１２とワイヤボンディングされる。このため、ドレインリード１６とダイパッド１４が一体成形され、ドレイン端子１２とダイパッド１４をワイヤボンディングされる従来の構成（図８）と比較すると、ドレイン配線の寄生インダクタンスはかえって増加する場合がある。しかしながら、図１０より、ソース配線側の寄生インダクタンス（図９のＬｓ１）を低減することが、ドレイン配線側の寄生インダクタンス（図９のＬｄ）を低減することよりも、ゲート電圧の発振を抑制するという点において重要であることが示されている。別の言い方をすると、図１０は、ゲート電圧の発振を抑制するという点において、ソース配線側の寄生インダクタンスを低減することで、ドレイン配線の寄生インダクタンスが増加することによるデメリットをはるかに上回るメリットが得られることを示すものである。そして、本発明は、これを積極的に利用するものである。   In the present invention, the drain lead 16 is wire-bonded to the drain terminal 12. For this reason, when compared with the conventional configuration (FIG. 8) in which the drain lead 16 and the die pad 14 are integrally formed and the drain terminal 12 and the die pad 14 are wire-bonded, the parasitic inductance of the drain wiring may increase. However, from FIG. 10, reducing the parasitic inductance on the source wiring side (Ls1 in FIG. 9) suppresses the oscillation of the gate voltage than reducing the parasitic inductance on the drain wiring side (Ld in FIG. 9). In that respect. In other words, FIG. 10 is advantageous in that the parasitic inductance on the source wiring side is reduced and the disadvantage due to the increase in the parasitic inductance of the drain wiring is greatly reduced in that the oscillation of the gate voltage is suppressed. It shows that it is obtained. And this invention utilizes this positively.

以上、本発明の半導体装置１０では、ＧａＮを用いたパワーデバイスの実装において、表面実装型のデバイス実装構造を採用し、ＧａＮチップ裏面をダイパッド１４の表面と電気的に接続し、ダイパッド１４とチップ表面のソース端子１１との接続をワイヤボンディングにより行うことで、ソースリード側の寄生インダクタンスを大幅に低減できる。これにより、半導体装置１０は、大きなゲート抵抗を付加することなく寄生発振を抑制でき、ＧａＮの特徴である低消費電力、高速応答特性を生かしたパワーデバイスが実現される。   As described above, the semiconductor device 10 of the present invention employs a surface mounting type device mounting structure for mounting a power device using GaN, and electrically connects the back surface of the GaN chip to the surface of the die pad 14. By connecting the source terminal 11 on the surface by wire bonding, the parasitic inductance on the source lead side can be greatly reduced. As a result, the semiconductor device 10 can suppress parasitic oscillation without adding a large gate resistance, and a power device utilizing the low power consumption and high-speed response characteristics that are the characteristics of GaN is realized.

本発明は、ＧａＮをスイッチング素子として用いるパワーデバイスの実装に利用可能である。   The present invention can be used for mounting a power device using GaN as a switching element.

１０： 半導体装置（ＧａＮデバイス）
１１： ソース端子
１２： ドレイン端子
１３： ゲート端子
１４： ダイパッド
１５： ソースリード
１６： ドレインリード
１７： ゲートリード
１８： 樹脂封止される領域
１９： ダイパッドの裏面の露出部分
２０： 基板
２１： バッファ層
２２： ＧａＮ層
２３： ＡｌＧａＮ層
２４： ソース電極
２５： ドレイン電極
２６： ゲート電極
２７： 絶縁膜
２８： コンタクトホール
２９： ２次元電子ガス
３０： チップ
３１： プリント基板
３２ａ、３２ｂ： 電極パッド
３２ｃ： ソースパッド
３３： 接着樹脂
３４： 封止樹脂
Ｘ： ソース端子とダイパッドとのワイヤボンディングにおけるダイパッド１４側のワイヤ接続位置 10: Semiconductor device (GaN device)
DESCRIPTION OF SYMBOLS 11: Source terminal 12: Drain terminal 13: Gate terminal 14: Die pad 15: Source lead 16: Drain lead 17: Gate lead 18: Resin-sealed area 19: Exposed portion 20 on the back surface of the die pad 20: Substrate 21: Buffer layer 22: GaN layer 23: AlGaN layer 24: source electrode 25: drain electrode 26: gate electrode 27: insulating film 28: contact hole 29: two-dimensional electron gas 30: chip 31: printed circuit board 32a, 32b: electrode pad 32c: source Pad 33: Adhesive resin 34: Sealing resin X: Wire connection position on the die pad 14 side in wire bonding between the source terminal and the die pad

Claims (6)

ソース端子、ドレイン端子、ゲート端子の少なくとも三端子が基板表面側に設けられた、ＧａＮを用いるパワーデバイスを搭載してなる半導体装置であって、
前記パワーデバイスが、表面実装タイプのリードフレームのダイパッド部の表面側に固定され、
前記パワーデバイスの前記ソース端子が前記ダイパッド部とワイヤ接続され、
前記パワーデバイスの前記ドレイン端子がドレインリードと、前記パワーデバイスの前記ゲート端子がゲートリードとワイヤ接続され、前記ダイパッド部の裏面がプリント基板上のソースパッドと接続するために露出したデバイス実装構造を有することを特徴とする半導体装置。 A semiconductor device comprising a power device using GaN, wherein at least three terminals of a source terminal, a drain terminal, and a gate terminal are provided on the substrate surface side,
The power device is fixed to the surface side of the die pad portion of the surface mount type lead frame,
The source terminal of the power device is wire-connected to the die pad portion;
A device mounting structure in which the drain terminal of the power device is connected to a drain lead, the gate terminal of the power device is connected to a gate lead, and the back surface of the die pad portion is exposed to connect to a source pad on a printed circuit board. A semiconductor device comprising: 前記ソース端子と前記ダイパッド部とのワイヤ接続における前記ダイパッド部側のワイヤとの接続位置に対応する裏面側が露出していることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a back surface side corresponding to a connection position of the wire on the die pad portion side in a wire connection between the source terminal and the die pad portion is exposed. 前記ドレインリード内の樹脂封止されるインナーリード部分の面積が、前記ゲートリード内の樹脂封止されるインナーリード部分の面積よりも大きいことを特徴とする請求項１又は２に記載の半導体装置。   3. The semiconductor device according to claim 1, wherein an area of the resin-encapsulated inner lead part in the drain lead is larger than an area of the resin-encapsulated inner lead part in the gate lead. . 前記ドレイン端子の長手方向に対して平行となるように前記ドレインリードが配置され、前記パワーデバイスの前記ダイパッド部上の位置が、前記ドレインリードが延伸する直線の延長線上に前記ドレイン端子があるように、且つ、前記ドレインリード側に片寄って配置されていることを特徴とする請求項１〜３の何れか一項に記載の半導体装置。   The drain lead is arranged so as to be parallel to the longitudinal direction of the drain terminal, and the position of the power device on the die pad portion is on the straight extension line extending the drain lead. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is disposed closer to the drain lead side. 前記パワーデバイスを構成するトランジスタが、
前記ソース端子と接続するソース電極、前記ドレイン端子と接続するドレイン電極、及び、前記ゲート端子と接続するゲート電極を備え、
前記ゲート電極が前記ドレイン電極よりも前記ソース電極側に片寄って配置される非対称構造を有することを特徴とする請求項１〜４の何れか一項に記載の半導体装置。 Transistors constituting the power device are
A source electrode connected to the source terminal; a drain electrode connected to the drain terminal; and a gate electrode connected to the gate terminal;
5. The semiconductor device according to claim 1, wherein the semiconductor device has an asymmetric structure in which the gate electrode is arranged closer to the source electrode side than the drain electrode. 前記ダイパッド部の裏面の露出部分には、前記ドレインリードよりも低電圧が供給されることを特徴とする請求項１〜５の何れか一項に記載の半導体装置。
The semiconductor device according to claim 1, wherein a voltage lower than that of the drain lead is supplied to an exposed portion of the back surface of the die pad portion.
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