JP2013110644A - Imaging apparatus and luminance control method - Google Patents

Imaging apparatus and luminance control method Download PDF

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JP2013110644A
JP2013110644A JP2011255190A JP2011255190A JP2013110644A JP 2013110644 A JP2013110644 A JP 2013110644A JP 2011255190 A JP2011255190 A JP 2011255190A JP 2011255190 A JP2011255190 A JP 2011255190A JP 2013110644 A JP2013110644 A JP 2013110644A
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Yasuyuki Kasai
康行 笠井
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Mitsubishi Electric Corp
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Abstract

PROBLEM TO BE SOLVED: To solve such a problem of luminance control by pixel addition that the luminance level can be adjusted only by integral multiplication, and small illuminance changes cannot be dealt with.SOLUTION: The factors can be controlled up to the decimal point, and finer control of the luminance level is possible because signal processing means 6 for outputting an imaging signal of a predetermined scanning system, pixel addition means 7 having delay means for outputting each pixel value of a target pixel and a plurality of peripheral pixels while delaying in units of field, line and pixel, calculation means for multiplying each pixel value by predetermined factors, respectively, and addition means for adding the pixel values multiplied by predetermined factors, and control means 10 for detecting the brightness of a screen and controlling the factors supplied to the pixel addition means 7 so that the brightness of the screen becomes constant are provided.

Description

本発明は、被写体照度に合わせて自動的に画面の明るさの調整を行う撮像装置、及び輝度制御方法に関する。   The present invention relates to an imaging apparatus that automatically adjusts screen brightness in accordance with subject illuminance, and a luminance control method.

従来、低照度の撮影環境での感度を向上させるため、スローシャッターやゲインアップ(信号増幅)といった手法が使用されてきた。ところが、スローシャッターは動きの多い被写体を撮影すると撮影画像に尾引きが発生し、ゲインアップにはノイズが増加するという問題があった。このような問題点を解決した感度向上の技術として、画素加算が知られている。画素加算は、注目画素と周辺の画素の輝度(色)レベルを加算することで、加算に使用した画素数の倍率だけ感度が向上する技術である。たとえば、注目画素があるフレームの前後のフレームにおいて、注目画素の上下に位置する画素を加算することによって、感度を5倍に向上させることができる。特許文献1は、画素加算を用いて感度を向上させる技術について開示している。   Conventionally, methods such as slow shutter and gain-up (signal amplification) have been used to improve sensitivity in a low-illumination shooting environment. However, the slow shutter has a problem in that when a subject with much movement is photographed, tailing occurs in the photographed image, and noise increases when the gain is increased. Pixel addition is known as a technique for improving sensitivity that solves such problems. Pixel addition is a technique in which the sensitivity is increased by the magnification of the number of pixels used for the addition by adding the luminance (color) levels of the target pixel and the surrounding pixels. For example, the sensitivity can be improved fivefold by adding pixels located above and below the target pixel in the frames before and after the frame where the target pixel is located. Patent Document 1 discloses a technique for improving sensitivity using pixel addition.

特開2011−109576JP2011-109576

ところで、撮像後の画像、もしくは映像を見やすいものにするためには、画面の明るさ(出力レベル)を、被写体照度によらず一定とすることが必要となる。このため、撮像装置にて調整を行い、最適な輝度レベルとなるように各種機能を制御するが、その際に輝度レベルの制御を細かく行う必要がある。しかし、特許文献1に記載の撮像装置が実施する画素加算は、周辺の画素を加算するという原理から整数倍でしか輝度レベルの調整を行うことができず、細かな照度変化に対応することができないという課題があった。   By the way, in order to make it easy to view an image or video after imaging, it is necessary to keep the screen brightness (output level) constant irrespective of subject illuminance. For this reason, adjustment is performed by the imaging apparatus and various functions are controlled so as to obtain an optimum luminance level. At that time, it is necessary to finely control the luminance level. However, the pixel addition performed by the imaging device described in Patent Document 1 can adjust the luminance level only by an integral multiple from the principle of adding neighboring pixels, and can deal with fine illuminance changes. There was a problem that it was not possible.

特許文献1に記載の撮像装置は、整数倍でしか輝度レベルの調整が出来ないという画素加算の問題点を補うため、細かな輝度レベルの制御が可能なゲインアップを画素加算と切り替えることにより、細かな輝度制御を実現していた。図9は、ゲインアップと画素加算を併用した輝度制御処理のイメージを示す説明図である。図9には、照度環境が明るい状態から暗い状態に遷移する過程において、最も明るい環境ではゲインアップのみによる輝度制御を実施するが、以降、暗い環境ではゲインアップと画素加算を切り替えて輝度制御を行うことが示されている。動作の詳細としては、画面の明るさが一定となるようにゲインアップを使用して輝度制御を実施し、ゲインアップの倍率が一定値以上になったときに、ゲインアップの倍率を1/2にすると同時に、2画素加算を行う制御を行っていた。また、その状態から続けて輝度制御を実施し、ゲインアップの倍率が一定値以上になった時に、ゲインアップの倍率を2/3にすると同時に、3画素加算を行う制御としていた。   In order to compensate for the pixel addition problem that the brightness level can be adjusted only by an integral multiple, the imaging device described in Patent Document 1 switches gain increase that enables fine brightness level control to pixel addition. Fine brightness control was realized. FIG. 9 is an explanatory diagram showing an image of luminance control processing using both gain-up and pixel addition. In FIG. 9, in the process of transition from a bright state to a dark state in the illuminance environment, luminance control is performed only by gain increase in the brightest environment. Thereafter, in the dark environment, luminance control is performed by switching between gain increase and pixel addition. Shown to do. As the details of the operation, brightness control is performed using gain-up so that the screen brightness is constant, and when the gain-up magnification becomes a certain value or more, the gain-up magnification is halved. At the same time, control for adding two pixels was performed. In addition, brightness control is continuously performed from this state, and when the gain-up magnification becomes a certain value or more, the gain-up magnification is set to 2/3 and at the same time, 3 pixels are added.

このように画素加算とゲインアップを切り替えることで、被写体照度によらず、常に同じ画面の明るさの出力レベルを保つことができる。しかしながら、画素加算とゲインアップを併用する輝度制御方法は、一定の照度下において、ゲインアップと画素加算という異なる高感度化手法を切り替えながら使用、つまり、ゲインアップの倍率を下げると同時に画素加算の加算画素数を増やすタイミングが存在するため、切替タイミングの前後で、解像度の変化やノイズ量の変化等、画面の見え方が大きく変わり、映像に乱れが発生することがあった。   By switching between pixel addition and gain increase in this way, it is possible to always maintain the same screen brightness output level regardless of subject illuminance. However, the luminance control method that uses both pixel addition and gain increase is to switch between different sensitivity enhancement methods, gain increase and pixel addition, under a certain illuminance. Since there is a timing to increase the number of added pixels, before and after the switching timing, the appearance of the screen changes greatly, such as a change in resolution and a change in noise amount, and the video may be disturbed.

また、常に映像を出力し続ける動画撮影では、画素加算による輝度変化のタイミングと、ゲインアップによる輝度変化のタイミングを完全に一致させる必要がある。少しでもタイミングがずれてしまうと、一瞬画面が明るくなる、もしくは一瞬画面が暗くなるなど、なめらかな輝度変化を実現できなくなる。そのため、二つの制御のタイミングを合わせるために、制御や回路が複雑になるという問題があった。   Further, in moving image shooting in which video is constantly output, it is necessary to completely match the timing of luminance change due to pixel addition and the timing of luminance change due to gain increase. If the timing is shifted even a little, it will not be possible to realize a smooth brightness change, such as the screen brightening for a moment or darkening for a moment. Therefore, there is a problem that the control and the circuit become complicated in order to match the timings of the two controls.

本発明に係る撮像装置は、撮像手段と、この撮像手段から読み出された信号に基づいて、所定の走査方式の撮像信号を出力する信号処理手段と、この信号処理手段から出力された撮像信号をフィールド単位、ライン単位及びピクセル単位で遅延させて注目画素及び複数の周辺画素の各画素値を出力する遅延手段、この遅延手段から出力された各画素値のそれぞれに対して、外部より供給された所定の係数を掛ける演算手段、この演算手段で所定の係数が掛けられた各画素値を加算する加算手段を有する画素加算手段と、この画素加算手段から出力された信号より画面の明るさを検出するとともに、画面の明るさが一定になるように、画素加算手段の演算手段に供給する係数を制御する制御手段とを設けたものである。   An imaging apparatus according to the present invention includes an imaging unit, a signal processing unit that outputs an imaging signal of a predetermined scanning method based on a signal read from the imaging unit, and an imaging signal output from the signal processing unit. The delay means outputs the pixel values of the pixel of interest and the plurality of peripheral pixels by delaying the pixel by field, line and pixel, and is supplied from the outside to each of the pixel values output from the delay means. A pixel adding means having an calculating means for multiplying the predetermined coefficient, an adding means for adding each pixel value multiplied by the predetermined coefficient by the calculating means, and the brightness of the screen from the signal output from the pixel adding means. And a control means for controlling a coefficient supplied to the calculation means of the pixel addition means so that the brightness of the screen becomes constant.

本発明に係る輝度制御方法は、撮像手段から読み出された信号に基づいて、所定の走査方式の撮像信号を出力する信号出力処理と、この信号出力処理された撮像信号をフィールド単位、ライン単位及びピクセル単位で遅延させて注目画素及び複数の周辺画素の各画素値を出力する遅延処理、この遅延処理された各画素値のそれぞれに対して、外部より供給された所定の係数を掛ける演算処理、この演算処理により所定の係数が掛けられた各画素値を加算する加算処理を含む画素加算処理と、この画素加算処理で加算された信号より画面の明るさを検出するとともに、画面の明るさが一定になるように、画素加算処理が実行する演算処理で使用される係数を制御する制御処理を含むものである。   The luminance control method according to the present invention includes a signal output process for outputting an imaging signal of a predetermined scanning method based on a signal read from the imaging means, and the imaged signal subjected to the signal output process for the field unit and the line unit. And a delay process for outputting each pixel value of the target pixel and a plurality of peripheral pixels with a delay in pixel units, and an arithmetic process for multiplying each of the delayed pixel values by a predetermined coefficient supplied from the outside , A pixel addition process including an addition process for adding each pixel value multiplied by a predetermined coefficient by this calculation process, and a screen brightness from the signal added by the pixel addition process, and a screen brightness Includes a control process for controlling a coefficient used in an arithmetic process executed by the pixel addition process so that the value is constant.

本発明は、撮像手段と、この撮像手段から読み出された信号に基づいて、所定の走査方式の撮像信号を出力する信号処理手段と、この信号処理手段から出力された撮像信号をフィールド単位、ライン単位及びピクセル単位で遅延させて注目画素及び複数の周辺画素の各画素値を出力する遅延手段、この遅延手段から出力された各画素値のそれぞれに対して、外部より供給された所定の係数を掛ける演算手段、この演算手段で所定の係数が掛けられた各画素値を加算する加算手段を有する画素加算手段と、この画素加算手段から出力された信号より画面の明るさを検出するとともに、画面の明るさが一定になるように、画素加算手段の演算手段に供給する係数を制御する制御手段とを設けたので、係数を小数点以下まで制御することが可能となり、従来の整数倍単位の制御に比べて、より細かな輝度レベルの制御を行うことが出来るという効果を奏する。   The present invention provides an image pickup means, a signal processing means for outputting an image pickup signal of a predetermined scanning method based on a signal read from the image pickup means, and an image pickup signal output from the signal processing means as a field unit, Delay means for outputting each pixel value of the target pixel and a plurality of peripheral pixels with a delay in line units and pixel units, and a predetermined coefficient supplied from the outside for each pixel value output from the delay means A pixel adding means having an adding means for adding each pixel value multiplied by a predetermined coefficient by the calculating means, and detecting the brightness of the screen from the signal output from the pixel adding means, Since the control means for controlling the coefficient supplied to the calculation means of the pixel addition means is provided so that the brightness of the screen is constant, the coefficient can be controlled to the decimal point. , As compared to the control conventional integral multiple units, there is an effect that it is possible to control the finer luminance levels.

本発明に係る輝度制御方法は、撮像手段から読み出された信号に基づいて、所定の走査方式の撮像信号を出力する信号出力処理と、この信号出力処理された撮像信号をフィールド単位、ライン単位及びピクセル単位で遅延させて注目画素及び複数の周辺画素の各画素値を出力する遅延処理、この遅延処理された各画素値のそれぞれに対して、外部より供給された所定の係数を掛ける演算処理、この演算処理により所定の係数が掛けられた各画素値を加算する加算処理を含む画素加算処理と、この画素加算処理で加算された信号より画面の明るさを検出するとともに、画面の明るさが一定になるように、画素加算処理が実行する演算処理で使用される係数を制御する制御処理を含むので、係数を小数点以下まで制御することが可能となり、従来の整数倍単位の制御に比べて、より細かな輝度レベルの制御を行うことが出来るという効果を奏する。   The luminance control method according to the present invention includes a signal output process for outputting an imaging signal of a predetermined scanning method based on a signal read from the imaging means, and the imaged signal subjected to the signal output process for the field unit and the line unit. And a delay process for outputting each pixel value of the target pixel and a plurality of peripheral pixels with a delay in pixel units, and an arithmetic process for multiplying each of the delayed pixel values by a predetermined coefficient supplied from the outside , A pixel addition process including an addition process for adding each pixel value multiplied by a predetermined coefficient by this calculation process, and a screen brightness from the signal added by the pixel addition process, and a screen brightness Includes a control process that controls the coefficient used in the calculation process executed by the pixel addition process so that the coefficient is constant, so that the coefficient can be controlled to the decimal point. Compared to the control of an integral multiple units, there is an effect that it is possible to control the finer luminance levels.

本発明に係る撮像装置の構成を示すブロック図である。It is a block diagram which shows the structure of the imaging device which concerns on this invention. 画素加算回路の詳細な構成を示すブロック図である。It is a block diagram which shows the detailed structure of a pixel addition circuit. 画素加算回路にて加算される画素の空間的位置、時間的位置の一例を示す説明図である。It is explanatory drawing which shows an example of the spatial position of a pixel added by a pixel addition circuit, and a temporal position. 本発明に係る撮像装置が実行する輝度制御処理のイメージを示す説明図である。It is explanatory drawing which shows the image of the brightness | luminance control processing which the imaging device which concerns on this invention performs. 本発明の実施の形態1に係る撮像装置が実行する輝度制御処理を示すフローチャートである。It is a flowchart which shows the brightness | luminance control processing which the imaging device which concerns on Embodiment 1 of this invention performs. 本発明の実施の形態2に係る撮像装置が実行する輝度制御処理を示すフローチャートである。It is a flowchart which shows the brightness | luminance control processing which the imaging device which concerns on Embodiment 2 of this invention performs. 増減量テーブルの一例を示す説明図である。It is explanatory drawing which shows an example of the increase / decrease amount table. 画素加算量テーブルの一例を示す説明図である。It is explanatory drawing which shows an example of a pixel addition amount table. ゲインアップと画素加算を併用した輝度制御処理のイメージを示す説明図である。It is explanatory drawing which shows the image of the brightness | luminance control processing which used gain up and pixel addition together.

実施の形態1.
図1は本発明の実施の形態1による撮像装置を示すブロック構成図である。図1において、レンズ群1の中にはフォーカス用レンズがあり、レンズ駆動回路11によって移動され、フォーカシングが行われることで、固体撮像素子2の撮像面上に合焦させる。固体撮像素子2は、タイミングジェネレータ12より指定されたタイミングで露光を行う。CDS(Correlated Double Sampling 相関二重サンプリング)3は、固体撮像素子2の出力信号に相関二重サンプリングを施すことで、ノイズ等の除去を行う。アンプ4は、CDS3の出力信号に、マイクロプロセッサ10から出力された制御信号の倍率にしたがってゲインアップ(信号増幅)を行う。A/D変換機5は、アンプ4の出力信号をデジタル信号に変換する。
Embodiment 1 FIG.
FIG. 1 is a block diagram showing an imaging apparatus according to Embodiment 1 of the present invention. In FIG. 1, the lens group 1 includes a focusing lens, which is moved by the lens driving circuit 11 and focused to focus on the imaging surface of the solid-state imaging device 2. The solid-state imaging device 2 performs exposure at a timing specified by the timing generator 12. CDS (Correlated Double Sampling) 3 removes noise and the like by performing correlated double sampling on the output signal of the solid-state imaging device 2. The amplifier 4 performs gain up (signal amplification) on the output signal of the CDS 3 according to the magnification of the control signal output from the microprocessor 10. The A / D converter 5 converts the output signal of the amplifier 4 into a digital signal.

映像信号処理部6は、A/D変換機5の出力信号に、欠陥画素補正処理や、色補間処理、階調補正処理、ノイズ低減処理、輪郭補正処理、白バランス調整処理、信号振幅調整処理、色補正処理などを加え、飛び越し走査方式の映像信号を出力する。画素加算回路7は映像信号処理部6の出力信号に画素加算を行うものであり、画素加算において、加算する周辺画素それぞれに加算前に係数を掛けることが出来る回路を備えている。輝度積分値計算部8は、画素加算回路7の出力信号の振幅より、画面内輝度積分値の計算を行う。映像信号出力部9は、輝度積分値計算部8の出力信号に最終処理を施し、撮像装置より外部へ出力を行う。   The video signal processing unit 6 applies a defective pixel correction process, a color interpolation process, a gradation correction process, a noise reduction process, a contour correction process, a white balance adjustment process, a signal amplitude adjustment process to the output signal of the A / D converter 5. Then, color correction processing is added, and an interlaced scanning video signal is output. The pixel addition circuit 7 performs pixel addition on the output signal of the video signal processing unit 6 and includes a circuit capable of multiplying each peripheral pixel to be added by a coefficient before the addition in the pixel addition. The luminance integral value calculation unit 8 calculates the in-screen luminance integral value from the amplitude of the output signal of the pixel addition circuit 7. The video signal output unit 9 performs a final process on the output signal of the luminance integral value calculation unit 8 and outputs it from the imaging apparatus to the outside.

マイクロプロセッサ10は、撮像信号の大きさに基づいて、例えば輝度積分値計算部8から供給された画面内輝度積分値に基づいて、レンズ1の絞りの制御、タイミングジェネレータ12が発生する固体撮像素子2の光電変換素子からの電荷読出しタイミング及び電荷強制排出タイミングの制御(露光時間の制御)、アンプ4のゲインアップ量の制御、並びに画素加算回路7の画素加算処理の制御を行う。具体的には、輝度積分値計算部8から得られる画面内輝度積分値が一定となるように自動露光制御を行う。明るい環境での撮像で画面内輝度積分値(信号振幅)が大きい時、マイクロプロセッサ10は、レンズ1の開口を絞るように制御(アイリス制御)して固体撮像素子2への入射光量を減らす。一方、暗い環境での撮像で画面内輝度積分値(信号振幅)が小さい時、マイクロプロセッサ10は、レンズ1の開口を開くように制御して固体撮像素子2への入射光量を増加させる。   The microprocessor 10 controls the aperture of the lens 1 based on the in-screen luminance integral value supplied from the luminance integral value calculation unit 8, for example, based on the magnitude of the imaging signal, and the solid-state imaging device generated by the timing generator 12 Control of charge readout timing and charge forced discharge timing (exposure time control) from the second photoelectric conversion element, control of the gain increase amount of the amplifier 4, and control of pixel addition processing of the pixel addition circuit 7 are performed. Specifically, automatic exposure control is performed so that the in-screen luminance integral value obtained from the luminance integral value calculation unit 8 is constant. When the in-screen luminance integral value (signal amplitude) is large in imaging in a bright environment, the microprocessor 10 performs control (iris control) to reduce the aperture of the lens 1 to reduce the amount of light incident on the solid-state imaging device 2. On the other hand, when the in-screen luminance integral value (signal amplitude) is small in imaging in a dark environment, the microprocessor 10 controls to open the aperture of the lens 1 to increase the amount of light incident on the solid-state imaging device 2.

マイクロプロセッサ10は、輝度を一定に保つため、アイリス制御のほか、ゲインアップ量の制御も行う。例えば、周辺照度が徐々に暗くなる環境での撮像で、画面内輝度積分値(信号振幅)が小さくなってきた時、アンプ4のゲインアップ量を増やすように制御して撮像信号を増幅する。逆に、周辺照度が徐々に明るくなる環境での撮像で、画面内輝度積分値(信号振幅)が大きくなってきた時、アンプ4のゲインアップ量を減らすように制御する。   In order to keep the luminance constant, the microprocessor 10 controls the gain increase amount in addition to the iris control. For example, when imaging in an environment where the ambient illuminance gradually becomes dark and the in-screen luminance integral value (signal amplitude) becomes smaller, the imaging signal is amplified by controlling to increase the gain increase amount of the amplifier 4. On the other hand, when the in-screen luminance integral value (signal amplitude) becomes large in imaging in an environment where the ambient illuminance gradually increases, control is performed to reduce the gain increase amount of the amplifier 4.

マイクロプロセッサ10は、周辺照度の変化によって、アイリス制御、ゲインアップ量の制御、画素加算による輝度制御方法を実行する。以下、周辺照度が変化したときの感度調整のための手順の一例を説明する。周辺照度が徐々に暗くなり、画面内輝度積分値(信号振幅)が下がってくると、レンズ1の絞りを開放方向に制御して、画面内輝度積分値(信号振幅)を維持する。レンズ1の絞りが開放(全開)になった後は、アンプ4のゲインアップ量を増やすように制御して、画面内輝度積分値(信号振幅)を維持する。アンプ4のゲインアップ量が最大になった後は、画素加算回路7の係数を増やすように制御して、画面内輝度積分値(信号振幅)を維持する。逆に、周辺照度が徐々に明るくなり、画面内輝度積分値(信号振幅)が上がってくると、画素加算回路7が係数を減らすように制御する。周辺照度がさらに明るくなると、アンプ4のゲインアップ量を減らすように制御して、画面内輝度積分値(信号振幅)を維持する。周辺照度がさらに明るくなると、レンズ1の絞りを遮光方向に制御して、画面内輝度積分値(信号振幅)を維持する。   The microprocessor 10 executes an iris control, a gain increase amount control, and a luminance control method by pixel addition according to a change in ambient illuminance. Hereinafter, an example of a procedure for adjusting sensitivity when the ambient illuminance changes will be described. When the ambient illuminance gradually becomes dark and the in-screen luminance integral value (signal amplitude) decreases, the aperture of the lens 1 is controlled in the open direction to maintain the in-screen luminance integral value (signal amplitude). After the aperture of the lens 1 is opened (fully opened), control is performed to increase the gain increase amount of the amplifier 4, and the in-screen luminance integrated value (signal amplitude) is maintained. After the gain increase amount of the amplifier 4 reaches the maximum, control is performed to increase the coefficient of the pixel addition circuit 7 to maintain the in-screen luminance integrated value (signal amplitude). Conversely, when the ambient illuminance gradually increases and the in-screen luminance integral value (signal amplitude) increases, the pixel addition circuit 7 controls to reduce the coefficient. When the ambient illuminance further increases, control is performed to reduce the gain increase amount of the amplifier 4, and the in-screen luminance integral value (signal amplitude) is maintained. When the ambient illuminance further increases, the aperture of the lens 1 is controlled in the light shielding direction to maintain the in-screen luminance integrated value (signal amplitude).

上記のように、マイクロプロセッサ10は、レンズ1の絞り、固体撮像素子2の露光時間、アンプ4のゲインアップ量、画素加算回路7における画素加算の各々の信号振幅調整機能を制御して画面内輝度積分値(信号振幅)を維持する。   As described above, the microprocessor 10 controls the signal amplitude adjustment function for each of the aperture of the lens 1, the exposure time of the solid-state imaging device 2, the gain increase amount of the amplifier 4, and the pixel addition in the pixel addition circuit 7. Maintains the integrated luminance value (signal amplitude).

図2は、画素加算回路の詳細な構成を示すブロック図である。以下、図2を参照して、画素加算回路7がNTSC方式(インターレース方式)の信号を処理する場合を例に説明する。画素加算処理はY信号、C信号ともに行う必要があるが、ここではY信号を代表として説明する。実際にはC信号についても同様の処理を行う必要がある。また、撮像装置によってはR、G、B信号など、異なる信号が入力される場合もあるが、処理の方法は同様である。映像信号処理部6より画素加算回路に入力された信号から、フィールド遅延部201にて、遅延なしの信号P1、262ライン(1フィールド)遅延した信号P2、525ライン(2フィールド)遅延した信号P3が生成される。フィールド遅延部201より出力された信号から、ライン遅延部202にて、P1から遅延なしの信号P11、P1から1ライン遅延の信号P12、P2から遅延なしの信号P21、P2から1ライン遅延の信号P22、P2から2ライン遅延の信号P23、P3から遅延なしの信号P31、P3から1ライン遅延の信号P32、が生成される。   FIG. 2 is a block diagram showing a detailed configuration of the pixel addition circuit. Hereinafter, a case where the pixel addition circuit 7 processes an NTSC (interlace) signal will be described as an example with reference to FIG. The pixel addition processing needs to be performed for both the Y signal and the C signal. Here, the Y signal will be described as a representative. Actually, it is necessary to perform the same processing for the C signal. Depending on the imaging device, different signals such as R, G, and B signals may be input, but the processing method is the same. From the signal input from the video signal processing unit 6 to the pixel addition circuit, the field delay unit 201 causes the signal P1, the delay-free signal P1, the signal P2 delayed by 262 lines (1 field), the signal P3 delayed by 525 lines (2 fields). Is generated. From the signal output from the field delay unit 201, in the line delay unit 202, the signal P11 without delay from P1, the signal P12 delayed by 1 line from P1, the signal P21 without delay from P2, the signal P21 without delay from P2, and the signal delayed by 1 line from P2 Signals P23 and P3 having a two-line delay are generated from P22 and P2, and signals P31 without a delay are generated from P3, and signals P32 having a one-line delay are generated from P3.

ライン遅延部202より出力された信号から、ピクセル遅延部203にて、P11から1ライン遅延の信号P112、P12から1ライン遅延の信号P122、P21から1ライン遅延の信号P212、P22から遅延なしの信号P221、P22から1ライン遅延の信号P222、P22から2ライン遅延の信号P223、P23から1ライン遅延の信号P232、P31から1ライン遅延の信号P312、P32から1ライン遅延の信号P322、が生成される。ピクセル遅延部203より出力された信号は、演算部204にて、それぞれマイクロプロセッサより指定された係数K112〜K322で乗算を行う。演算部204より出力された信号は、加算部205にて加算される。加算部205より出力された信号は、輝度積分値計算部8に入力される。なお、演算部203より出力された信号のうち、1フィールド遅延、1ライン遅延、1ピクセル遅延を行った信号P222を注目画素とし、それ以外を周辺画素とする。   From the signal output from the line delay unit 202, in the pixel delay unit 203, the signal P112 is delayed from P11, the signal P122 is delayed from P12 by P122, the signal P122 is delayed from P21, and the signals P212 and P22 are delayed from P21. Signals P221 and P22 generate a one-line delayed signal P222, P22 to a two-line delayed signal P223, P23 to a one-line delayed signal P232, P31 to a one-line delayed signal P312 and P32 to a one-line delayed signal P322. Is done. Signals output from the pixel delay unit 203 are multiplied by coefficients K112 to K322 respectively designated by the microprocessor in the arithmetic unit 204. The signal output from the arithmetic unit 204 is added by the adding unit 205. The signal output from the adder 205 is input to the luminance integral value calculator 8. Of the signals output from the arithmetic unit 203, a signal P222 subjected to one field delay, one line delay, and one pixel delay is set as a pixel of interest, and the others are set as peripheral pixels.

図3は、画素加算回路にて加算される画素の空間的位置、時間的位置の一例を示す説明図である。以下、図3を参照して、上記遅延信号の空間的位置、時間的位置を説明する。縦に垂直軸V、横に水平軸Hをとったインタレース方式の映像信号の画素配置図である。垂直525ラインのうち、1ラインから262ラインの真ん中までが奇数フィールド、262ラインの真ん中から525ラインまでが偶数フィールドである。P221は注目画素P222と同一フィールドで、注目画素から水平に1画素前の位置であり、P223は1画素後ろの位置である。P212は注目画素と同一フィールドで、注目画素から1ライン前(2画素上)の位置であり、P232は1ライン後(2画素下)の位置である。P112は注目画素の1フィールド前で、注目画素の真上の位置であり、P122は注目画素の真下の位置である。P312は注目画素の1フィールド後で、注目画素の真上の位置であり、P322は注目画素の真下の位置である。   FIG. 3 is an explanatory diagram illustrating an example of a spatial position and a temporal position of pixels added by the pixel addition circuit. Hereinafter, the spatial position and the temporal position of the delayed signal will be described with reference to FIG. It is a pixel arrangement diagram of an interlaced video signal having a vertical axis V in the vertical direction and a horizontal axis H in the horizontal direction. Of the vertical 525 lines, the odd field is from the first line to the middle of the 262 line, and the even field is from the middle of the 262 line to the 525 line. P221 is the same field as the target pixel P222, and is a position one pixel before and horizontally from the target pixel, and P223 is a position one pixel behind. P212 is the same field as the target pixel and is a position one line before (two pixels above) from the target pixel, and P232 is a position one line after (two pixels below). P112 is a position immediately above the target pixel, one field before the target pixel, and P122 is a position immediately below the target pixel. P312 is a position immediately above the target pixel after one field of the target pixel, and P322 is a position immediately below the target pixel.

演算部の係数を、(K112、K122、K212、K221、K222、K223、K232、K312、K322)=(0、0、0、0、1、0、0、0、0)とした場合、注目画素の1倍、つまり入力画像がそのまま出力されることとなり、画素加算回路がない(画素加算機能がOFF)場合と同様となる。また、演算部の係数を(K112、K122、K212、K221、K222、K223、K232、K312、K322)=(0、0、0、1、1、1、0、0、0)とすることで水平3画素加算となり、3倍の感度向上が実現できる。また、(K112、K122、K212、K221、K222、K223、K232、K312、K322)=(1、1、0、0、1、0、0、1、1)とすることで3フィールドにわたる5画素加算となり、5倍の感度向上が実現できる。このように係数を制御することで、画素加算の動作を制御することができる。上記説明のように、本発明に係る撮像装置は、画素加算において、加算する周辺画素それぞれに加算前に係数を掛けることが出来る回路を備えている。   When the coefficients of the calculation unit are (K112, K122, K212, K221, K222, K223, K232, K312, K322) = (0, 0, 0, 0, 1, 0, 0, 0, 0) One pixel, that is, the input image is output as it is, which is the same as when there is no pixel addition circuit (pixel addition function is OFF). Further, by setting the coefficients of the calculation unit to (K112, K122, K212, K221, K222, K223, K232, K312, K322) = (0, 0, 0, 1, 1, 1, 0, 0, 0) It becomes horizontal 3 pixel addition, and the sensitivity improvement of 3 times is realizable. Also, by setting (K112, K122, K212, K221, K222, K223, K232, K312, K322) = (1, 1, 0, 0, 1, 0, 0, 1, 1), 5 pixels over 3 fields As a result of addition, a fivefold improvement in sensitivity can be realized. By controlling the coefficients in this way, the pixel addition operation can be controlled. As described above, the imaging apparatus according to the present invention includes a circuit capable of multiplying each peripheral pixel to be added by a coefficient before the addition in the pixel addition.

図4は、本発明に係る撮像装置が実行する輝度制御処理のイメージを示す説明図である。ここで、演算部204の係数を小数点以下の単位まで制御可能な構成とすると、整数倍単位の輝度制御だけでなく、細かい輝度制御が可能になる。例えば、演算部204の係数を(K112、K122、K212、K221、K222、K223、K232、K312、K322)=(0、0、0、0.125、1、0.125、0、0、0)とすることで、1.25倍の感度向上が実現できる。このように、演算部204の係数を小数点以下の単位で制御することで、ゲインアップを併用することなく、図4に示すように細かい輝度制御を行うことができる。   FIG. 4 is an explanatory diagram showing an image of luminance control processing executed by the imaging apparatus according to the present invention. Here, if the coefficient of the arithmetic unit 204 can be controlled to the unit after the decimal point, not only the luminance control in integer multiple units but also fine luminance control becomes possible. For example, the coefficient of the arithmetic unit 204 is (K112, K122, K212, K221, K222, K223, K232, K312, K322) = (0, 0, 0, 0.125, 1, 0.125, 0, 0, 0 ), A 1.25 times sensitivity improvement can be realized. In this way, by controlling the coefficient of the arithmetic unit 204 in units of decimals, fine luminance control can be performed as shown in FIG. 4 without using gain increase.

図5は、本発明の実施の形態1に係る撮像装置が実行する輝度制御処理を示すフローチャートである。以下、図5を用いて、本発明に係る撮像装置が実行する輝度制御処理について説明する。マイクロプロセッサ10は、輝度積分値計算部8の入力信号から画面内輝度積分値を算出する(ステップS1)。輝度積分値計算部8の入力信号は、全ての感度アップの処理が行われた後であるため、この時点での画面内輝度積分値は、全ての画素の輝度レベルを足し合わせたものである。また、画面の明るさの目標値は、目標輝度積分値としてあらかじめ設定しておく。ハンチングを防止するため、目標輝度積分値にはある程度の幅を持たせることとし、目標輝度積分値上限と、目標輝度積分値下限を定める。   FIG. 5 is a flowchart showing the brightness control processing executed by the imaging apparatus according to Embodiment 1 of the present invention. Hereinafter, the brightness control process executed by the imaging apparatus according to the present invention will be described with reference to FIG. The microprocessor 10 calculates the in-screen luminance integral value from the input signal of the luminance integral value calculation unit 8 (step S1). Since the input signal of the luminance integral value calculation unit 8 is after all the processing for increasing sensitivity has been performed, the luminance integral value in the screen at this point is the sum of the luminance levels of all pixels. . The target value of the screen brightness is set in advance as a target luminance integrated value. In order to prevent hunting, the target luminance integrated value is given a certain range, and a target luminance integrated value upper limit and a target luminance integrated value lower limit are determined.

次に、マイクロプロセッサ10は、画面内輝度積分値と目標輝度積分値上限の比較を行う(ステップS2)。このステップS2の判定において、画面内輝度積分値が目標輝度積分値上限より大きい場合(ステップS2でYes)、マイクロプロセッサ10は演算部204の係数を減少させる(ステップS4)。一方、画面内輝度積分値が目標輝度積分値上限以下の場合(ステップS2でNo)、マイクロプロセッサ10は、画面内輝度積分値と目標輝度積分値下限を比較する(ステップS3)。このステップS3の判定において、目標輝度積分値が目標輝度積分値下限より小さい場合(ステップS3でYes)、マイクロプロセッサ10は、演算部204の係数を増加させる(ステップS5)。一方、画面内輝度積分値が目標輝度積分値下限以上の場合(ステップS3でNo)、マイクロプロセッサ10は演算部204の係数の調整は行わない。このような処理を繰り返し行うことで、画面内輝度積分値が目標輝度積分値に近づくこととなる。   Next, the microprocessor 10 compares the in-screen luminance integrated value with the target luminance integrated value upper limit (step S2). If the in-screen luminance integral value is larger than the target luminance integral value upper limit in the determination in step S2 (Yes in step S2), the microprocessor 10 decreases the coefficient of the calculation unit 204 (step S4). On the other hand, when the in-screen luminance integral value is less than or equal to the target luminance integral value upper limit (No in step S2), the microprocessor 10 compares the in-screen luminance integral value with the target luminance integral value lower limit (step S3). If it is determined in step S3 that the target luminance integral value is smaller than the target luminance integral value lower limit (Yes in step S3), the microprocessor 10 increases the coefficient of the calculation unit 204 (step S5). On the other hand, if the in-screen luminance integral value is equal to or greater than the target luminance integral value lower limit (No in step S3), the microprocessor 10 does not adjust the coefficient of the calculation unit 204. By repeatedly performing such processing, the in-screen luminance integral value approaches the target luminance integral value.

ゲインアップと画素加算を併用した輝度制御処理のイメージを示す図9は、照度環境が明るい状態から暗い状態に遷移する過程において、最も明るい環境ではゲインアップのみによる輝度制御を実施するが、以降、暗い環境ではゲインアップと画素加算を同時使用して輝度制御を行うことを示す。つまり、ゲインアップによる輝度制御量と画素加算による輝度制御量を切り替える照度領域が存在する。ゲインアップと画素加算という異なる高感度化手法を併用する場合、切り替えのタイミングで解像度の変化やノイズ量の変化等、画面の見え方が大きく変わり、映像に乱れが発生するという課題があった。一方、本発明は、画素加算において、加算する周辺画素それぞれに加算前に係数を掛けることが出来る回路を備えることにより、係数を小数点以下まで制御することが可能となり、従来の整数倍単位の制御に比べて、より細かな輝度レベルの制御を行うことが出来るようになった。図4は、本発明に係る撮像装置が実行する輝度制御処理のイメージを示す説明図である。図4と図9を比較すると、本発明の撮像装置が実行する画素加算処理は「画素加算なし」から「5画素加算」のいずれの画素加算でも細かく輝度レベルを制御できることが分かる。したがって、ゲインアップと併用しなくても、細かな輝度レベルの制御を行うことが可能となり、瞬時の照度変化に対応することが出来るという効果がある。また、図9はゲインアップと画素加算を切り替える照度領域(タイミング)が存在することを示しているが、図4によると、ゲインアップと画素加算を切り替える照度領域(タイミング)は存在しないことが分かる。   FIG. 9 showing an image of luminance control processing using both gain-up and pixel addition performs luminance control only by gain-up in the brightest environment in the process of transition from a bright state to a dark state. In a dark environment, it indicates that luminance control is performed using gain increase and pixel addition simultaneously. That is, there is an illuminance region that switches between a luminance control amount by gain increase and a luminance control amount by pixel addition. When different sensitivity enhancement methods such as gain increase and pixel addition are used in combination, there is a problem that the appearance of the screen changes greatly at the timing of switching, such as a change in resolution and a change in noise amount, and the image is disturbed. On the other hand, according to the present invention, in the pixel addition, by providing a circuit capable of multiplying each peripheral pixel to be added by a coefficient before the addition, the coefficient can be controlled to the decimal point, and the conventional control of integer multiple units is possible. Compared to the above, the brightness level can be controlled more finely. FIG. 4 is an explanatory diagram showing an image of luminance control processing executed by the imaging apparatus according to the present invention. Comparing FIG. 4 and FIG. 9, it can be seen that the pixel addition process executed by the imaging apparatus of the present invention can finely control the luminance level by any pixel addition from “no pixel addition” to “5 pixel addition”. Therefore, it is possible to perform fine brightness level control without using it together with gain increase, and there is an effect that it is possible to cope with an instantaneous illuminance change. 9 shows that there is an illuminance area (timing) for switching between gain-up and pixel addition, but according to FIG. 4, it can be seen that there is no illuminance area (timing) for switching between gain-up and pixel addition. .

また、常に映像を出力し続ける動画撮影では、画素加算による輝度変化のタイミングとゲインアップによる輝度変化のタイミングを完全に一致させる必要があり、少しでもタイミングがずれてしまうと、なめらかな輝度変化を実現できないという課題があった。しかし、本発明は、加算する周辺画素それぞれに加算前に係数を掛けることが出来る回路を備えることにより、係数を小数点以下まで制御することが可能となり、従来の整数倍単位の制御に比べて、より細かな輝度レベルの制御を行うことが出来るので、ある照度下で、ゲインアップと併用しなくても、細かな輝度レベルの制御を行うことが可能である。したがって、画素加算とゲインアップによる輝度変化のタイミングを合わせるための特段の対策を行う必要がない。   Also, in video shooting that always outputs video, it is necessary to make the timing of luminance change due to pixel addition completely match the timing of luminance change due to gain increase, and if the timing is slightly shifted, smooth luminance changes will occur. There was a problem that could not be realized. However, according to the present invention, it is possible to control the coefficient to the decimal point by providing a circuit that can multiply the peripheral pixels to be added before the addition, compared to the conventional integer multiple unit control, Since it is possible to control the brightness level more finely, it is possible to control the brightness level finely under certain illuminance without using the gain increase. Therefore, it is not necessary to take special measures to match the timing of luminance change due to pixel addition and gain increase.

なお、上記説明では、画素加算によって輝度制御を行う実施例を説明したが、シャッター速度の調整のほか、照度の変化に伴いアイリス制御、ゲインアップ量の調整を行い、アイリス制御、ゲインアップ量の調整による感度アップが上限に達した時に画素加算を動作させるようにしても良い。従来のように、一定の照度下で、画素加算による制御を詳細化するためにゲインアップを同時使用する必要がないので、ゲインアップと画素加算の動作モードの切り替えタイミングでの映像に乱れは抑制される。   In the above description, the embodiment in which the brightness control is performed by pixel addition has been described. However, in addition to the adjustment of the shutter speed, the iris control and the gain increase amount are adjusted in accordance with the change in illuminance, and the iris control and the gain increase amount are adjusted. Pixel addition may be operated when the sensitivity increase due to the adjustment reaches the upper limit. As in the past, there is no need to use gain-up at the same time to refine control by pixel addition under a fixed illuminance, so disturbances in the video at the timing of switching between gain-up and pixel addition operation modes are suppressed. Is done.

実施の形態2.
次に、本発明の実施の形態2について説明する。本実施の形態では、演算部204の係数の増減にテーブルを使用する方法について説明する。本実施の形態に係る撮像装置の構成は図1、図2で説明したものと同様である。図6は、本発明の実施の形態2に係る撮像装置が実行する輝度制御処理を示すフローチャートである。図6において、輝度積分値計算部8は画面内輝度積分値の算出を行う(ステップ11)。次に、マイクロプロセッサ10は、輝度積分値計算部8が計算した画面内輝度積分値と目標輝度積分値の割合を算出し(ステップ12)、増減量テーブルから増減量を読み取る(ステップ13)。
Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described. In the present embodiment, a method of using a table for increasing / decreasing the coefficient of the arithmetic unit 204 will be described. The configuration of the imaging apparatus according to this embodiment is the same as that described with reference to FIGS. FIG. 6 is a flowchart showing the brightness control processing executed by the imaging apparatus according to Embodiment 2 of the present invention. In FIG. 6, the luminance integral value calculation unit 8 calculates the in-screen luminance integral value (step 11). Next, the microprocessor 10 calculates the ratio of the in-screen luminance integral value calculated by the luminance integral value calculation unit 8 and the target luminance integral value (step 12), and reads the increase / decrease amount from the increase / decrease amount table (step 13).

図7は、増減量テーブルの一例を示す説明図である。図8は、画素加算量テーブルの一例を示す説明図である。例えば、画面内輝度積分値と目標輝度積分値の割合が1.8のとき、図7に示すテーブルの「画素加算量テーブル加減算値」は+2を示している。この「+2」は、画面内輝度積分値と目標輝度積分値の割合が1.8のとき、現在使用している画素加算量テーブルのテーブル番号に+2のテーブル番号が付された画素加算量テーブルに変更することを示す。   FIG. 7 is an explanatory diagram showing an example of the increase / decrease amount table. FIG. 8 is an explanatory diagram illustrating an example of a pixel addition amount table. For example, when the ratio between the in-screen luminance integral value and the target luminance integral value is 1.8, the “pixel addition amount table addition / subtraction value” in the table shown in FIG. 7 indicates +2. This “+2” is a pixel addition amount table in which the table number of +2 is added to the table number of the currently used pixel addition amount table when the ratio between the in-screen luminance integration value and the target luminance integration value is 1.8. Indicates change.

マイクロプロセッサ10は、図7に示す増減量テーブルより読み取った増減量だけ、画素加算量テーブルのテーブル番号を増減し、係数を読み取る(ステップ14)。例えば、現在の画素加算量がテーブル番号5であった場合に、増減量を+2(2増加)とすると、図7より画素加算量テーブルは7となる。図8を参照してテーブル番号7を見ると、係数K223は0から0.5に変化させることが分かる。このように、演算部204の係数をテーブルで管理することによって、多数ある係数を一元管理することができ、係数を滑らかに変化させることができる。また、テーブルの増減量を輝度割合から決めることで、輝度差が大きい時ほど画素加算量も大きく変化する制御となるため、被写体照度に対する追従性が向上する。   The microprocessor 10 increases or decreases the table number of the pixel addition amount table by the increase / decrease amount read from the increase / decrease amount table shown in FIG. 7, and reads the coefficient (step 14). For example, if the current pixel addition amount is table number 5 and the increase / decrease amount is +2 (increase by 2), the pixel addition amount table is 7 from FIG. Looking at table number 7 with reference to FIG. 8, it can be seen that the coefficient K223 is changed from 0 to 0.5. In this way, by managing the coefficients of the calculation unit 204 in a table, a large number of coefficients can be managed in a unified manner, and the coefficients can be changed smoothly. Further, by determining the amount of increase / decrease in the table from the luminance ratio, the control is such that the pixel addition amount changes greatly as the luminance difference increases, so that the followability to the subject illuminance is improved.

なお、これまでに説明したテーブルや図は一例であり、さらに細かく画素加算量を制御するテーブルを使用することで、よりスムーズな輝度変化を実現することができる。また、ここまで説明した形態では、画素加算による輝度制御の方法についてのみ述べたが、ゲインアップ、アイリス制御、高速シャッター等、他の輝度制御が搭載されている撮像装置であれば、他の輝度制御による感度アップが上限に達した時に画素加算を動作させるなど、併用して使用しても良い。また、今回は9画素を加算する場合を例に説明したが、9画素である必要性はなく、さらに周辺の画素を加算する構成として感度を向上させたり、加算する画素数を減らして回路を簡略化しても良い。   Note that the tables and figures described so far are merely examples, and smoother changes in luminance can be realized by using a table that controls the pixel addition amount more finely. In the embodiments described so far, only the luminance control method by pixel addition has been described. However, if the imaging apparatus is equipped with other luminance controls such as gain-up, iris control, high-speed shutter, etc. It may be used in combination, for example, pixel addition is activated when the sensitivity increase by control reaches the upper limit. In addition, the case where 9 pixels are added has been described as an example this time, but there is no need for 9 pixels. Further, the configuration is such that the peripheral pixels are added, the sensitivity is improved, or the circuit is reduced by reducing the number of pixels to be added. It may be simplified.

また、今回はテーブルを使用して加算する画素の位置を決めていたが、テーブルである必要はない。例えば、注目画素との差分の少ない画素を優先的に使用する構成とすることで、解像度の低下を抑えることができる。また、今回は画面内輝度積分値の算出に全画素を加算したが、全ての画素を用いる必要はない。例えば、一定箇所の画素のみを用いて輝度積分値を算出したり、画素をいくつかのエリアにわけてそれぞれで画面内輝度積分値を算出し、個別に輝度制御を行っても良い。また、目標輝度積分値も常に一定である必要はない。例えば、照度が暗くなる(ゲイン増幅量や画素加算量が上がる)時に目標輝度積分値が低くなる設定とすることで、発生するノイズを目立たなくすることができる。   In addition, although the position of the pixel to be added is determined using a table this time, it does not have to be a table. For example, it is possible to suppress a decrease in resolution by preferentially using a pixel having a small difference from the target pixel. In addition, although all the pixels are added to the calculation of the in-screen luminance integral value this time, it is not necessary to use all the pixels. For example, the luminance integrated value may be calculated using only pixels at a fixed location, or the luminance integrated value within the screen may be calculated for each of the pixels divided into several areas, and the luminance control may be performed individually. Further, the target luminance integral value does not always have to be constant. For example, the noise generated can be made inconspicuous by setting the target luminance integrated value to be low when the illuminance becomes dark (the gain amplification amount or the pixel addition amount increases).

また、今回はNTSC方式(インターレース方式)を例に挙げたが、PAL方式やプログレッシブ方式(時間軸方向の画素加算は、フィールド遅延ではなくフレーム遅延となる)の信号であっても良い。信号の種類についても、輝度信号と色差信号の組み合わせや、RGB信号や、モノクロ映像で輝度信号のみ等、種類を問わない。また、アナログ信号だけに限らず、デジタル信号でも良い。また、固体撮像素子については、CCDやCMOS等、撮像可能なイメージセンサであればどのようなものでも良い。   In addition, the NTSC system (interlace system) is taken as an example this time, but a PAL system or progressive system signal (pixel addition in the time axis direction is not a field delay but a frame delay) may be used. The type of signal may be any type, such as a combination of a luminance signal and a color difference signal, an RGB signal, or only a luminance signal in a monochrome image. Further, not only analog signals but also digital signals may be used. The solid-state image sensor may be any image sensor that can capture an image, such as a CCD or CMOS.

上記説明のように、演算部204の係数をテーブルで管理することによって、多数ある係数を一元管理することができ、係数を滑らかに変化させることができる。また、テーブルの増減量を輝度割合から決めることで、輝度差が大きい時ほど画素加算量も大きく変化する制御となるため、被写体照度に対する追従性が向上し、照度変化に対する映像の乱れを最小限にすることができる。   As described above, by managing the coefficients of the calculation unit 204 in a table, a large number of coefficients can be managed in a unified manner, and the coefficients can be changed smoothly. In addition, by determining the amount of increase / decrease in the table from the luminance ratio, the amount of pixel addition changes greatly as the luminance difference increases, improving followability with subject illuminance and minimizing image disturbance due to illuminance changes. Can be.

1 レンズ群、2 固体撮像素子、3 CDS、4 アンプ、5 A/D変換器、
6 映像信号処理部、7 画素加算回路、8 輝度積分値計算部、9 映像信号出力部、
10 マイクロプロセッサ、11 レンズ駆動回路、12 タイミングジェネレータ、
201 フィールド遅延部、202 ライン遅延部、203 ピクセル遅延部、
204 演算部、205 加算部
1 lens group, 2 solid-state imaging device, 3 CDS, 4 amplifier, 5 A / D converter,
6 video signal processing unit, 7 pixel addition circuit, 8 luminance integrated value calculation unit, 9 video signal output unit,
10 microprocessor, 11 lens drive circuit, 12 timing generator,
201 field delay unit, 202 line delay unit, 203 pixel delay unit,
204 arithmetic unit, 205 addition unit

Claims (4)

撮像手段と、
この撮像手段から読み出された信号に基づいて、所定の走査方式の撮像信号を出力する信号処理手段と、
この信号処理手段から出力された前記撮像信号をフィールド単位、ライン単位及びピクセル単位で遅延させて注目画素及び複数の周辺画素の各画素値を出力する遅延手段、この遅延手段から出力された各画素値のそれぞれに対して、外部より供給された所定の係数を掛ける演算手段、この演算手段で所定の係数が掛けられた各画素値を加算する加算手段を有する画素加算手段と、
この画素加算手段から出力された信号より画面の明るさを検出するとともに、画面の明るさが一定になるように、前記画素加算手段の演算手段に供給する前記係数を制御する制御手段とを設けたことを特徴とする撮像装置。
Imaging means;
A signal processing means for outputting an imaging signal of a predetermined scanning method based on the signal read from the imaging means;
Delay means for delaying the imaging signal output from the signal processing means in field units, line units, and pixel units to output pixel values of the target pixel and a plurality of peripheral pixels, and each pixel output from the delay means A pixel adding means having a calculating means for multiplying each of the values by a predetermined coefficient supplied from the outside, and an adding means for adding each pixel value multiplied by the predetermined coefficient by the calculating means;
Control means for detecting the brightness of the screen from the signal output from the pixel addition means and for controlling the coefficient supplied to the calculation means of the pixel addition means so that the brightness of the screen is constant; An imaging apparatus characterized by that.
制御手段は、画素加算手段が有する演算手段が各画素値に乗じる係数をテーブルとして記憶しており、画面の明るさに基づいて前記係数を制御することを特徴とする請求項1に記載の撮像装置。 2. The imaging according to claim 1, wherein the control unit stores, as a table, a coefficient by which the calculation unit included in the pixel addition unit multiplies each pixel value, and controls the coefficient based on the brightness of the screen. apparatus. 制御手段は、撮像環境の照度に応じて、撮像手段に入射する光量を調節するアイリス制御、撮像信号の増幅利得を調節する利得制御を実行して用いて輝度制御を行うとともに、前記利得制御と画素加算を照度に応じて選択的に実行することを特徴とする請求項1または2に記載の撮像装置。 The control means performs brightness control by performing iris control for adjusting the amount of light incident on the image pickup means and gain control for adjusting the amplification gain of the image pickup signal in accordance with the illuminance of the image pickup environment. The image pickup apparatus according to claim 1, wherein pixel addition is selectively executed according to illuminance. 撮像手段から読み出された信号に基づいて、所定の走査方式の撮像信号を出力する信号出力処理と、
この信号出力処理された前記撮像信号をフィールド単位、ライン単位及びピクセル単位で遅延させて注目画素及び複数の周辺画素の各画素値を出力する遅延処理、この遅延処理された各画素値のそれぞれに対して、外部より供給された所定の係数を掛ける演算処理、この演算処理により所定の係数が掛けられた各画素値を加算する加算処理を含む画素加算処理と、
この画素加算処理で加算された信号より画面の明るさを検出するとともに、画面の明るさが一定になるように、前記画素加算処理が実行する演算処理で使用される前記係数を制御する制御処理とを含むことを特徴とする輝度制御方法。
A signal output process for outputting an imaging signal of a predetermined scanning method based on a signal read from the imaging means;
Delay processing for outputting the pixel values of the target pixel and a plurality of peripheral pixels by delaying the imaging signal subjected to the signal output processing in a field unit, a line unit, and a pixel unit, and each of the delayed pixel values On the other hand, a pixel addition process including an arithmetic process for multiplying a predetermined coefficient supplied from the outside, an addition process for adding each pixel value multiplied by the predetermined coefficient by this arithmetic process,
A control process for detecting the brightness of the screen from the signals added in the pixel addition process and for controlling the coefficient used in the arithmetic process executed by the pixel addition process so that the brightness of the screen is constant. A brightness control method comprising:
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