JP2013030498A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- JP2013030498A JP2013030498A JP2009259240A JP2009259240A JP2013030498A JP 2013030498 A JP2013030498 A JP 2013030498A JP 2009259240 A JP2009259240 A JP 2009259240A JP 2009259240 A JP2009259240 A JP 2009259240A JP 2013030498 A JP2013030498 A JP 2013030498A
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- Prior art keywords
- insulating film
- electrode pad
- opening
- semiconductor device
- ubm
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Abstract
Description
本発明は、半導体装置に関し、特に、半田バンプの下に形成されるアンダーバリアメタル(Under Barrier Metal:UBM)を備える半導体装置に関する。 The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an under barrier metal (UBM) formed under a solder bump.
半導体装置をフリップ実装するためには、一般に、電極パッドの上にバンプを設けたバンプ電極構造を採用する。例えば、特許文献1に開示されている技術を従来技術として挙げることができる。図16を参照しながら、特許文献1に記載されている内容について説明する。
In order to flip-mount a semiconductor device, a bump electrode structure in which bumps are provided on electrode pads is generally employed. For example, the technique disclosed in
図16に示すように、アルミパッド114の上には、アルミパッド114を露出する開口部を有するパッシベーション膜113が形成されている。この開口部には、密着金属層115aとバリア金属層115bとが順次形成され、その上に、金属メッキバンプ116が形成されている。金属メッキバンプ116の上には、半田バンプ120が形成されている。ここで、特許文献1では、図16に示すように、開口部の全面を覆い、且つ、パッシベーション膜113の上面に達するまで連続的に密着金属層115aとバリア金属層115bを形成している。また、他にも関連する文献として、特許文献2〜9がある。
As shown in FIG. 16, a
前記従来の技術においては、開口部の全面を覆い、且つ、パッシベーション膜の上面に達するまで連続的にUBMを形成し、その上に半田バンプを形成している。このようにすると、パッシベーション膜の開口部に形成される段差部(開口部におけるパッシベーション膜の表面からアルミパッドに向かう部分)にまでUBMが形成されることとなる。 In the conventional technique, the UBM is continuously formed so as to cover the entire surface of the opening and reach the upper surface of the passivation film, and solder bumps are formed thereon. In this way, the UBM is formed up to the stepped portion formed in the opening of the passivation film (portion from the surface of the passivation film toward the aluminum pad in the opening).
しかし、このようなバンプ電極構造において、段差部の段差が大きいと、段差部においてUBMの応力が大きくなり、半導体装置に形成されたトランジスタの特性が変動してしまう。 However, in such a bump electrode structure, if the level difference of the stepped portion is large, the stress of the UBM becomes large in the stepped portion, and the characteristics of the transistor formed in the semiconductor device will fluctuate.
また、最近の微細プロセスでは、電気特性の向上のために、配線が形成される層間絶縁膜に抵誘電率のlow−k材料等を用いることが多く、これらの材料は、従来よりも脆弱で且つ密着性が悪い。このため、半導体装置を組み立てる際に、UBM及びその上の半田バンプから応力を受けると、層間絶縁膜において密着力の低下等が引き起こされるおそれがある。 In recent fine processes, a low-k material having a dielectric constant is often used for an interlayer insulating film on which wiring is formed in order to improve electrical characteristics, and these materials are more fragile than conventional ones. In addition, the adhesion is poor. For this reason, when assembling a semiconductor device, if stress is received from the UBM and the solder bumps thereon, there is a risk of causing a decrease in the adhesion of the interlayer insulating film.
本発明は、前記従来の問題に鑑み、その目的は、UBMに起因する応力集中を緩和し、トランジスタの特性の変動を抑制することができるパッド電極構造を備える半導体装置を得られるようにすることにある。 The present invention has been made in view of the above-described conventional problems, and an object thereof is to obtain a semiconductor device having a pad electrode structure that can relieve stress concentration caused by UBM and suppress fluctuations in transistor characteristics. It is in.
前記の目的を達成するために、本発明に係る第1の半導体装置は、基板の上に形成された電極パッドと、電極パッドの上に形成され、且つ、電極パッドの一部が露出するような第1開口部を有する第1絶縁膜と、第1絶縁膜の上に形成され、且つ、第1開口部における少なくとも一部が露出するような第2開口部を有する第2絶縁膜と、第2絶縁膜及び電極パッドの上に形成されたアンダーバリアメタルとを備え、アンダーバリアメタルは、第2絶縁膜の表面における第2開口部の外側である第1領域と電極パッドの表面における第2開口部の内側である第2領域とにより挟まれる第3領域によって分離されていることを特徴とする。 To achieve the above object, a first semiconductor device according to the present invention is formed on an electrode pad formed on a substrate, on the electrode pad, and a part of the electrode pad is exposed. A first insulating film having a first opening, a second insulating film formed on the first insulating film and having a second opening so that at least a part of the first opening is exposed; An under-barrier metal formed on the second insulating film and the electrode pad, the under-barrier metal being a first region outside the second opening on the surface of the second insulating film and the first barrier on the surface of the electrode pad. It is characterized by being separated by a third region sandwiched between a second region inside the two openings.
本発明に係る第1の半導体装置は、アンダーバリアメタルの上に半田バンプが形成されていることが好ましい。 In the first semiconductor device according to the present invention, it is preferable that solder bumps are formed on the under barrier metal.
この場合、第3領域において、半田バンプは、第2絶縁膜又は電極パッドとの間に空隙を形成していてもよい。 In this case, in the third region, the solder bump may form a gap between the second insulating film or the electrode pad.
本発明に係る第1の半導体装置は、第2領域において、アンダーバリアメタルは、第1絶縁膜と接触していてもよい。 In the first semiconductor device according to the present invention, the under barrier metal may be in contact with the first insulating film in the second region.
本発明に係る第1の半導体装置は、第1領域において、アンダーバリアメタルは、複数に分割されていることが好ましい。 In the first semiconductor device according to the present invention, the under barrier metal is preferably divided into a plurality of parts in the first region.
本発明に係る第1の半導体装置は、第2領域において、アンダーバリアメタルは、複数に分割されていることが好ましい。 In the first semiconductor device according to the present invention, the under barrier metal is preferably divided into a plurality of parts in the second region.
本発明に係る第2の半導体装置は、基板の上に形成された電極パッドと、電極パッドの上に形成され、且つ、電極パッドの一部が露出するような第1開口部を有する第1絶縁膜と、第1絶縁膜の上に形成され、且つ、第1開口部における少なくとも一部が露出するような第2開口部を有する第2絶縁膜と、第2絶縁膜及び電極パッドの上に形成されたアンダーバリアメタルとを備え、第2絶縁膜は、第2絶縁膜の表面から電極パッドに向かう傾斜部を有し、傾斜部における基板の平面方向に対する傾斜角は45度以下であることを特徴とする。 A second semiconductor device according to the present invention includes an electrode pad formed on a substrate, and a first opening formed on the electrode pad and having a first opening that exposes a part of the electrode pad. An insulating film, a second insulating film formed on the first insulating film and having a second opening so that at least a part of the first opening is exposed, and on the second insulating film and the electrode pad The second insulating film has an inclined portion directed from the surface of the second insulating film to the electrode pad, and an inclination angle of the inclined portion with respect to the planar direction of the substrate is 45 degrees or less. It is characterized by that.
本発明に係る第2の半導体装置において、第1絶縁膜は、複数の段差を有し、アンダーバリアメタルは、複数の段差を含む第1絶縁膜の上にも形成されることが好ましい。 In the second semiconductor device according to the present invention, it is preferable that the first insulating film has a plurality of steps, and the under barrier metal is also formed on the first insulating film including the plurality of steps.
本発明に係る第2の半導体装置において、傾斜部及び複数の段差における基板の平面方向に対する傾斜角の平均値は、45度以下であることが好ましい。 In the second semiconductor device according to the present invention, it is preferable that the average value of the inclination angle with respect to the planar direction of the substrate at the inclined portion and the plurality of steps is 45 degrees or less.
本発明に係る第3の半導体装置は、基板の上に形成された電極パッドと、電極パッドの上に形成され、且つ、電極パッドの一部が露出するような第1開口部を有する第1絶縁膜と、第1絶縁膜の上に形成され、且つ、第1開口部における少なくとも一部が露出するような第2開口部を有する第2絶縁膜と、第1絶縁膜及び電極パッドの上に形成されたアンダーバリアメタルとを備え、第1絶縁膜は、複数の段差を有し、アンダーバリアメタルは、複数の段差を含む第1絶縁膜の上に形成されることを特徴とする。 A third semiconductor device according to the present invention includes an electrode pad formed on a substrate, and a first opening formed on the electrode pad and having a first opening that exposes part of the electrode pad. An insulating film, a second insulating film formed on the first insulating film and having a second opening that exposes at least a part of the first opening, and on the first insulating film and the electrode pad And the under barrier metal is formed on the first insulating film including the plurality of steps. The under barrier metal is formed on the first insulating film including the plurality of steps.
本発明に係る第3の半導体装置において、複数の段差における基板の平面方向に対する傾斜角の平均値は、45度以下であることが好ましい。 In the third semiconductor device according to the present invention, the average value of the inclination angles with respect to the planar direction of the substrate at the plurality of steps is preferably 45 degrees or less.
本発明に係る第2の半導体装置及び第3の半導体装置は、アンダーバリアメタルの上に半田バンプが形成されていることが好ましい。 In the second semiconductor device and the third semiconductor device according to the present invention, it is preferable that solder bumps are formed on the under barrier metal.
本発明に係る第1の半導体装置、第2の半導体装置及び第3の半導体装置において、第1絶縁膜は、窒化シリコン、窒素含有酸化シリコン又は酸化シリコンからなる無機材料膜を含むことが好ましい。 In the first semiconductor device, the second semiconductor device, and the third semiconductor device according to the present invention, the first insulating film preferably includes an inorganic material film made of silicon nitride, nitrogen-containing silicon oxide, or silicon oxide.
本発明に係る第1の半導体装置、第2の半導体装置及び第3の半導体装置において、第2絶縁膜は、ポリイミド、ベンゾシクロブテン又はフッ素樹脂からなる有機材料膜を含むことが好ましい。 In the first semiconductor device, the second semiconductor device, and the third semiconductor device according to the present invention, the second insulating film preferably includes an organic material film made of polyimide, benzocyclobutene, or a fluororesin.
本発明に係る半導体装置によると、電極パッドの上に形成されるUBMに起因する応力集中を十分に緩和することが可能となる。そのため、半導体装置に形成されたトランジスタの特性変動を抑制することができ、回路動作マージンを確保でき、安定した動作を可能とする。 According to the semiconductor device of the present invention, it is possible to sufficiently relax the stress concentration caused by the UBM formed on the electrode pad. Therefore, characteristic variation of the transistor formed in the semiconductor device can be suppressed, a circuit operation margin can be secured, and stable operation can be performed.
本発明の半導体装置の実施形態について図面を参照しながら説明する。また、以下に示す各図、種々の構成要素の形状、材料及び寸法等はいずれも望ましい例を挙げるものであり、示した内容には限定されない。発明の趣旨を逸脱しない範囲であれば、記載内容に限定されることなく適宜変更可能である。また、他の実施形態および変形例に記載の内容を矛盾の無い範囲で適宜組み合わせることも可能である。 Embodiments of a semiconductor device of the present invention will be described with reference to the drawings. Further, each of the following drawings and shapes, materials, dimensions, and the like of various components are preferable examples, and are not limited to the contents shown. As long as it does not deviate from the gist of the invention, it can be appropriately changed without being limited to the description. Moreover, it is also possible to combine suitably the content as described in other embodiment and modification in the range without a contradiction.
(第1の実施形態)
本発明の第1の実施形態に係る半導体装置ついて図1及び図2を用いて説明する。なお、図2は、半田バンプ11を省略している。
(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. In FIG. 2, the
図1に示すように、トランジスタ等の回路素子2を有する半導体基板1の上には、複数の配線からなる第1配線層3が形成され、その上には、複数の配線からなる複数の第2配線層4が形成されている。最上層配線の上に形成された第3絶縁膜5には電極パッド6が形成されている(最上層配線と電極パッド6とは接続している)。第3絶縁膜5を含む電極パッド6の上には、電極パッド6の一部が露出するような第1開口部を有する第1絶縁膜7が形成されている。第1絶縁膜7の上には、第1開口部の少なくとも一部を含むような(第1開口部の少なくとも一部を露出するような)、第2開口部を有する第2絶縁膜8が形成されている。第2絶縁膜8及び電極パッド6の上には、アンダーバリアメタル(UBM)の一部であるシード層9及びUBM層10が形成されている。UBM層10の上には、半田バンプ11が形成されている。
As shown in FIG. 1, a
ここで、シード層9及びUBM層10からなるUBMは、第2絶縁膜8の表面における第2開口部の外側である第1領域と、電極パッド6の表面における第2開口部の内側である第2領域とで挟まれる第3領域により分離されている。言い換えれば、第2絶縁膜8の第2開口部に形成される段差部(第2開口部における、第2絶縁膜8の表面から電極パッド6に向かう部分)には、UBMが形成されていない。
Here, the UBM composed of the
次に、段差部の近傍におけるUBMの構造について図2を参照しながら説明する。 Next, the structure of the UBM in the vicinity of the step portion will be described with reference to FIG.
図2に示すように、第2絶縁膜8の第2開口部の近傍に形成されるUBM層10は、第2開口部の縁部13よりも外側である第1領域と、電極パッド6の表面における第2開口部の縁部13よりも内側である第2領域に形成されている。一方、第1領域と第2領域とにより挟まれる第3領域においては、UBM層10が形成されていない。このように、第2絶縁膜8の第2開口部に形成される段差部には、UBMが形成されていない。
As shown in FIG. 2, the
本実施形態に係る半導体装置によると、第2絶縁膜8の段差部にUBMを形成しないことにより、UBMに段差部が無い構造(応力緩和構造)とすることができ、第2絶縁膜8の段差部において、UBMに起因する応力集中を緩和することができる効果がある。
According to the semiconductor device according to the present embodiment, by not forming the UBM at the stepped portion of the second
従来は、第3領域においてもUBMを形成していた。言い換えれば、第2開口部の全てを含むようにして、段差部を被覆するようにUBMを形成していた。しかし、従来の構造では、第2絶縁膜8の段差部にUBMからの応力が集中することになる。一方、本実施形態に係る半導体装置によると、第2絶縁膜8の段差部にUBMを形成しないので、UBMに起因する応力が段差部に集中するのを抑制することが可能となる。
Conventionally, the UBM is also formed in the third region. In other words, the UBM is formed so as to cover the stepped portion so as to include all of the second opening. However, in the conventional structure, the stress from the UBM concentrates on the step portion of the second
なお、第3領域の幅は、5μm〜10μm程度であることが好ましい。言い換えれば、UBM層10が形成されていない部分の幅が5μm〜10μm程度であることが好ましい。さらに言い換えれば、内側のUBM層10と外側のUBM層10との間の距離が5μm〜10μm程度であることが好ましい。
The width of the third region is preferably about 5 μm to 10 μm. In other words, the width of the portion where the
また、UBMとは、アルミニウム等が形成されている層(第3絶縁膜5が形成される層)と半田バンプ11との密着性を確保するために形成される。
UBM is formed in order to ensure adhesion between a layer in which aluminum or the like is formed (layer in which the third
また、UBMは、中央部と中央部を囲むリング部とにより構成されることとなるが、半田バンプ11によって、両者が電気的に接続されていることとなる。
The UBM is composed of a central portion and a ring portion surrounding the central portion, and both are electrically connected by the
また、本実施形態では、段差部全てにUBMがない構造としている。しかし、部分的には第2絶縁膜8における段差部又は第3領域に、UBMが形成されていても構わない。段差部における応力集中を緩和できる程度に、段差部にUBMが形成されていれば構わない。
Moreover, in this embodiment, it is set as the structure without UBM in all the level | step-difference parts. However, the UBM may be partially formed in the stepped portion or the third region in the second
また、本実施形態では、パッドの開口部の形状を円形としているが、八角形等の形状としても構わない。 In the present embodiment, the shape of the opening of the pad is circular, but it may be an octagon or the like.
次に、本発明の第1の実施形態に係る半導体装置の製造方法ついて図3〜図6を参照しながら説明する。なお、図3及び図4を用いて、UBMを形成するまでの製造方法を説明し、図5及び図6を用いて、UBMの上に半田を形成する方法について説明する。なお、図5及び図6においては、半田めっきを行う方法について説明しているが、半田印刷法等の他の方法を用いても構わない。 Next, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. A manufacturing method until the UBM is formed will be described with reference to FIGS. 3 and 4, and a method of forming solder on the UBM will be described with reference to FIGS. 5 and 6. 5 and 6, the method for performing solder plating is described, but other methods such as a solder printing method may be used.
まず、図3(a)に示すように、半導体基板1にトランジスタ等を構成する回路素子2を形成する。次に、配線層のうち最下層に位置し且つ複数の配線からなる第1配線層3、及びその上に位置する複数の第2配線層4を有する層間絶縁膜を形成する。なお、この層間絶縁膜は、複数の絶縁膜から構成されている。次に、層間絶縁膜の上に第3絶縁膜5を形成し、第3絶縁膜5内に電極パッド6を形成する。次に、電極パッド6及び第3絶縁膜5の上に、第1絶縁膜7を形成し、電極パッド6の一部が露出するような第1開口部を形成する。次に、第1絶縁膜7の上に第2絶縁膜8を形成し、第1開口部の少なくとも一部を含むような第2開口部を形成する。
First, as shown in FIG. 3A, a
ここで、第1絶縁膜7は、窒化シリコン(SiNx)、窒素含有酸化シリコン(SiON)又は酸化シリコン(SiO2)からなる無機材料膜等により形成され、例えば0.5μm〜1μm程度の厚さとなるように形成することが好ましい。また、第2絶縁膜8は、ポリイミド、ベンゾシクロブテン(BCB)又はフッ素樹脂からなる有機材料膜等により形成され、例えば3μm〜10μm程度の厚さとなるように形成することが好ましい。有機絶縁膜のような柔らかい膜を使用することにより、後の工程において形成される半田バンプの横方向の応力を抑制すると共に、縦方向の応力も緩和できる構造となる。また、第2開口部の開口径は、第1開口部の開口径よりも小さいことが好ましい。第2開口部が形成される第2絶縁膜8の上には、UBMを介して半田バンプが形成されることとなる。その際の応力緩和の効果を鑑みると、第2開口部の開口径は、第1開口部の開口径よりも小さいことが好ましく、例えば、60μm程度であることが好ましい。
Here, the first insulating
次に、図3(b)に示すように、第2開口部を含む第2絶縁膜8の上の全面に、シード層9を形成する。その後、UBMを形成する領域がパターニングされたレジスト膜12を形成する。
Next, as shown in FIG. 3B, a
次に、図3(c)に示すように、電解めっき法を用いることによって、例えばニッケル(Ni)等によりシード層9の上にUBM層10を形成する。なお、UBM層10の最上面には金(Au)等がめっきされる。
Next, as shown in FIG. 3C, the
次に、図4(a)に示すように、レジスト膜12を除去する。
Next, as shown in FIG. 4A, the resist
次に、半田バンプを形成するが、ここでは、半田ボールの搭載又は半田印刷法によりUBMの上に半田バンプを形成する方法について説明する。図4(b)に示すように、形成されたUBM層10をマスクとして用い、UBM層10が形成されていない部分に存在するシード層9を除去する。その後、半田ボールの搭載又は半田印刷法によりUBMの上に半田バンプを形成する(図示せず)。このようにして、本実施形態に係る半導体装置を形成することができる。
Next, solder bumps are formed. Here, a method for forming solder bumps on the UBM by mounting solder balls or by solder printing will be described. As shown in FIG. 4B, the formed
また、半田めっき法によって半田バンプを形成する方法について、図5及び図6を参照しながら説明する。 A method for forming solder bumps by solder plating will be described with reference to FIGS.
図4(a)のような状態の半導体装置の上に、図5(a)に示すように、レジスト膜12を形成する。ここで、UBM層10が形成されている部分にはレジストが形成されないようにパターニングされたレジスト膜12を用意する。又は、図3(b)において形成するレジスト膜12の厚さを厚くすることにより、図5(a)のようなレジスト膜12を用意しても構わない。
As shown in FIG. 5A, a resist
次に、図5(b)に示すように、めっき法を用いて、UBM層10の上に半田めっき膜11Aを形成する。
Next, as shown in FIG. 5B, a
次に、図6(a)に示すように、レジスト膜12を除去する。その後、形成されているUBM層10をマスクとして使用して、UBM層10が形成されていない部分に存在するシード層9を除去する。
Next, as shown in FIG. 6A, the resist
次に、図6(b)に示すように、リフローを行うことにより、ボール形状の半田バンプ11がUBMの上に形成されることとなる。ここで、UBMの厚さは5μm〜10μm程度となり、半田バンプ11を上から見た径は、80μm〜100μm程度となる。
Next, as shown in FIG. 6B, by performing reflow, the ball-shaped solder bumps 11 are formed on the UBM. Here, the thickness of the UBM is about 5 μm to 10 μm, and the diameter of the
(第1の実施形態の第1の変形例)
本発明の第1の実施形態の第1の変形例に係る半導体装置ついて図7を参照しながら説明する。
(First modification of the first embodiment)
A semiconductor device according to a first modification of the first embodiment of the present invention will be described with reference to FIG.
第1の実施形態においては、図1に示すように、半田バンプ11が第3領域にも埋め込まれる構造を説明した。しかしながら、本変形例においては、図7に示すように、半田バンプ11が第3領域において埋め込まれない構造としても構わない。他の言い方をすると、半田バンプと第2絶縁膜8又は電極パッド6との間に空隙を形成していても構わない。
In the first embodiment, as shown in FIG. 1, the structure in which the solder bumps 11 are embedded in the third region has been described. However, in this modification, as shown in FIG. 7, a structure in which the solder bumps 11 are not embedded in the third region may be used. In other words, a gap may be formed between the solder bump and the second
本変形例によると、半田バンプ11と第2絶縁膜8又は電極パッド6との間に空隙を形成する構造とすることによって、より応力を緩和する構造とすることができる効果がある。
According to the present modification, by forming a gap between the
(第1の実施形態の第2の変形例)
本発明の第1の実施形態の第2の変形例に係る半導体装置ついて図8及び図9を参照しながら説明する。なお、図9は半田バンプ11を省略している。
(Second modification of the first embodiment)
A semiconductor device according to a second modification of the first embodiment of the present invention will be described with reference to FIGS. In FIG. 9, the solder bumps 11 are omitted.
第1の実施形態においては、図1及び図2に示すように、第1絶縁膜7に形成される第1開口部に、第2絶縁膜8に形成される第2開口部が完全に含まれていた。言い換えれば、第2開口部の内側には第1絶縁膜7は形成されていなかった。しかし、図8に示すように、第1絶縁膜7に形成される第1開口部の全てが、第2絶縁膜8に形成される第2開口部の内側に配置されるようにしても構わない。言い換えれば、第2開口部の内側にまで第1絶縁膜7が形成されるようにしても構わない。
In the first embodiment, as shown in FIGS. 1 and 2, the first opening formed in the first insulating
上記構成とすると、図9に示すように、UBMの中央部とその周囲を取り囲むように形成されるリング形状部との間に、第1絶縁膜7と第2絶縁膜8とが積層されて配置されることとなる。
With the above configuration, as shown in FIG. 9, the first insulating
第1の実施形態においては、UBMをめっきした後の工程において、UBMが形成されていない領域に存在するシード層9の直下に電極パッド6が形成されていることがある。このシード層9を除去する際に、シード層9の直下の電極パッド6もエッチングされてしまう可能性がある。それに対して、本変形例においては、UBMの中央部とその周囲を取り囲むように形成されるリング形上部との間に、第1絶縁膜7と第2絶縁膜8とが積層されて配置されることとなる。そのため、UBMをめっきした後の工程において、UBMが形成されていない領域に存在するシード層9の直下には、第1絶縁膜7又は第2絶縁膜8が形成されることとなる。そのため、シード層9をエッチングする際に、電極パッド6のエッチングを抑制することができ、安定したプロセスとすることができる効果がある。
In the first embodiment, in the step after plating the UBM, the
(第1の実施形態の第3の変形例)
本発明の第1の実施形態の第3の変形例に係る半導体装置ついて図10を参照しながら説明する。なお、図10は半田バンプ11を省略している。
(Third Modification of First Embodiment)
A semiconductor device according to a third modification of the first embodiment of the present invention will be described with reference to FIG. In FIG. 10, the solder bumps 11 are omitted.
第1の実施形態においては、図2に示すように、UBM層10の中央部の周囲を取り囲むように形成されるリング形状部は、中央部を連続的に取り囲むように形成されていた。しかし、本変形例に係る半導体装置においては、図10に示すように、UBM層10におけるリング形状部は、中央部を不連続に取り囲むように形成されている。他の言い方をすれば、第2絶縁膜8の上の、第2開口部の外側である第1領域において、UBMは、複数に分割されて形成されている。このように、UBMにおけるリング形状部を複数に分割することによって、UBMによる応力をさらに緩和することができる効果がある。
In the first embodiment, as shown in FIG. 2, the ring-shaped portion formed so as to surround the central portion of the
なお、図10においては、UBMにおけるリング形状部を4分割した形状を示しているが、分割数を多くしても、少なくしても構わない。 In FIG. 10, the ring shape portion in the UBM is divided into four parts, but the number of divisions may be increased or decreased.
(第1の実施形態の第4の変形例)
本発明の第1の実施形態の第4の変形例に係る半導体装置ついて図11を参照しながら説明する。なお、図11は半田バンプ11を省略している。
(Fourth modification of the first embodiment)
A semiconductor device according to a fourth modification of the first embodiment of the present invention will be described with reference to FIG. In FIG. 11, the solder bumps 11 are omitted.
図11に示すように、本変形例は、第1の実施形態の第3の変形例と比較して、UBM層10の中央部がさらに複数に分割されて形成されている。他の言い方をすれば、電極パッド6の上の第2開口部の内側である第2領域において、UBMは、複数に分割されて形成されている。このように、UBMにおける内側部分を複数に分割することによって、UBMによる応力をさらに緩和することができる効果がある。
As shown in FIG. 11, in the present modification, the central portion of the
なお、図11においては、UBMにおける内側部を4分割した形状を示しているが、分割数を多くしても、少なくしても構わない。 In addition, in FIG. 11, although the shape which divided the inner part in UBM into 4 is shown, you may increase or decrease the number of divisions.
(第2の実施形態)
本発明の第2の実施形態について図12及び図13を参照しながら説明する。
(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIGS.
図12に示すように、本実施形態では、第1の実施形態と比較して、第2絶縁膜8の段差部に形成されるUBMに違いがある。具体的には、第1の実施形態に係る半導体装置の第2絶縁膜8は、第2開口部における、電極パッド6から第2絶縁膜8の表面に向かう部分の電極パッド6の表面に対する傾斜角が90度である。一方、本実施形態では、図12に示すように、電極パッド6から第2絶縁膜8の表面に向かう部分がゆるやかな傾斜となっており、第2絶縁膜8はゆるやかな段差部を有している。電極パッド6の表面に対する段差部の傾斜角が45度以下となっている。また、シード層9及びUBM層10からなるUBMが、この傾斜部を含む第2絶縁膜8の上及び電極パッド6の上に、連続的に形成されている。
As shown in FIG. 12, the present embodiment is different from the first embodiment in the UBM formed in the step portion of the second
本実施形態に係る半導体装置によると、第2絶縁膜8の段差部がゆるやかな構造となっているために、UBMが段差部に形成されたとしてもUBMに大きな段差が生じることが無くなる。そのため、段差部への応力集中を低減することができ、UBMに起因する応力集中を抑制することができる効果がある。
According to the semiconductor device according to the present embodiment, since the step portion of the second
図13は、段差部の傾斜角(電極パッド6の表面に対する段差部の傾斜角)を横軸に取り、それぞれの傾斜角に応じた、第2開口部の近傍に加わる応力(相対値)を縦軸に取ったグラフである。図13に示すように、段差部の傾斜角が45度を超えると、第2開口部の近傍に加わる応力が急激に増大する。従って、UBMに起因する応力集中を抑制するためにも、傾斜角を45度以下とすることが好ましい。 FIG. 13 shows the inclination angle of the step portion (inclination angle of the step portion with respect to the surface of the electrode pad 6) on the horizontal axis, and shows the stress (relative value) applied to the vicinity of the second opening according to each inclination angle. It is the graph taken on the vertical axis. As shown in FIG. 13, when the inclination angle of the stepped portion exceeds 45 degrees, the stress applied in the vicinity of the second opening portion rapidly increases. Therefore, in order to suppress stress concentration caused by UBM, it is preferable to set the inclination angle to 45 degrees or less.
(第3の実施形態)
本発明の第3の実施形態について図14を参照しながら説明する。
(Third embodiment)
A third embodiment of the present invention will be described with reference to FIG.
図14に示すように、本実施形態では、第2の実施形態と比較して、第1絶縁膜7が、第2開口部の内側にまで形成されている点が異なる。そのため、シード層9及びUBM層10からなるUBMが、第2開口部の内側の第1絶縁膜7の上にまで形成されている。このような形態とすることにより、第2絶縁膜8の表面から電極パッド6に向かって(第1絶縁膜7における第2開口部の内側部分に向かって)、第1段差部が形成されることに加えて、第1絶縁膜7における第2開口部の内側部分に電極パッド6方向に向かう第2段差部が形成され、第1絶縁膜7における第1開口部の内側部分に電極パッド6方向に向かう第3段差部が形成されることとなる。また、第1段差部、第2段差部及び第3段差部を含む第1絶縁膜7、第2絶縁膜8及び電極パッド6の上の全体にUBMが形成されることとなる。
As shown in FIG. 14, the present embodiment is different from the second embodiment in that the first insulating
本実施形態においては、第1絶縁膜7が第2絶縁膜8よりも薄いために、第1絶縁膜7における第2段差部又は第3段差部が、第2絶縁膜8における第1段差部よりも急な角度であったとしても、第1段差部がゆるやかであるならば、第2開口部の近傍に加わる応力集中を抑制することが可能となる。
In the present embodiment, since the first insulating
なお、第1段差部の電極パッド6の表面に対する第1傾斜角と、第2段差部の電極パッド6の表面に対する第2傾斜角と、第3段差部の電極パッド6の表面に対する第3傾斜角との平均傾斜角が45度以下であることが好ましい。このように、第2開口部の近傍において複数の段差部を有する場合においても、段差部の傾斜角の平均傾斜角を45度以下とすることにより、第2開口部の近傍に加わる応力集中をより抑制することが可能となる。
In addition, the 1st inclination angle with respect to the surface of the
(第4の実施形態)
本発明の第4の実施形態について図15を参照しながら説明する。
(Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to FIG.
図15に示すように、本実施形態では、第3の実施形態と比較して、第2開口部の開口径が大きく形成されている。そのため、シード層9及びUBM層10からなるUBMは、第2絶縁膜8の上には形成されず、第2絶縁膜8よりも薄い第1絶縁膜7及び電極パッド6の上にのみ形成されることとなる。第1絶縁膜7は、第3の実施形態と同様に複数の段差部を有しているが、第2絶縁膜8よりも十分に薄いために、UBMに起因する応力集中を十分に緩和することが可能となる。
As shown in FIG. 15, in this embodiment, the opening diameter of the second opening is formed larger than that of the third embodiment. Therefore, the UBM composed of the
また、本実施形態においては、第1絶縁膜7に形成される複数の段差部の電極パッド6の表面に対する角度の平均値を45度以下とすることが好ましい。
In the present embodiment, it is preferable that the average value of the angles of the plurality of step portions formed in the first insulating
本発明に係る半導体装置は、電極パッドの上に形成されるUBMに起因する応力集中を十分に緩和することができるため、半導体装置に形成されたトランジスタの特性変動を抑制することができ、特に、半田バンプの下に形成されるUBMを備える半導体装置等に有用である。 Since the semiconductor device according to the present invention can sufficiently relieve stress concentration caused by the UBM formed on the electrode pad, the characteristic variation of the transistor formed in the semiconductor device can be suppressed. This is useful for a semiconductor device including a UBM formed under a solder bump.
1 半導体基板
2 回路素子
3 第1配線層
4 第2配線層
5 第3絶縁膜
6 電極パッド
7 第1絶縁膜
8 第2絶縁膜
9 シード層(アンダーバリアメタルの一部)
10 アンダーバリアメタル(UBM)層
11A 半田めっき膜
11 半田バンプ
12 レジスト膜
13 第2開口部の縁部
DESCRIPTION OF
10 Under barrier metal (UBM)
Claims (14)
前記電極パッドの上に形成され、且つ、前記電極パッドの一部が露出するような第1開口部を有する第1絶縁膜と、
前記第1絶縁膜の上に形成され、且つ、前記第1開口部における少なくとも一部が露出するような第2開口部を有する第2絶縁膜と、
前記第2絶縁膜及び電極パッドの上に形成されたアンダーバリアメタルとを備え、
前記アンダーバリアメタルは、前記第2絶縁膜の表面における前記第2開口部の外側である第1領域と前記電極パッドの表面における前記第2開口部の内側である第2領域とにより挟まれる第3領域によって分離されていることを特徴とする半導体装置。 An electrode pad formed on the substrate;
A first insulating film formed on the electrode pad and having a first opening that exposes a portion of the electrode pad;
A second insulating film formed on the first insulating film and having a second opening such that at least a part of the first opening is exposed;
An under barrier metal formed on the second insulating film and the electrode pad,
The under barrier metal is sandwiched between a first region outside the second opening on the surface of the second insulating film and a second region inside the second opening on the surface of the electrode pad. A semiconductor device characterized by being separated by three regions.
前記電極パッドの上に形成され、且つ、前記電極パッドの一部が露出するような第1開口部を有する第1絶縁膜と、
前記第1絶縁膜の上に形成され、且つ、前記第1開口部における少なくとも一部が露出するような第2開口部を有する第2絶縁膜と、
前記第2絶縁膜及び電極パッドの上に形成されたアンダーバリアメタルとを備え、
前記第2絶縁膜は、前記第2絶縁膜の表面から前記電極パッドに向かう傾斜部を有し、
前記傾斜部における前記基板の平面方向に対する傾斜角は45度以下であることを特徴とする半導体装置。 An electrode pad formed on the substrate;
A first insulating film formed on the electrode pad and having a first opening that exposes a portion of the electrode pad;
A second insulating film formed on the first insulating film and having a second opening such that at least a part of the first opening is exposed;
An under barrier metal formed on the second insulating film and the electrode pad,
The second insulating film has an inclined portion from the surface of the second insulating film toward the electrode pad,
A tilt angle of the tilted portion with respect to a planar direction of the substrate is 45 degrees or less.
前記アンダーバリアメタルは、前記複数の段差を含む前記第1絶縁膜の上にも形成されることを特徴とする請求項7記載の半導体装置。 The first insulating film has a plurality of steps.
The semiconductor device according to claim 7, wherein the under barrier metal is also formed on the first insulating film including the plurality of steps.
前記電極パッドの上に形成され、且つ、前記電極パッドの一部が露出するような第1開口部を有する第1絶縁膜と、
前記第1絶縁膜の上に形成され、且つ、前記第1開口部における少なくとも一部が露出するような第2開口部を有する第2絶縁膜と、
前記第1絶縁膜及び電極パッドの上に形成されたアンダーバリアメタルとを備え、
前記第1絶縁膜は、複数の段差を有し、
前記アンダーバリアメタルは、前記複数の段差を含む前記第1絶縁膜の上に形成されることを特徴とする半導体装置。 An electrode pad formed on the substrate;
A first insulating film formed on the electrode pad and having a first opening that exposes a portion of the electrode pad;
A second insulating film formed on the first insulating film and having a second opening such that at least a part of the first opening is exposed;
An under barrier metal formed on the first insulating film and the electrode pad,
The first insulating film has a plurality of steps.
The under barrier metal is formed on the first insulating film including the plurality of steps.
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KR20200079160A (en) * | 2018-12-24 | 2020-07-02 | 주식회사 네패스 | Semiconductor package |
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US11824026B2 (en) * | 2015-12-31 | 2023-11-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Connector structure and method of forming same |
KR20200079160A (en) * | 2018-12-24 | 2020-07-02 | 주식회사 네패스 | Semiconductor package |
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