JP2013016842A - Semiconductor package - Google Patents

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JP2013016842A
JP2013016842A JP2012197608A JP2012197608A JP2013016842A JP 2013016842 A JP2013016842 A JP 2013016842A JP 2012197608 A JP2012197608 A JP 2012197608A JP 2012197608 A JP2012197608 A JP 2012197608A JP 2013016842 A JP2013016842 A JP 2013016842A
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resin layer
terminal
support plate
semiconductor
semiconductor element
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Yuji Kunimoto
裕治 国本
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package allowing increase in the density of a wiring pattern which can be led through a gap between exposed surfaces of bumps formed on respective electrode terminals in a plurality of semiconductor elements having different thicknesses and fixed to one surface of a support plate.SOLUTION: In the semiconductor package, a plurality of semiconductor elements 14a and 14b having different thicknesses are fixed to one surface of a support plate 10 through a resin layer 12 so that terminal surfaces of electrode terminals 16 of the semiconductor elements 14a and 14b may be flush. The resin layer 12 is provided on the entire of the one surface of the support plate 10. The semiconductor elements 14a and 14b have the opposite surfaces of the terminal surfaces fixed to the resin layer 12. There is provided an insulating layer 20 for covering at least a part of the terminal surfaces and lateral surfaces of the semiconductor elements 14a and 14b and the entire surface of the resin layer 12. Tapered bumps 18 formed on the terminal surfaces of the semiconductor elements 14a, 14b are formed penetrating through the insulating layer 20, and the tip surfaces of the tapered bumps 18 exposed on the surface of the insulating layer 20 are connected to wiring patterns 22.

Description

本発明は半導体パッケージに関し、更に詳細には複数の半導体素子が搭載されている半導体パッケージに関する。   The present invention relates to a semiconductor package, and more particularly to a semiconductor package in which a plurality of semiconductor elements are mounted.

複数の半導体素子が搭載された半導体パッケージについては、例えば下記特許文献１に記載されている。かかる半導体パッケージを図６に示す。図６に示す半導体パッケージでは、ベース基板１００の一面側に形成された、アース用の導体層１０２に、厚さの異なる半導体素子１０４ａ，１０４ｂの底面が接着されている。かかる半導体素子１０４ａ，１０４ｂの表面側に形成された各電極端子１０６は、絶縁層１０８を貫通するバンプ１１０を介して、絶縁樹脂層１０８の表面に形成された配線パターン１１２に電気的に接続されている。
また、導体層１０２に一端が接続された導電ブロック１１４の他端が、絶縁層１０８の表面に形成された配線パターン１１２に電気的に接続されている。 A semiconductor package on which a plurality of semiconductor elements are mounted is described in, for example, Patent Document 1 below. Such a semiconductor package is shown in FIG. In the semiconductor package shown in FIG. 6, the bottom surfaces of semiconductor elements 104 a and 104 b having different thicknesses are bonded to a grounding conductor layer 102 formed on one surface side of a base substrate 100. Each electrode terminal 106 formed on the surface side of the semiconductor elements 104a and 104b is electrically connected to a wiring pattern 112 formed on the surface of the insulating resin layer 108 through a bump 110 penetrating the insulating layer 108. ing.
Further, the other end of the conductive block 114 having one end connected to the conductor layer 102 is electrically connected to the wiring pattern 112 formed on the surface of the insulating layer 108.

図６に示す半導体パッケージは、図７に示す製造方法で得ることができる。図７に示す製造方法では、先ず、図７（ａ）に示す様に、ベース基板１００の一面側に形成した、アース用の導体層１０２に、導電ブロック１１４を立設すると共に、厚さの異なる半導体素子１０４ａ，１０４ｂの底面を接着し、その表面側に形成された電極端子１０６，１０６・・の各々に、電極端子１０６と略同一径のバンプ１１０を形成する。形成したバンプ１１０，１１０・・の各長さは、半導体素子１０４ａ，１０４ｂで異なるが、バンプ１１０，１１０・・の各先端面は、導電ブロック１１４の先端面と同一面内である。
次いで、図７（ｂ）に示す様に、形成した導電ブロック１１４、バンプ１１０を含む半導体素子１０４ａ，１０４ｂの端子形成面側を絶縁樹脂層１０８によって覆った後、絶縁樹脂層１０８の表面を研磨又は研削して平坦面として、図７（ｃ）に示す様に、導電ブロック１１４、バンプ１１０の先端面を露出する。
その後、導電ブロック１１４、バンプ１１０の各先端面が露出した絶縁樹脂層１０８の平坦面に、配線パターン１１２，１１２・・を形成して、図６に示す半導体パッケージを得ることができる。 The semiconductor package shown in FIG. 6 can be obtained by the manufacturing method shown in FIG. In the manufacturing method shown in FIG. 7, first, as shown in FIG. 7A, the conductive block 114 is erected on the grounding conductor layer 102 formed on one surface side of the base substrate 100, and the thickness of the conductive block 114 is increased. The bottom surfaces of different semiconductor elements 104a and 104b are bonded together, and bumps 110 having substantially the same diameter as the electrode terminals 106 are formed on the electrode terminals 106, 106,. The lengths of the formed bumps 110, 110,... Differ depending on the semiconductor elements 104 a, 104 b, but the tip surfaces of the bumps 110, 110,.
Next, as shown in FIG. 7B, the surface of the insulating resin layer 108 is polished after covering the terminal formation surface side of the semiconductor elements 104 a and 104 b including the formed conductive block 114 and bump 110 with the insulating resin layer 108. Alternatively, as shown in FIG. 7C, the front end surfaces of the conductive block 114 and the bump 110 are exposed as a flat surface by grinding.
Thereafter, the wiring patterns 112, 112,... Are formed on the flat surface of the insulating resin layer 108 where the respective front end surfaces of the conductive block 114 and the bump 110 are exposed, whereby the semiconductor package shown in FIG. 6 can be obtained.

特開平１０−２２３８３２号公報Japanese Patent Laid-Open No. 10-223832

図６及び図７に示す半導体パッケージでは、同一の半導体パッケージ内に厚さの異なる複数の半導体素子を設けることができる。
しかし、図６及び図７に示す半導体パッケージでは、ベース基板１００の一面側に底面を接着した厚さの異なる半導体素子１０４ａ，１０４ｂの電極端子１０６，１０６・・の各々に、形成する電極端子１０６と略同一径のバンプ１１０を、各先端面が同一面となるように形成している。
一方、近年、半導体素子１０４ａ，１０４ｂの小型化等に伴って、電極端子１０６，１０６・・の形成密度が高密度化してきている。
しかし、図６及び図７に示す半導体パッケージでは、電極端子１０６と略同一径のバンプ１１０を形成しているため、バンプ１１０の露出面から引き出す配線パターンの微細化は困難である。
しかも、隣接するバンプ１１０，１１０の露出面間の間隙（バンプの露出面間隙と称することがある）が狭いため、バンプ１１０の露出面から引き出す配線パターンの微細化が困難であることと相俟って、バンプの露出面間隙を通して引き回すことのできる配線パターン数が著しく制限され、配線パターンの高密度化を図ることは困難である。
また、一般的には、図６及び図７に示す半導体パッケージの如く、厚さの異なる半導体素子１０４ａ，１０４ｂの各電極端子１０６に、先端面が同一面となるように、長さの異なるバンプ１１０，１１０・・を形成する際には、半導体素子１０４ａ，１０４ｂの各電極端子１０６を覆う樹脂層を形成した後、この樹脂層に各電極端子１０６の表面が底面に露出する凹部をレーザによって形成し、次いで、電解めっきによってめっき金属を凹部内に充填してバンプ１１０を形成することが考えられる。
しかしながら、レーザによって樹脂層に形成した凹部は、通常、底面積よりも開口部面積が大きくなるテーパ状凹部に形成されるため、最終的に得られるバンプは電極端子１０６に接続する接続面よりも絶縁樹脂層１０８の表面に露出する露出面の面積が大きくなる。このため、バンプ１１０の露出面から引き出す配線パターンが幅広化され、且つ隣接するバンプ１１０，１１０のバンプの露出面間隙も半導体素子１０４ａ，１０４ｂの隣接する電極端子１０６，１０６の間隙よりも更に狭くなり、バンプの露出面間隙を通して引き回すことのできる配線パターン数が更に一層制限される。
そこで、本発明の課題は、支持板の一面側に固着された厚さの異なる複数の半導体素子の各電極端子に形成されたバンプの露出面間隙を通して引き回すことのできる配線パターンの高密度化を図ることが困難な従来の半導体パッケージの課題を解決し、支持板の一面側に固着された厚さの異なる複数の半導体素子の各電極端子に形成されたバンプの露出面間隙を通して引き回すことのできる配線パターンの高密度化を図ることができる半導体パッケージを提供することにある。 In the semiconductor package shown in FIGS. 6 and 7, a plurality of semiconductor elements having different thicknesses can be provided in the same semiconductor package.
However, in the semiconductor package shown in FIGS. 6 and 7, the electrode terminal 106 formed on each of the electrode terminals 106, 106,... Of the semiconductor elements 104a, 104b having different thicknesses with the bottom surface bonded to one surface side of the base substrate 100. The bumps 110 having substantially the same diameter are formed so that the tip surfaces are the same.
On the other hand, in recent years, the formation density of the electrode terminals 106, 106,... Has increased with the miniaturization of the semiconductor elements 104a, 104b.
However, in the semiconductor package shown in FIGS. 6 and 7, since the bumps 110 having substantially the same diameter as the electrode terminals 106 are formed, it is difficult to make the wiring pattern drawn out from the exposed surface of the bumps 110 fine.
In addition, since the gap between the exposed surfaces of the adjacent bumps 110 and 110 (sometimes referred to as a bump exposed surface gap) is narrow, it is difficult to make the wiring pattern drawn out from the exposed surface of the bump 110 difficult. Therefore, the number of wiring patterns that can be routed through the gap between the exposed surfaces of the bumps is remarkably limited, and it is difficult to increase the density of the wiring patterns.
In general, as in the semiconductor package shown in FIGS. 6 and 7, bumps having different lengths are provided on the electrode terminals 106 of the semiconductor elements 104a and 104b having different thicknesses so that the front end surfaces thereof are the same. 110, 110,..., A resin layer covering each electrode terminal 106 of the semiconductor elements 104a, 104b is formed, and then a recess in which the surface of each electrode terminal 106 is exposed on the bottom surface is formed on the resin layer by a laser. It is conceivable that the bump 110 is formed by filling the recess with electrolytic metal by electrolytic plating.
However, since the recess formed in the resin layer by the laser is usually formed in a tapered recess whose opening area is larger than the bottom area, the finally obtained bump is more than the connection surface connected to the electrode terminal 106. The area of the exposed surface exposed on the surface of the insulating resin layer 108 is increased. For this reason, the wiring pattern drawn out from the exposed surface of the bump 110 is widened, and the exposed surface gap between the adjacent bumps 110 and 110 is further narrower than the gap between the adjacent electrode terminals 106 and 106 of the semiconductor elements 104a and 104b. Thus, the number of wiring patterns that can be routed through the gap between the exposed surfaces of the bumps is further limited.
Accordingly, an object of the present invention is to increase the density of the wiring pattern that can be routed through the exposed surface gaps of the bumps formed on each electrode terminal of a plurality of semiconductor elements fixed to one side of the support plate and having different thicknesses. It is possible to solve the problem of the conventional semiconductor package which is difficult to achieve and to be routed through the exposed surface gap of the bump formed on each electrode terminal of a plurality of semiconductor elements having different thicknesses fixed to one side of the support plate An object of the present invention is to provide a semiconductor package capable of increasing the density of wiring patterns.

本発明者は、前記課題を解決すべく検討した結果、厚さの異なる複数の半導体素子を、電極端子の端子面が同一面となるように支持板の一面側に固着し、且つ半導体素子の電極端子に形成した先細り状のバンプを、半導体素子の端子形成面側を覆う絶縁層を貫通して形成することによって、絶縁層の表面に露出するバンプの露出面間を通して引き回すことのできる配線パターンの高密度化を図ることができることを見出し、本発明に到達した。
すなわち、本発明は、厚さの異なる複数の半導体素子が、それぞれの電極端子の端子面が同一面となるように、支持板の一面側に樹脂層によって固着されている半導体パッケージであって、前記樹脂層は、前記支持板の一面側の全面に設けられており、前記複数の半導体素子は、前記端子面の反対側の面が前記樹脂層に固着されており、前記複数の半導体素子の端子面および側面の少なくとも一部、ならびに前記樹脂層の表面の全面を被覆する絶縁層が設けられ、前記複数の半導体素子の端子面に形成されたバンプが、前記絶縁層を貫通し、且つ前記絶縁層の表面に先端面を露出して設けられており、前記バンプの先端面が、前記絶縁層の表面に形成された配線パターンに接続されていることを特徴とする半導体パッケージにある。 As a result of studying to solve the above problems, the present inventor fixed a plurality of semiconductor elements having different thicknesses to one surface side of the support plate so that the terminal surfaces of the electrode terminals are the same surface, and A wiring pattern that can be routed between exposed surfaces of bumps exposed on the surface of the insulating layer by forming tapered bumps formed on the electrode terminals through the insulating layer covering the terminal forming surface side of the semiconductor element As a result, the present invention has been achieved.
That is, the present invention is a semiconductor package in which a plurality of semiconductor elements having different thicknesses are fixed to one surface side of a support plate by a resin layer so that the terminal surfaces of the respective electrode terminals are the same surface, The resin layer is provided on the entire surface of one surface of the support plate, and the plurality of semiconductor elements have a surface opposite to the terminal surface fixed to the resin layer. An insulating layer that covers at least a part of the terminal surface and the side surface and the entire surface of the resin layer is provided, and bumps formed on the terminal surfaces of the plurality of semiconductor elements penetrate the insulating layer, and The semiconductor package is characterized in that the front end face is exposed on the surface of the insulating layer, and the front end face of the bump is connected to a wiring pattern formed on the surface of the insulating layer.

かかる本発明において、前記複数の半導体素子の電極端子に形成された前記バンプが、前記先端面が前記端子面よりも小面積に形成された先細り状のバンプであることによって、各半導体素子の電極端子に亘ってバンプの露出面間隙を通して引き回すことのできる配線パターンの高密度化を図ることができる。
また、前記複数の半導体素子の電極端子に形成された前記バンプが、前記先細り状のバンプと柱状のバンプとからなることによって、電極端子の用途に応じて最適なバンプ、例えば信号用の電極端子には先細り状のバンプを形成し、電源用や接地用の電極端子には柱状のバンプを形成できる。
かかる前記先細り状のバンプとしては、前記半導体素子の電極端子に一端部を圧着した金属ワイヤにより形成できる。この前記金属ワイヤが、金から成るワイヤであることが好ましい。
更に、前記支持板を、放熱板として用いることのできる金属製の支持板とすることによって、半導体パッケージの放熱性を向上できる。
また、厚さの薄い半導体素子は、該厚さの薄い半導体素子の端子形成面に対して反対面と前記支持板の一面との間に前記樹脂層が介在して、前記支持板の一面側に前記樹脂層によって固着され、前記厚さの薄い半導体素子よりも厚さの厚い半導体素子は、該厚さの厚い半導体素子の端子形成面に対して反対面が前記支持板の一面に直接接触した状態で、前記支持板の一面側に前記樹脂層によって固着されている。
また、厚さの薄い半導体素子は、該厚さの薄い半導体素子の端子形成面に対して反対面と前記支持板の一面との間に前記樹脂層が介在して、前記支持板の一面側に前記樹脂層によって固着され、前記厚さの薄い半導体素子よりも厚さの厚い半導体素子は、該厚さの厚い半導体素子の端子形成面に対して反対面と前記支持板の一面との間に前記樹脂層が介在して、前記支持板の一面側に前記樹脂層によって固着され、前記厚さの薄い半導体素子の反対面と前記支持板の一面との間に介在する前記樹脂層の高さは、前記厚さの厚い半導体素子の反対面と前記支持板の一面との間に介在する前記樹脂層の高さよりも高い。
また、前記絶縁層が、前記半導体素子の端子形成面から側面の少なくとも一部にかけて該半導体素子を覆う。
また、前記配線パターン上には、更に他の絶縁層と配線パターンが多層に積層されている。 In the present invention, the bumps formed on the electrode terminals of the plurality of semiconductor elements are tapered bumps whose tip surfaces are formed in a smaller area than the terminal surfaces, so that the electrodes of each semiconductor element It is possible to increase the density of the wiring pattern that can be routed through the exposed surface gap of the bump across the terminal.
Further, the bumps formed on the electrode terminals of the plurality of semiconductor elements include the tapered bumps and the columnar bumps, so that an optimum bump according to the use of the electrode terminals, for example, an electrode terminal for signals A tapered bump can be formed, and a columnar bump can be formed on the electrode terminal for power supply or ground.
The tapered bump can be formed of a metal wire having one end crimped to the electrode terminal of the semiconductor element. The metal wire is preferably a wire made of gold.
Furthermore, the heat dissipation of a semiconductor package can be improved by using the said support plate as a metal support plate which can be used as a heat sink.
Further, the thin semiconductor element has one surface side of the support plate with the resin layer interposed between the surface opposite to the terminal forming surface of the thin semiconductor element and the one surface of the support plate. The semiconductor element fixed by the resin layer and thicker than the thin semiconductor element is in direct contact with one surface of the support plate with respect to the terminal forming surface of the thick semiconductor element. In this state, the resin layer is fixed to one surface side of the support plate.
Further, the thin semiconductor element has one surface side of the support plate with the resin layer interposed between the surface opposite to the terminal forming surface of the thin semiconductor element and the one surface of the support plate. The semiconductor element fixed by the resin layer and thicker than the thin semiconductor element is between the surface opposite to the terminal forming surface of the thick semiconductor element and one surface of the support plate. The resin layer is interposed between the opposite surface of the thin semiconductor element and the one surface of the support plate, and is fixed to the one surface side of the support plate by the resin layer. The height is higher than the height of the resin layer interposed between the opposite surface of the thick semiconductor element and one surface of the support plate.
The insulating layer covers the semiconductor element from the terminal formation surface of the semiconductor element to at least a part of the side surface.
In addition, other insulating layers and wiring patterns are laminated in multiple layers on the wiring pattern.

本発明では、厚さの異なる複数の半導体素子を、電極端子の端子面が同一面となるように支持板の一面側に固着している。このため、厚さの異なる複数の半導体素子の端子形成面側を覆う絶縁層を貫通する同一長さのバンプを、半導体素子の各電極端子の端子面に形成でき、半導体素子の各電極端子の端子面に長さの異なるバンプを形成する場合に比較して、バンプを容易に形成できる。
しかも、本発明に係る半導体パッケージでは、半導体素子の電極端子の端子面に形成した、先細り状のバンプの先端面を絶縁層の表面に露出し、配線パターンと接続している。かかる先細り状のバンプの先端面は、半導体素子の電極端子の端子面よりも小面積に形成できる。
従って、厚さの異なる複数の半導体素子の端子形成面側を覆う絶縁層を貫通する同一長さのバンプを、半導体素子の電極端子の端子面に形成できることと相俟って、バンプの露出面から微細な配線パターンを引き出すことができ、且つバンプの露出面間を広くできるため、バンプの露出面間隙を通して引き回すことのできる配線パターンの高密度化を図ることができる。
その結果、半導体素子の小型化等に伴う半導体素子の電極端子の高密度化に対応できる。 In the present invention, a plurality of semiconductor elements having different thicknesses are fixed to one surface side of the support plate so that the terminal surfaces of the electrode terminals are the same surface. For this reason, bumps of the same length penetrating the insulating layer covering the terminal formation surface side of a plurality of semiconductor elements having different thicknesses can be formed on the terminal surfaces of the respective electrode terminals of the semiconductor element. Bumps can be formed more easily than when bumps having different lengths are formed on the terminal surface.
Moreover, in the semiconductor package according to the present invention, the tip end surface of the tapered bump formed on the terminal surface of the electrode terminal of the semiconductor element is exposed on the surface of the insulating layer and connected to the wiring pattern. The tip surface of the tapered bump can be formed in a smaller area than the terminal surface of the electrode terminal of the semiconductor element.
Therefore, in combination with the fact that bumps of the same length penetrating the insulating layer covering the terminal formation surface side of the plurality of semiconductor elements having different thicknesses can be formed on the terminal surface of the electrode terminal of the semiconductor element, the exposed surface of the bump Since a fine wiring pattern can be drawn from the gap and the space between the exposed surfaces of the bumps can be widened, it is possible to increase the density of the wiring pattern that can be routed through the gap between the exposed surfaces of the bumps.
As a result, it is possible to cope with the increase in the density of the electrode terminals of the semiconductor element accompanying the downsizing of the semiconductor element.

本発明に係る半導体パッケージの一例を説明するための縦断面図である。It is a longitudinal section for explaining an example of a semiconductor package concerning the present invention. 図１に示す半導体パッケージの製造工程の一部を説明する工程図である。FIG. 7 is a process diagram illustrating part of a manufacturing process of the semiconductor package shown in FIG. 1. 図１に示す半導体パッケージの製造工程の残りを説明する工程図である。FIG. 7 is a process diagram illustrating the remainder of the manufacturing process for the semiconductor package shown in FIG. 1. 本発明に係る半導体パッケージの他の例を説明するための縦断面図である。It is a longitudinal cross-sectional view for demonstrating the other example of the semiconductor package which concerns on this invention. 図５に示す半導体パッケージの製造工程を説明する工程図である。FIG. 6 is a process diagram illustrating a manufacturing process of the semiconductor package shown in FIG. 5. 従来の半導体パッケージを説明するための縦断面図である。It is a longitudinal cross-sectional view for demonstrating the conventional semiconductor package. 図６に示す半導体パッケージの製造工程を説明する工程図である。FIG. 7 is a process diagram illustrating a manufacturing process of the semiconductor package shown in FIG. 6.

本発明に係る半導体パッケージの一例を図１に示す。図１に示す半導体パッケージは、鉄、銅、アルミニウム等の熱伝導性に優れた金属製であって、放熱板としての役割を果たすことのできる支持板１０の一面側に、樹脂層１２によって半導体素子としての半導体素子１４ａ，１４ｂが固着されている。半導体素子１４ａ，１４ｂは、その厚さが異なっているが、半導体素子１４ａ，１４ｂに形成された電極端子１６，１６，・・の各端子面が同一面となるように位置決めされている。
かかる電極端子１６，１６，・・の各端子面には、先細り状のバンプ１８が、半導体素子１４ａ，１４ｂの端子形成面側を覆う樹脂製の絶縁層２０を貫通して形成されている。この先細り状のバンプ１８は、後述する様に、金ワイヤの端部を電極端子１６の端子面に圧着した後、この金ワイヤを引き千切って形成した先端部をコイニングして、先端面を平坦化し且つ高さを揃えて形成したものである。 An example of a semiconductor package according to the present invention is shown in FIG. The semiconductor package shown in FIG. 1 is made of a metal having excellent thermal conductivity, such as iron, copper, and aluminum, and the semiconductor layer is formed on one side of a support plate 10 that can serve as a heat sink by a resin layer 12. Semiconductor elements 14a and 14b as elements are fixed. The semiconductor elements 14a and 14b have different thicknesses, but are positioned so that the terminal surfaces of the electrode terminals 16, 16,... Formed on the semiconductor elements 14a and 14b are the same surface.
On each terminal surface of the electrode terminals 16, 16,..., Tapered bumps 18 are formed penetrating through a resin insulating layer 20 covering the terminal forming surface side of the semiconductor elements 14a, 14b. As will be described later, the tapered bump 18 is formed by crimping the end portion of the gold wire after crimping the end portion of the gold wire to the terminal surface of the electrode terminal 16 and then stripping the gold wire. It is flattened and formed with the same height.

かかるバンプ１８，１８・・の各先端面は、絶縁層２０の表面に露出しており、その露出面積は、バンプ１８の他端が接続されている電極端子１６の端子面よりも小面積に形成されている。このため、絶縁層２０の表面に形成され、先細り状のバンプ１８，１８・・の各先端面から引き出された配線パターン２２を、電極端子１６の端子面よりも微細化できる。
従って、各電極端子１８に形成された先細り状のバンプ１８の先端面から配線パターン２２を引き出すことができ、且つ隣接するバンプ１８，１８の露出面間の間隙（バンプの露出面間隙）を広くできる。このため、バンプの露出面間隙を通して引き回せる配線パターンの高密度化を図ることができ、半導体素子１４ａ，１４ｂの電極端子１６，１６・・に高密度化に対応できる。
かかる配線パターン２２，２２・・上には、図１に示す様に、必要に応じて複数の配線パターンを絶縁層を介して多層に積層し、絶縁層を貫通するヴィアによって配線パターン間を電気的に接続するようにしてもよい。
また、図１に示す半導体パッケージの最上層には、ソルダレジスト層２４が形成され、外部接続端子としてのはんだボールを装着するパッド２６，２６・・がソルダレジスト層２４から露出している。かかるパッド２６，２６・・には、チップキャパシタ、抵抗、インダクタ等の任意の電子部品を搭載することもできる。
この様な、図１に示す半導体パッケージでは、搭載した半導体素子１４ａの電極端子１６と、半導体素子１４ｂの電極端子１６とが、バンプ１８，１８の露出面に接続された配線パターン２２によって電気的に接続することができる。
尚、図１に示す半導体パッケージでは、支持板１０として、放熱板としての役割を果たすことができるように、熱伝導性に優れた金属製の支持板を用いていたが、支持体１０が放熱板としての役割を考慮しなくてもよい場合には、ガラス板やシリコン板等から成る支持板を用いることができる。 The front end surfaces of the bumps 18, 18,... Are exposed on the surface of the insulating layer 20, and the exposed area is smaller than the terminal surface of the electrode terminal 16 to which the other end of the bump 18 is connected. Is formed. For this reason, the wiring pattern 22 formed on the surface of the insulating layer 20 and drawn out from the tip surfaces of the tapered bumps 18, 18... Can be made finer than the terminal surface of the electrode terminal 16.
Accordingly, the wiring pattern 22 can be drawn out from the tip end surface of the tapered bump 18 formed on each electrode terminal 18, and the gap between the exposed surfaces of the adjacent bumps 18 and 18 (bump exposed surface gap) is widened. it can. For this reason, it is possible to increase the density of the wiring pattern that can be routed through the gap between the exposed surfaces of the bumps, and it is possible to cope with the increase in the density of the electrode terminals 16, 16.
As shown in FIG. 1, a plurality of wiring patterns are laminated on the wiring patterns 22, 22... Via an insulating layer as necessary, and the wiring patterns are electrically connected by vias penetrating the insulating layer. May be connected to each other.
Further, a solder resist layer 24 is formed on the uppermost layer of the semiconductor package shown in FIG. 1, and pads 26, 26,... For mounting solder balls as external connection terminals are exposed from the solder resist layer 24. Arbitrary electronic components such as a chip capacitor, a resistor, and an inductor can be mounted on the pads 26, 26,.
In such a semiconductor package shown in FIG. 1, the electrode terminal 16 of the mounted semiconductor element 14a and the electrode terminal 16 of the semiconductor element 14b are electrically connected by the wiring pattern 22 connected to the exposed surfaces of the bumps 18 and 18. Can be connected to.
In the semiconductor package shown in FIG. 1, a metal support plate having excellent thermal conductivity is used as the support plate 10 so that it can serve as a heat dissipation plate. When it is not necessary to consider the role as a plate, a support plate made of a glass plate, a silicon plate, or the like can be used.

図１に示す半導体パッケージは、図２及び図３に製造方法によって製造できる。先ず、図２（ａ）に示す様に、ガラス板等の剛性を有する板体５０の一面側に、厚さの異なる半導体素子としての半導体素子１４ａ，１４ｂの電極端子１６，１６・・が形成された端子形成面側を、接着層５２によって剥離可能に接着する。この際に、半導体素子１４ａ，１４ｂの各々に形成された電極端子１６，１６・・の各端子面が同一面となるように、半導体素子１４ａ，１４ｂの各々を位置調整する。
更に、図２（ｂ）に示す様に、板体５０の一面側に、端子形成面側を接着層５２によって接着した半導体素子１４ａ，１４ｂの各端子形成面側の反対面側を、支持板１０の一面側に形成した樹脂層１２によって固着する。
次いで、板体５０及び接着層５２を剥離し、図２（ｃ）に示す様に、支持板１０の一面側に樹脂層１２により固着した半導体素子１４ａ，１４ｂの電極端子１６，１６・・を露出する。露出された電極端子１６，１６・・の各端子面は、厚さの異なる半導体素子１４ａ，１４ｂであっても、同一面とすることができる。 The semiconductor package shown in FIG. 1 can be manufactured by the manufacturing method shown in FIGS. First, as shown in FIG. 2A, electrode terminals 16, 16,... Of semiconductor elements 14a, 14b as semiconductor elements having different thicknesses are formed on one surface side of a plate 50 having rigidity such as a glass plate. The terminal forming surface side thus bonded is detachably bonded by the adhesive layer 52. At this time, the positions of the semiconductor elements 14a and 14b are adjusted so that the terminal surfaces of the electrode terminals 16, 16... Formed on the semiconductor elements 14a and 14b are the same surface.
Further, as shown in FIG. 2B, the opposite side of each terminal forming surface side of the semiconductor elements 14a and 14b, in which the terminal forming surface side is bonded to the one surface side of the plate body 50 by the adhesive layer 52, is provided on the supporting plate. 10 is fixed by a resin layer 12 formed on one surface side.
Next, the plate body 50 and the adhesive layer 52 are peeled off, and as shown in FIG. 2C, the electrode terminals 16, 16... Of the semiconductor elements 14a, 14b fixed to the one surface side of the support plate 10 by the resin layer 12. Exposed. The exposed terminal surfaces of the electrode terminals 16, 16,... Can be the same surface even if the semiconductor elements 14a, 14b have different thicknesses.

図２（ｃ）に示す半導体素子１４ａ，１４ｂの電極端子１６，１６・・の各端子面には、図３（ａ）に示す様に、先端部が細長く形成されたバンプ１７を形成する。このバンプ１７は、金ワイヤの端部を電極端子１６の端子面に圧着した後、この金ワイヤを引き千切って形成したものである。かかるバンプ１７は、半導体装置の製造で用いられているボンディング装置を用いて形成できる。
図３（ａ）に示すバンプ１７，１７・・は、図３（ｂ）に示す様に、その先端部をコイニング板（金型）１９によってコイニングして平坦化する。これによって、先細り状のバンプ１８，１８・・を形成する。かかる先細り状のバンプ１８，１８・・の各先端面は、電極端子１６の端子面よりも小面積であって、同一高さで且つ略同一面積である。 As shown in FIG. 3 (a), bumps 17 having elongated tips are formed on the terminal surfaces of the electrode terminals 16, 16,... Of the semiconductor elements 14a, 14b shown in FIG. The bump 17 is formed by crimping the end portion of the gold wire to the terminal surface of the electrode terminal 16 and then cutting the gold wire. Such bumps 17 can be formed using a bonding apparatus used in the manufacture of semiconductor devices.
The bumps 17, 17... Shown in FIG. 3A are flattened by coining the tip portion with a coining plate (mold) 19 as shown in FIG. Thereby, the tapered bumps 18, 18,... Are formed. The tip surfaces of the tapered bumps 18, 18,... Have a smaller area than the terminal surface of the electrode terminal 16, and have the same height and substantially the same area.

次いで、形成した先細り状のバンプ１８，１８・・を含む半導体素子１４ａ，１４ｂの各端子形成面を、図３（ｃ）に示す様に、絶縁性樹脂から成る絶縁層２０によって被覆する。この絶縁層２０は、エポキシ樹脂やポリイミド樹脂等の絶縁性樹脂の塗布、或いはこれらの絶縁性樹脂から成るフィルムの積層によって形成できる。
かかる絶縁層２０には、図３（ｄ）に示す様に、研磨又は研削を施して、先細り状のバンプ１８，１８・・の各先端面を露出する。
その後、露出した先細り状のバンプ１８，１８・・の各先端面が接続される配線パターン２２，２２・・を、絶縁層２０の表面に形成する。絶縁層２０の表面に露出する先細り状のバンプ１８，１８・・の各先端面は、半導体素子１４ａ，１４ｂに形成された電極端子１６，１６・・の端子面よりも小面積に形成できる。このため、配線パターン２２は、接続する先細り状のバンプ１８が形成された電極端子１６の端子面よりも幅狭に形成でき、微細化された配線パターン２２を形成できる。
また、隣接するバンプ１８，１８のバンプの露出面間隙を、バンプ１８，１８を形成した電極端子１６，１６の端子面間隙よりも広くできる。
従って、バンプの露出面間隙から引き回す配線パターン２２，２２・・の高密度化を可能にでき、半導体素子１４ａ，１４ｂの小型化等に因る電極端子１６，１６・・の高密度化に対しても対応できる。
配線パターン２２，２２・・上には、必要に応じて複数の配線パターンを絶縁層を介して多層に積層し、絶縁層を貫通するヴィアによって配線パターン間を電気的に接続することによって、図１に示す半導体パッケージを得ることができる。
この様に、配線パターン２２，２２・・上に複数の配線パターンを絶縁層を介して多層に積層する際には、公知のアディティブ法やセミアディティブ法を利用できる。 Next, each terminal forming surface of the semiconductor elements 14a, 14b including the formed tapered bumps 18, 18,... Is covered with an insulating layer 20 made of an insulating resin, as shown in FIG. The insulating layer 20 can be formed by applying an insulating resin such as an epoxy resin or a polyimide resin, or by laminating films made of these insulating resins.
As shown in FIG. 3 (d), the insulating layer 20 is polished or ground to expose the tip surfaces of the tapered bumps 18, 18,.
After that, wiring patterns 22, 22... To which the respective tip surfaces of the exposed tapered bumps 18, 18... Are connected are formed on the surface of the insulating layer 20. The tip end surfaces of the tapered bumps 18, 18,... Exposed on the surface of the insulating layer 20 can be formed in a smaller area than the terminal surfaces of the electrode terminals 16, 16 ... formed on the semiconductor elements 14a, 14b. For this reason, the wiring pattern 22 can be formed narrower than the terminal surface of the electrode terminal 16 on which the tapered bumps 18 to be connected are formed, and a finer wiring pattern 22 can be formed.
In addition, the exposed surface gap of the bumps 18 and 18 adjacent to each other can be made wider than the terminal surface gap of the electrode terminals 16 and 16 on which the bumps 18 and 18 are formed.
Therefore, it is possible to increase the density of the wiring patterns 22, 22... Drawn from the gap between the exposed surfaces of the bumps, and to increase the density of the electrode terminals 16, 16. But it can respond.
A plurality of wiring patterns are laminated on the wiring patterns 22, 22... As necessary through insulating layers, and the wiring patterns are electrically connected by vias penetrating the insulating layers. 1 can be obtained.
In this way, when a plurality of wiring patterns are laminated on the wiring patterns 22, 22... Via the insulating layer, a known additive method or semi-additive method can be used.

図１〜図３に示す半導体パッケージには、支持板１０の一面側に載置された半導体素子１４ａ，１４ｂの全電極端子１６の端子面に先細り状のバンプ１８が形成されているが、図４に示す半導体パッケージの様に、半導体素子１４ａの電極端子１６，１６・・の各端子面に、先細り状のバンプ１８を形成し、半導体素子１４ｂの電極端子１６，１６・・の各端子面に、柱状のバンプ３０を形成してもよい。
図４に示す半導体パッケージの半導体素子１４ｂでは、電極端子１６，１６・・の形成密度が、高密度化されておらず、柱状のバンプ３０を形成しても、バンプ３０と接続する配線パターン２２を容易に形成できるためである。
この様に、先細り状のバンプ１８と柱状のバンプ３０とを混在して形成することによって、電極端子１６，１６・・の各用途に応じて最適なバンプ、例えば信号用の電極端子には先細り状のバンプ１８を形成し、電源用や接地用の電極端子には柱状のバンプ３０を形成できる。 In the semiconductor package shown in FIGS. 1 to 3, tapered bumps 18 are formed on the terminal surfaces of all the electrode terminals 16 of the semiconductor elements 14 a and 14 b placed on one surface side of the support plate 10. 4, tapered bumps 18 are formed on the terminal surfaces of the electrode terminals 16, 16... Of the semiconductor element 14 a, and the terminal surfaces of the electrode terminals 16, 16. In addition, the columnar bumps 30 may be formed.
In the semiconductor element 14b of the semiconductor package shown in FIG. 4, the formation density of the electrode terminals 16, 16,... Is not increased, and the wiring pattern 22 connected to the bump 30 is formed even if the columnar bump 30 is formed. This is because it can be easily formed.
Thus, by forming the tapered bumps 18 and the columnar bumps 30 in a mixed manner, the optimum bumps, for example, signal electrode terminals, are tapered depending on the application of the electrode terminals 16, 16. A columnar bump 18 can be formed on the electrode terminal for power supply or grounding.

図４に示す様に、先細り状のバンプ１８と柱状のバンプ３０とが混在して形成された半導体パッケージを製造する際には、前述した図２（ａ）〜（ｃ）に示す工程と同様にして、支持板１０の一面側に樹脂層１２によって固着した半導体素子１４ａ，１４ｂの電極端子１６，１６・・の各端子面を露出する。
この半導体素子１４ａの電極端子１６，１６・・の各端子面には、図３（ａ）〜（ｂ）に示す工程と同様にして、先細り状のバンプ１８を形成する。この際に、半導体素子１４ｂの電極端子１６，１６・・の各端子面には、バンプを何等形成しない。
次いで、図５（ａ）に示す様に、半導体素子１４の電極端子１６，１６・・の各端子面に形成したバンプ１８を含む半導体素子１４ａ，１４ｂの各端子形成面を、絶縁性樹脂から成る絶縁層２０によって被覆した後、図５（ｂ）に示す様に、絶縁層２０を研磨又は研削して、半導体素子１４に形成した先細り状のバンプ１８，１８・・の各先端面を露出する。
更に、図５（ｃ）に示す様に、半導体素子１４ｂの電極端子１６，１６・・の各端子面が底面に露出するように、凹部２８，２８・・をレーザによって形成する。
その後、図５（ｄ）に示す様に、凹部２８，２８・・をめっき金属で充填して柱状のバンプ３０を形成すると共に、先細り状のバンプ１８の先端面と柱状のバンプ３０との各々に接続する配線パターン２２，２２・・を形成する。 As shown in FIG. 4, when manufacturing a semiconductor package in which tapered bumps 18 and columnar bumps 30 are mixed, the same process as shown in FIGS. 2A to 2C is performed. Thus, the terminal surfaces of the electrode terminals 16, 16,... Of the semiconductor elements 14a, 14b fixed by the resin layer 12 on one surface side of the support plate 10 are exposed.
The tapered bumps 18 are formed on the terminal surfaces of the electrode terminals 16, 16,... Of the semiconductor element 14a in the same manner as in the steps shown in FIGS. At this time, no bumps are formed on the terminal surfaces of the electrode terminals 16, 16,... Of the semiconductor element 14b.
Next, as shown in FIG. 5A, the terminal forming surfaces of the semiconductor elements 14a, 14b including the bumps 18 formed on the terminal surfaces of the electrode terminals 16, 16,. After covering with the insulating layer 20, the insulating layer 20 is polished or ground as shown in FIG. 5B to expose the respective tip surfaces of the tapered bumps 18, 18... Formed on the semiconductor element 14. To do.
Further, as shown in FIG. 5C, the recesses 28, 28,... Are formed by laser so that the terminal surfaces of the electrode terminals 16, 16,.
Thereafter, as shown in FIG. 5 (d), the recesses 28, 28,... Are filled with plating metal to form columnar bumps 30, and each of the tip end surface of the tapered bump 18 and the columnar bumps 30 is formed. Wiring patterns 22, 22... Connected to are formed.

かかる柱状のバンプ３０と配線パターン２２，２２・・を形成する際には、例えば図５（ｃ）に示す凹部２８，２８・・の各内壁面を含む絶縁層２０の全面に、無電解めっき、蒸着又はスパッタによって薄金属層を形成する。
更に、この薄金属層の表面に形成した感光性樹脂層に、形成する配線パターンに沿って薄金属層が露出するようにパターニングを施した後、薄金属層を給電層とする電解めっきを施して、凹部２８，２８・・をめっき金属で充填する共に、配線パターン２２，２２・・を形成する。
次いで、感光性樹脂層を剥離して、露出した薄金属層をエッチングすることによって、図５（ｄ）に示す柱状のバンプ３０と配線パターン２２，２２・・を形成できる。
かかる配線パターン２２，２２・・上には、必要に応じて複数の配線パターンを絶縁層を介して多層に積層し、絶縁層を貫通するヴィアによって配線パターン間を電気的に接続することによって、図４に示す半導体パッケージを得ることができる。
この様に、配線パターン２２，２２・・上に複数の配線パターンを絶縁層を介して多層に積層する際には、公知のアディティブ法やセミアディティブ法を利用できる。
尚、図４及び図５では、半導体素子１４ｂのみに柱状のバンプ３０を形成したが、半導体素子１４ａ，１４ｂの一方又は両方に、先細り状のバンプ１８と柱状のバンプ３０とを混在させてもよい。 When forming the columnar bumps 30 and the wiring patterns 22, 22..., For example, electroless plating is performed on the entire surface of the insulating layer 20 including the inner wall surfaces of the recesses 28, 28. A thin metal layer is formed by vapor deposition or sputtering.
Further, after patterning the photosensitive resin layer formed on the surface of the thin metal layer so that the thin metal layer is exposed along the wiring pattern to be formed, electrolytic plating using the thin metal layer as a power feeding layer is performed. The recesses 28, 28,... Are filled with plating metal, and the wiring patterns 22, 22,.
Next, the photosensitive resin layer is peeled off, and the exposed thin metal layer is etched to form the columnar bumps 30 and the wiring patterns 22, 22... Shown in FIG.
On the wiring patterns 22, 22..., A plurality of wiring patterns are laminated in multiple layers via an insulating layer as necessary, and the wiring patterns are electrically connected by vias penetrating the insulating layer, The semiconductor package shown in FIG. 4 can be obtained.
In this way, when a plurality of wiring patterns are laminated on the wiring patterns 22, 22... Via the insulating layer, a known additive method or semi-additive method can be used.
4 and 5, the columnar bump 30 is formed only on the semiconductor element 14b. However, the tapered bump 18 and the columnar bump 30 may be mixed in one or both of the semiconductor elements 14a and 14b. Good.

図１〜図５に示す半導体パッケージでは、厚さの異なる半導体素子１４ａ，１４ｂを、それらの電極端子１６，１６・・の端子面が同一面となるように支持板１０の一面側に固着している。このため、半導体素子１４ａ，１４ｂの電極端子１６，１６・・の各端子面に、同一長さのバンプを形成でき、半導体素子１４ａの電極端子１６，１６・・と、半導体素子１４ｂの電極端子１６，１６・・との各端子面に形成するバンプの長さが異なる場合に比較して、バンプを容易に形成できる。
また、図１〜図５に示す半導体パッケージでは、半導体素子１４ａ，１４ｂの両方又は一方の電極端子１６，１６・・の各端子面に先細り状のバンプ１８を形成している。このため、先細り状のバンプ１８の絶縁層２０の表面に露出する先端面の面積を、電極端子１６の端子面の面積よりも小さくでき、先細り状のバンプ１８の先端面と接続する配線パターン２２の微細化を図ることができ、且つ隣接するバンプ１８，１８の露出面間隙を、バンプ１８，１８を形成した電極端子１６，１６の端子面間隙よりも広くできる。
かかる図１〜図５に示す半導体パッケージでは、隣接するバンプ１８，１８のバンプの露出面間隙を通して引き回す配線パターン２２，２２・・の高密度化を図ることができ、半導体素子１４ａ，１４ｂの小型化等に伴う電極端子１６，１６・・の高密度化に対応できる。
尚、図１〜図５に示す半導体パッケージでは、半導体素子のみを搭載した例について説明したが、半導体素子と共に、例えばコンデンサ、抵抗、インダクタ等を搭載できる。 In the semiconductor package shown in FIGS. 1 to 5, the semiconductor elements 14a and 14b having different thicknesses are fixed to one surface side of the support plate 10 such that the terminal surfaces of the electrode terminals 16, 16,. ing. Therefore, bumps having the same length can be formed on the terminal surfaces of the electrode terminals 16, 16,... Of the semiconductor elements 14a, 14b, and the electrode terminals 16, 16,. Compared to the case where the lengths of the bumps formed on the terminal surfaces 16, 16,... Are different, the bumps can be formed easily.
In the semiconductor package shown in FIGS. 1 to 5, tapered bumps 18 are formed on the terminal surfaces of both the semiconductor elements 14a and 14b or one of the electrode terminals 16, 16,. For this reason, the area of the front end surface exposed to the surface of the insulating layer 20 of the tapered bump 18 can be made smaller than the area of the terminal surface of the electrode terminal 16, and the wiring pattern 22 connected to the front end surface of the tapered bump 18. The gap between the exposed surfaces of the adjacent bumps 18 and 18 can be made wider than the gap between the terminal surfaces of the electrode terminals 16 and 16 on which the bumps 18 and 18 are formed.
In the semiconductor package shown in FIGS. 1 to 5, it is possible to increase the density of the wiring patterns 22, 22... Drawn through the gaps between the exposed surfaces of the adjacent bumps 18, 18, and to reduce the size of the semiconductor elements 14 a, 14 b. It is possible to cope with the high density of the electrode terminals 16, 16.
In the semiconductor package shown in FIGS. 1 to 5, the example in which only the semiconductor element is mounted has been described. However, for example, a capacitor, a resistor, an inductor, and the like can be mounted together with the semiconductor element.

１０ 支持板
１２ 樹脂層
１４ａ，１４ｂ 半導体素子
１６ 電極端子
１８ 先細り状のバンプ
１９ コイニング板
２０ 絶縁層
２２ 配線パターン
２４ ソルダレジスト層
２６ パッド
２８ 凹部
３０ 柱状のバンプ
５０ 板体
５２ 接着層 DESCRIPTION OF SYMBOLS 10 Support plate 12 Resin layer 14a, 14b Semiconductor element 16 Electrode terminal 18 Tapered bump 19 Coining board 20 Insulating layer 22 Wiring pattern 24 Solder resist layer 26 Pad 28 Recess 30 Columnar bump 50 Plate body 52 Adhesive layer

Claims (10)

厚さの異なる複数の半導体素子が、それぞれの電極端子の端子面が同一面となるように、支持板の一面側に樹脂層によって固着されている半導体パッケージであって、
前記樹脂層は、前記支持板の一面側の全面に設けられており、
前記複数の半導体素子は、前記端子面の反対側の面が前記樹脂層に固着されており、
前記複数の半導体素子の端子面および側面の少なくとも一部、ならびに前記樹脂層の表面の全面を被覆する絶縁層が設けられ、
前記複数の半導体素子の端子面に形成されたバンプが、前記絶縁層を貫通し、且つ前記絶縁層の表面に先端面を露出して設けられており、
前記バンプの先端面が、前記絶縁層の表面に形成された配線パターンに接続されていることを特徴とする半導体パッケージ。 A plurality of semiconductor elements having different thicknesses are semiconductor packages fixed to one surface side of the support plate by a resin layer so that the terminal surfaces of the respective electrode terminals are the same surface,
The resin layer is provided on the entire surface on one side of the support plate,
The plurality of semiconductor elements have a surface opposite to the terminal surface fixed to the resin layer,
An insulating layer covering at least part of the terminal surfaces and side surfaces of the plurality of semiconductor elements, and the entire surface of the resin layer;
Bumps formed on the terminal surfaces of the plurality of semiconductor elements are provided so as to penetrate the insulating layer and expose the front end surface on the surface of the insulating layer,
A semiconductor package, wherein a front end surface of the bump is connected to a wiring pattern formed on a surface of the insulating layer. 前記複数の半導体素子の電極端子に形成された前記バンプが、前記先端面が前記端子面よりも小面積に形成された先細り状のバンプである請求項１記載の半導体パッケージ。   2. The semiconductor package according to claim 1, wherein the bumps formed on the electrode terminals of the plurality of semiconductor elements are tapered bumps having the tip end surface formed in a smaller area than the terminal surface. 前記複数の半導体素子の電極端子に形成された前記バンプが、前記先細り状のバンプと柱状のバンプとからなる請求項２記載の半導体パッケージ。   3. The semiconductor package according to claim 2, wherein the bumps formed on the electrode terminals of the plurality of semiconductor elements include the tapered bumps and the columnar bumps. 前記先細り状のバンプが、前記半導体素子の電極端子に端部を圧着した金属ワイヤにより形成されている請求項２または３記載の半導体パッケージ。   4. The semiconductor package according to claim 2, wherein the tapered bump is formed of a metal wire having an end pressed against an electrode terminal of the semiconductor element. 前記金属ワイヤが、金から成るワイヤである請求項４記載の半導体パッケージ。   The semiconductor package according to claim 4, wherein the metal wire is a wire made of gold. 前記支持板が、金属製である請求項１〜５のいずれか一項記載の半導体パッケージ。   The semiconductor package according to claim 1, wherein the support plate is made of metal. 厚さの薄い半導体素子は、該厚さの薄い半導体素子の端子形成面に対して反対面と前記支持板の一面との間に前記樹脂層が介在して、前記支持板の一面側に前記樹脂層によって固着され、
前記厚さの薄い半導体素子よりも厚さの厚い半導体素子は、該厚さの厚い半導体素子の端子形成面に対して反対面が前記支持板の一面に直接接触した状態で、前記支持板の一面側に前記樹脂層によって固着されている請求項１〜６のいずれか一項記載の半導体パッケージ。 The thin semiconductor element has the resin layer interposed between the surface opposite to the terminal forming surface of the thin semiconductor element and one surface of the support plate, and the one side of the support plate Fixed by resin layer,
The semiconductor element thicker than the thin semiconductor element has a surface opposite to the terminal forming surface of the thick semiconductor element in direct contact with one surface of the support plate. The semiconductor package as described in any one of Claims 1-6 currently fixed to the one surface side by the said resin layer. 厚さの薄い半導体素子は、該厚さの薄い半導体素子の端子形成面に対して反対面と前記支持板の一面との間に前記樹脂層が介在して、前記支持板の一面側に前記樹脂層によって固着され、
前記厚さの薄い半導体素子よりも厚さの厚い半導体素子は、該厚さの厚い半導体素子の端子形成面に対して反対面と前記支持板の一面との間に前記樹脂層が介在して、前記支持板の一面側に前記樹脂層によって固着され、
前記厚さの薄い半導体素子の反対面と前記支持板の一面との間に介在する前記樹脂層の高さは、前記厚さの厚い半導体素子の反対面と前記支持板の一面との間に介在する前記樹脂層の高さよりも高い請求項１〜６のいずれか一項記載の半導体パッケージ。 The thin semiconductor element has the resin layer interposed between the surface opposite to the terminal forming surface of the thin semiconductor element and one surface of the support plate, and the one side of the support plate Fixed by resin layer,
The semiconductor element thicker than the thin semiconductor element has the resin layer interposed between the surface opposite to the terminal forming surface of the thick semiconductor element and one surface of the support plate. , Fixed to the one surface side of the support plate by the resin layer,
The height of the resin layer interposed between the opposite surface of the thin semiconductor element and one surface of the support plate is between the opposite surface of the thick semiconductor element and one surface of the support plate. The semiconductor package as described in any one of Claims 1-6 higher than the height of the said resin layer to interpose. 前記絶縁層が、前記半導体素子の端子形成面から側面の少なくとも一部にかけて該半導体素子を覆う請求項１〜８のいずれか一項記載の半導体パッケージ。   The semiconductor package according to claim 1, wherein the insulating layer covers the semiconductor element from a terminal formation surface of the semiconductor element to at least a part of a side surface. 前記配線パターン上には、更に他の絶縁層と配線パターンが多層に積層されている請求項１〜９のいずれか一項記載の半導体パッケージ。   The semiconductor package according to any one of claims 1 to 9, wherein another insulating layer and a wiring pattern are laminated in a multilayer on the wiring pattern.
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