JP2013004756A - Element mounting substrate - Google Patents

Element mounting substrate Download PDF

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JP2013004756A
JP2013004756A JP2011134692A JP2011134692A JP2013004756A JP 2013004756 A JP2013004756 A JP 2013004756A JP 2011134692 A JP2011134692 A JP 2011134692A JP 2011134692 A JP2011134692 A JP 2011134692A JP 2013004756 A JP2013004756 A JP 2013004756A
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metal layer
substrate
mounting
wiring pattern
hard metal
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JP5784998B2 (en
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Masahito Furuya
正仁 古屋
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Citizen Holdings Co Ltd
Citizen Electronics Co Ltd
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Citizen Holdings Co Ltd
Citizen Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

PROBLEM TO BE SOLVED: To provide an element mounting substrate in which heat dissipation is improved while maintaining the connectibility by mounting in excellent state.SOLUTION: An element mounting substrate 10 has a substrate 11 and a wiring pattern 12. The wiring pattern 12 consists of a base metal layer 13 formed on the substrate 11 and having a high heat conductivity, a hard metal layer 14 formed thereon, and a surface metal layer 15 formed on the base metal layer 13 and the hard metal layer 14 and having a high heat conductivity. The hard metal layer 14 having a high hardness is placed only at the mounting point P of a bump 17 or a wire 27 for connection with the element 16 in the wiring pattern 12. Since the hard metal layer 14 is provided only at the mounting point P, a solder barrier at the mounting point P or propagation of an ultrasonic wave during the mounting is improved.

Description

本発明は、ＬＥＤ等の素子を実装する基板に関するものであり、特に、バンプの接続性又はワイヤーのボンディング性を良好な状態で保ちながら、放熱性を向上した素子実装用基板に関する。   The present invention relates to a substrate on which an element such as an LED is mounted, and more particularly, to an element mounting substrate with improved heat dissipation while maintaining good bump connectivity or wire bonding.

従来、この種の実装用基板としては、図４に示すように、チップ部品５を良好に実装するため、基板１の表面に銅メッキ層２、ニッケルメッキ層３、金メッキ層４が積層されて設けられていた。銅メッキ層２は、基板１の表面に設けられる線路として形成されており、ニッケルメッキ層３と金メッキ層４は、銅メッキ層２上のトランジスタチップ等のチップ部品５を実装する領域全体に形成されていた（例えば、特許文献１、図２参照）。上記従来の実装用基板では、実装領域以外をレジスト膜６で覆うことで、実装領域全体にニッケルメッキ層３と金メッキ層４を形成していた。   Conventionally, as this type of mounting substrate, as shown in FIG. 4, a copper plating layer 2, a nickel plating layer 3, and a gold plating layer 4 are laminated on the surface of the substrate 1 in order to mount the chip component 5 satisfactorily. It was provided. The copper plating layer 2 is formed as a line provided on the surface of the substrate 1, and the nickel plating layer 3 and the gold plating layer 4 are formed on the entire region on which the chip component 5 such as a transistor chip is mounted on the copper plating layer 2. (For example, see Patent Document 1 and FIG. 2). In the conventional mounting substrate, the nickel plating layer 3 and the gold plating layer 4 are formed over the entire mounting area by covering the area other than the mounting area with the resist film 6.

上記従来の実装用基板におけるチップ部品５は、ニッケルメッキ層３と金メッキ層４が設けられた実装領域内に実装されていた。このため、チップ部品５が発する熱は、金メッキ層４からニッケルメッキ層３に伝わることになるが、ニッケルの熱伝導率が金や銅に比べて非常に低いため、金メッキ層４からニッケルメッキ層３には熱が殆んど伝わらない。しかも、この従来技術では、金メッキ層４を設ける部分が限られて面積が小さくなり、熱の移動をより困難にしていた。このように従来の実装用基板では、放熱性が悪いという問題があった。   The chip component 5 in the conventional mounting substrate is mounted in a mounting area where the nickel plating layer 3 and the gold plating layer 4 are provided. For this reason, the heat generated by the chip component 5 is transferred from the gold plating layer 4 to the nickel plating layer 3, but since the thermal conductivity of nickel is much lower than that of gold or copper, the gold plating layer 4 to the nickel plating layer. 3 hardly receives heat. In addition, in this prior art, the portion where the gold plating layer 4 is provided is limited, the area is reduced, and heat transfer is made more difficult. Thus, the conventional mounting substrate has a problem of poor heat dissipation.

近年、上記のように実装される素子には、大電流を流すことが多く、例えば、ＬＥＤ素子の場合、照明用として使用するときにより明るく発光させるため、以前よりも大きい電流を流している。このように素子に大電流を流すと、素子の発熱量が増し、効率良く放熱しないと素子の能力低下や損傷を招くことになる。従って、良好な実装を行うと同時に、実装部周辺の放熱性を向上させることが必要であった。   In recent years, a large current is often passed through the elements mounted as described above. For example, in the case of an LED element, a larger current is passed than before in order to emit light brighter when used for illumination. If a large current is passed through the element in this way, the amount of heat generated by the element increases, and if the heat is not efficiently dissipated, the capacity of the element will be reduced or damaged. Accordingly, it is necessary to improve the heat dissipation around the mounting portion while performing good mounting.

特開平９−２１３７３０号公報Japanese Patent Laid-Open No. 9-213730

本発明が解決しようとする課題は、上記従来技術の問題点を解決し、実装による接続性を良好な状態に保ちながら、放熱性を改善した素子実装用基板を提供することにある。   The problem to be solved by the present invention is to solve the above-mentioned problems of the prior art and to provide a device mounting board with improved heat dissipation while maintaining good connectivity by mounting.

本発明の素子実装用基板は、基板と、該基板の素子実装面上に形成された配線パターンとを有し、その配線パターンにおける素子に接続するバンプ又はワイヤーの実装ポイントにのみ硬度が高い硬質金属層を配置したものである。実装ポイントにのみ硬質金属層を設けることで、実装ポイントにおける半田バリアあるいは実装時の超音波の伝わりを良好にしている。   The element mounting substrate of the present invention has a substrate and a wiring pattern formed on the element mounting surface of the substrate, and has a high hardness only at a mounting point of a bump or wire connected to the element in the wiring pattern. A metal layer is arranged. By providing the hard metal layer only at the mounting point, the solder barrier at the mounting point or the transmission of ultrasonic waves at the time of mounting is improved.

配線パターンは、基板の素子実装面上に形成された高い熱伝導率を有する下地金属層と、その上に形成された硬質金属層と、下地金属層及び硬質金属層の上に形成された高い熱伝導率を有する表面金属層とから構成されている。また、この下地金属層及び硬質金属層はそれぞれ銅とニッケルからなり、表面金属層は金又は銀からなる。   The wiring pattern includes a base metal layer having high thermal conductivity formed on the element mounting surface of the substrate, a hard metal layer formed thereon, and a high metal layer formed on the base metal layer and the hard metal layer. And a surface metal layer having thermal conductivity. The base metal layer and the hard metal layer are made of copper and nickel, respectively, and the surface metal layer is made of gold or silver.

本発明の素子実装用基板では、基板上の配線パターンにおけるバンプ又はワイヤーの実装ポイントにのみ硬度が高いニッケルからなる硬質金属層を設けている。これにより、配線パターンは実装ポイントを除くほぼ全域が熱伝導率の高い銅や金等からなる下地金属層と表面金属層で構成され、この配線パターン上に実装された素子が発する熱を表面金属層から下地金属層へ広く直接伝えて放熱することができる。   In the element mounting substrate of the present invention, a hard metal layer made of nickel having high hardness is provided only at a bump or wire mounting point in a wiring pattern on the substrate. As a result, the wiring pattern is almost composed of a base metal layer and surface metal layer made of copper, gold, etc. with high thermal conductivity, except for the mounting point, and the heat generated by the elements mounted on this wiring pattern is generated by the surface metal. It is possible to dissipate heat by directly transmitting from the layer to the underlying metal layer.

また、素子に接続するバンプ又はワイヤーの実装ポイントには、硬度が高い硬質金属層を設けているので、柔らかい金あるいは銅等からなる表面金属層と下地金属層に比べて超音波の伝わりが良い。これにより、超音波を用いたボンディングによる実装がし易く、実装による接続性を良好に保つことができる。   Also, since the hard metal layer with high hardness is provided at the mounting point of the bump or wire connected to the element, the ultrasonic wave is better transmitted than the surface metal layer made of soft gold or copper and the base metal layer. . Thereby, it is easy to mount by bonding using ultrasonic waves, and the connectivity by mounting can be kept good.

また、素子のバンプとして金バンプだけでなく半田バンプを用いた場合であっても、硬質金属層が半田バリアとなって、表面金属層や下地金属層としての金や銅が半田に大量に溶け込む金食われや銅食われの発生を防ぐことができる。   Even when not only gold bumps but also solder bumps are used as element bumps, the hard metal layer serves as a solder barrier, and gold and copper as the surface metal layer and the base metal layer dissolve in a large amount in the solder. It is possible to prevent the occurrence of gold and copper erosion.

本発明の一実施例に係る素子実装用基板を示す断面図である。It is sectional drawing which shows the element mounting board | substrate which concerns on one Example of this invention. 図１に示す素子実装用基板をワイヤーボンディングに対応するように変更した変形例を示す断面図である。It is sectional drawing which shows the modification which changed the element mounting board | substrate shown in FIG. 1 so that it might respond to wire bonding. 図２に示す素子実装用基板のワイヤーの実装ポイントを示す拡大断面図である。It is an expanded sectional view which shows the mounting point of the wire of the board | substrate for element mounting shown in FIG. 従来の素子実装用基板の構造を示す断面図である。It is sectional drawing which shows the structure of the conventional board | substrate for element mounting.

図１は本発明の一実施例に係る素子実装用基板の断面図である。この実施例に係る素子実装用基板１０は、基板１１と、その基板１１上に設けられた配線パターン１２とを有している。基板１１は、アルミニウム、アルミナ等を主成分とするセラミック、有機材料等からなる。   FIG. 1 is a cross-sectional view of an element mounting board according to an embodiment of the present invention. The element mounting board 10 according to this embodiment includes a board 11 and a wiring pattern 12 provided on the board 11. The substrate 11 is made of ceramic, organic material, or the like whose main component is aluminum, alumina, or the like.

配線パターン１２は、基板１１上に実装される素子１６をマザーボード（図示せず）等に設けられた回路や電源に接続するものであり、素子１６を実装する素子実装面１１a上に設けられている。この配線パターン１２は、下地金属層１３と、硬質金属層１４と、表面金属層１５とから構成されている。   The wiring pattern 12 connects the element 16 mounted on the substrate 11 to a circuit or a power source provided on a mother board (not shown) or the like, and is provided on the element mounting surface 11a on which the element 16 is mounted. Yes. The wiring pattern 12 includes a base metal layer 13, a hard metal layer 14, and a surface metal layer 15.

下地金属層１３は、例えば銅からなり、基板１１の素子実装面１１a上に形成されている。硬質金属層１４は、例えばニッケルからなり、下地金属層１３の上で且つ素子１６を固着接続するバンプ１７が表面金属層１５に接触接合される実装ポイントＰに形成されている。表面金属層１５は、例えば金又は銀からなり、下地金属層１３に沿って下地金属層１３及び硬質金属層１４を覆うように形成されている。   The base metal layer 13 is made of, for example, copper, and is formed on the element mounting surface 11 a of the substrate 11. The hard metal layer 14 is made of, for example, nickel, and is formed on the base metal layer 13 and at the mounting point P where the bumps 17 for fixing and connecting the elements 16 are bonded to the surface metal layer 15. The surface metal layer 15 is made of, for example, gold or silver, and is formed so as to cover the base metal layer 13 and the hard metal layer 14 along the base metal layer 13.

実装ポイントＰは、バンプ１７が配線パターン１２に接触接合される地点であり、実装する際に球状、凸状等をなすバンプ１７のほぼ直径に相当する。従って、配線パターン１２における硬質金属層１４は、バンプ１７の直径と同じかあるいは直径よりやや大きい円形あるいは矩形をなすように形成される。バンプ１７は、金、半田等からなり、１０〜１００μｍの高さ（直径）を有するため、硬質金属層１４はこのバンプ１７に対応する大きさに形成される。   The mounting point P is a point where the bump 17 is brought into contact with the wiring pattern 12 and corresponds to the diameter of the bump 17 that is spherical or convex when mounted. Therefore, the hard metal layer 14 in the wiring pattern 12 is formed to have a circular shape or a rectangular shape that is the same as or slightly larger than the diameter of the bump 17. The bump 17 is made of gold, solder, or the like, and has a height (diameter) of 10 to 100 μm. Therefore, the hard metal layer 14 is formed in a size corresponding to the bump 17.

上記素子実装用基板１０にＬＥＤ等の素子１６を実装すると、バンプ１７が接合される実装ポイントＰには、表面金属層１５の下に硬質金属層１４が配置されている。これにより、実装ポイントＰに超音波を印加すると、ニッケルからなる硬質金属層１４によって超音波が確実に実装ポイントＰに受け止められ、バンプ１７が接合される。   When the element 16 such as an LED is mounted on the element mounting substrate 10, the hard metal layer 14 is disposed under the surface metal layer 15 at the mounting point P to which the bump 17 is bonded. Thus, when an ultrasonic wave is applied to the mounting point P, the ultrasonic wave is reliably received by the mounting point P by the hard metal layer 14 made of nickel, and the bumps 17 are joined.

また、バンプ１７として半田バンプを用いた場合、実装時に金又は銀からなる表面金属層１５の一部がバンプ１７に取り込まれても、硬質金属層１４が半田バリアとなって周辺の表面金属層１５や銅からなる下地金属層１３が取り込まれる金食われあるいは銅食われを防ぐことができる。   When a solder bump is used as the bump 17, even if a part of the surface metal layer 15 made of gold or silver is taken into the bump 17 at the time of mounting, the hard metal layer 14 becomes a solder barrier and the peripheral surface metal layer. It is possible to prevent erosion of gold or copper erosion in which the base metal layer 13 made of 15 or copper is taken in.

上記のように基板１１の配線パターン１２上に素子１６が実装されると、その素子１６が発する熱は、配線パターン１２の表面金属層１５からその表面金属層１５に広く直接接触している下地金属層１３へと直ぐに伝導する。このときに硬質金属層１４は、バンプ１７の実装ポイントＰにのみ形成されているため、表面金属層１５から下地金属層１３への熱の移動を妨げることがない。   When the element 16 is mounted on the wiring pattern 12 of the substrate 11 as described above, the heat generated by the element 16 is widely exposed directly from the surface metal layer 15 of the wiring pattern 12 to the surface metal layer 15. Immediate conduction to the metal layer 13. At this time, since the hard metal layer 14 is formed only at the mounting point P of the bump 17, heat transfer from the surface metal layer 15 to the base metal layer 13 is not hindered.

本実施例においては、表面金属層１５が金（熱伝導率３１７W/(m・k)）、硬質金属層１４がニッケル（熱伝導率９０．７W/(m・k)）、下地金属層１３が銅（熱伝導率４０１W/(m・k)）であるため、熱伝導率が低い硬質金属層１４があっても、熱伝導率が高い表面金属層１５から下地金属層１３へ素子１６で発生した熱が容易に伝わり、極めて放熱性に優れた構造となる。   In this embodiment, the surface metal layer 15 is gold (thermal conductivity 317 W / (m · k)), the hard metal layer 14 is nickel (thermal conductivity 90.7 W / (m · k)), and the base metal layer 13. Is copper (thermal conductivity 401 W / (m · k)), so that even if there is a hard metal layer 14 with low thermal conductivity, the element 16 passes from the surface metal layer 15 with high thermal conductivity to the base metal layer 13. The generated heat is easily transmitted and the structure is extremely excellent in heat dissipation.

なお、アルミニウム（熱伝導率２３７W/(m・k)）を主成分とする基板１１の場合には、素子１６から下地金属層１３に移動された熱を更に移動して放熱することが可能であるがアルミナ（熱伝導率２０〜３０W/(m・k)）を主成分とする基板１１の場合には、熱の移動が期待できないため、配線パターン１２による熱の移動と放熱が極めて重要となる。従って、本実施例の素子実装用基板１０のように、配線パターン１２による熱の移動が優れているものでは、基板１１の材質にかかわらず放熱性を向上させることが可能である。   In the case of the substrate 11 mainly composed of aluminum (thermal conductivity 237 W / (m · k)), it is possible to further dissipate the heat transferred from the element 16 to the base metal layer 13 by moving it. However, in the case of the substrate 11 whose main component is alumina (thermal conductivity 20 to 30 W / (m · k)), since heat transfer cannot be expected, heat transfer and heat dissipation by the wiring pattern 12 are extremely important. Become. Accordingly, in the case where the heat transfer by the wiring pattern 12 is excellent as in the element mounting substrate 10 of the present embodiment, the heat dissipation can be improved regardless of the material of the substrate 11.

図２は図１に示す素子実装用基板１０をワイヤーボンディングに対応するように変更した変形例を示す断面図であり、図３はその拡大断面図である。図２及び図３に示す素子実装用基板２０は、基本的な構成、即ち基板１１、下地金属層１３、硬質金属層１４及び表面金属層１５の材質及びそれらを設けることに関しては図１に示した素子実装用基板１０と同様である。したがって、同様の構成には同一の符号を付すことによって、詳細な説明を省略する。   FIG. 2 is a cross-sectional view showing a modification in which the element mounting substrate 10 shown in FIG. 1 is modified to correspond to wire bonding, and FIG. 3 is an enlarged cross-sectional view thereof. The element mounting substrate 20 shown in FIGS. 2 and 3 is shown in FIG. 1 with respect to the basic configuration, that is, the materials of the substrate 11, the base metal layer 13, the hard metal layer 14, and the surface metal layer 15. This is the same as the element mounting substrate 10. Therefore, detailed description is abbreviate | omitted by attaching | subjecting the same code | symbol to the same structure.

この変形例において、素子実装用基板２０における硬質金属層１４は、素子２６をワイヤーボンディングする金線等からなるワイヤー２７を接合する実装ポイントＰのみに設けられている。このため、配線パターン１２における素子２６をダイボンディングする部分は、下地金属層１３と表面金属層１５だけが積層された構造となっている。   In this modification, the hard metal layer 14 in the element mounting substrate 20 is provided only at the mounting point P where the wire 27 made of a gold wire or the like for wire bonding the element 26 is bonded. Therefore, the portion of the wiring pattern 12 where the element 26 is die-bonded has a structure in which only the base metal layer 13 and the surface metal layer 15 are laminated.

この素子実装用基板２０における硬質金属層１４は、図３に示すように、ワイヤー２７がボンディングされる実装ポイントＰに対応する大きさ及び形状に形成されている。このワイヤー２７は、１０〜３０μｍの線径を有する金線を素子２６の電極に接合した後、キャピラリ（図示せず）で延伸すると共にキャピラリ先端で加圧し且つ超音波を印加することで配線パターン１２に接合される。このため、ワイヤー２７の実装ポイントＰは、ワイヤー２７が接合するときに潰れて線径よりもわずかに大きくなる。これに対応して、硬質金属層１４は、ワイヤー２７の線径よりわずかに大きい円形、矩形等に形成され、これにより実装ポイントＰをカバーするように設定されている。このように硬質金属層１４を形成することで、実装時の超音波の伝導を良くすることができる。   As shown in FIG. 3, the hard metal layer 14 in the element mounting substrate 20 is formed in a size and shape corresponding to the mounting point P to which the wire 27 is bonded. The wire 27 is formed by bonding a gold wire having a wire diameter of 10 to 30 μm to the electrode of the element 26, stretching with a capillary (not shown), applying pressure at the tip of the capillary, and applying ultrasonic waves. 12 is joined. For this reason, the mounting point P of the wire 27 is crushed when the wire 27 is joined, and becomes slightly larger than the wire diameter. Correspondingly, the hard metal layer 14 is formed in a circular shape, a rectangular shape, or the like that is slightly larger than the wire diameter of the wire 27, thereby setting the mounting point P to be covered. By forming the hard metal layer 14 in this way, it is possible to improve the conduction of ultrasonic waves during mounting.

また、この素子実装用基板２０では、配線パターン１２における素子２６がダイボンディングされる部分に熱伝導率が低い硬質金属層１４がないので、素子２６が発する熱を熱伝導率が高い表面金属層１５から同じく熱伝導率が高い下地金属層１３へ直ぐに伝導させて放熱することができる。   Further, in this element mounting substrate 20, since there is no hard metal layer 14 having a low thermal conductivity at the portion where the element 26 is die-bonded in the wiring pattern 12, the surface metal layer having a high thermal conductivity for the heat generated by the element 26. 15 can be immediately conducted to the base metal layer 13 having the same high thermal conductivity to dissipate heat.

１，１１ 基板
２ 銅メッキ層
３ ニッケルメッキ層
４ 金メッキ層
５ チップ部品
６ レジスト膜
１０，２０ 素子実装用基板
１１ａ 素子実装面
１２ 配線パターン
１３ 下地金属層
１４ 硬質金属層
１５ 表面金属層
１６，２６ 素子
１７ バンプ
２７ ワイヤー
Ｐ 実装ポイント DESCRIPTION OF SYMBOLS 1,11 Substrate 2 Copper plating layer 3 Nickel plating layer 4 Gold plating layer 5 Chip component 6 Resist film 10, 20 Device mounting substrate 11a Device mounting surface 12 Wiring pattern 13 Base metal layer 14 Hard metal layer 15 Surface metal layer 16, 26 Element 17 Bump 27 Wire P Mounting point

Claims (3)

基板と、
該基板の素子実装面上に形成された配線パターンとを有し、
前記配線パターンにおける素子に接続するバンプ又はワイヤーの実装ポイントにのみ硬度が高い硬質金属層を配置したことを特徴とする素子実装用基板。 A substrate,
A wiring pattern formed on the element mounting surface of the substrate;
A device mounting board, wherein a hard metal layer having a high hardness is disposed only at a mounting point of a bump or wire connected to the device in the wiring pattern. 前記配線パターンは、前記基板の素子実装面上に形成された高い熱伝導率を有する下地金属層と、該下地金属層の上に形成された前記硬質金属層と、前記下地金属層及び前記硬質金属層の上に形成された高い熱伝導率を有する表面金属層と、から構成されている請求項１に記載の素子実装用基板。   The wiring pattern includes a base metal layer having high thermal conductivity formed on an element mounting surface of the substrate, the hard metal layer formed on the base metal layer, the base metal layer, and the hard metal layer. The element mounting substrate according to claim 1, comprising a surface metal layer having a high thermal conductivity formed on the metal layer. 前記下地金属層は銅、前記硬質金属層はニッケル、前記表面金属層は金又は銀からなる請求項２に記載の素子実装用基板。   The element mounting substrate according to claim 2, wherein the base metal layer is made of copper, the hard metal layer is made of nickel, and the surface metal layer is made of gold or silver.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015046215A (en) * 2013-08-27 2015-03-12 エイチジーエスティーネザーランドビーブイ Soldering electrode for high thermal conductivity material
JP2017152506A (en) * 2016-02-24 2017-08-31 三菱マテリアル株式会社 Board for power module and power module and manufacturing method of board for power module
JP2019169605A (en) * 2018-03-23 2019-10-03 三菱マテリアル株式会社 Insulative circuit board

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09213730A (en) * 1996-02-01 1997-08-15 Matsushita Electron Corp High-frequency module substrate and high-frequency power amplification module having it
JPH10335522A (en) * 1997-05-29 1998-12-18 Matsushita Electric Ind Co Ltd Ic mounting board
JP2002368155A (en) * 2001-06-05 2002-12-20 Hitachi Cable Ltd Wiring board, manufacturing method therefor, and semiconductor device
JP2003037135A (en) * 2001-07-24 2003-02-07 Hitachi Cable Ltd Wiring substrate and method of manufacturing the same
JP2010206193A (en) * 2009-02-27 2010-09-16 Ibiden Co Ltd Method for manufacturing printed wiring board and printed wiring board
JP2011091091A (en) * 2009-10-20 2011-05-06 Japan Radio Co Ltd Structure and method for mounting electronic component

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09213730A (en) * 1996-02-01 1997-08-15 Matsushita Electron Corp High-frequency module substrate and high-frequency power amplification module having it
JPH10335522A (en) * 1997-05-29 1998-12-18 Matsushita Electric Ind Co Ltd Ic mounting board
JP2002368155A (en) * 2001-06-05 2002-12-20 Hitachi Cable Ltd Wiring board, manufacturing method therefor, and semiconductor device
JP2003037135A (en) * 2001-07-24 2003-02-07 Hitachi Cable Ltd Wiring substrate and method of manufacturing the same
JP2010206193A (en) * 2009-02-27 2010-09-16 Ibiden Co Ltd Method for manufacturing printed wiring board and printed wiring board
JP2011091091A (en) * 2009-10-20 2011-05-06 Japan Radio Co Ltd Structure and method for mounting electronic component

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015046215A (en) * 2013-08-27 2015-03-12 エイチジーエスティーネザーランドビーブイ Soldering electrode for high thermal conductivity material
JP2017152506A (en) * 2016-02-24 2017-08-31 三菱マテリアル株式会社 Board for power module and power module and manufacturing method of board for power module
JP2019169605A (en) * 2018-03-23 2019-10-03 三菱マテリアル株式会社 Insulative circuit board

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