JP2012253187A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2012253187A
JP2012253187A JP2011124394A JP2011124394A JP2012253187A JP 2012253187 A JP2012253187 A JP 2012253187A JP 2011124394 A JP2011124394 A JP 2011124394A JP 2011124394 A JP2011124394 A JP 2011124394A JP 2012253187 A JP2012253187 A JP 2012253187A
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semiconductor element
tape
bonded
strain
semiconductor device
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Akira Kato
彰 加藤
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Toyota Motor Corp
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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
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    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a configuration in which a solder layer bonds a substrate and a semiconductor element with each other, and a tape-like lead wire (a tape bond) is bonded to the semiconductor element, and being capable of reducing stress generated in the solder layer when the semiconductor element generates heat and of suppressing damage caused by the stress.SOLUTION: In a semiconductor device 10, a position P for bonding a tape-like lead wire 4 on a surface of a semiconductor element 1 is set to be outside a position where a ratio to the maximum value of the internal strain is 0.84 and to a position where the ratio is smaller than 0.84, in the case that the internal strain generated inside the semiconductor element by a linear expansion difference between a metal plate 2 and the semiconductor element 1 to be bonded with each other presents such a strain distribution that the internal strain becomes the largest at the center and becomes smaller toward outside when the semiconductor element is planarly viewed, when the semiconductor element generates heat by energizing the semiconductor element in a state that no tape-like lead wire 4 is bonded to the semiconductor element 1.

Description

本発明は、半導体素子の表面にテープ状の導線がボンディングされた構成の半導体装置に関するものである。   The present invention relates to a semiconductor device having a configuration in which a tape-shaped lead wire is bonded to the surface of a semiconductor element.

ＩＧＢＴ（Insulated Gate Bipolar Transistor）等の半導体素子を搭載した半導体装置（パワーモジュール）の基本構成は、絶縁基板上にある回路を形成する金属板と半導体素子がはんだ層を介して接合され、半導体素子に外部電極に通じる導線（ワイヤ）がワイヤボンディングされたものが一般的であり、絶縁基板と半導体素子の間に銅板や純アルミニウム板等の金属板が積層してなる形態、絶縁基板の下方にヒートシンクやヒートシンクと冷却器等がろう付けされた冷却機構を具備する形態、さらには、絶縁基板と半導体素子の接続体がケース内に収容され、封止樹脂体でポッティングされた形態など、その構成形態は多岐に亘っている。   The basic configuration of a semiconductor device (power module) equipped with a semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) is such that a metal plate forming a circuit on an insulating substrate and the semiconductor element are joined via a solder layer. In general, a lead wire (wire) leading to an external electrode is wire-bonded, and a form in which a metal plate such as a copper plate or a pure aluminum plate is laminated between an insulating substrate and a semiconductor element, below the insulating substrate. A configuration including a heat sink, a cooling mechanism in which a heat sink and a cooler are brazed, and a configuration in which a connection body of an insulating substrate and a semiconductor element is accommodated in a case and potted with a sealing resin body There are various forms.

いずれの形態の半導体装置であっても、半導体素子に通電して発熱した際には、はんだ層を介して相互に接続された線膨張係数の異なる半導体素子と絶縁基板上にある回路を形成する金属板の線膨張差に起因して、半導体素子の内部には内部歪（非弾性歪）が生じることになる（半導体素子の線膨張係数は３ｐｐｍ／Ｋ程度、絶縁基板上にある回路を形成する金属板の線膨張係数は、金属板がアルミニウムからなる場合は２２ｐｐｍ／Ｋ程度、銅からなる場合は１６ｐｐｍ／Ｋ程度である。   In any type of semiconductor device, when a semiconductor element is energized to generate heat, a semiconductor element having a different linear expansion coefficient connected to each other through a solder layer and a circuit on an insulating substrate are formed. Due to the difference in the linear expansion of the metal plate, internal strain (inelastic strain) occurs inside the semiconductor element (the linear expansion coefficient of the semiconductor element is about 3 ppm / K, forming a circuit on an insulating substrate). The linear expansion coefficient of the metal plate is about 22 ppm / K when the metal plate is made of aluminum, and about 16 ppm / K when the metal plate is made of copper.

たとえば平面視正方形の半導体素子を例示するに、この半導体素子が発熱した際には、その中央領域に熱が篭り易いことから発熱量が周辺領域に比して多くなり、したがって中央領域における内部歪は相対的に大きくなるのが一般的である。   For example, in the case of a semiconductor element having a square shape in plan view, when this semiconductor element generates heat, the amount of heat generated is larger than that in the peripheral area because heat is easily generated in the central area. Is generally relatively large.

実際に熱応力解析などをおこなうと、中央領域から外周に向かって内部歪が徐々に小さくなる同心円状、もしくは略同心円状の内部歪コンターが解析結果としてコンピュータ画面上で確認できる。   When an actual thermal stress analysis or the like is performed, a concentric or substantially concentric internal strain contour in which the internal strain gradually decreases from the central region toward the outer periphery can be confirmed on the computer screen as an analysis result.

そして、半導体素子と金属板を繋ぐはんだ層は半導体素子や金属板に比して剛性が小さく、構造弱部であることから、はんだ層の中でも半導体素子の内部歪が最も大きな領域に対応する領域のストレスが最も大きくなり、この領域にクラックが生じ易くなっている。   Since the solder layer connecting the semiconductor element and the metal plate is less rigid than the semiconductor element or metal plate and has a weak structure, the area corresponding to the area where the internal strain of the semiconductor element is the largest among the solder layers. The stress is the largest, and cracks are likely to occur in this region.

半導体装置の小型化が進むにつれて該装置への電流密度や装置内で生じる発熱量も大きくなることから、はんだ層の特に半導体素子の内部歪が最も大きな領域に対応する領域におけるストレスの増大とこれに起因するクラックの発生はより一層顕著なものとなる。   As the semiconductor device is further miniaturized, the current density to the device and the amount of heat generated in the device also increase. Therefore, an increase in stress in the solder layer, particularly in the region corresponding to the region where the internal strain of the semiconductor element is the largest, is increased. The occurrence of cracks due to this becomes even more remarkable.

一方、電流密度の高密度化に対応するべく、これまでのワイヤボンディングに代わって、テープ状で比較的幅広の導線を用いてこれを半導体素子の表面にボンディングし（いわゆるテープボンディング）、このテープ状の導線（テープボンド）を介して外部電極から半導体素子に通電する形態の半導体装置も開発されており、このような形態の半導体装置におけるテープボンディング方法やそのための装置が特許文献１に開示されている。   On the other hand, instead of the conventional wire bonding, this tape is bonded to the surface of a semiconductor element using a relatively wide conductive wire (so-called tape bonding) in order to cope with the increase in current density. A semiconductor device having a configuration in which a semiconductor element is energized from an external electrode via a conductive wire (tape bond) has been developed, and a tape bonding method in such a semiconductor device and an apparatus therefor are disclosed in Patent Document 1. ing.

ところで、テープボンドがボンディングされた従来の半導体装置では、半導体素子の表面においてテープボンドをボンディングする位置の設定に特に注意が払われることはなかったが、はんだ層に付与されるストレスの観点で言えば、テープボンドがボンディングされる半導体素子位置に対応するはんだ層部位においてストレスがより一層大きくなり得ることが本発明者等によって特定されている。   By the way, in the conventional semiconductor device in which the tape bond is bonded, no particular attention is paid to the setting of the position where the tape bond is bonded on the surface of the semiconductor element, but it can be said from the viewpoint of the stress applied to the solder layer. For example, the present inventors have specified that the stress can be further increased in the solder layer portion corresponding to the position of the semiconductor element to which the tape bond is bonded.

このことを本発明者等によってなされた解析結果を示す図７〜図９を参照して説明する。図７ａには、回路を形成する金属板Ｋと半導体素子Ｓがはんだ層Ｈを介して接合され、半導体素子Ｓの表面に４つのテープ状導線Ｔがそれぞれ２箇所のボンディング位置Ｐ，Ｐでテープボンディングされている従来の半導体装置の解析モデルを示しており、図７ｂは図７ａのｂ矢視図（平面図）を示している。   This will be described with reference to FIGS. 7 to 9 showing analysis results made by the present inventors. In FIG. 7a, a metal plate K forming a circuit and a semiconductor element S are joined via a solder layer H, and four tape-shaped conductors T are taped to the surface of the semiconductor element S at two bonding positions P and P, respectively. FIG. 7B shows an analysis model of a conventional semiconductor device that is bonded, and FIG. 7B shows a view (plan view) of FIG.

本解析は図７で示す解析モデルの半導体素子に温度履歴を付与する熱応力解析であり、テープボンドのない解析モデルで半導体素子が発熱した際に該半導体素子内で生じる非弾性歪を求めた解析結果を図８ａに、そのIXａ矢視図を図９ａに、図７で示すテープボンドのある解析モデルで半導体素子が発熱した際に該半導体素子内で生じる非弾性歪を求めた解析結果を図８ｂに、そのIXｂ矢視図を図９ｂにそれぞれ示している。なお、解析結果の歪コンター図は、図７ｂの平面図の中央ラインＬの上下で対象であることから、図８の解析結果は図７ｂの上領域Ａのみを示している。   This analysis is a thermal stress analysis that gives a temperature history to the semiconductor element of the analysis model shown in FIG. 7, and the inelastic strain generated in the semiconductor element when the semiconductor element generates heat in the analysis model without a tape bond was obtained. The analysis result is shown in FIG. 8a, the IXa arrow view is shown in FIG. 9a, and the analysis result obtained for the inelastic strain generated in the semiconductor element when the semiconductor element generates heat in the analysis model with the tape bond shown in FIG. FIG. 8b shows an IXb arrow view of FIG. 9b. Since the distortion contour diagram of the analysis result is an object above and below the central line L in the plan view of FIG. 7b, the analysis result of FIG. 8 shows only the upper region A of FIG. 7b.

図９ａ，ｂを比較すると明りょうであるが、図９ａの歪グラフは金属板に半導体素子が接合され、双方の線膨張係数の相違に起因する結果であり、テープボンドのない解析モデルにおける内部歪の最大値は熱の篭り易い中央位置ｘ０で最大値ε０を示す。それに対し、テープボンドのある解析モデルにおける内部歪の最大値は、図９ｂで示すように、図９ａの歪グラフに対してテープボンドをボンディングしたことに起因する内部歪の増加分が加わってボンディング位置ｘ３でε１（＞ε０）、ボンディング位置ｘ４でε２（＞ε１＞ε０）を示す結果となっている。   9A and 9B, it is clear that the strain graph of FIG. 9A is a result of the difference between the linear expansion coefficients of the semiconductor element bonded to the metal plate. The maximum value of the strain shows a maximum value ε0 at the center position x0 where heat is easily generated. On the other hand, as shown in FIG. 9b, the maximum value of the internal strain in the analysis model with the tape bond is increased by adding an increase in internal strain resulting from bonding the tape bond to the strain graph of FIG. 9a. The result shows ε1 (> ε0) at the position x3 and ε2 (> ε1> ε0) at the bonding position x4.

このような解析結果を踏まえ、本発明者等は半導体素子に対するテープボンドのボンディング位置に着目し、従来構造の半導体装置に比してはんだ層にストレスが付与され難く、もってクラック等の破損が生じ難い構造の半導体装置の発案に至っている。   Based on such analysis results, the present inventors pay attention to the bonding position of the tape bond to the semiconductor element, and stress is not easily applied to the solder layer as compared with a semiconductor device having a conventional structure, and thus breakage such as a crack occurs. The idea of a semiconductor device having a difficult structure has been reached.

特開２００７−２５０５７１号公報JP 2007-250571 A

本発明は上記する問題に鑑みてなされたものであり、回路を形成する金属板と半導体素子をはんだ層が接合し、半導体素子にテープ状の導線（テープボンド）がボンディングされた構成の半導体装置に関し、半導体素子が発熱した際のはんだ層に生じるストレスが低減され、当該ストレスに起因する破損を抑制することのできる半導体装置を提供することを目的とする。   The present invention has been made in view of the above problems, and a semiconductor device having a configuration in which a solder layer is joined to a metal plate forming a circuit and a semiconductor element, and a tape-shaped conductor (tape bond) is bonded to the semiconductor element. An object of the present invention is to provide a semiconductor device in which stress generated in a solder layer when a semiconductor element generates heat is reduced and damage caused by the stress can be suppressed.

前記目的を達成すべく、本発明による半導体装置は、絶縁基板上で回路を形成する金属板と半導体素子がはんだ層を介して接合され、半導体素子の表面にテープ状の導線がボンディングされてなる半導体装置であって、半導体素子の表面において前記テープ状の導線がボンディングされる位置は、半導体素子にテープ状の導線がボンディングされていない状態において半導体素子に通電して半導体素子が発熱した際に、相互に接合される金属板と半導体素子の線膨張差によって該半導体素子の内部で生じる内部歪が半導体素子を平面的に見た際にその中央で最も大きく、外側に向かって内部歪が小さくなる歪分布を呈するものにおいて、内部歪の最大値に対する比率が０．８４となる位置よりも外側であって該比率が０．８４未満となっている位置に設定されているものである。   In order to achieve the above object, a semiconductor device according to the present invention is formed by bonding a metal plate forming a circuit on an insulating substrate and a semiconductor element via a solder layer, and bonding a tape-shaped lead wire to the surface of the semiconductor element. In the semiconductor device, the position where the tape-shaped conductor is bonded to the surface of the semiconductor element is when the semiconductor element generates heat when the semiconductor element is energized in a state where the tape-shaped conductor is not bonded to the semiconductor element. The internal strain generated inside the semiconductor element due to the difference in linear expansion between the metal plate and the semiconductor element joined to each other is the largest at the center when the semiconductor element is viewed in a plane, and the internal strain is small toward the outside. In which the ratio to the maximum value of the internal strain is 0.84 and the ratio is less than 0.84. Are those set in position.

本発明の半導体装置は、その構成要素である半導体素子の表面にテープ状の導線（テープボンド）がボンディングされた構成の装置に関し、テープボンドのボンディング位置を最適な範囲に調整することにより、テープボンドをボンディングすることによって半導体素子が発熱した際にその内部歪（非弾性歪）が増加した場合であっても、その内部歪の最大値をテープボンドがボンディングされない構成の内部歪の最大値よりも小さくすることのできる装置である。   The semiconductor device of the present invention relates to a device having a structure in which a tape-shaped lead wire (tape bond) is bonded to the surface of a semiconductor element which is a component thereof, and by adjusting the bonding position of the tape bond to an optimum range, Even when the internal strain (inelastic strain) increases when a semiconductor element generates heat by bonding a bond, the maximum value of the internal strain is greater than the maximum value of the internal strain of the configuration in which the tape bond is not bonded. It is a device that can be made smaller.

すなわち、半導体素子表面におけるテープボンドのボンディング位置のみを調整しただけの極めて簡易な構造改良により、半導体素子が発熱した際の内部歪に起因する構造弱部であるはんだ層に付与されるストレスを低減するものである。   In other words, the stress applied to the solder layer, which is a weak structure due to internal strain when the semiconductor element generates heat, is reduced by adjusting the bonding position of the tape bond on the surface of the semiconductor element. To do.

ここで、半導体装置を構成して回路を形成する金属板は、銅やアルミニウム、もしくはこれらの合金から形成できる。また、回路を形成する金属板の下方に位置する絶縁基板には、たとえば純アルミニウムからなる基板と窒化アルミニウムからなる基盤とを積層してなる積層体（ＤＢＡ）などが含まれる。さらに、半導体素子は、ＩＣチップ（シリコンチップ）やトランジスタ、ダイオードなどの素子全般を示称している。   Here, the metal plate forming the circuit by forming the semiconductor device can be formed of copper, aluminum, or an alloy thereof. The insulating substrate positioned below the metal plate forming the circuit includes, for example, a laminate (DBA) formed by laminating a substrate made of pure aluminum and a base made of aluminum nitride. Further, the semiconductor element indicates all elements such as an IC chip (silicon chip), a transistor, and a diode.

また、半導体装置には、上記する絶縁基板の下方に、ヒートシンク板や、ヒートシンク板と冷媒還流路を具備する冷却器とのアルミダイキャスト一体成形体を具備するものであってもよく、さらには、半導体素子、回路を形成する金属板、絶縁基板、およびヒートシンク板等の積層体が絶縁素材（セラミックス、熱硬化性もしくは熱可塑性の樹脂素材、アルミニウムやその合金素材など）のケース内に収容されるものであっても、ケースレス構造のものであってもよい。さらに、半導体素子や金属板の表面に絶縁性を付与するべく、比較的高剛性なポッティング樹脂体、低剛性で可撓性に富むゲル状のポッティング樹脂体などを、半導体素子や金属板の表面上に具備する形態であってもよい。   Further, the semiconductor device may be provided with an aluminum die-cast integrally formed body of a heat sink plate or a cooler having a heat sink plate and a refrigerant reflux path below the insulating substrate described above. Laminates such as semiconductor elements, circuit-forming metal plates, insulating substrates, and heat sink plates are housed in cases of insulating materials (ceramics, thermosetting or thermoplastic resin materials, aluminum and its alloy materials, etc.) Even a thing of a caseless structure may be sufficient. Furthermore, in order to provide insulation to the surface of a semiconductor element or a metal plate, a relatively high-rigidity potting resin body, a low-rigidity and highly flexible gel-like potting resin body, or the like is applied to the surface of a semiconductor element or a metal plate. The form provided above may be sufficient.

既述するように、テープボンドがボンディングされていない構成の半導体装置を取り上げると、半導体素子が発熱した際には、その中央領域で熱が篭り易く、したがって、発熱時の内部歪分布は中央領域で最も大きくなり、外側に向かって同心円状もしくは略同心円状で内部歪は小さくなる傾向を呈する。   As described above, when a semiconductor device having a structure in which a tape bond is not bonded is taken up, when the semiconductor element generates heat, heat is easily generated in the central region. Therefore, the internal strain distribution at the time of heat generation is the central region. Tends to be concentric or substantially concentric toward the outside, and the internal strain tends to be small.

そして、テープボンドがボンディングされると、このボンディング位置で半導体素子の内部歪が増加することになるが、本発明者等によれば、このボンディング位置が半導体素子の中央領域に近い一定の範囲にある場合は、テープボンドがボンディングされていない場合の最大値よりも大きな内部歪となることが実証されている。   When the tape bond is bonded, the internal strain of the semiconductor element increases at this bonding position. According to the present inventors, the bonding position is within a certain range close to the central region of the semiconductor element. In some cases it has been demonstrated that the internal strain is greater than the maximum value when the tape bond is not bonded.

本発明者等によれば、テープボンドがボンディングされていない状態での半導体素子において、その中央位置の最大の内部歪で各部位の内部歪を規格化（各部位の内部歪を最大値で除する）した値が０．８４よりも小さな範囲にテープボンドをボンディングすることにより、半導体素子表面にテープボンドをボンディングした場合であっても内部歪の最大値は増加しないことが見出されている。   According to the present inventors, in a semiconductor element in which a tape bond is not bonded, the internal strain of each part is normalized by the maximum internal strain at the center position (the internal strain of each part is divided by the maximum value). It has been found that the maximum value of the internal strain does not increase even when the tape bond is bonded to the surface of the semiconductor element by bonding the tape bond to a range smaller than 0.84. .

そこで、テープボンドのボンディング位置を、半導体素子が発熱した際に、相互に接合される金属板と半導体素子の線膨張差によって該半導体素子の内部で生じる内部歪が半導体素子を平面的に見た際にその中央で最も大きく、外側に向かって内部歪が小さくなる歪分布を呈するものにおいて、内部歪の最大値に対する比率が０．８４となる位置よりも外側であって該比率が０．８４未満となっている位置に設定することにより、当該ボンディングに起因する半導体素子の内部歪の増大を抑止することができ、構造弱部であるはんだ層に付与されるストレスの増加を抑止することでそのクラック等の破損の抑制を図ることが可能となる。   Therefore, when the semiconductor element generates heat at the bonding position of the tape bond, the internal strain generated inside the semiconductor element due to the difference in linear expansion between the metal plate and the semiconductor element bonded to each other is seen in a plan view of the semiconductor element. In the case where the strain distribution is the largest at the center and the internal strain decreases toward the outside, the ratio is 0.84 outside the position where the ratio to the maximum value of the internal strain is 0.84. By setting to a position that is less than, it is possible to suppress an increase in internal strain of the semiconductor element due to the bonding, and to suppress an increase in stress applied to the solder layer that is a weak structure It becomes possible to suppress breakage such as cracks.

上記する半導体装置によれば、その小型化と高電流密度化に対応するべく、テープボンドを介して半導体素子に通電がおこなわれる構成の半導体装置であっても、半導体素子が発熱した際のはんだ層の破損は効果的に抑制されていることから、その車載機器に高性能かつ高耐久が要求される、近時のハイブリッド車や電気自動車に車載されるインバータ等への適用に最適である。   According to the semiconductor device described above, even when the semiconductor device is configured to energize the semiconductor element through the tape bond in order to cope with the downsizing and high current density, the solder when the semiconductor element generates heat is used. Since damage to the layer is effectively suppressed, it is optimal for application to inverters mounted on recent hybrid vehicles and electric vehicles, which require high performance and high durability for the in-vehicle devices.

以上の説明から理解できるように、本発明の半導体装置によれば、半導体素子の表面にテープボンドがボンディングされた構成の装置であっても、テープボンドのボンディング位置が最適な範囲に調整されていることにより、テープボンドをボンディングすることに起因する半導体素子発熱時の内部歪（非弾性歪）の増加によってもその内部歪の最大値をテープボンドがボンディングされない構成の場合の内部歪よりも小さくすることができ、半導体素子の内部歪によって付与されるはんだ層のストレスが増加することを抑止することができ、もってはんだ層の破損を効果的に抑止して半導体装置の耐久低下を防止することができる。   As can be understood from the above description, according to the semiconductor device of the present invention, the bonding position of the tape bond is adjusted to the optimum range even in the device having the tape bond bonded to the surface of the semiconductor element. Therefore, even if the internal strain (inelastic strain) increases when the semiconductor element generates heat due to the bonding of the tape bond, the maximum value of the internal strain is smaller than the internal strain in the configuration in which the tape bond is not bonded. It is possible to suppress an increase in the stress of the solder layer imparted by the internal strain of the semiconductor element, thereby effectively preventing the solder layer from being damaged and preventing a decrease in the durability of the semiconductor device. Can do.

本発明の半導体装置の一実施の形態の縦断面図である。It is a longitudinal cross-sectional view of one embodiment of a semiconductor device of the present invention. 図１のII−II矢視図であって本発明の半導体装置の一実施の形態の平面図である。FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 1 and illustrating a semiconductor device according to an embodiment of the present invention. （ａ）は、テープボンドのボンディング位置を規定するための解析で用いた解析モデルを示す模式図であり、（ｂ）は、解析条件である半導体素子の温度履歴グラフを示す図である。(A) is a schematic diagram which shows the analysis model used by the analysis for prescribing | bonding the bonding position of a tape bond, (b) is a figure which shows the temperature history graph of the semiconductor element which is analysis conditions. （ａ）は、テープボンドをボンディングしていないモデルの温度応力解析結果の非弾性歪の歪分布を示す図であり、（ｂ）は、（ａ）の解析結果を用いて、中央の最大値で各部位を規格化した規格化後の歪分布を示す図である。(A) is a figure which shows the strain distribution of the inelastic strain of the temperature stress analysis result of the model which has not bonded the tape bond, (b) is the maximum value of the center using the analysis result of (a). It is a figure which shows the distortion distribution after normalization which normalized each site | part. （ａ）は、テープボンドがボンディングされている解析モデルの温度応力解析結果の非弾性歪の歪分布を示す図であり、（ｂ）は、（ａ）の解析結果を用いて、中央の値（最大値ではない）で各部位を規格化した規格化後の歪分布を示す図である。(A) is a figure which shows strain distribution of the inelastic strain of the thermal stress analysis result of the analytical model to which the tape bond is bonded, (b) is a center value using the analysis result of (a). It is a figure which shows the distortion distribution after normalization which normalized each site | part (it is not the maximum value). 温度応力解析結果を示すグラフである。It is a graph which shows a temperature stress analysis result. （ａ）は、従来構造のテープボンドがボンディングされてなる半導体装置を示す模式図であり、（ｂ）は（ａ）のｂ矢視図である。(A) is a schematic diagram which shows the semiconductor device by which the tape bond of a conventional structure is bonded, (b) is a b arrow line view of (a). （ａ）は、図７で示す構造からテープボンドを廃した構成の半導体装置をモデル化して温度応力解析をおこなった結果を示す図であり、（ｂ）は図７で示す構成の半導体装置をモデル化して温度応力解析をおこなった結果を示す図である。(A) is a figure which shows the result of having modeled the semiconductor device of the structure which abolished the tape bond from the structure shown in FIG. 7, and performed the temperature stress analysis, (b) is a figure which shows the semiconductor device of the structure shown in FIG. It is a figure which shows the result of having modeled and performing the temperature stress analysis. （ａ）は、図８ａのIXａ−IXａ矢視図であり、（ｂ）は、図８ｂのIXｂ−IXｂ矢視図である。(A) is an IXa-IXa arrow view of FIG. 8a, (b) is an IXb-IXb arrow view of FIG. 8b.

以下、図面を参照して本発明の半導体装置の実施の形態を説明する。図１は本発明の半導体装置の一実施の形態の縦断面図であり、図２は図１のII−II矢視図であってその平面図となっている。   Hereinafter, embodiments of a semiconductor device of the present invention will be described with reference to the drawings. FIG. 1 is a longitudinal sectional view of an embodiment of a semiconductor device of the present invention, and FIG. 2 is a plan view taken along the line II-II in FIG.

図１，２で示す半導体装置１０は、回路を形成する金属板２の一側面にはんだ層３を介して半導体素子１が接続され、半導体素子１の表面には幅広のテープ状の導線（テープボンド４）が２つのボンディング位置Ｐ，Ｐでボンディングされてその全体が大略構成されている。なお、テープボンド４のボンディング位置の基数は図示例に何等限定されるものではない。   A semiconductor device 10 shown in FIGS. 1 and 2 has a semiconductor element 1 connected to one side surface of a metal plate 2 forming a circuit via a solder layer 3, and a wide tape-shaped conductor (tape) is attached to the surface of the semiconductor element 1. The bond 4) is bonded at two bonding positions P and P, and the whole is generally constituted. The number of bonding positions of the tape bond 4 is not limited to the illustrated example.

回路を形成する金属板２は、銅やアルミニウム、もしくはこれらの合金を素材とするものであり、その下方には、不図示の絶縁基板やさらに不図示の応力緩和基板等が設けられており、この絶縁基板には、たとえば純アルミニウムからなる基板と窒化アルミニウムからなる基盤とを積層してなる積層体（ＤＢＡ）などが含まれる。   The metal plate 2 forming the circuit is made of copper, aluminum, or an alloy thereof, and an insulating substrate (not shown) or a stress relaxation substrate (not shown) is provided below the metal plate 2. This insulating substrate includes, for example, a laminate (DBA) formed by laminating a substrate made of pure aluminum and a base made of aluminum nitride.

一方、半導体素子１には、ＩＣチップ（シリコンチップ）やトランジスタ、ダイオードなどのいずれか一種が適用できる。   On the other hand, any one of an IC chip (silicon chip), a transistor, a diode, and the like can be applied to the semiconductor element 1.

はんだ層３は、Ｐｂ系はんだ、Ｐｂフリーはんだのいずれであってもよいが、環境影響負荷低減を図るべく、Ｓｎ−Ａｇ系はんだ、Ｓｎ−Ｃｕ系はんだ、Ｓｎ−Ａｇ−Ｃｕ系はんだ、Ｓｎ−Ｚｎ系はんだ、Ｓｎ−Ｓｂ系はんだなどのＰｂフリーはんだからなるものが好ましい。   The solder layer 3 may be either Pb-based solder or Pb-free solder, but in order to reduce environmental impact load, Sn-Ag solder, Sn-Cu solder, Sn-Ag-Cu solder, Sn Those made of Pb-free solder such as -Zn solder and Sn-Sb solder are preferable.

図２で示すように、半導体素子１の表面でテープボンド４がボンディングされるボンディング位置Ｐは、最適なボンディング位置を規定する環状ラインＱよりも外側となるように設定される。   As shown in FIG. 2, the bonding position P where the tape bond 4 is bonded on the surface of the semiconductor element 1 is set to be outside the annular line Q that defines the optimum bonding position.

この環状ラインＱは、後述する本発明者等による温度応力解析結果に基づいて半導体素子１が発熱した際に生じる非弾性歪の最大値が、テープボンドを具備しない構造の半導体装置の場合の非弾性歪の最大値よりも小さくなる、もしくはこの最大値以下となる境界ラインであり、この環状ラインＱよりも外側にボンディング位置Ｐを設定するようにしたものである。   This annular line Q is a non-elastic strain in the case of a semiconductor device having a structure that does not have a tape bond when the maximum value of inelastic strain generated when the semiconductor element 1 generates heat based on a temperature stress analysis result by the present inventors described later. This is a boundary line that is smaller than the maximum value of the elastic strain or less than this maximum value, and the bonding position P is set outside the annular line Q.

テープボンド４をボンディングすることにより、半導体素子１が発熱した際には、この半導体装置１にはテープボンド４とはんだ層３を介して金属板２とから拘束を受け、非弾性歪み分布は、半導体素子１の中央とテープボンド４のボンディング位置で歪みのピークを有する歪分布を呈することになる。その際に、ボンディング位置が環状ラインＱよりも内側に存在すると、ボンディング位置における非弾性歪のピーク値が半導体素子の中央位置におけるピーク値よりも高くなってしまう。   When the semiconductor element 1 generates heat by bonding the tape bond 4, the semiconductor device 1 is restrained by the metal plate 2 via the tape bond 4 and the solder layer 3, and the inelastic strain distribution is A strain distribution having a strain peak at the center of the semiconductor element 1 and the bonding position of the tape bond 4 is exhibited. At this time, if the bonding position exists inside the annular line Q, the peak value of the inelastic strain at the bonding position becomes higher than the peak value at the center position of the semiconductor element.

そこで、ボンディング位置を環状ラインＱよりも外側に設定することにより、テープボンド４をボンディングした構成の半導体装置１０においても、テープボンドをボンディングしない構成の半導体装置よりも半導体素子１が発熱した際に生じる非弾性歪（内部歪）を小さくすることができる。そして、このように非弾性歪が小さくなることにより、この半導体素子１内で生じる非弾性歪に起因してはんだ層３に付与されるストレスを低減することができ、このストレスに起因して生じ得るクラック等の破損を抑制することができる。そしてこのことは、テープボンドをボンディングしたことに起因する半導体装置の耐久低下を抑制することに繋がるものである。   Therefore, by setting the bonding position outside the annular line Q, even in the semiconductor device 10 configured to bond the tape bond 4, when the semiconductor element 1 generates heat compared to the semiconductor device configured to not bond the tape bond. The generated inelastic strain (internal strain) can be reduced. Since the inelastic strain is thus reduced, the stress applied to the solder layer 3 due to the inelastic strain generated in the semiconductor element 1 can be reduced, and the stress is generated due to the stress. Damage such as cracks obtained can be suppressed. This leads to suppression of a decrease in durability of the semiconductor device due to the bonding of the tape bond.

なお、この環状ラインＱは、後述する解析結果に基づき、図２で示すように半導体装置１０を平面的に見た際に、テープボンドがボンディングされていない構成の場合の中央位置における非弾性歪の最大値に対して比率０．８４の非弾性歪を与える部位から構成されるラインとなっている。   This annular line Q is based on an analysis result to be described later. When the semiconductor device 10 is viewed in plan as shown in FIG. 2, the inelastic strain at the center position in the case where the tape bond is not bonded is shown. It is a line comprised from the site | part which gives the inelastic strain of the ratio 0.84 with respect to the maximum value.

[テープボンドのボンディング位置を規定するための温度応力解析とその結果]
本発明者等は、図３ａで示すように金属板モデルＭ２と半導体素子モデルＭ１がはんだ層モデルＭ３を介して接続され、半導体素子モデルＭ１にテープボンドモデルＭ４がボンディングされた解析モデルＭ、および、この解析モデルＭからテープボンドを廃した別途の解析モデル（不図示）をコンピュータ内で作成し、それぞれの解析モデルに対して図３ｂで示す温度履歴を半導体素子モデルに付与して各解析モデルの半導体素子に生じる非弾性歪を求めた。 [Thermal stress analysis and results to define the bonding position of tape bond]
As shown in FIG. 3a, the inventors have an analysis model M in which a metal plate model M2 and a semiconductor element model M1 are connected via a solder layer model M3, and a tape bond model M4 is bonded to the semiconductor element model M1, and Then, a separate analysis model (not shown) in which the tape bond is removed from the analysis model M is created in a computer, and the temperature history shown in FIG. The inelastic strain generated in the semiconductor element was determined.

図４ａは、テープボンドをボンディングしていない解析モデルの温度応力解析結果の非弾性歪の歪分布を示す図であり、図４ｂは、図４ａの解析結果を用いて、中央の最大値で各部位を規格化した規格化後の歪分布を示す図である。一方、図５ａは、テープボンドがボンディングされた図３aで示す解析モデルの温度応力解析結果の非弾性歪の歪分布を示す図であり、図５ｂは、図５ａの解析結果を用いて、中央の最大値で各部位を規格化した規格化後の歪分布を示す図である。   FIG. 4A is a diagram showing a strain distribution of inelastic strain of a thermal stress analysis result of an analytical model in which no tape bond is bonded, and FIG. 4B is a graph showing each of the maximum values at the center using the analysis result of FIG. It is a figure which shows the distortion distribution after normalization which normalized the site | part. On the other hand, FIG. 5a is a diagram showing the strain distribution of the inelastic strain of the thermal stress analysis result of the analytical model shown in FIG. 3a to which the tape bond is bonded, and FIG. It is a figure which shows the distortion distribution after normalization which normalized each site | part with the maximum value of.

図５ａ，ｂより、テープボンドのボンディング位置によっては、中央の非弾性歪の値よりもボンディング位置における非弾性歪の値が高くなっている。   5A and 5B, depending on the bonding position of the tape bond, the value of the inelastic strain at the bonding position is higher than the value of the inelastic strain at the center.

一方、図４ａで示す温度応力解析の結果に基づき、非弾性歪の値が最大となる中央位置の値で他の部位の値を除して規格化し、図４ｂで示す結果を得ている。   On the other hand, based on the result of the temperature stress analysis shown in FIG. 4a, the value of the other part is divided by the value of the central position where the value of the inelastic strain becomes maximum, and the result shown in FIG. 4b is obtained.

この図４ｂ、図５ｂの各規格化後の結果に基づき、それぞれの解析モデルの半導体素子において共通した複数点での各規格値を求め、テープボンドがボンディングされた解析モデルの規格値の結果を縦軸に、テープボンドがボンディングされていない解析モデルの規格値の結果を横軸とし、複数点（本解析では４点）の結果をプロットしてその近似直線を求めたものを図６に示している。なお、各プロットから近似直線（もしくは回帰直線）を作成する方法としては、直線方程式：ｙ＝ａｘ＋ｂを仮に設定し、最小二乗法にてａ，ｂを求める方法などを使用できる。   Based on the results after normalization in FIGS. 4b and 5b, the standard values at a plurality of points common to the semiconductor elements of the respective analysis models are obtained, and the results of the standard values of the analysis model to which the tape bond is bonded are obtained. The vertical axis shows the result of the standard value of the analysis model with no tape bond bonded, and the result of multiple points (4 points in this analysis) is plotted to obtain the approximate straight line. ing. In addition, as a method of creating an approximate line (or regression line) from each plot, a method of obtaining a and b by the least square method by temporarily setting a linear equation: y = ax + b can be used.

同図において、縦軸の１に対応する近似直線の横軸を読んで０．８４が特定される。   In the figure, 0.84 is specified by reading the horizontal axis of the approximate straight line corresponding to 1 on the vertical axis.

縦軸で１よりも大きな範囲はテープボンドがボンディングされた構成の半導体装置においてボンディング位置の非弾性歪の値が中央位置の値よりも高くなる範囲を示しており、縦軸で１以下の範囲はボンディング位置の非弾性歪の値が中央位置の値以下となる範囲を示している。   A range larger than 1 on the vertical axis indicates a range where the value of the inelastic strain at the bonding position is higher than the value at the central position in the semiconductor device having a configuration in which the tape bond is bonded. Indicates a range in which the value of the inelastic strain at the bonding position is not more than the value at the center position.

したがって、縦軸１に対応する横軸０．８４以下（もしくは０．８４未満）の範囲に相当する半導体素子の平面位置を特定し、この範囲よりも外側（図２の環状ラインＱの外側）にボンディング位置を設定することにより、テープボンドをボンディングしたことによる半導体素子における内部歪の増加とこれに起因するはんだ層のストレス増加の問題は解消され、テープボンドがボンディングされてなる半導体装置においてもその耐久低下という課題が解消されるものとなる。   Therefore, the planar position of the semiconductor element corresponding to the range of 0.84 or less (or less than 0.84) corresponding to the vertical axis 1 is specified, and outside this range (outside the annular line Q in FIG. 2). By setting the bonding position, the problem of the increase in internal strain in the semiconductor element due to the bonding of the tape bond and the increase in the stress of the solder layer due to the bonding is solved, and even in the semiconductor device in which the tape bond is bonded The problem of lowering the durability is solved.

以上、本発明の実施の形態を図面を用いて詳述してきたが、具体的な構成はこの実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲における設計変更等があっても、それらは本発明に含まれるものである。   The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and there are design changes and the like without departing from the gist of the present invention. They are also included in the present invention.

１…半導体素子、２…金属板、３…はんだ層、４…テープボンド（テープ状の導線）、１０…半導体装置、Ｐ…ボンディング位置、Ｑ…最適なボンディング位置を規定する環状ライン DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Metal plate, 3 ... Solder layer, 4 ... Tape bond (tape-like conducting wire), 10 ... Semiconductor device, P ... Bonding position, Q ... Ring line which prescribes | regulates optimal bonding position

Claims (1)

絶縁基板上で回路を形成する金属板と半導体素子がはんだ層を介して接合され、半導体素子の表面にテープ状の導線がボンディングされてなる半導体装置であって、
半導体素子の表面において前記テープ状の導線がボンディングされる位置は、半導体素子にテープ状の導線がボンディングされていない状態において半導体素子に通電して半導体素子が発熱した際に、相互に接合される金属板と半導体素子の線膨張差によって該半導体素子の内部で生じる内部歪が半導体素子を平面的に見た際にその中央で最も大きく、外側に向かって内部歪が小さくなる歪分布を呈するものにおいて、内部歪の最大値に対する比率が０．８４となる位置よりも外側であって該比率が０．８４未満となっている位置に設定されている半導体装置。 A semiconductor device in which a metal plate that forms a circuit on an insulating substrate and a semiconductor element are bonded via a solder layer, and a tape-shaped lead wire is bonded to the surface of the semiconductor element,
The position where the tape-shaped conductor is bonded on the surface of the semiconductor element is bonded to the semiconductor element when the semiconductor element generates heat when the semiconductor element is energized without the tape-shaped conductor being bonded to the semiconductor element. The internal strain generated inside the semiconductor element due to the difference in linear expansion between the metal plate and the semiconductor element is the largest when the semiconductor element is viewed in a plane, and exhibits a strain distribution in which the internal strain decreases toward the outside. The semiconductor device is set at a position outside the position where the ratio of the internal strain to the maximum value is 0.84 and the ratio is less than 0.84.
JP2011124394A 2011-06-02 2011-06-02 Semiconductor device Pending JP2012253187A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006188378A (en) * 2005-01-05 2006-07-20 National Institute Of Advanced Industrial & Technology Method for producing isolated carbon nanotube
JP2009076675A (en) * 2007-09-20 2009-04-09 Toshiba Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006188378A (en) * 2005-01-05 2006-07-20 National Institute Of Advanced Industrial & Technology Method for producing isolated carbon nanotube
JP2009076675A (en) * 2007-09-20 2009-04-09 Toshiba Corp Semiconductor device

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