JP2012238887A - Manufacturing method of trench mos type silicon carbide semiconductor device - Google Patents

Manufacturing method of trench mos type silicon carbide semiconductor device Download PDF

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JP2012238887A
JP2012238887A JP2012173521A JP2012173521A JP2012238887A JP 2012238887 A JP2012238887 A JP 2012238887A JP 2012173521 A JP2012173521 A JP 2012173521A JP 2012173521 A JP2012173521 A JP 2012173521A JP 2012238887 A JP2012238887 A JP 2012238887A
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trench
layer
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silicon carbide
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JP5556862B2 (en
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Takashi Tsuji
崇 辻
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Fuji Electric Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a trench MOS type silicon carbide semiconductor device in which the on-resistance can be decreased without forming an electrode film being connected conductively with a trench bottom player anew, even when the player provided on the bottom of a trench is required to have the earth potential.SOLUTION: The trench MOS type silicon carbide semiconductor device includes a first conductivity type drift layer, a second conductivity type base layer, and a first conductivity type source layer laminated in this order on a first conductivity type semiconductor substrate, a stripe-shaped trench extending from the surface of the first conductivity type source layer to reach the drift layer, and a second conductivity type layer having a region matching that of the trench bottom under the gate oxide film thereof. The second conductivity type layer on the trench bottom and the second conductivity type base layer are connected conductively by an epitaxial SiC region formed at the longitudinal end of the trench by using a TaC film as a mask.

Description

本発明は半導体材料として炭化珪素（以下ＳｉＣとも言う）を用い、特にトレンチゲート構造を有するＭＯＳＦＥＴ、ＩＧＢＴ等の電圧駆動型の（ＭＯＳ型電力用）炭化珪素半導体装置の製造方法に関する。 The present invention using silicon carbide as a semiconductor material (hereinafter referred to as SiC), in particular MOSFET having a trench gate structure, the voltage-driven, such as IGBT (for MOS type power) method of manufacturing a silicon carbide semiconductor equipment.

炭化珪素半導体材料は、シリコン半導体材料と比較して大きなバンドギャップを持つため、高い絶縁破壊電界強度を有する。導通状態における抵抗であるオン抵抗は、その絶縁破壊電界強度の３乗に逆比例するため、例えば広く用いられている４Ｈ型と呼ばれる炭化珪素半導体においてはそのオン抵抗をシリコン半導体の数１００分の１に抑制することができる。放熱が容易となる大きな熱伝導度の特性ともあいまって、次世代の低損失な電力用半導体装置としての期待が持たれている。近年、炭化珪素ウエハ（半導体基板）の品質向上と大口径化の進展ともあいまって、シリコン半導体装置の特性を大きく上回る金属酸化物半導体電界効果型トランジスタ（ＭＯＳＦＥＴ）、バイポーラトランジスタ、接合型電界効果型トランジスタ（ＪＦＥＴ）などの開発が盛んである。中でもＭＯＳＦＥＴは、電圧駆動型素子なのでゲート駆動回路が低コストで済むだけでなく、電子あるいは正孔のみの多数キャリア素子であって導通時の素子内にキャリアの蓄積がないので、ターンオフ時にそれらのキャリアを素子外に掃き出す時間を必要とせず、たとえば、電子、正孔の両方が伝導に寄与するバイポーラ型素子と比較して高速スイッチングが可能となる特長を有する。   Since silicon carbide semiconductor material has a larger band gap than silicon semiconductor material, it has high breakdown field strength. Since the on-resistance which is the resistance in the conductive state is inversely proportional to the cube of the dielectric breakdown electric field strength, for example, in the widely used silicon carbide semiconductor called 4H type, the on-resistance is several hundreds of minutes of the silicon semiconductor. 1 can be suppressed. Combined with the characteristic of large thermal conductivity that facilitates heat dissipation, there is an expectation as a next-generation low-loss power semiconductor device. In recent years, metal oxide semiconductor field effect transistors (MOSFETs), bipolar transistors, junction field effect types, which greatly exceed the characteristics of silicon semiconductor devices, coupled with the improvement in quality of silicon carbide wafers (semiconductor substrates) and the increase in diameter. Development of transistors (JFET) and the like is active. Among them, MOSFET is a voltage driven element, so that not only the gate drive circuit is low cost, but also a majority carrier element with only electrons or holes, and there is no accumulation of carriers in the element when conducting, so those at the time of turn-off. It does not require time for sweeping carriers out of the device, and has a feature that enables high-speed switching as compared with, for example, a bipolar device in which both electrons and holes contribute to conduction.

図９に従来の一般的なトレンチゲート構造を有するＵＭＯＳＦＥＴ（主面に垂直な側壁のトレンチゲートを有するＭＯＳＦＥＴ、以下同様）の１セルピッチの断面構造を示す。ｎ型低抵抗炭化珪素基板（ドレイン層）２１上に、高抵抗ｎ型ドリフト層２２、ｐ型ベース層２３を順次エピタキシャルＳｉＣ成長により形成し、その後、ｐ型ベース層２３の表面からイオン注入によりｎ＋型ソース領域２４を形成する。このような炭化珪素ウエハ３０にゲートトレンチ２５を形成する。ゲート酸化膜２６、ゲート電極２７、ソース／ベース電極２８、ドレイン電極２９を順次形成して完成する。 FIG. 9 shows a cross-sectional structure of one cell pitch of a UMOSFET having a conventional general trench gate structure (a MOSFET having a trench gate with a sidewall perpendicular to the main surface, the same applies hereinafter). A high-resistance n-type drift layer 22 and a p-type base layer 23 are sequentially formed on the n-type low-resistance silicon carbide substrate (drain layer) 21 by epitaxial SiC growth, and then ion implantation from the surface of the p-type base layer 23 is performed. An n + type source region 24 is formed. Gate trench 25 is formed in such a silicon carbide wafer 30. A gate oxide film 26, a gate electrode 27, a source / base electrode 28, and a drain electrode 29 are sequentially formed and completed.

オフ状態時には、ソース／ベース電極２８をアース電位にしておき、ゲート電極２７に十分大きな負バイアスを印加すると、ソース領域２４とドリフト層２２に挟まれたｐベース層２３のゲート酸化膜２６との界面近傍の領域には正孔が誘起された蓄積状態となり、伝導キャリアである電子の経路が遮断されるので電流は流れない。ドレイン電極２９に正の高電圧を印加するとｐベース層２３とドリフト層２２間の接合が逆バイアス状態になるので、空乏層がｐベース領域２３内とドリフト層領域２２内に広がり、電流を低く抑えたまま高電圧が維持されている。   When the source / base electrode 28 is kept at the ground potential in the off state and a sufficiently large negative bias is applied to the gate electrode 27, the source region 24 and the gate oxide film 26 of the p base layer 23 sandwiched between the drift layer 22 and In the region near the interface, holes are induced and accumulated, and the path of electrons as conduction carriers is blocked, so no current flows. When a positive high voltage is applied to the drain electrode 29, the junction between the p base layer 23 and the drift layer 22 is in a reverse bias state, so that the depletion layer extends into the p base region 23 and the drift layer region 22, and the current is reduced. The high voltage is maintained while being suppressed.

また、オン状態時には、ゲート電極２７に十分大きい正バイアスを印加するとソース領域２４とドリフト層２２に挟まれたｐベース層２３のトレンチ２５の表面近傍の領域に電子が誘起された反転状態になり、電子がソース電極２８、ソース領域２４、ｐベース層２３のゲート酸化膜２６に接する反転層（図示せず）、ドリフト層２２、基板２１、ドレイン電極２９の順にキャリアが流れる。   In addition, when a sufficiently large positive bias is applied to the gate electrode 27 in the on state, an inverted state is generated in which electrons are induced in a region near the surface of the trench 25 of the p base layer 23 sandwiched between the source region 24 and the drift layer 22. Electrons flow through the source electrode 28, the source region 24, the inversion layer (not shown) in contact with the gate oxide film 26 of the p base layer 23, the drift layer 22, the substrate 21, and the drain electrode 29 in this order.

オン状態における抵抗について、構造上、図１０に示されるような一般的なＤＩＭＯＳＦＥＴでは加算されるドリフト層３２のゲート酸化膜３６との界面近傍を電子が移動するときの蓄積層抵抗と、ドリフト層３２内のゲート酸化膜３６近傍から下方のドレインに向かって流れるときにｎ型ドリフト層３２が両隣のｐ型ベース層３３に挟まれていることによって発生し易いＪＦＥＴ抵抗とが、前記図９に示すトレンチゲート型のＵＭＯＳＦＥＴでは発生しないという長所がある。このため、ＤＩＭＯＳＦＥＴではセルピッチを小さくして行くと、あるセルピッチ距離からＪＦＥＴ抵抗が現れて、オン抵抗が増加するのに対し、ＵＭＯＳＦＥＴではセルピッチを小さくすればするほどオン抵抗が単調に減少するという長所がある。特に約３ｋＶ以下の耐圧を持つＭＯＳＦＥＴにおいては、ＭＯＳチャネル抵抗が無視できないために微細化によるセルピッチの縮小が必須であり、ＵＭＯＳＦＥＴを使用する方が望ましい。   Regarding the resistance in the ON state, in the structure of a general DIMOSFET as shown in FIG. 10, the accumulation layer resistance when electrons move near the interface between the drift layer 32 and the gate oxide film 36 added, and the drift layer FIG. 9 shows the JFET resistance that is likely to occur when the n-type drift layer 32 is sandwiched between the adjacent p-type base layers 33 when flowing from the vicinity of the gate oxide film 36 to the lower drain in FIG. The trench gate type UMOSFET shown in FIG. For this reason, when the cell pitch is reduced in the DIMOSFET, the JFET resistance appears from a certain cell pitch distance and the on-resistance increases, whereas in the UMOSFET, the on-resistance decreases monotonously as the cell pitch is reduced. There is. In particular, in a MOSFET having a withstand voltage of about 3 kV or less, since the MOS channel resistance cannot be ignored, it is essential to reduce the cell pitch by miniaturization, and it is preferable to use a UMOSFET.

図１１にＵＭＯＳＦＥＴの構造を示す要部断面図と、この断面図に対応するように、破線の枠で示すｐｎ接合部およびＭＯＳ構造部について、基板の厚さ方向に縦軸を合わせ、横軸にオフ状態における電界強度を表す電界強度分布図を示す。図１１から分かるように、トレンチ底部において酸化膜（ＳｉＯ２膜）２６に印加される電界強度が非常に大きくなる。これは、炭化珪素の比誘電率（４Ｈ−ＳｉＣで９．７）とＳｉＯ２膜の比誘電率（３．８）との差によるものである。さらに図には示されていないが、トレンチコーナー部の酸化膜にかかる電界強度は、電界集中のためさらに高くなる。図１１に示されるｐｎ接合部（２３／２２間）でのピークの電界強度が炭化珪素の絶縁破壊電界強度に至って破壊を生じるのが理想であるが、ＵＭＯＳＦＥＴの場合には、ｐｎ接合（２３／２２間）がその絶縁破壊電界強度に達する前に、トレンチ底部の酸化膜（ＳｉＯ２膜）２６がその絶縁破壊電界強度（約１０ＭＶ／ｃｍ）に先に到達して、理論耐圧より低い電圧で絶縁破壊を起こしてしまう問題がある。シリコン半導体においては、絶縁破壊電界強度が０．２ＭＶ／ｃｍと酸化膜の１０ＭＶ／ｃｍより２桁低いため、ほぼｐｎ接合部で絶縁破壊が起きるが、炭化珪素（４Ｈ）の場合では、絶縁破壊電界強度が２ＭＶ／ｃｍと大きく、酸化膜（ＳｉＯ２膜）の絶縁破壊電界強度と１桁しか違わないので、酸化膜（ＳｉＯ２膜）での絶縁破壊の問題が顕著になる。 FIG. 11 is a cross-sectional view of the principal part showing the structure of the UMOSFET, and the pn junction part and the MOS structure part indicated by the broken line frame are aligned with the vertical direction in the thickness direction of the substrate so as to correspond to this cross-sectional view. Shows an electric field strength distribution diagram showing the electric field strength in the off state. As can be seen from FIG. 11, the electric field strength applied to the oxide film (SiO 2 film) 26 at the bottom of the trench becomes very large. This is due to the difference between the relative dielectric constant of silicon carbide (9.7 for 4H-SiC) and the relative dielectric constant of the SiO 2 film (3.8). Further, although not shown in the figure, the electric field strength applied to the oxide film at the trench corner portion is further increased due to the electric field concentration. It is ideal that the peak electric field strength at the pn junction (between 23/22) shown in FIG. 11 reaches the breakdown electric field strength of silicon carbide to cause breakdown, but in the case of UMOSFET, the pn junction (23 / 22) reaches the dielectric breakdown field strength before the oxide film (SiO 2 film) 26 at the bottom of the trench reaches the dielectric breakdown field strength (about 10 MV / cm) first, and the voltage is lower than the theoretical breakdown voltage. There is a problem that causes dielectric breakdown. In a silicon semiconductor, the dielectric breakdown electric field strength is 0.2 MV / cm, which is two orders of magnitude lower than 10 MV / cm of the oxide film, so that dielectric breakdown occurs almost at the pn junction, but in the case of silicon carbide (4H), dielectric breakdown occurs. field intensity is as large as 2 MV / cm, since due solely breakdown field strength and the 1 digit oxide film (SiO 2 film), a problem of dielectric breakdown of an oxide film (SiO 2 film) becomes remarkable.

このような問題の対策の一方法として、たとえば、タン（Ｊ．Ｔａｎ）らはトレンチ形成直後に素子全面にＡｌやＢのイオン注入を行い、トレンチ底部のみに不純物濃度１×１０１８ｃｍ−３程度、厚さ０．５μｍ程度のトレンチ底部ｐ＋層を形成する工程を経てＵＭＯＳＦＥＴを作製している（非特許文献１）。そうすることにより、ＳｉＣ基板表裏をトレンチ底部の位置で切断する断面における電界強度分布は、従来の構造では図１１のように酸化膜（ＳｉＯ２膜）２６に大きな電界強度がかかっていたものが、図１２に示されるようにトレンチ底部のｐ＋層（電界緩和層）４０により電界が吸収され、酸化膜（ＳｉＯ２膜）２６には電界はかからず、酸化膜（ＳｉＯ２膜）２６中における絶縁破壊を防いで耐圧の向上が実現される。 As a method for solving such a problem, for example, Tan (J. Tan) et al. Performs ion implantation of Al or B on the entire surface of the device immediately after forming the trench, and an impurity concentration of 1 × 10 18 cm −3 only at the bottom of the trench. A UMOSFET is manufactured through a process of forming a trench bottom p + layer having a thickness of about 0.5 μm (Non-patent Document 1). By doing so, the electric field strength distribution in the cross section where the SiC substrate front and back are cut at the bottom of the trench is such that in the conventional structure, a large electric field strength is applied to the oxide film (SiO 2 film) 26 as shown in FIG. As shown in FIG. 12, the electric field is absorbed by the p + layer (electric field relaxation layer) 40 at the bottom of the trench, and no electric field is applied to the oxide film (SiO 2 film) 26, and the oxide film (SiO 2 film) 26. The breakdown voltage is prevented and the breakdown voltage is improved.

トレンチ内面に沿ってｐ＋層を形成してサージ吸収用のダイオードを形成する炭化珪素半導体装置に関する記載がある（特許文献１）。また、トレンチ内面に沿ってトレンチ底部にゲート領域のｐ＋＋コンタクト層を設けて外部から電圧供給可能にすることにより、ゲート抵抗を小さくし、高速スイッチング可能な炭化珪素半導体装置が知られている（特許文献２）。さらにまた、トレンチ底面にｐ型ゲート層を設けることにより、スイッチオフ特性に優れた高耐圧炭化珪素半導体装置が公開されている（特許文献３）。さらに、ＵＭＯＳＦＥＴのトレンチ内の絶縁層の下部のドリフト層内にドリフト層の導電型とは反対の導電型の電界緩和領域（ｐ＋領域）を設けることにより、高耐圧化を可能にする発明が知られている（特許文献４）。 There is a description related to a silicon carbide semiconductor device in which a p + layer is formed along the inner surface of a trench to form a diode for surge absorption (Patent Document 1). Also, a silicon carbide semiconductor device is known in which a gate resistance is reduced and high-speed switching is possible by providing a p ++ contact layer in the gate region at the bottom of the trench along the inner surface of the trench so that voltage can be supplied from the outside. Patent Document 2). Furthermore, a high voltage silicon carbide semiconductor device having an excellent switch-off characteristic by providing a p-type gate layer on the bottom surface of the trench is disclosed (Patent Document 3). Furthermore, an invention that enables a high breakdown voltage by providing an electric field relaxation region (p + region) having a conductivity type opposite to the conductivity type of the drift layer in the drift layer below the insulating layer in the trench of the UMOSFET. Known (Patent Document 4).

特許第３７１１９０６号Japanese Patent No. 3711906 特開２００６−９３１８６号公報JP 2006-93186 A 特開２００４−６７２３号公報JP 2004-6723 A 特開平１０−９８１８８号公報Japanese Patent Laid-Open No. 10-98188

Ｊ．Ｔａｎ ｅｔ ａｌ．， ＩＥＥＥ Ｅｌｅｃｔｒｏｎ． Ｄｅｖ． Ｌｅｔｔ．， Ｖｏｌ．１９， ｐ．４８７− （１９９８）J. et al. Tan et al. , IEEE Electron. Dev. Lett. , Vol. 19, p. 487- (1998)

しかしながら、前記の特許文献４に記載の方法では、トレンチ底部のｐ＋層をアース電位にしなければならないため、このｐ＋層の表面への取り出し電極が必要になる。そのため、素子加工面（表面）側には、ゲート、ソースおよびトレンチ底部のｐ＋層用の３つの電極パッドが必要になる。通常の構造では、ゲート、ソースの２つの電極パッドでよいので、電極パッドが増える分、素子内で電流が流れる活性領域が減り、チップ全体で見た単位面積あたりの抵抗（オン抵抗）が増加すると言う問題がある。また、電極を外部回路に取り出すためのワイヤーボンディング箇所も従来の２箇所から３箇所に増え、工程が増えるという問題もある。 However, in the method described in Patent Document 4, since the p + layer at the bottom of the trench must be grounded, an extraction electrode on the surface of the p + layer is required. Therefore, three electrode pads for the gate, source, and p + layer at the bottom of the trench are required on the element processing surface (front surface) side. In the normal structure, two electrode pads, gate and source, are sufficient, so the electrode pad increases, the active area where current flows in the element decreases, and the resistance per unit area (on-resistance) increases in the entire chip. There is a problem to say. There is also a problem that the number of wire bonding locations for taking out the electrodes to the external circuit is increased from the conventional two locations to three, and the number of processes is increased.

本発明は、以上説明した点に鑑みてなされたものであり、本発明の目的は、トレンチ底部に設けられるトレンチ底部ｐ＋層をアース電位にする必要のあるＭＯＳ構造を有する炭化珪素半導体装置の場合でも、前記トレンチ底部ｐ＋層に導電接続される電極形成を新たに必要とせず、オン抵抗も小さくすることのできるトレンチＭＯＳ型炭化珪素半導体装置の製造方法を提供することである。 The present invention has been made in view of the above-described points, and an object of the present invention is to provide a silicon carbide semiconductor device having a MOS structure in which the trench bottom p + layer provided at the bottom of the trench needs to be grounded. even if not require a new electrode formed to be electrically connected to the trench bottom p + layer is to provide a manufacturing method of a trench MOS-type silicon carbide semiconductor equipment that can be smaller on-resistance.

特許請求の範囲の請求項１記載の発明によれば、第一導電型半導体基板上に第一導電型ドリフト層、第二導電型ベース層、第一導電型ソース層とこの順に積層され、該第一導電型ソース層の表面から前記ドリフト層に達するストライプ状トレンチと、このストライプ状トレンチの側壁及び底面にはゲート酸化膜を介してゲート電極を有し、該トレンチ底部のゲート酸化膜下にはトレンチ底部と一致した領域の第二導電型層を備える炭化珪素からなるトレンチＭＯＳ型炭化珪素半導体装置であって、選択マスクとして用いるＴａＣ膜を半導体基板表面側の全面に形成後、ストライプ状トレンチの長手方向端部の前記ＴａＣ膜を窓開け除去し、該窓開け除去した部分に選択的にエピタキシャルＳｉＣ領域を成長させ前記トレンチ底部の第二導電型層と前記第二導電型ベース層とを導電接続する第二導電型領域を形成するトレンチＭＯＳ型炭化珪素半導体装置の製造方法とすることにより、前記本発明の目的は達成される。 According to the invention of claim 1, wherein in the claims, a first conductive type drift layer to a first conductivity type semiconductor substrate, the second conductivity type base layer, laminated in this order and the first-conductivity-type source layer, the A stripe-shaped trench that reaches the drift layer from the surface of the first conductivity type source layer, and has a gate electrode on the side wall and bottom surface of the stripe-shaped trench via a gate oxide film, below the gate oxide film at the bottom of the trench Is a trench MOS type silicon carbide semiconductor device made of silicon carbide having a second conductivity type layer in a region coinciding with the bottom of the trench , and a striped trench is formed after a TaC film used as a selection mask is formed on the entire surface of the semiconductor substrate surface side. The TaC film at the longitudinal end of the window is removed by opening a window, and an epitaxial SiC region is selectively grown on the portion removed by opening the window, so that the second conductivity type at the bottom of the trench With the manufacturing method of the trench MOS type SiC semiconductor device to form a second conductivity type region to electrically conductive connection between said second conductivity type base layer and the object of the present invention can be achieved.

前述した課題を解決するためには、要するにトレンチ底部ｐ＋層とｐベース層をトレンチ内部表面に形成したｐ＋領域により導電接続する構造とするのである。その製造方法としては、ストライプ状のトレンチを有するＭＯＳＦＥＴ基板にＴａＣ膜を全面に形成した後、トレンチ底部とトレンチの少なくとも一端部の短辺側の側壁部分のみＴａＣ膜を開口した後、ＴａＣ膜をマスクとして、導電接続ｐ＋領域をエピタキシャルＳｉＣ成長させて形成する方法とする。 In order to solve the above-mentioned problems, in short, a structure is formed in which the trench bottom p + layer and the p base layer are conductively connected by a p + region formed on the inner surface of the trench. As a manufacturing method thereof, a TaC film is formed on the entire surface of a MOSFET substrate having a stripe-shaped trench, and then the TaC film is opened only on the trench bottom and the side wall portion on the short side of at least one end of the trench, and then the TaC film is formed. As a mask, the conductive connection p + region is formed by epitaxial SiC growth.

本発明によれば、トレンチ底部に設けられるトレンチ底部ｐ＋層をアース電位にする必要のあるＭＯＳ構造を有する炭化珪素半導体装置の場合でも、前記トレンチ底部ｐ＋層に導電接続される電極形成を新たに必要とせず、オン抵抗も小さくすることのできるトレンチＭＯＳ型炭化珪素半導体装置の製造方法を提供することができる。 According to the present invention, even in the case of a silicon carbide semiconductor device having a MOS structure in which the trench bottom p + layer provided at the bottom of the trench needs to be at ground potential, the electrode conductively connected to the trench bottom p + layer is formed. newly without requiring manufacturing method of a trench MOS-type silicon carbide semiconductor equipment that can be smaller on-resistance can be provided.

本発明にかかる半導体装置の製造方法を示す半導体基板の要部断面図（その１）、Sectional drawing of the principal part of the semiconductor substrate which shows the manufacturing method of the semiconductor device concerning this invention (the 1), 本発明にかかる半導体装置の製造方法を示す半導体基板の要部断面図（その２）、Sectional drawing of the principal part of the semiconductor substrate which shows the manufacturing method of the semiconductor device concerning this invention (the 2), 本発明にかかる半導体装置の製造方法を示す半導体基板の要部断面図（その３）、Sectional view (Part 3) of the principal part of the semiconductor substrate showing the manufacturing method of the semiconductor device according to the present invention, 本発明にかかる半導体装置の製造方法を示す半導体基板の要部断面図（その４）、Sectional drawing (the 4) principal part of a semiconductor substrate which shows the manufacturing method of the semiconductor device concerning this invention, 本発明にかかる半導体装置の製造方法を示す半導体基板の要部断面図（その５）、Sectional drawing (the 5) principal part of a semiconductor substrate which shows the manufacturing method of the semiconductor device concerning this invention, 本発明の参考例１にかかるトレンチパターン平面図、The trench pattern top view concerning the reference example 1 of this invention, 本発明の参考例１にかかる斜めイオン注入を示す半導体基板の断面図、Sectional drawing of the semiconductor substrate which shows the diagonal ion implantation concerning the reference example 1 of this invention, 本発明の参考例１にかかる半導体基板のｎ＋ソース層の切り欠き領域の拡大斜視図、The expanded perspective view of the notch area | region of the n + source layer of the semiconductor substrate concerning the reference example 1 of this invention, 本発明の実施例１にかかるＵＭＯＳＦＥＴの半導体基板の要部断面図、Sectional drawing of the principal part of the semiconductor substrate of UMOSFET concerning Example 1 of this invention, 本発明の実施例１にかかるイオン注入の照射方向を示す半導体基板の断面図、Sectional drawing of the semiconductor substrate which shows the irradiation direction of the ion implantation concerning Example 1 of this invention, 本発明の実施例１にかかるＴａＣ膜パターンを示す平面図、The top view which shows the TaC film | membrane pattern concerning Example 1 of this invention, 本発明の実施例１にかかる半導体基板の要部断面図、Sectional drawing of the principal part of the semiconductor substrate concerning Example 1 of this invention, 従来の一般的なＵＭＯＳＦＥＴの１セルピッチの断面図、1 is a cross-sectional view of a conventional UMOSFET of 1 cell pitch, 従来の一般的なＭＯＳＦＥＴの断面図、Sectional view of a conventional general MOSFET, ＵＭＯＳＦＥＴの電界強度分布図、UMOSFET field strength distribution map, 従来のＵＭＯＳＦＥＴの電界強度分布図である。It is an electric field strength distribution map of the conventional UMOSFET.

以下、本発明の実施例について図面を参照しながら、詳細に説明する。
図１、図２は本発明にかかるトレンチＭＯＳ型炭化珪素半導体装置の製造方法を示す半導体基板の要部断面図である。図３は本発明の参考例１にかかるｎ＋型ソース層６へのトレンチパターンを示す平面図である。図４−１は本発明の参考例１にかかる斜めイオン注入の照射方向を示す半導体基板の断面図である。図４−２は本発明の参考例１にかかる半導体基板のｎ＋ソース層の切り欠き領域の拡大斜視図、図５は本発明の実施例１にかかる炭化珪素ＵＭＯＳＦＥＴの半導体基板の要部断面図、図６は本発明の実施例１にかかるイオン注入の照射方向を示す半導体基板の断面図である。図７は本発明の実施例１にかかるＴａＣ膜マスクパターンを示す平面図である。図８は本発明の実施例１にかかる炭化珪素ＵＭＯＳＦＥＴの半導体基板の要部断面図である。
[参考例１]
以下、本発明にかかるトレンチＭＯＳ型炭化珪素半導体装置の製造方法について、図面を用いて詳細に説明する。本発明はその要旨を超えない限り、以下に説明する実施例の記載に限定されるものではない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
1 and 2 are cross-sectional views of a principal part of a semiconductor substrate showing a method of manufacturing a trench MOS type silicon carbide semiconductor device according to the present invention. FIG. 3 is a plan view showing a trench pattern for the n + -type source layer 6 according to Reference Example 1 of the present invention. FIG. 4-1 is a cross-sectional view of a semiconductor substrate showing the irradiation direction of oblique ion implantation according to Reference Example 1 of the present invention. 4-2 is an enlarged perspective view of a notch region of the n + source layer of the semiconductor substrate according to Reference Example 1 of the present invention, and FIG. 5 is a cross-sectional view of the main part of the semiconductor substrate of the silicon carbide UMOSFET according to Example 1 of the present invention. 6 and 6 are cross-sectional views of the semiconductor substrate showing the irradiation direction of ion implantation according to Example 1 of the present invention. FIG. 7 is a plan view showing a TaC film mask pattern according to Example 1 of the present invention. FIG. 8 is a cross-sectional view of main parts of the semiconductor substrate of the silicon carbide UMOSFET according to Example 1 of the present invention.
[Reference Example 1]
Hereinafter, a method of manufacturing a trench MOS type silicon carbide semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.

厚み約４００μｍ、不純物濃度１×１０１８ｃｍ−３であって低抵抗のｎ型４Ｈ−ＳｉＣ基板１と、この基板上に順次、それぞれエピタキシャルＳｉＣ成長により形成される、膜厚０．５μｍ、不純物濃度１×１０１８ｃｍ−３のｎ＋型バッファー層２と、膜厚１０μｍ、不純物濃度１×１０１６ｃｍ−３のｎ型ドリフト層３と、膜厚０．４μｍ、不純物濃度１×１０１７ｃｍ−３のｎ型電流拡散層４と、膜厚１μｍ、不純物濃度１×１０１７ｃｍ−３のｐ型ベース層５と、膜厚０．５μｍ、不純物濃度１×１０１９ｃｍ−３のｎ＋型ソース層６とを主要層とする積層エピタキシャルウエハ（図１−１）を準備する。その後、マスクであるＴＥＯＳ酸化膜を全面堆積し、フォトリソグラフィ技術によりＢＨＦエッチング液（ふっ酸緩衝液）を用いて図１−２に示すＴＥＯＳパターンにする。その後、ＴＥＯＳ酸化膜をマスクとして、ｎ＋型ソース層６をＲＩＥ法により異方性エッチングして除去してｐ型ベース層５を選択的に露出させる。マスクとしたＴＥＯＳ酸化膜をすべて除去すると、図１−２のパターン状にｎ＋ソース層６が残り、その周辺にｐ型ベース層５が露出することになる。この状態を図１-３に示す。図１−３は図１−２のＣ−Ｃ線における断面図である。この状態で全面にＳｉＣ基板に対してｐ導電型の元素であるＡｌのイオン注入を行う。イオン注入と活性化後のｐ＋領域５−１の不純物濃度は１×１０１８ｃｍ−３であって、このｐ＋領域の深さは０．３μｍである。この状態を、前記同様のＣ−Ｃ線における断面図として図１−４に示す。 An n-type 4H—SiC substrate 1 having a thickness of about 400 μm and an impurity concentration of 1 × 10 18 cm −3 and a low resistance, and sequentially formed on each of these substrates by epitaxial SiC growth, a film thickness of 0.5 μm, an impurity An n + type buffer layer 2 having a concentration of 1 × 10 18 cm −3 , a thickness of 10 μm, an n type drift layer 3 having an impurity concentration of 1 × 10 16 cm −3 , a thickness of 0.4 μm, and an impurity concentration of 1 × 10 17 and n-type current diffusion layer 4 cm -3, film thickness 1 [mu] m, and p-type base layer 5 having an impurity concentration 1 × 10 17 cm -3, film thickness 0.5 [mu] m, n impurity concentration of 1 × 10 19 cm -3 A laminated epitaxial wafer (FIG. 1A) having a + type source layer 6 as a main layer is prepared. Thereafter, a TEOS oxide film as a mask is deposited on the entire surface, and a TEOS pattern shown in FIG. 1-2 is formed by using a BHF etching solution (hydrofluoric acid buffer solution) by a photolithography technique. Thereafter, using the TEOS oxide film as a mask, the n + -type source layer 6 is removed by anisotropic etching by the RIE method to selectively expose the p-type base layer 5. When all of the TEOS oxide film used as a mask is removed, the n + source layer 6 remains in the pattern of FIG. 1-2, and the p-type base layer 5 is exposed in the vicinity thereof. This state is shown in Fig. 1-3. 1-3 is a cross-sectional view taken along the line CC of FIG. 1-2. In this state, ion implantation of Al, which is a p conductivity type element, is performed on the entire surface of the SiC substrate. The impurity concentration of the p + region 5-1 after ion implantation and activation is 1 × 10 18 cm −3 , and the depth of the p + region is 0.3 μm. This state is shown in FIGS. 1-4 as a cross-sectional view taken along the line C-C as described above.

さらに、図２に示すようにｎ＋型ソース層６側の主表面からシリコン酸化膜（ＴＥＯＳ酸化膜）をマスクとして、垂直にＲＩＥ法によりトレンチ７を形成する。前記ＴＥＯＳはＴｅｔｒａ ＥｔｈｙｌＯｘｉｄｅ Ｓｉｌｉｃａｔｅの略。このときトレンチ底部の深さは少なくとも電流拡散層４の下端より深くする（図２）。このときのｎ＋型ソース層６内の表面に形成されるトレンチ７のパターン形状を図３の平面図に示す。次に、このストライプ状トレンチ７が形成されているウエハ主表面側に、ｐ導電型となるＡｌを図４−１の矢印線で示す照射方向からイオン注入する。この図４−１は、図３の平面図中のＡ−Ａで示すトレンチ中心を長手方向に沿ってウエハを切断したときの中央部を省略した部分断面図である。図３に示す表面パターンでトレンチ７が形成された積層エピタキシャルウエハに対して、図４−１の矢印線に示すように、垂直イオン注入およびウエハを±４５°傾けて行う傾斜イオン注入が合わせて３回実施される。図４−１では便宜上、ウエハを傾けないで、イオン注入方向を示す矢印線を傾ける描画により、前記傾斜イオン注入を示した。この図４−１におけるトレンチ底部で、段差によって低くなっている部分は、図３において、ｎ＋ソース層６の切り欠き領域６−１内のトレンチ部分に相当する。図４−２はこの切り欠き領域６−１内にトレンチ７の端部が形成されていることを示す斜視図である。このときのウエハを傾ける方向はストライプトレンチの長手方向に直角方向を回転軸として傾ける方向である。そうすることによって、トレンチパターン部以外はＴＥＯＳ酸化膜でマスクされてイオン注入されず、かつ、側壁の大部分を占める、長辺方向の側壁（そのうち、特にはチャネル（反転層）が形成される領域）にもイオン注入されず、前述のように、トレンチ両端の短辺の側壁とトレンチ底部ｐ＋層１３およびｎ＋ソース層６の切り欠き領域６−１内のトレンチ端部側壁７−１（太線で示す）にのみにイオン注入が行われる。その結果、ゲートしきい値電圧の変動や移動度への影響がほとんどなくなる。図３のストライプ状トレンチの端部にイオン注入されるので、この部分により、トレンチ底部ｐ＋層１３と表面のｐ＋領域５−１とが電気的に接続される。すなわち、このイオン注入によりトレンチ端部に形成されるｐ＋領域１２により、トレンチ底部のｐ＋ＳｉＣ層１３と主表面側のｐベース領域５およびソース電極９との電気的な接続が可能になり、従来のようにトレンチ底部ｐ＋ＳｉＣ層１３と電気的に接続される電極膜を新たに設ける必要がなくなる。この後、高温アニールを行って注入Ａｌを電気的に活性化する。その後、ゲート酸化膜８、ソース電極９、ドレイン電極１０、ゲート電極１１を順次形成して、ＵＭＯＳＦＥＴは完成する（図５）。
[実施例１]
実施例１にかかるＳｉＣ半導体装置の製造方法は、図２のトレンチ形成工程までは、参考例１と同様である。続くＡｌのイオン注入はＳｉＣウエハの主表面に対する垂直方向からの照射だけで、ＳｉＣウエハを傾けて行う傾斜イオン注入は行わない（図６）。図６は図７に示す平面図中のＢ−Ｂにおけるトレンチの中を長手方向に沿って切断した断面図である。この垂直入射イオン注入により、トレンチの底部にのみ、ｐ＋ＳｉＣ層１３が形成される。その後、ＳｉＣウエハの表面側の全面にＴａ金属をスパッタした後、Ｃ３Ｈ８中でアニールすることにより形成されるＴａＣ層１４をウエハ全面に形成する。さらに、フォトリソグラフィーとＢＨＦウェットエッチングにより図７のように、トレンチの表面パターン７の端部に対応する部分１６のＴａＣ層１４を窓開けして除去し、トレンチ底部ｐ＋ＳｉＣ層１３を露出させる。続いてｐ＋エピタキシャルＳｉＣ成長によりｐ＋エピタキシャルＳｉＣ領域１５を形成すると、ＴａＣ層１４上にはＳｉＣはエピタキシャル成長しないので、図８に示すように、トレンチ端部における部分１６のトレンチ底部とトレンチの側壁において選択成長されたｐ＋エピタキシャルＳｉＣ領域１５が形成され、この選択成長ｐ＋エピタキシャルＳｉＣ領域１５により、トレンチ底部のｐ＋層１３とｐベース領域５とを電気的に接続することができる。この後、参考例１と同様に高温アニールを行って注入Ａｌを電気的に活性化する。さらに、ゲート酸化膜８、ソース電極９、ドレイン電極１０、ゲート電極１１を順次形成して、ＵＭＯＳＦＥＴは完成する（図５）。 Further, as shown in FIG. 2, trenches 7 are formed vertically from the main surface on the n + -type source layer 6 side by a RIE method using a silicon oxide film (TEOS oxide film) as a mask. TEOS is an abbreviation for Tetra Ethyl Oxide Silicate. At this time, the depth of the bottom of the trench is made deeper than at least the lower end of the current diffusion layer 4 (FIG. 2). The pattern shape of the trench 7 formed on the surface in the n + type source layer 6 at this time is shown in the plan view of FIG. Next, Al of p conductivity type is ion-implanted into the wafer main surface side where the stripe-shaped trench 7 is formed from the irradiation direction indicated by the arrow line in FIG. FIG. 4A is a partial cross-sectional view in which the central portion when the wafer is cut along the longitudinal direction at the trench center indicated by AA in the plan view of FIG. 3 is omitted. As shown by the arrow line in FIG. 4A, vertical ion implantation and inclined ion implantation performed by tilting the wafer by ± 45 ° are combined with the stacked epitaxial wafer having the trench 7 formed in the surface pattern shown in FIG. Performed 3 times. In FIG. 4A, for the sake of convenience, the tilted ion implantation is shown by drawing in which the arrow line indicating the ion implantation direction is tilted without tilting the wafer. The portion of the trench bottom in FIG. 4A that is lowered due to the step corresponds to the trench portion in the notch region 6-1 of the n + source layer 6 in FIG. FIG. 4B is a perspective view showing that the end of the trench 7 is formed in the notch region 6-1. The direction in which the wafer is tilted at this time is a direction in which the direction perpendicular to the longitudinal direction of the stripe trench is tilted. By doing so, other than the trench pattern portion is masked with the TEOS oxide film and is not ion-implanted, and a side wall in the long side direction (particularly, a channel (inversion layer) is formed which occupies most of the side wall. As described above, the trench side wall 7-1 in the notched region 6-1 in the notch region 6-1 in the trench bottom p + layer 13 and the n + source layer 6 is used. Ion implantation is performed only (indicated by bold lines). As a result, there is almost no influence on the gate threshold voltage fluctuation or mobility. Since ions are implanted into the end of the stripe-shaped trench in FIG. 3, the trench bottom p + layer 13 and the surface p + region 5-1 are electrically connected by this portion. In other words, the p + region 12 formed at the end of the trench by this ion implantation enables electrical connection between the p + SiC layer 13 at the bottom of the trench and the p base region 5 and the source electrode 9 on the main surface side. Thus, there is no need to newly provide an electrode film electrically connected to the trench bottom p + SiC layer 13 as in the prior art. Thereafter, high temperature annealing is performed to electrically activate the implanted Al. Thereafter, the gate oxide film 8, the source electrode 9, the drain electrode 10, and the gate electrode 11 are sequentially formed to complete the UMOSFET (FIG. 5).
[Example 1]
Method for manufacturing a SiC semiconductor device according to the first embodiment, until the trench formation step of Figure 2 is similar to that in Reference Example 1. The subsequent ion implantation of Al is only performed from the direction perpendicular to the main surface of the SiC wafer, and the tilted ion implantation performed by tilting the SiC wafer is not performed (FIG. 6). FIG. 6 is a cross-sectional view taken along the longitudinal direction in the trench at BB in the plan view shown in FIG. By this normal incidence ion implantation, the p + SiC layer 13 is formed only at the bottom of the trench. Thereafter, Ta metal is sputtered on the entire surface of the SiC wafer and annealed in C 3 H 8 to form a TaC layer 14 formed on the entire surface of the wafer. Further, the TaC layer 14 in the portion 16 corresponding to the end portion of the surface pattern 7 of the trench is removed by opening a window by photolithography and BHF wet etching to expose the trench bottom p + SiC layer 13 as shown in FIG. . When subsequently forming the p + epitaxial SiC region 15 by p + epitaxial SiC growth, since on TaC layer 14 SiC is not epitaxially grown, as shown in FIG. 8, the trench bottom and sidewalls of the trench portion 16 at the trench end The p + epitaxial SiC region 15 selectively grown in step (b) is formed, and the selective growth p + epitaxial SiC region 15 can electrically connect the p + layer 13 and the p base region 5 at the bottom of the trench. Thereafter, high-temperature annealing is performed as in Reference Example 1 to electrically activate the implanted Al. Further, the gate oxide film 8, the source electrode 9, the drain electrode 10, and the gate electrode 11 are sequentially formed to complete the UMOSFET (FIG. 5).

以上、参考例１と実施例１に説明したような構造のＳｉＣ−ＵＭＯＳＦＥＴとすることにより、トレンチ底部のｐ＋層に電気的に接続される電極膜パッドを新たに作る必要がなくなるので、オン抵抗を低減できる。この効果は、電流容量が小さく、電極面積が小さくなるほど顕著になる。たとえば、電流容量が１００Ａ（アンペア）のＳｉＣ半導体装置では、オン抵抗の低減率が５％であったものが、電流容量が１０Ａ（アンペア）のＳｉＣ半導体装置では２０％ものオン抵抗の低減を実現できた。また、ワイヤーボンディングを行う場所を１デバイスあたり３箇所から２箇所に減らすことができた。 As described above, the SiC-UMOSFET having the structure as described in Reference Example 1 and Example 1 eliminates the need to make a new electrode film pad electrically connected to the p + layer at the bottom of the trench. Resistance can be reduced. This effect becomes more prominent as the current capacity is smaller and the electrode area is smaller. For example, in a SiC semiconductor device having a current capacity of 100 A (ampere), the on-resistance reduction rate was 5%, but in a SiC semiconductor device having a current capacity of 10 A (ampere), a reduction in on-resistance of 20% was realized. did it. In addition, the number of places where wire bonding is performed can be reduced from three places to two places per device.

１ ｎ型ＳｉＣ半導体基板
２ ｎ＋型バッファー層
３ ｎ型ドリフト層３
４ ｎ型電流拡散層
５ ｐ型ベース層
６ ｎ＋型ソース層
７ トレンチ
８ ゲート酸化膜
９ ソース電極
１０ ドレイン電極
１１ ゲート電極
１２ ｐ＋ＳｉＣ領域（ｐ＋領域）
１３ トレンチ底部ｐ＋層
１４ ＴａＣ層
１５ ｐ＋エピタキシャルＳｉＣ領域。 1 n-type SiC semiconductor substrate 2 n + -type buffer layer 3 n-type drift layer 3
4 n-type current diffusion layer 5 p-type base layer 6 n + -type source layer 7 trench 8 gate oxide film 9 source electrode 10 drain electrode 11 gate electrode 12 p + SiC region (p + region)
13 trench bottom p + layer 14 TaC layer 15 p + epitaxial SiC region.

Claims (1)

第一導電型半導体基板上に第一導電型ドリフト層、第二導電型ベース層、第一導電型ソース層とこの順に積層され、該第一導電型ソース層の表面から前記ドリフト層に達するストライプ状トレンチと、このストライプ状トレンチの側壁及び底面にはゲート酸化膜を介してゲート電極を有し、該トレンチ底部のゲート酸化膜下にはトレンチ底部と一致した領域の第二導電型層を備える炭化珪素からなるトレンチＭＯＳ型炭化珪素半導体装置であって、選択マスクとして用いるＴａＣ膜を半導体基板表面側の全面に形成後、ストライプ状トレンチの長手方向端部の前記ＴａＣ膜を窓開け除去し、該窓開け除去した部分に選択的にエピタキシャルＳｉＣ領域を成長させ前記トレンチ底部の第二導電型層と前記第二導電型ベース層とを導電接続する第二導電型領域を形成するトレンチＭＯＳ型炭化珪素半導体装置の製造方法。 A first conductivity type drift layer, a second conductivity type base layer, and a first conductivity type source layer are stacked in this order on a first conductivity type semiconductor substrate, and the stripe reaches the drift layer from the surface of the first conductivity type source layer. And a stripe-shaped trench having a gate electrode through a gate oxide film on the side wall and bottom surface of the stripe-shaped trench , and a second conductivity type layer in a region coinciding with the trench bottom is provided below the gate oxide film at the bottom of the trench. A trench MOS type silicon carbide semiconductor device made of silicon carbide, wherein a TaC film used as a selection mask is formed on the entire surface of the semiconductor substrate surface side, and then the TaC film at the longitudinal end of the stripe-shaped trench is opened and removed. An epitaxial SiC region is selectively grown on the portion removed by opening the window to electrically connect the second conductivity type layer at the bottom of the trench and the second conductivity type base layer. Manufacturing method of a trench MOS-type silicon carbide semiconductor device for forming a conductive region.
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