JP2012169433A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 239000007772 electrode material Substances 0.000 claims description 51
- 230000003071 parasitic effect Effects 0.000 abstract description 14
- 239000000463 material Substances 0.000 description 64
- 238000004519 manufacturing process Methods 0.000 description 28
- 238000000034 method Methods 0.000 description 28
- 229910004298 SiO 2 Inorganic materials 0.000 description 23
- 239000010410 layer Substances 0.000 description 16
- 230000008569 process Effects 0.000 description 12
- 239000012535 impurity Substances 0.000 description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 230000001133 acceleration Effects 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 239000002210 silicon-based material Substances 0.000 description 5
- 239000007788 liquid Substances 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 239000000470 constituent Substances 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
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- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
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- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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Abstract
【解決手段】ゲート絶縁膜201を介して形成されたゲート電極202を挟むように形成された、第1導電型のソース領域121及び前記第1導電型とは逆導電型の第2導電型のドレイン領域122と、基板101内において前記ソース領域121と前記ドレイン領域122との間に形成された、第2導電型のチャネル領域123とを備える。そして、前記ゲート絶縁膜201は、前記ソース領域上に位置し、チャネル幅方向に平行な第1のエッジE1と、前記チャネル領域上又は前記ソース領域上に位置し、チャネル幅方向に平行な第2のエッジE2とを有し、第1の膜厚を有する第1の絶縁膜部分を有する。さらに、前記ゲート絶縁膜201は、前記第1の絶縁膜部分に対して前記ドレイン領域側に位置し、前記第1の膜厚よりも厚い第2の膜厚を有する第2の絶縁膜部分を有する。
【選択図】図1
Description
図1は、第1実施形態の半導体装置の構成を示す側方断面図である。
次に、図1を再び参照して、第1実施形態の半導体装置の効果について説明する。
次に、図3〜図5を参照し、第1実施形態の半導体装置の製造方法を説明する。図3〜図5は、第1実施形態の半導体装置の製造方法を示す側方断面図である。
図6は、第2実施形態の半導体装置の構成を示す側方断面図である。
次に、図6を再び参照して、第2実施形態の半導体装置の効果について説明する。
次に、図8〜図10を参照し、第2実施形態の半導体装置の製造方法を説明する。図8〜図10は、第2実施形態の半導体装置の製造方法を示す側方断面図である。
図11は、第3実施形態の半導体装置の構成を示す側方断面図である。
次に、図12〜図15を参照し、第3実施形態の半導体装置の製造方法を説明する。図12〜図15は、第3実施形態の半導体装置の製造方法を示す側方断面図である。
図16は、第4実施形態の半導体装置の構成を示す側方断面図である。
次に、図17〜図19を参照し、第4実施形態の半導体装置の製造方法を説明する。図17〜図19は、第4実施形態の半導体装置の製造方法を示す側方断面図である。
121:ソース領域、122:ドレイン領域、123:チャネル領域、
124:ポケット領域、131:シリサイド層、
201:ゲート絶縁膜、202:ゲート電極、203:側壁絶縁膜、
211:層間絶縁膜、221:第1のゲート絶縁膜、
222:第2のゲート絶縁膜、223:第3のゲート絶縁膜、
301:ゲート絶縁膜材料、302:第1のゲート電極材、
303:ハードマスク材、304:第2のゲート電極材、305:側壁絶縁膜材料、
311:レジスト膜、312:レジスト膜、
401:第1のゲート絶縁膜材料、402:第2のゲート絶縁膜材料、
403:ゲート電極材、404:ハードマスク材、405:側壁絶縁膜材料、
411:レジスト膜、412:レジスト膜
Claims (5)
- 基板と、
前記基板上にゲート絶縁膜を介して形成されたゲート電極と、
前記基板内において前記ゲート電極を挟むように形成された、第1導電型のソース領域及び前記第1導電型とは逆導電型の第2導電型のドレイン領域と、
前記基板内において前記ソース領域と前記ドレイン領域との間に形成された、前記第2導電型のチャネル領域とを備え、
前記ゲート絶縁膜は、
前記ソース領域上に位置し、チャネル幅方向に平行な第1のエッジと、前記チャネル領域上又は前記ソース領域上に位置し、チャネル幅方向に平行な第2のエッジとを有し、第1の膜厚を有する第1の絶縁膜部分と、
前記第1の絶縁膜部分に対して前記ドレイン領域側に位置し、前記第1の膜厚よりも厚い第2の膜厚を有する第2の絶縁膜部分と、
を有する半導体装置。 - 前記ゲート電極は、
前記第2の絶縁膜部分上に形成された第1の電極部分と、
前記第1の絶縁膜部分上に形成された第2の電極部分と、
を有する請求項1に記載の半導体装置。 - 前記第2の絶縁膜部分のチャネル幅方向に平行なエッジは、前記第1の電極部分のチャネル幅方向に平行な側面に対し、前記第1の電極部分の内側方向に後退しており、
前記第2の電極部分の一部は、前記第2の絶縁膜部分の前記エッジが前記第1の電極部分の前記側面に対して後退した部分に入り込んでいる請求項2に記載の半導体装置。 - 前記ゲート電極は、前記第1の絶縁膜部分上と前記第2の絶縁膜部分上に同一のゲート電極材が形成された構造を有する請求項1に記載の半導体装置。
- さらに、前記ゲート電極下の前記ソース領域内に形成された、前記第2導電型のポケット領域を備える請求項1から4のいずれか1項に記載の半導体装置。
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JP2011028759A JP5404671B2 (ja) | 2011-02-14 | 2011-02-14 | 半導体装置 |
US13/355,901 US8735999B2 (en) | 2011-02-14 | 2012-01-23 | Semiconductor device |
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JP2011028759A JP5404671B2 (ja) | 2011-02-14 | 2011-02-14 | 半導体装置 |
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JP2012169433A true JP2012169433A (ja) | 2012-09-06 |
JP5404671B2 JP5404671B2 (ja) | 2014-02-05 |
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JP (1) | JP5404671B2 (ja) |
Cited By (2)
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JP2014146647A (ja) * | 2013-01-28 | 2014-08-14 | Toshiba Corp | 半導体装置 |
WO2022085304A1 (ja) * | 2020-10-22 | 2022-04-28 | ソニーセミコンダクタソリューションズ株式会社 | 固体撮像装置及びその製造方法、並びに電子機器 |
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JP5784652B2 (ja) | 2013-02-14 | 2015-09-24 | 株式会社東芝 | 半導体装置 |
WO2017004409A1 (en) * | 2015-07-02 | 2017-01-05 | The Regents Of The University Of California | Gate-induced source tunneling field-effect transistor |
WO2017079928A1 (zh) * | 2015-11-11 | 2017-05-18 | 华为技术有限公司 | 隧穿场效应晶体管及其制备方法 |
CN105390550B (zh) * | 2015-12-04 | 2018-02-06 | 上海斐讯数据通信技术有限公司 | 复合多晶硅栅mos器件及其制造方法 |
EP3179514B1 (en) * | 2015-12-11 | 2024-01-24 | IMEC vzw | Transistor device with reduced hot carrier injection effect |
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US20180138307A1 (en) * | 2016-11-17 | 2018-05-17 | Globalfoundries Inc. | Tunnel finfet with self-aligned gate |
WO2019000416A1 (zh) * | 2017-06-30 | 2019-01-03 | 华为技术有限公司 | 一种隧穿场效应晶体管及其制备方法 |
US10141398B1 (en) * | 2017-12-18 | 2018-11-27 | United Microelectronics Corp. | High voltage MOS structure and its manufacturing method |
WO2019132887A1 (en) * | 2017-12-27 | 2019-07-04 | Intel Corporation | Reduced electric field by thickening dielectric on the drain side |
US11195754B2 (en) | 2018-10-09 | 2021-12-07 | International Business Machines Corporation | Transistor with reduced gate resistance and improved process margin of forming self-aligned contact |
US11088241B2 (en) | 2019-01-16 | 2021-08-10 | Stmicroelectronics (Rousset) Sas | Pin diode including a conductive layer, and fabrication process |
FR3091786B1 (fr) * | 2019-01-16 | 2021-03-19 | St Microelectronics Rousset | Diode de type PIN comportant une couche conductrice, et procédé de fabrication |
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JPH05190847A (ja) * | 1992-01-08 | 1993-07-30 | Kawasaki Steel Corp | Mos型半導体装置 |
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JP2006147805A (ja) * | 2004-11-18 | 2006-06-08 | Matsushita Electric Ind Co Ltd | 半導体装置 |
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JP2011100986A (ja) * | 2009-10-06 | 2011-05-19 | Imec | 改良された閾値下の振れを有するトンネル電界効果トランジスタ |
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JPH07263677A (ja) | 1994-03-18 | 1995-10-13 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
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2011
- 2011-02-14 JP JP2011028759A patent/JP5404671B2/ja not_active Expired - Fee Related
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2012
- 2012-01-23 US US13/355,901 patent/US8735999B2/en not_active Expired - Fee Related
Patent Citations (5)
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JPH05190847A (ja) * | 1992-01-08 | 1993-07-30 | Kawasaki Steel Corp | Mos型半導体装置 |
JPH06196643A (ja) * | 1992-12-22 | 1994-07-15 | Victor Co Of Japan Ltd | 半導体装置 |
JP2006147805A (ja) * | 2004-11-18 | 2006-06-08 | Matsushita Electric Ind Co Ltd | 半導体装置 |
US20070178650A1 (en) * | 2006-02-01 | 2007-08-02 | International Business Machines Corporation | Heterojunction tunneling field effect transistors, and methods for fabricating the same |
JP2011100986A (ja) * | 2009-10-06 | 2011-05-19 | Imec | 改良された閾値下の振れを有するトンネル電界効果トランジスタ |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014146647A (ja) * | 2013-01-28 | 2014-08-14 | Toshiba Corp | 半導体装置 |
US9324798B2 (en) | 2013-01-28 | 2016-04-26 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
WO2022085304A1 (ja) * | 2020-10-22 | 2022-04-28 | ソニーセミコンダクタソリューションズ株式会社 | 固体撮像装置及びその製造方法、並びに電子機器 |
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