JP2012129399A - Surface-mount optical semiconductor device - Google Patents

Surface-mount optical semiconductor device Download PDF

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JP2012129399A
JP2012129399A JP2010280503A JP2010280503A JP2012129399A JP 2012129399 A JP2012129399 A JP 2012129399A JP 2010280503 A JP2010280503 A JP 2010280503A JP 2010280503 A JP2010280503 A JP 2010280503A JP 2012129399 A JP2012129399 A JP 2012129399A
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optical semiconductor
bare chip
resin
region
strip
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Hidenori Kodama
英範 兒玉
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Stanley Electric Co Ltd
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Stanley Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • Light Receiving Elements (AREA)

Abstract

PROBLEM TO BE SOLVED: To form an identification mark of good visibility on a surface-mount optical semiconductor device.SOLUTION: In the surface-mount optical semiconductor device, an optical semiconductor chip 1 is mounted on a circuit board 2, and a sealing resin part 3 where the surface of the board is sealed with a sealing resin, produced by mixing a transmittance lowering material to a transparent resin, is provided. A strip-like pattern 5 is formed as a polarity identification mark by a resist or silk printing plate along any side of the board surface where an electrode terminal is not formed while avoiding the optical semiconductor mounting region. A strip-like area 7a where the strip-like pattern is visible is created by cutting an area of the sealing resin part above the strip-like pattern thinly.

Description

本発明は、電極を施した基板上に光半導体ベアチップを搭載し、ダイボンドおよびワイヤボンド等により前記電極と接続を行い、前記ベアチップおよび前記接続部周辺保護のために透光性樹脂で封止することにより形成された表面実装型光半導体装置に関するものである。   In the present invention, an optical semiconductor bare chip is mounted on a substrate provided with an electrode, connected to the electrode by die bonding, wire bonding, or the like, and sealed with a translucent resin for protecting the periphery of the bare chip and the connecting portion. The present invention relates to a surface-mount optical semiconductor device formed by the above method.

この種の表面実装型光半導体装置光は従来から、当業者間においてチップ型またはチップタイプと呼称されているものの一種であり、プリント回路基板等に表面実装されるものである。   This type of surface-mounted optical semiconductor device light is a kind of what is conventionally referred to as a chip type or chip type by those skilled in the art, and is surface-mounted on a printed circuit board or the like.

前記表面実装型光半導体装置で、現在よく用いられているパッケージの形態は以下の二種類である。
図１５は一つめの形態である表面実装型光半導体装置１５０を示したもので、一対の対向する二辺縁部には表裏両面に敷設され、側面を介して導通される電極端子パターン部１５３ａ、１５３ｂが形成され、表面の中央部には光半導体ベアチップ実装領域と光半導体ベアチップ１５２が接続され前記電極端子パターン部１５３ａ、１５３ｂを繋ぐ二つの配線パターンが形成された四角形の基板と、前記基板の上面中央部の光半導体ベアチップ実装領域に実装された光半導体ベアチップ、及び光半導体ベアチップ表面と前記基板上面の光半導体ベアチップ実装領域周辺部を覆うように封止樹脂部１５４を備えている。 In the surface mount optical semiconductor device, there are the following two types of packages that are often used at present.
FIG. 15 shows a surface-mount type optical semiconductor device 150 which is a first form. An electrode terminal pattern portion 153a which is laid on both front and back surfaces on a pair of two opposite edge portions and is conducted through side surfaces. , 153b is formed, and a rectangular substrate on which an optical semiconductor bare chip mounting region and an optical semiconductor bare chip 152 are connected to each other at the center of the surface and two wiring patterns are formed to connect the electrode terminal pattern portions 153a and 153b, and the substrate An optical semiconductor bare chip mounted on the optical semiconductor bare chip mounting region at the center of the upper surface of the optical semiconductor, and a sealing resin portion 154 so as to cover the surface of the optical semiconductor bare chip and the peripheral portion of the optical semiconductor bare chip mounting region on the upper surface of the substrate.

一般的に、光半導体ベアチップ１５２がＬＥＤベアチップのときに良く用いられるパッケージである。近年では、このパッケージ形態により、青色ＬＥＤと蛍光体を混和させ封止樹脂部を組合せて白色発光させるものや、ＬＥＤベアチップを複数個搭載したものや、封止樹脂を可視光カット樹脂として、ＬＥＤベアチップの代わりに受光ベアチップを搭載したものも製品化されている。   Generally, this is a package often used when the optical semiconductor bare chip 152 is an LED bare chip. In recent years, depending on this package form, blue LEDs and phosphors are mixed and the sealing resin portion is combined to emit white light, a plurality of LED bare chips are mounted, and the sealing resin is a visible light cut resin. Products with light-receiving bare chips instead of bare chips have been commercialized.

図１６は二つめの形態である表面実装型光半導体装置１６０を示したもので、基板１６１の裏面部には電極端子パターン１６３ａ、１６３ｂが敷設され、基板１６１の表面の中央部には光半導体ベアチップ実装領域と光半導体ベアチップ１６５に接続され電極数に応じた数の配線パターンが形成され、前記配線パターンは前記電極端子パターンとスルーホールを介して導通されており、四角形の基板１６１と、前記基板の上面中央部の光半導体ベアチップ実装領域に実装された光半導体ベアチップ１６５、及び光半導体ベアチップ表面と前記基板表面の前面を覆うように形成された封止樹脂部１６４を備えている。   FIG. 16 shows a surface-mount type optical semiconductor device 160 which is the second form. Electrode terminal patterns 163a and 163b are laid on the back surface of the substrate 161, and an optical semiconductor is formed at the center of the surface of the substrate 161. A number of wiring patterns corresponding to the number of electrodes connected to the bare chip mounting region and the optical semiconductor bare chip 165 are formed, and the wiring patterns are electrically connected to the electrode terminal patterns through through holes, and the rectangular substrate 161, An optical semiconductor bare chip 165 mounted in the optical semiconductor bare chip mounting region at the center of the upper surface of the substrate, and a sealing resin portion 164 formed so as to cover the surface of the optical semiconductor bare chip and the front surface of the substrate surface are provided.

このパッケージは多面付けされた基板上一面に樹脂を塗布し、硬化後に回路サイズに応じた位置で切断するという方法で製造され、封止型を使用しない。また電極端子パターンは裏面パターンのみで形成されるため、電極の数が二つ以上であっても対応できる。
従って、近年では、様々な受光面サイズへの対応が求められる光センサー用途に、封止樹脂を可視光カット樹脂として、受光ベアチップや受光ＩＣチップを搭載した光半導体装置等に用いられる様になってきている。 This package is manufactured by a method in which a resin is applied to one side of a multi-sided substrate and cut at a position corresponding to the circuit size after curing, and does not use a sealing mold. Further, since the electrode terminal pattern is formed only by the back surface pattern, it can be handled even when the number of electrodes is two or more.
Therefore, in recent years, it has come to be used in optical semiconductor devices equipped with a light-receiving bare chip or a light-receiving IC chip by using a sealing resin as a visible light cut resin for optical sensor applications that require various light-receiving surface sizes. It is coming.

ところで前記表面実装型光半導体装置１５０および１６０をプリント回路基板などに組付けるとき、あるいは検査するときに極性の識別が必要である。このためこれら表面実装型光半導体装置では極性識別マークが施こされている。   By the way, when the surface-mount type optical semiconductor devices 150 and 160 are assembled on a printed circuit board or the like or inspected, it is necessary to identify the polarity. For this reason, these surface mount optical semiconductor devices are provided with a polarity identification mark.

例えば、文献１（実開昭62-010456）は、封止樹脂の内部あるいは外部に極性識別マークが施こすものである。   For example, Document 1 (Japanese Utility Model Laid-Open No. 62-010456) applies a polarity identification mark to the inside or the outside of the sealing resin.

また文献２（特開2007123704）は樹脂封止部の外形を正負電極方向に沿って非対称形状とするものである。   Further, Document 2 (Japanese Patent Laid-Open No. 2007123704) makes the outer shape of the resin sealing portion an asymmetric shape along the positive and negative electrode directions.

また、今日、一般的に使用されているもので、基板部裏面に極性識別マークが設けるようにしているものがある。例えば、図１７は前記基板部裏面を示すものであり、表面から導通している裏面電極１７０ａ、１７０ｂの間にレジストもしくはシルクによる極性識別マーク１７１が形成されている。図１７の例では極性識別マークが矢尻形状となっていて裏面電極１７０ａ、１７０ｂの位置が識別できるようになっている。   In addition, there is one that is generally used today, and a polarity identification mark is provided on the back surface of the substrate portion. For example, FIG. 17 shows the back surface of the substrate portion, and a polarity identification mark 171 made of resist or silk is formed between the back surface electrodes 170a and 170b that are conductive from the front surface. In the example of FIG. 17, the polarity identification mark has an arrowhead shape so that the positions of the back electrodes 170a and 170b can be identified.

また文献３は、前記表面実装型光半導体装置１５０の構造例のみの適用に限られるが、図１８に示すように、基板部１８４上面の正負端子部１８１ａ、１８１ｂに平行するＬＥＤベアチップ１８３とその接続部周辺を覆う樹脂封止部１８２の基板部１８４と接する接合線９６を含むようにハンダレジスト膜１８０ａ、１８０ｂが設けられており、この前記ハンダレジスト膜１８０ａ、１８０ｂの色を夫々異なる色とすることにより極性の識別を行うものとしている。   Reference 3 is limited to the application of only the structural example of the surface-mounted optical semiconductor device 150. As shown in FIG. 18, the LED bare chip 183 parallel to the positive and negative terminal portions 181a and 181b on the upper surface of the substrate portion 184 and its Solder resist films 180a and 180b are provided so as to include a bonding line 96 in contact with the substrate portion 184 of the resin sealing portion 182 covering the periphery of the connection portion, and the colors of the solder resist films 180a and 180b are different from each other. By doing so, the polarity is identified.

また文献４も、前記表面実装型光半導体装置１５０の構造例のみの適用に限られるが、図１９に示すように、電極１９０ａ、１９０ｂのいずれか一方の基板部１９３の表面側で封止樹脂体１９２より外側に位置する電極端子パターン領域に電極端子パターンを中抜きすることにより極性識別マーク１９１を形成するものである。   Reference 4 is also limited to the application of the structural example of the surface-mounted optical semiconductor device 150, but as shown in FIG. 19, a sealing resin is formed on the surface side of one of the substrates 193 of the electrodes 190a and 190b. The polarity identification mark 191 is formed by hollowing out the electrode terminal pattern in the electrode terminal pattern region located outside the body 192.

実開昭６２−０１０４５６号公報Japanese Utility Model Publication No. 62-010456 特開２００７−１２３７０４号公報JP 2007-123704 A 特開平８−３３０６３７号公報JP-A-8-330637 特開２００８−２５８４５５号公報JP 2008-258455 A

しかしながら、文献１の極性識別マークの場合、樹脂封止領域外に電極パターン以外のスペースが必要となる。また基板表面の全面が封止樹脂で覆われた前記表面実装型光半導体装置１６０のパッケージ形態の場合、封止樹脂領域内部に極性識別マークを設けることになるが、封止樹脂が例えば、透明樹脂に顔料や染料や拡散材などの透過率低下部材が混和されている場合や可視光カット樹脂が使用されている場合には、極性識別マークの視認は困難になってしまう。   However, in the case of the polarity identification mark of Document 1, a space other than the electrode pattern is required outside the resin sealing region. In the case of the package form of the surface mount optical semiconductor device 160 in which the entire surface of the substrate is covered with the sealing resin, a polarity identification mark is provided inside the sealing resin region. When the resin is mixed with a transmittance reducing member such as a pigment, dye, or diffusing material, or when a visible light cut resin is used, it is difficult to visually recognize the polarity identification mark.

また文献２の極性識別マークについては、近年の表面実装型光半導体装置の小型化の傾向に伴って、樹脂封止体の一部に形状変化を持たせたのみでは容易に極性識別マークを視認できないという問題も生じてきた。また形状変化箇所を装置サイズに対して大きくすると配光特性に悪影響という懸念もある。
また前記表面実装型光半導体装置１６０のパッケージ形態で用いられる製法では採用困難である。 As for the polarity identification mark of Document 2, the polarity identification mark can be easily visually recognized only by giving a shape change to a part of the resin sealing body in accordance with the recent trend toward downsizing of the surface mount optical semiconductor device. The problem of being unable to do so has also arisen. Further, there is a concern that the light distribution characteristic is adversely affected if the shape change portion is increased with respect to the apparatus size.
In addition, it is difficult to adopt the manufacturing method used in the package form of the surface mount optical semiconductor device 160.

極性識別マークを基板部裏面に形成した場合は、基板アセンブリ段階でプリント基板に実装後に極性識別マークが視認できなくなるという問題がある。   When the polarity identification mark is formed on the back surface of the substrate portion, there is a problem that the polarity identification mark cannot be visually recognized after being mounted on the printed circuit board at the substrate assembly stage.

また文献３の極性識別マークは、近年の表面実装型光半導体装置の小型化の傾向に伴って、基板部自体が小型となり電極パターン領域に充分なスペースが確保できなくなってきているため、封止樹脂が例えば、透明樹脂に顔料や染料や拡散材などの透過率低下部材が混和されている場合、外部からの目視では極性識別マークのレジストパターンが樹脂封止体の外部にはみ出す極小部分しか確認できず、正負極の確認が困難となっている。   In addition, the polarity identification mark of Document 3 is sealed because the substrate portion itself has become smaller and sufficient space cannot be secured in the electrode pattern region in accordance with the recent trend toward miniaturization of the surface-mounted optical semiconductor device. For example, if the resin is mixed with a transparent resin with a transmittance-reducing member such as pigment, dye, or diffusing material, only the smallest part where the resist pattern of the polarity identification mark protrudes to the outside of the resin encapsulant is visually confirmed from the outside. It is not possible to confirm the positive and negative electrodes.

また文献４の極性識別マークにおいても、基板部自体が小型となり電極パターン領域も小さくなってきているため、極性識別マークを中抜きで入れるようなスペースが確保できなくなってきている。仮に極性識別マークを設けたとしても、視認が困難なほど極小になってしまう。
また前記表面実装型光半導体装置１６０のパッケージ形態では基板表面部に電極パターン領域が配置されていない為、採用すらできない。 Also in the polarity identification mark of Document 4, since the substrate portion itself is small and the electrode pattern area is also small, it is impossible to secure a space for inserting the polarity identification mark. Even if the polarity identification mark is provided, it becomes so small that the visual recognition is difficult.
Further, in the package form of the surface-mount type optical semiconductor device 160, the electrode pattern region is not arranged on the surface portion of the substrate.

さらに文献３および４の極性識別マークに共通して、面実装型光半導体装置の小型化とともに薄型化も求められており、それに伴って基板部自体も薄型化の傾向があり、０．１〜０．２mm程の基板を用いたものが一般化した状況である。このようなものをリフローはんだプロセスではんだ付けすると、前記基板上面の電極パターン領域まではんだが這い上がってくるのが通常の現象であり、その場合、クリームはんだの残留フラックスの付着により、極性識別マークを視認できないものとしてしまう。   Further, in common with the polarity identification marks of Documents 3 and 4, there is a demand for a reduction in thickness and thickness of the surface-mount type optical semiconductor device, and accordingly, the substrate portion itself tends to be reduced in thickness. This is a generalized situation using a substrate of about 0.2 mm. When such a thing is soldered by a reflow soldering process, it is a normal phenomenon that the solder crawls up to the electrode pattern area on the upper surface of the substrate. Will not be visible.

そこで、本発明は、上記した特許文献の問題点に鑑み、極性識別マーク形成のために樹脂封止金型や治具を複雑にせず、外側の電極部スペースを極小化でき、且つプリント基板等へ実装後も表面から識別できる極性識別マークを備えた表面実装型半導体装置およびその製造方法を提供とすることを目的とする。   Therefore, in view of the problems of the above-described patent documents, the present invention does not complicate a resin sealing mold and jig for forming a polarity identification mark, can minimize the outer electrode portion space, and can be used for a printed circuit board or the like. It is an object of the present invention to provide a surface-mount type semiconductor device having a polarity identification mark that can be identified from the surface even after being mounted on the surface, and a method for manufacturing the same.

本発明は、上記した課題を解決するためになされたもので、請求項１の表面実装型光半導体装置は、前記表面実装型光半導体装置１５０の形態のパッケージを対象とするもので、
一対の対向する二辺縁部の各々には表裏両面に敷設され側面を介して導通される少なくとも一つ以上の電極端子パターンと、表面中央部の光半導体ベアチップ実装領域で光半導体ベアチップに接続される複数のボンディングパッドと、前記ボンディングパッドと前記電極端子パターンの各々を繋ぐ複数の配線パターンが形成された四角形の基板と、
前記光半導体ベアチップ実装領域に実装された光半導体ベアチップと、
前記光半導体ベアチップと前記光半導体ベアチップ実装領域周辺部および前記配線パターンとを覆う樹脂封止部を備えた表面実装型光半導体装置において、
前記基板の表面には光半導体ベアチップ実装領域を避けて、電極端子パターン形成されていない二辺のいずれかに沿うように、レジストもしくはシルク版による短冊状パターンが形成され
前記封止樹脂部は透明樹脂に透過率低下部材が混和されており、
さらに、前記封止樹脂部における前記短冊状パターンの上の領域が、半導体ベアチップ実装領域上の領域よりも薄くした帯状に形成され、該帯状領域を通して前記短冊状パターンが視認可能であることを特徴とする。 The present invention has been made to solve the above-described problems, and the surface-mount optical semiconductor device according to claim 1 is intended for a package in the form of the surface-mount optical semiconductor device 150.
At least one electrode terminal pattern that is laid on both the front and back sides and is conducted through the side surfaces on each of a pair of two opposite edges, and is connected to the optical semiconductor bare chip at the optical semiconductor bare chip mounting region at the center of the surface. A plurality of bonding pads, and a rectangular substrate on which a plurality of wiring patterns connecting each of the bonding pads and the electrode terminal patterns are formed,
An optical semiconductor bare chip mounted in the optical semiconductor bare chip mounting region;
In a surface-mounted optical semiconductor device comprising a resin sealing portion that covers the optical semiconductor bare chip, the optical semiconductor bare chip mounting region peripheral portion, and the wiring pattern,
A strip-like pattern is formed on the surface of the substrate by a resist or a silk plate so as to avoid an optical semiconductor bare chip mounting region and along one of the two sides where the electrode terminal pattern is not formed, and the sealing resin portion is transparent A material with reduced transmittance is mixed in the resin,
Furthermore, the region above the strip-shaped pattern in the sealing resin portion is formed in a strip shape thinner than the region on the semiconductor bare chip mounting region, and the strip-shaped pattern is visible through the strip-shaped region. And

また、請求項２の表面実装型光半導体装置は、前記前記表面実装型光半導体装置１６０の形態のパッケージを対象とするもので、
表面中央部の光半導体ベアチップ実装領域で光半導体ベアチップに接続されるボンディングパッドと、裏面部には電極端子パターンと、前記ボンディングパッドと裏面の前記電極端子パターンをスルーホールを介して導通させる配線パターンを複数組形成された四角形の基板と、
前記光半導体ベアチップ実装領域に実装された光半導体ベアチップと、
前記基板の表面の全面を覆う封止樹脂部を備えた表面実装型光半導体装置において
前記基板の表面には光半導体ベアチップ実装領域を避けて、四辺のいずれかに沿うように、レジストもしくはシルク版による短冊状パターンが形成され
前記封止樹脂部は透明樹脂に透過率低下部材が混和されており、
さらに、前記封止樹脂部における前記短冊状パターンの上の領域が、半導体ベアチップ実装領域上の領域よりも薄くした帯状に形成され、該帯状領域を通して前記短冊状パターンが視認可能であることを特徴とする。 The surface mount optical semiconductor device according to claim 2 is intended for a package in the form of the surface mount optical semiconductor device 160.
Bonding pads connected to the optical semiconductor bare chip in the optical semiconductor bare chip mounting area at the center of the front surface, electrode terminal patterns on the back surface, and wiring patterns for conducting the bonding pads and the electrode terminal patterns on the back surface through through holes A plurality of rectangular substrates formed,
An optical semiconductor bare chip mounted in the optical semiconductor bare chip mounting region;
In a surface mount type optical semiconductor device provided with a sealing resin portion covering the entire surface of the substrate, a resist or a silk plate is provided along one of the four sides on the surface of the substrate, avoiding an optical semiconductor bare chip mounting region. A strip-shaped pattern is formed, and the sealing resin portion is mixed with a transparent resin and a transmittance decreasing member,
Furthermore, the region above the strip-shaped pattern in the sealing resin portion is formed in a strip shape thinner than the region on the semiconductor bare chip mounting region, and the strip-shaped pattern is visible through the strip-shaped region. And

また、請求項３の表面実装型光半導体装置は、前記透過率低下部材が蛍光体顔料である場合においても請求項１および２の構成を適用するものである。   The surface-mount type optical semiconductor device of claim 3 applies the configuration of claims 1 and 2 even when the transmittance reducing member is a phosphor pigment.

また、請求項４の表面実装型光半導体装置は、光半導体ベアチップが受光ベアチップの場合に封止樹脂として可視光カット樹脂が用いられることを想定したもので、請求項１および２の構成に関して、前記透過率低下部材が混和された透明樹脂は可視光カット樹脂で、カットオフ波長以下の短波長側に透過率ピークが５％以下のバンドパス波長領域を有しているものであり、
前記短冊状パターンの色または前記基板の表面色のどちらかが前記バンドパス波長領域内のいずれかの波長で示される色が選択されていることを特徴としたものである。 Further, the surface-mounted optical semiconductor device according to claim 4 is based on the assumption that a visible light cut resin is used as a sealing resin when the optical semiconductor bare chip is a light-receiving bare chip. The transparent resin mixed with the transmittance lowering member is a visible light cut resin, and has a bandpass wavelength region having a transmittance peak of 5% or less on the short wavelength side below the cutoff wavelength,
A color in which either the color of the strip-shaped pattern or the surface color of the substrate is indicated by any wavelength within the bandpass wavelength region is selected.

また、請求項５による製造方法は、請求項１乃至４記載の表面実装型光半導体装置に関して、
分割ラインに沿う所定の位置に前記短冊状パターンが形成された請求項１または２における四角形の基板回路パターンが複数個形成された多面付け基板を用意する工程と、
前記多面付け基板に取り数に応じた数の光半導体ベアチップを前記回路基板に実装し、回路と接続するボンディング工程と、
光半導体ベアチップが実装された前記面付け回路基板の光半導体ベアチップ実装面側に透過率低下部材が混和された樹脂を塗布あるいは成形型により注入した後に加熱硬化させて行う樹脂封止工程と、
多面付け基板の分割ラインに重なるように前記短冊状パターンが視認可能となる樹脂厚みですりわり状の溝を削成する溝削成工程と、
前記溝の幅以下の刃幅を持つ切断機で前記溝幅内の分割ラインに沿って、前記回路基板と前記溝底面の樹脂を同時に切断した後に分離する切断・分離工程からなることを特徴とする。 A manufacturing method according to claim 5 relates to the surface-mounted optical semiconductor device according to claims 1 to 4,
A step of preparing a multi-sided substrate in which a plurality of rectangular substrate circuit patterns according to claim 1 or 2 in which the strip pattern is formed at a predetermined position along a dividing line;
A bonding step of mounting a number of optical semiconductor bare chips on the multi-sided substrate according to the number to be mounted on the circuit board and connecting to the circuit;
A resin sealing step that is performed by applying a resin mixed with a transmittance lowering member to the optical semiconductor bare chip mounting surface side of the surface mounted circuit board on which the optical semiconductor bare chip is mounted, or by heat-curing after injecting by a mold;
A groove cutting step of cutting a slot-shaped groove with a resin thickness such that the strip-like pattern is visible so as to overlap the dividing line of the multi-sided substrate;
It comprises a cutting / separating step of separating the circuit board and the resin at the bottom of the groove simultaneously after being cut along a dividing line within the groove width by a cutting machine having a blade width equal to or less than the width of the groove. To do.

本発明によれば、前記表面実装型光半導体装置１５０および前記表面実装型光半導体装置１６０のパッケージ形態の双方において、透明樹脂に染料や顔料や散乱材などの透過率低下部材が混和された封止樹脂部を持つ場合に、基板表面の封止樹脂内に設けられた短冊上の極性識別マークを前記封止樹脂部に設けられた薄肉の帯状領域を通して視認可能としたことで、電極パターン領域に充分なスペースがなくとも極性識別マークを設けることが可能であり、アセンブリ基板へのはんだ付け実装工程後も極性識別マークがはんだのフラックスに埋もれることなく、実装後も確実に認識でき、製品検査時にも、誤組立が行われたものの発見を容易とすることができる。   According to the present invention, in both the surface-mount type optical semiconductor device 150 and the surface-mount type optical semiconductor device 160 package form, a transparent resin is mixed with a transmittance-reducing member such as a dye, pigment, or scattering material. In the case of having a stop resin portion, the polarity identification mark on the strip provided in the sealing resin on the surface of the substrate is made visible through the thin strip-like region provided in the sealing resin portion. Even if there is not enough space, it is possible to provide a polarity identification mark, and the polarity identification mark is not buried in the solder flux even after the soldering mounting process to the assembly board, so that it can be reliably recognized after mounting and product inspection Sometimes it is easy to find what was misassembled.

さらに前記表面実装型光半導体装置が封止樹脂として可視光カット樹脂を備えた受光装置であっても前記可視光カット樹脂をカットオフ波長以下の短波長側に透過率ピークが５％以下のバンドパス波長領域を有しているものを採用し、短冊上の極性識別マークの色または前記基板の表面色のどちらかが前記バンドパス波長領域内のいずれかの波長で示される色が選択することで、極性識別マークが充分に視認可能な可視光カット樹脂付の表面実装型受光装置とすることができる。   Further, even if the surface-mounted optical semiconductor device is a light receiving device provided with a visible light cut resin as a sealing resin, the visible light cut resin is a band having a transmittance peak of 5% or less on the short wavelength side that is not longer than the cutoff wavelength. Use one having a pass wavelength region, and select either the color of the polarity identification mark on the strip or the surface color of the substrate as the color indicated by any wavelength within the bandpass wavelength region. Thus, the surface mount type light receiving device with visible light cut resin in which the polarity identification mark can be sufficiently visually recognized can be obtained.

さらに前記封止樹脂部の帯状領域の加工を前記表面実装型光半導体装置の切断分離工程における切断をダイサーブレードの刃幅を変えて二段階で行うことにより、前記表面実装型光半導体装置１５０および前記表面実装型光半導体装置１６０のパッケージ形態双方で採用可能となり、樹脂封止金型や樹脂塗布に用いる治具等を複雑化させたり、精度を高めたりせずに従来製造工程を極端に変更することなく作成が可能となる。   Further, the surface-mount type optical semiconductor device 150 and the surface-mount type optical semiconductor device 150 are processed in two steps by changing the blade width of the dicer blade in the cutting and separating step of the surface-mount type optical semiconductor device. The surface mount type optical semiconductor device 160 can be used in both package forms, and the conventional manufacturing process can be changed drastically without complicating a resin-sealing mold or a jig used for resin coating or increasing accuracy. You can create without having to.

図１は本発明による実施形態を示すものである。FIG. 1 shows an embodiment according to the present invention. 図２は図１の実施形態を上方から見た様子を示す模式図である。FIG. 2 is a schematic diagram showing the embodiment of FIG. 1 as viewed from above. 図３は本発明による別の実施形態を示すものである。FIG. 3 shows another embodiment according to the present invention. 図４は本発明による別の実施形態で採用される可視光カット樹脂の分光透過率特性例である。FIG. 4 is an example of spectral transmittance characteristics of a visible light cut resin employed in another embodiment of the present invention. 図５は図３の実施形態を上方から見た様子を示す模式図である。FIG. 5 is a schematic view showing the embodiment of FIG. 3 as viewed from above. 図６は光半導体装置の製造プロセスを模式的に示すものである。FIG. 6 schematically shows a manufacturing process of the optical semiconductor device. 図７は別の光半導体装置の製造プロセスを模式的に示すものである。FIG. 7 schematically shows a manufacturing process of another optical semiconductor device. 図８はトランスファモールド工法でモールド欠陥の発生する様子を模式的に示したものである。FIG. 8 schematically shows how mold defects occur in the transfer mold method. 図９は帯状領域をスタンピングで作成する場合に治具類が複雑になり、光半導体ベアチップへの損傷が生ずる可能性があることを説明する模式図である。FIG. 9 is a schematic diagram for explaining that the jigs are complicated when the band-like region is formed by stamping, and the optical semiconductor bare chip may be damaged. 図１０は本発明による溝削成工程を模式的に示すものである。FIG. 10 schematically shows the groove cutting process according to the present invention. 図１１は本発明による切断・分離工程を模式的に示すものである。FIG. 11 schematically shows a cutting / separating process according to the present invention. 図１２は本発明による溝と分割ラインの関係を示したものである。FIG. 12 shows the relationship between grooves and dividing lines according to the present invention. 図１３は本発明の別の実施形態で用いられる回路基板のパターン配置にチップボンディングされた状態を示すものである。FIG. 13 shows a state of chip bonding to a circuit board pattern arrangement used in another embodiment of the present invention. 図１４は本発明の別の実施形態を示すものである。FIG. 14 shows another embodiment of the present invention. 図１５は従来の光半導体装置のパーケージ形態を示すものである。FIG. 15 shows a package configuration of a conventional optical semiconductor device. 図１６は従来の別の光半導体装置のパーケージ形態を示すものである。FIG. 16 shows a package form of another conventional optical semiconductor device. 図１７は従来の極性識別マークの例を示すものである。FIG. 17 shows an example of a conventional polarity identification mark. 図１８は従来の別の極性識別マークの例を示すものである。FIG. 18 shows another conventional polarity identification mark. 図１９は従来の別の極性識別マークの例を示すものである。FIG. 19 shows an example of another conventional polarity identification mark.

（第一の実施形態）つぎに、本発明を図に示す実施形態に基づいて詳細に説明する。図１は本発明に係る表面実装型光半導体装置の第一実施形態であり、前記光半導体装置１５０のパッケージ形態に対応するものとして、ＬＥＤベアチップ１を搭載したチップ型ＬＥＤを示すものである。このチップ型ＬＥＤの、例えば長方形とした基板２の表面側には、短辺側に電極パターン４ａ、４ｂが設けられている。 (First Embodiment) Next, the present invention will be described in detail based on the embodiment shown in the drawings. FIG. 1 shows a first embodiment of a surface-mounted optical semiconductor device according to the present invention, and shows a chip-type LED on which an LED bare chip 1 is mounted, corresponding to the package form of the optical semiconductor device 150. On the surface side of the chip-shaped LED, for example, a rectangular substrate 2, electrode patterns 4a and 4b are provided on the short side.

そして、前記基板２の前記電極パターン４ａ、４ｂに対応して裏面側に裏電極パターンが４ａ’、４ｂ’敷設されている。そして、表電極パターン４ａと裏電極パターン４ａ’は、基板２の板厚面に施された無電界メッキなどにより各々電気的に接続され、同様に、表電極パターン４ｂと裏電極パターン４ｂ’も電気的に接続されている。   Then, back electrode patterns 4 a ′ and 4 b ′ are laid on the back side corresponding to the electrode patterns 4 a and 4 b of the substrate 2. The front electrode pattern 4a and the back electrode pattern 4a 'are electrically connected to each other by electroless plating or the like applied to the plate thickness surface of the substrate 2, and similarly, the front electrode pattern 4b and the back electrode pattern 4b' Electrically connected.

また、前記基板２の表面側においては、表電極パターン４ａ上にＬＥＤベアチップ１がダイボンドされ、金線６などで表電極パターン４ｂと接続される。そしてエポキシ樹脂などによる樹脂封止部３がトランスファモールド等適宜な方法で形成され、前記ＬＥＤベアチップ１、及び、金線６を覆い、湿度、外部応力などから保護している。尚、ＬＥＤベアチップの接続は電極配置に応じて、バンプや共晶接続によるフリップチップボンディング等様々な接続方法が選択される。   On the surface side of the substrate 2, the LED bare chip 1 is die-bonded on the surface electrode pattern 4a and connected to the surface electrode pattern 4b by a gold wire 6 or the like. A resin sealing portion 3 made of epoxy resin or the like is formed by an appropriate method such as transfer molding, and covers the LED bare chip 1 and the gold wire 6 to protect them from humidity, external stress, and the like. For connection of the LED bare chip, various connection methods such as flip chip bonding by bump or eutectic connection are selected according to the electrode arrangement.

尚、図１では樹脂封止部を透視して描いているが、前記樹脂封止部３は透明樹脂に光学的機能付与を目的として添加剤を加え透明度が低下している樹脂である。
具体的には、散乱効果を付与するために散乱材が混和された樹脂、青色ＬＥＤと白色光を合成するための補色光を発する蛍光体顔料が混和された樹脂あるいは前記散乱材もさらに加えた樹脂、可視光成分を遮断するようなフィルタ特性を付与する染料が混和された可視光カット樹脂、などがある。 In FIG. 1, the resin sealing portion 3 is illustrated with a perspective, but the resin sealing portion 3 is a resin whose transparency is lowered by adding an additive to the transparent resin for the purpose of imparting an optical function.
Specifically, a resin mixed with a scattering material for imparting a scattering effect, a resin mixed with a blue LED and a phosphor pigment that emits complementary color light for synthesizing white light, or the scattering material was further added. Resins, visible light cut resins mixed with dyes that impart filter characteristics that block visible light components, and the like.

ここで、本実施形態においては、前記基板２の表面側二つの正負電極パターン４ａ、４ｂが敷設されていない他の二辺のいずれかに沿うように、ＬＥＤベアチップ１の実装領域を避けて極性識別マーク５がレジストもしくはシルク版による短冊状のパターンで設けられている。   Here, in this embodiment, the polarity of the LED 2 is avoided by avoiding the mounting area of the LED bare chip 1 so as to be along one of the other two sides where the two positive and negative electrode patterns 4a and 4b on the surface side of the substrate 2 are not laid. The identification mark 5 is provided in a strip-like pattern made of a resist or a silk plate.

さらに前記封止樹脂３の極性識別マーク５の上の領域が、前記ＬＥＤベアチップ１実装領域上の領域よりも薄くした帯状に形成され、該帯状領域を通して前記短冊状パターン５が視認可能となるようにしている。   Further, the region of the sealing resin 3 above the polarity identification mark 5 is formed in a strip shape thinner than the region on the LED bare chip 1 mounting region, so that the strip pattern 5 can be visually recognized through the strip region. I have to.

次に、図２は、図１におけるチップ型ＬＥＤを上方から見た様子を模式的に表した図である。ここで、前記帯状領域７ａの短手寸法Ｓ１は前記極性識別マーク５を特別な光学検査装置を使用せずに視認可能とするために少なくとも０．２ｍｍ、好ましくは０．３ｍｍ以上であることが望ましい。   Next, FIG. 2 is a diagram schematically showing the chip LED in FIG. 1 as viewed from above. Here, the short dimension S1 of the band-like region 7a is at least 0.2 mm, preferably 0.3 mm or more in order to make the polarity identification mark 5 visible without using a special optical inspection device. desirable.

また、前記極性識別マーク５に関する留意点として、表示コントラストを稼ぐため、図２に示すように、長手寸法Ｌ２は前記帯状領域７ａの長手寸法Ｌ１よりも短くし、周囲に対して明度対比が高くなるような表示色を選択しておくことが好ましい。
例えば、図１の光半導体装置１５０が青色ＬＥＤベアチップと補色発光用の蛍光材を混和し封止樹脂で構成される白色ＬＥＤであれば、樹脂色は外光によって蛍光材が励起されるため、薄黄色として視認される色となっている。この場合、極性識別マーク５の表示色は黒色や濃い緑色を選択すればよい。これらの色はレジストとして一般的に供給されているものである。
尚、前記帯状領域７ａの短手寸法Ｓ１が非常に小さく、この範囲で前述のように方向識別用マーク５の配置によって明度対比を感じるのは困難である。また方向識別用マーク５を視認するためには、太さが必要であり、細すぎると汚れなどと識別できない。それ故、方向識別用マーク５の短手寸法Ｓ２は、可能なかぎり前記短手寸法Ｓ１の幅一杯に方向識別用マーク５の短手寸法Ｓ２を設定するのが望ましく、さらに、図２に示すように、方向識別用マーク５の短手寸法Ｓ２を大きくして、前記帯状領域７ａの短手寸法Ｓ１による範囲を超えて光半導体ベアチップ搭載領域にはみ出すように設定してもよい。 Further, as a point to be noted regarding the polarity identification mark 5, in order to increase display contrast, as shown in FIG. 2, the longitudinal dimension L2 is shorter than the longitudinal dimension L1 of the belt-like region 7a, and the brightness contrast is high with respect to the surroundings. It is preferable to select such a display color.
For example, if the optical semiconductor device 150 in FIG. 1 is a white LED composed of a sealing resin mixed with a blue LED bare chip and a fluorescent material for complementary color light emission, the fluorescent material is excited by external light. The color is visible as light yellow. In this case, the display color of the polarity identification mark 5 may be black or dark green. These colors are generally supplied as resists.
Note that the short dimension S1 of the band-like region 7a is very small, and it is difficult to feel the brightness contrast by the arrangement of the direction identification mark 5 as described above within this range. Further, in order to visually recognize the direction identification mark 5, the thickness is necessary, and if it is too thin, it cannot be identified as dirt. Therefore, it is desirable to set the short dimension S2 of the direction identification mark 5 to the full width of the short dimension S1 as much as possible as shown in FIG. As described above, the short dimension S2 of the direction identification mark 5 may be increased so as to protrude beyond the range of the short dimension S1 of the band-shaped region 7a into the optical semiconductor bare chip mounting region.

尚、図２において７ｂで示される帯状領域は製造過程で帯状領域７ａを形成するときに、副次的に形成されるものである。また製造過程の初期に用いられる多面付け回路基板における個々のパターンの配置によっては前記領域７ｂ形成されないようにすることも可能である。領域７ｂの形成の有無については後述する製造方法とともに説明する。   In FIG. 2, the belt-like region 7b is formed as a secondary when the belt-like region 7a is formed in the manufacturing process. It is also possible to prevent the region 7b from being formed depending on the arrangement of individual patterns on the multi-sided circuit board used at the beginning of the manufacturing process. Whether or not the region 7b is formed will be described together with a manufacturing method described later.

（第二の実施形態）次に、本発明の別の実施形態について説明する。図３は本発明に係る光半導体装置の別の実施形態であり、前記光半導体装置１６０のパッケージ形態に対応するものとして、受光ベアチップ３１を搭載した面実装光半導体受光装置を示すものである。この面実装光半導体受光装置の、基板３２の表面側には、受光ベアチップ３１が戴置され前記受光ベアチップ３１の電極パッドと接続するための表面パターンが敷説されている（図示せず）。また前記基板３２の裏面側には面実装光半導体受光装置の端子電極パターン３４ａ、３４ｂが敷設されており、各々前記表面パターンとスルーホール等を介して導通されている。 (Second Embodiment) Next, another embodiment of the present invention will be described. FIG. 3 shows another embodiment of the optical semiconductor device according to the present invention, and shows a surface-mount optical semiconductor light-receiving device on which a light-receiving bare chip 31 is mounted, corresponding to the package form of the optical semiconductor device 160. In this surface-mounted optical semiconductor light-receiving device, a light-receiving bare chip 31 is placed on the surface side of the substrate 32 and a surface pattern for connecting to the electrode pads of the light-receiving bare chip 31 is provided (not shown). Further, terminal electrode patterns 34a and 34b of a surface-mounted optical semiconductor light receiving device are laid on the back surface side of the substrate 32, and are electrically connected to the surface pattern via a through hole or the like.

尚、図３では端子電極パターンを二端子として図示しているが、本実施形態では受光ベアチップ３１の電極数に応じて、前記基板３２の裏面側に端子電極パターンの数を設けることが可能である。
即ち、前記受光ベアチップ３１の電極数は、例えばフォトダイオードであれば、正負電極の二端子で、フォトトランジスタであれば、コレクタ、エミッタ、ベース、の三端子となり、その他フォトＩＣであれば電源の二端子に出力を加えた三端子以上であり、面実装光半導体受光装置の端子電極パターンは前記受光ベアチップ３１の電極数に応じたそして、基板裏面内で適宜配置が決められる。 In FIG. 3, the terminal electrode pattern is shown as two terminals, but in the present embodiment, the number of terminal electrode patterns can be provided on the back side of the substrate 32 according to the number of electrodes of the light receiving bare chip 31. is there.
That is, the number of electrodes of the light receiving bare chip 31 is, for example, two terminals of positive and negative electrodes in the case of a photodiode, three terminals of a collector, an emitter, and a base in the case of a phototransistor. The terminal electrode pattern of the surface-mount optical semiconductor light-receiving device is determined according to the number of electrodes of the light-receiving bare chip 31 and appropriately arranged on the back surface of the substrate.

そして、受光ベアチップ３１は前記表面パターンとワイヤーボンディングあるいはフリップバンプボンディング等により接続され、更にエポキシ樹脂などによる樹脂封止部３３が基板３２の表面全面に形成され、前記受光ベアチップ３１、及び、基板３２表面全体を覆い、湿度、外部応力などから保護している。   The light receiving bare chip 31 is connected to the surface pattern by wire bonding or flip bump bonding, and a resin sealing portion 33 made of epoxy resin or the like is further formed on the entire surface of the substrate 32. The light receiving bare chip 31 and the substrate 32 are also formed. Covers the entire surface and protects it from humidity, external stress, etc.

ここで、図３では樹脂封止部３３を透視して描いているが、本実施例においては、前記樹脂封止部３３は、例えば７５０ｎｍ以下の光をカットし赤外光を透過するフィルタ特性を有する可視光カット樹脂用いており、実物は黒く不透明に観えている。可視光カット樹脂の分校透過率特性を図４に示す。このような樹脂材料は日東電工株式会社製よりＮＴ−８５１０−７５０００として入手できる。一般に染料添加方式による赤外透過の可視光カットフィルタでは、カットオフ波長以下の短波長側にバンドパス波長領域が発生しやすい傾向にあり、市場に供給されている可視光カット樹脂の代表的特性例である。尚、該バンドパス波長領域は図４の例で一点鎖線内示される部分であり、ピーク透過率が５％以下と軽微なため実使用上は問題にならない。   Here, in FIG. 3, the resin sealing portion 33 is drawn through, but in this embodiment, the resin sealing portion 33 has a filter characteristic that cuts light of, for example, 750 nm or less and transmits infrared light. The visible light cut resin is used, and the real thing looks black and opaque. FIG. 4 shows the branching transmittance characteristics of the visible light cut resin. Such a resin material can be obtained as NT-8510-75000 from Nitto Denko Corporation. In general, visible light cut filters with infrared transmission using dye addition methods tend to generate a bandpass wavelength region on the short wavelength side below the cut-off wavelength. Typical characteristics of visible light cut resins supplied to the market It is an example. The bandpass wavelength region is a portion indicated by a one-dot chain line in the example of FIG. 4, and the peak transmittance is as small as 5% or less, so there is no problem in practical use.

また、本実施形態においても、第一の実施形態の措置と同様に、前記基板３２の表面側の各四辺のいずれか一つに沿うように極性識別マーク３５がレジストもしくはシルク版による短冊状パターンを用いて設けられており、さらに前記封止樹脂３３の極性識別マーク３５の上の領域が、前記受光ベアチップ３１実装領域上の領域よりも薄くした帯状に形成され、該帯状領域を通して前記短冊状パターン３５が視認可能となるようにしている。   Also in this embodiment, as in the measures of the first embodiment, the polarity identification mark 35 is a strip-shaped pattern made of a resist or a silk plate so as to follow any one of the four sides on the surface side of the substrate 32. Further, a region of the sealing resin 33 on the polarity identification mark 35 is formed in a strip shape thinner than a region on the light receiving bare chip 31 mounting region, and the strip shape is formed through the strip region. The pattern 35 is made visible.

ここで、本実施形態では、前記極性識別マーク３５の視認性を確保するために、前記極性識別マーク３５あるいは基板３２の表面のいずれか一方は前記バンドパス波長領域内の少なくとも一部の光波長を反射可能な色が選択される。この場合、もう一方は該選択色に明度対比を考慮してコントラストを保たれる色を選択しておくことが好ましい。すなわち、第一の実施形態と異なり、極性識別マーク３５が明度対比の比較対象は周囲の樹脂色ではなく、背景の基板色であることに留意が必要である。
例えば、前記基板３２において、基材がガラエポ＿ＦＲ−４のように基材色が薄青色、あるいはＢＴレジン（三菱瓦斯化学株式会社商標）のように基材を白色化したものの場合、極性識別マークは黒色が好ましく、また基材表面が予めレジストにより黒色や濃い緑色に着色されている場合、極性識別マークは黄色や白色のシルク版が好ましい。 Here, in the present embodiment, in order to ensure the visibility of the polarity identification mark 35, either the polarity identification mark 35 or the surface of the substrate 32 is at least part of the light wavelength within the bandpass wavelength region. A reflective color is selected. In this case, it is preferable that the other color is selected for maintaining the contrast in consideration of brightness contrast. That is, it should be noted that, unlike the first embodiment, the polarity identification mark 35 is compared with the background substrate color instead of the surrounding resin color.
For example, in the substrate 32, when the base material is a light blue base material such as glass epoxy_FR-4, or a white base material such as BT resin (trademark of Mitsubishi Gas Chemical Co., Ltd.), the polarity identification mark Is preferably black, and when the substrate surface is colored in black or dark green in advance by a resist, the polarity identification mark is preferably a yellow or white silk plate.

次に、図５は、図３における面実装光半導体受光装置を上方から見た様子を模式的に表した図である。ここで、前記帯状領域３７ａの短手寸法Ｓ１’は前記極性識別マーク３５を特別な光学検査装置を使用せずに視認可能とするために少なくとも０．２ｍｍ、好ましくは０．３ｍｍ以上であることが望ましい。   Next, FIG. 5 is a diagram schematically showing the surface mounted optical semiconductor light receiving device in FIG. 3 as viewed from above. Here, the short dimension S1 ′ of the band-shaped region 37a is at least 0.2 mm, preferably 0.3 mm or more in order to make the polarity identification mark 35 visible without using a special optical inspection device. Is desirable.

さらに、前記極性識別マーク３５に関する留意点として、表示コントラストを稼ぐため、図５に示すように、長手寸法Ｌ２’は前記帯状領域３７ａの長手寸法Ｌ１’よりも短くしておくことが望ましい。
尚、前記帯状領域３７ａの短手寸法Ｓ１’が非常に小さく、この範囲で前述のように方向識別用マーク３５の配置によって明度対比を感じるのは困難である。また方向識別用マーク３５を視認するためには、太さが必要であり、細すぎると汚れなどと識別できない。それ故、方向識別用マーク３５の短手寸法Ｓ２’は、可能なかぎり前記短手寸法Ｓ１’の幅一杯に方向識別用マーク３５の短手寸法Ｓ２’を設定するのが望ましく、さらに、図２に示すように、方向識別用マーク３５の短手寸法Ｓ２’を大きくして、前記帯状領域３７ａの短手寸法Ｓ１’による範囲を超えて光半導体ベアチップ搭載領域にはみ出すように設定してもよい。 Further, as a point to be noted regarding the polarity identification mark 35, in order to increase display contrast, it is desirable that the longitudinal dimension L2 ′ be shorter than the longitudinal dimension L1 ′ of the strip-shaped region 37a as shown in FIG.
Note that the short dimension S1 ′ of the belt-like region 37a is very small, and it is difficult to feel the brightness contrast by the arrangement of the direction identification mark 35 as described above within this range. Further, in order to visually recognize the direction identification mark 35, the thickness is necessary. If it is too thin, it cannot be identified as dirt. Therefore, it is desirable that the short dimension S2 ′ of the direction identification mark 35 is set to the full width of the short dimension S1 ′ as much as possible. As shown in FIG. 2, the short dimension S2 ′ of the direction identification mark 35 may be increased so that it extends beyond the range of the short dimension S1 ′ of the band-shaped region 37a and protrudes into the optical semiconductor bare chip mounting region. Good.

尚、図５において３７ｂで示される帯状領域は製造過程で帯状領域３７ａを形成するときに、副次的に形成されるものである。また製造過程の初期に用いられる多面付け回路基板における個々のパターンの配置によっては前記領域３７ｂを形成されないようにすることも可能である。領域３７ｂの形成の有無については後述する製造方法とともに説明する。   In FIG. 5, the belt-like region indicated by 37b is formed as a secondary when the belt-like region 37a is formed in the manufacturing process. It is also possible to prevent the region 37b from being formed depending on the arrangement of individual patterns on the multi-sided circuit board used at the beginning of the manufacturing process. Whether or not the region 37b is formed will be described together with a manufacturing method described later.

（樹脂厚みに関する透視性評価試験）ここで、蛍光体が混和された透明樹脂と可視カット樹脂の二つの不透明樹脂を用いて、樹脂厚みに関して透視性の評価を行った。
試料の構成を以下に示す。透視性評価マークは前述のように周囲および背景に対して明度対比が高くなる組み合わせを選択した。
以下の試料構成１および試料構成２でトランスファー工法により図６における面実装光半導体装置６０の形状に基板上に封止樹脂部を形成したものを各々試料１、試料２とした。
・試料構成１
樹脂：オルトシリケート系蛍光材１５％重量費で混合したエポキシ樹脂
基板：ＢＴレジン（三菱瓦斯化学株式会社商標）
透視性評価マーク：緑色レジスト、大きさ１．２Ｘ０．３ｍｍの短冊形状
・試料構成２
樹脂：図４の分光透過率特性と同等のカットオフ波長７５０ｎｍのフィルタ特性を有するエポキシベースの可視光カット樹脂
基板：ガラエポ（ＦＲ−４）、表面に黒レジスト面付き
透視性評価マーク：黄色レジスト、大きさ１．２Ｘ０．３ｍｍの短冊形状 (Transparency Evaluation Test Regarding Resin Thickness) Here, the transparency of the resin thickness was evaluated using two opaque resins, a transparent resin mixed with a phosphor and a visible cut resin.
The configuration of the sample is shown below. As described above, the combination of the transparency evaluation marks having a high brightness contrast with respect to the surroundings and the background was selected.
Samples 1 and 2 in which the sealing resin portion was formed on the substrate in the shape of the surface mount optical semiconductor device 60 in FIG.
・ Sample configuration 1
Resin: Epoxy resin mixed with orthosilicate phosphor at 15% weight
Substrate: BT resin (trademark of Mitsubishi Gas Chemical Co., Inc.)
Permeability evaluation mark: Green resist, strip shape of size 1.2X0.3mm, sample configuration 2
Resin: Epoxy-based visible light cut resin having a filter characteristic with a cutoff wavelength of 750 nm equivalent to the spectral transmittance characteristic of FIG. 4 Substrate: Glass Epoxy (FR-4), with a black resist surface on the surface Transparency evaluation mark: Yellow resist , Strip shape of size 1.2X0.3mm

次に、試料１および試料２の透視性評価マーク上方の樹脂領域を樹脂封止部上面から樹脂厚みを都度測定しながら少しずつ薄くなるよう削った。尚、加工には電動式ハンドリューターを用いた。   Next, the resin regions above the transparency evaluation marks of Sample 1 and Sample 2 were shaved gradually from the upper surface of the resin sealing portion while measuring the resin thickness each time. An electric hand leuter was used for processing.

試料１では、樹脂厚みがほぼ２００μｍとなる時に、蛍光色により黄色く見える樹脂面に前記透視性評価マークが緑斑状に視認可能となることを確認した。
試料２では、樹脂厚みがほぼ３００μｍとなる時に、黒い基板面に対して黄色レジストによるマークが浮かび上がるようにして視認可能となることを確認した。
従って、マーク上方の樹脂厚みをさらに薄く安定して削成すれば、着実に視認可能な方向識別マークとして機能することが確認できた。 In Sample 1, it was confirmed that when the resin thickness was approximately 200 μm, the transparency evaluation mark was visible in a green spot on the resin surface that appeared yellow due to the fluorescent color.
In sample 2, when the resin thickness was approximately 300 μm, it was confirmed that a yellow resist mark was visible on the black substrate surface and was visible.
Therefore, it was confirmed that if the resin thickness above the mark was further reduced and stably cut, it functioned as a direction identification mark that could be steadily visible.

（ 製造方法 ）第１の実施の形態のように基板部表面にも電極端子パターンを有した形態の装置は、図６に示す様なプロセスで製造される。尚図６は用いる光半導体ベアチップがＬＥＤベアチップの場合を例に描いているが、受光ベアチップを用いる場合も同様のプロセスである。 (Manufacturing method) An apparatus having an electrode terminal pattern on the surface of the substrate as in the first embodiment is manufactured by a process as shown in FIG. Although FIG. 6 shows an example in which the optical semiconductor bare chip to be used is an LED bare chip, the same process is performed when a light receiving bare chip is used.

図６において６１はＬＥＤベアチップ、６２はＬＥＤ接続回路パターンを多面付け状に敷設した回路基板である。まずＬＥＤボンディング工程では、回路基板６２の面付け数に応じた複数個のＬＥＤベアチップ６１が回路基板６２のＬＥＤ接続回路パターンに戴置しワイヤーやバンプ等を用いて接続される。
次の樹脂封止工程では、前記ＬＥＤベアチップ６１とその接続部周辺を被覆するために、封止金型にセットし、トランスファモールド工法により、一列毎にエポキシ樹脂で封止して前記基板６２の表面に棒状の封止体６３を作成する。
そして切断・分離工程では、基板裏面に粘着シート（図示せず）を貼り、ダイサーブレード６４により前記基板６２と封止樹脂による棒状の封止体６３を同時に切断した後、前記粘着シートから個々のチップ型ＬＥＤを剥がし、個片状態とする。 In FIG. 6, 61 is an LED bare chip, and 62 is a circuit board on which LED connection circuit patterns are laid in a multi-sided manner. First, in the LED bonding step, a plurality of LED bare chips 61 corresponding to the number of impositions of the circuit board 62 are placed on the LED connection circuit pattern of the circuit board 62 and connected using wires, bumps, or the like.
In the next resin sealing step, in order to cover the LED bare chip 61 and the periphery of the connection portion, it is set in a sealing mold, and is sealed with an epoxy resin for each row by a transfer mold method. A rod-shaped sealing body 63 is formed on the surface.
In the cutting / separating step, an adhesive sheet (not shown) is attached to the back surface of the substrate, and the substrate 62 and the rod-shaped sealing body 63 made of a sealing resin are simultaneously cut by the dicer blade 64, and then each individual piece is separated from the adhesive sheet. The chip-type LED is peeled off to obtain individual pieces.

尚、封止樹脂に顔料や染料や拡散材などの光学的添加剤が混和された樹脂を用いる場合、該添加剤は予め粉体化したエポキシ樹脂と所定の混合比で混合した後に打錠されてタブレット状に加工して用いられる。この場合、封止体成形条件のみが設定変更されるだけで、樹脂封止工程手順に変化はない。   In addition, when using resin in which optical additives such as pigments, dyes, and diffusing materials are mixed in the sealing resin, the additive is mixed with a pre-powdered epoxy resin at a predetermined mixing ratio and then compressed into tablets. And processed into a tablet. In this case, only the sealing body molding conditions are changed, and the resin sealing process procedure is not changed.

次に第２の実施形態のように基板部表面前面を樹脂封止部が覆う形態の装置は、図７に示すようなプロセスで製造される。図６のプロセスと類似しているが、樹脂封止が金型を使用しないで行われるという違いがあり、金型を使用しないため様々な大きさの半導体ベアチップに基板の回路パターンと分割ラインを変更するだけで対応可能という利点がある。   Next, an apparatus having a form in which the front surface of the substrate portion is covered with the resin sealing portion as in the second embodiment is manufactured by a process as shown in FIG. Similar to the process of FIG. 6, there is a difference that the resin sealing is performed without using a mold, and since the mold is not used, the circuit pattern and the dividing line of the substrate are formed on the semiconductor bare chips of various sizes. There is an advantage that it is possible to respond by simply changing.

図７において７１は光半導体ベアチップ、７２は光半導体接続回路パターンを多面付け状に敷設した回路基板である。まずチップボンディング工程では、回路基板７２の面付け数に応じた複数個の光半導体ベアチップ７１が回路基板７２の光半導体接続回路パターンに戴置しワイヤーやバンプ等を用いて接続される。
次の樹脂封止の段階は、塗布・第１硬化工程と、平坦化・第２硬化工程の二段階で構成される。塗布・第１硬化工程では、チップボンディングされた基板７２に液状の樹脂を真空下で印刷により塗布し、前記樹脂を加熱して、外部からの加圧により変形可能な程度の半硬化状態まで硬化させて半硬化封止樹脂層７３を形成する。平坦化・第２硬化工程では、前記第１硬化工程後に室温まで冷却し、当該室温下において前記樹脂の表面に金属平板を押しつけて樹脂表面を平坦面７４とした後に樹脂を加熱して硬化させる。
そして切断・分離工程では、基板裏面に粘着シート（図示せず）を貼り、ダイサーブレード７５により前記基板７２と封止樹脂７６を同時に切断した後、前記粘着シートから個々のチップ型光半導体装置を剥がし、個片状態とする。 In FIG. 7, reference numeral 71 denotes an optical semiconductor bare chip, and 72 denotes a circuit board on which optical semiconductor connection circuit patterns are laid in a multi-sided manner. First, in the chip bonding step, a plurality of optical semiconductor bare chips 71 corresponding to the number of impositions of the circuit board 72 are placed on the optical semiconductor connection circuit pattern of the circuit board 72 and connected using wires, bumps, or the like.
The next stage of resin sealing is composed of two stages: an application / first curing step and a planarization / second curing step. In the coating / first curing step, a liquid resin is applied to the chip-bonded substrate 72 by printing under vacuum, and the resin is heated to cure to a semi-cured state that can be deformed by external pressure. Thus, a semi-cured sealing resin layer 73 is formed. In the flattening / second curing step, after cooling down to the room temperature after the first curing step, a metal flat plate is pressed against the surface of the resin at the room temperature to make the resin surface a flat surface 74, and then the resin is heated and cured. .
In the cutting / separating step, an adhesive sheet (not shown) is pasted on the back surface of the substrate, the substrate 72 and the sealing resin 76 are simultaneously cut by the dicer blade 75, and then each chip type optical semiconductor device is separated from the adhesive sheet. Peel off to make a piece.

ここで本発明は、前述の図６および図７よる製造プロセスにより製造される光半導体装置に関するものであるため、樹脂封止部は多面付け付けされた光半導体ベアチップ及び回路パターン部を全体一括に、あるいは一列毎にまとめて樹脂が塗布される。従って、方向識別用マークの上の領域を薄くして帯状領域を形成するのは、樹脂封止後に削成する方法が実現性があり合理的である。   Here, since the present invention relates to an optical semiconductor device manufactured by the manufacturing process shown in FIGS. 6 and 7 described above, the resin-encapsulated portion includes the optical semiconductor bare chip and the circuit pattern portion that are multifaceted as a whole. Or resin is apply | coated collectively for every row. Therefore, forming the band-like region by thinning the region above the direction identification mark is feasible and rational with a method of cutting after resin sealing.

すなわち、図６の製造プロセスでは元来トランスファモールド工法における射出圧力は一般的に低く設定されるものであるため、前述のような薄肉となる帯状領域を介してキャビティから次のキャビティへと樹脂を送ることは容易でなく、未充填となるモールド欠陥が発生する。図８は、樹脂の流れ８４が薄肉部８２を基板８３の界面に接しながら押し出され次のキャビティで圧力が低下してモールド欠陥８１が発生している様子を模式的に表したものである。   That is, in the manufacturing process of FIG. 6, since the injection pressure in the transfer mold method is generally set to be low, the resin is passed from the cavity to the next cavity through the strip-shaped region as described above. It is not easy to send, and unfilled mold defects occur. FIG. 8 schematically shows a state in which the resin flow 84 is pushed out while contacting the thin-walled portion 82 with the interface of the substrate 83 and the mold defect 81 is generated due to the pressure drop in the next cavity.

また図７の製造プロセスでは、樹脂平坦化工程用いる治具類が複雑になる。図９はその様子を模式的に描いたもので、９１は樹脂押さえ板、９２は半硬化状態の樹脂層、９３は多面付け回路基板、９４は光半導体ベアチップである。樹脂押さえ板９１は帯状領域をスタンピングで作成するために、平板ではなく下駄歯状の突起部を持つ。従って、多面付け回路基板９３および半導体ベアチップとの位置合わせに精度が求められることになる。   In the manufacturing process of FIG. 7, jigs used in the resin flattening step are complicated. FIG. 9 schematically shows the state, in which 91 is a resin pressing plate, 92 is a semi-cured resin layer, 93 is a multi-sided circuit board, and 94 is an optical semiconductor bare chip. The resin pressing plate 91 has a clog-like protrusion instead of a flat plate in order to create a band-like region by stamping. Therefore, accuracy is required for alignment between the multi-sided circuit board 93 and the semiconductor bare chip.

図９（ｂ）は前記樹脂押さえ板９１を樹脂層９２に押さえ始めた様子を描いたもので、押さえ時に余分となる樹脂の逃げを矢印９５で表している。この場合、樹脂が半硬化状態光であるため接続ワイヤーへのストレスを与える懸念や、添加剤が混和された樹脂が使用される場合は、フィラーアタックにより光半導体ベアチップに損傷が生ずる可能性もある。   FIG. 9B depicts a state in which the resin pressing plate 91 is started to be pressed by the resin layer 92, and an escape of the resin that is excessive when pressing is indicated by an arrow 95. In this case, there is a possibility that the optical semiconductor bare chip may be damaged by the filler attack when the resin is in a semi-cured state light and there is a concern of giving stress to the connection wire or when a resin mixed with an additive is used. .

従って、本発明における極性識別マークを視認するための薄肉箇所の形成には、図６および図７の製造プロセスにより樹脂封止まで終えた後に、極性識別マーク上方の樹脂を削るのが簡便である。例えばすりわり状の溝を削成し、視認可能となるまで溝底面に樹脂を薄く残すようにした後に、切断を行うようにすればよい。   Therefore, in forming the thin portion for visually recognizing the polarity identification mark in the present invention, it is easy to scrape the resin above the polarity identification mark after finishing the resin sealing by the manufacturing process of FIGS. . For example, a slot-shaped groove may be cut and the resin may be thinly left on the bottom of the groove until it is visible, and then cut.

そこで、本発明においては、第１の実施の形態および第２の実施の形態の製造方法、すなわち前述の図６および図７による製造プロセスにおける切断・分離工程を次の溝削成工程と、切断・分離工程の二つの工程にて実施する。   Therefore, in the present invention, the manufacturing method of the first embodiment and the second embodiment, that is, the cutting / separating step in the manufacturing process shown in FIGS. -Implement in two steps of separation process.

ここで本発明における製造プロセスを纏めると、まず、光半導体ベアチップ実装領域と光半導体ベアチップと接続されるボンディングパッドや電極端子パターンおよびそれらを繋ぐ配線パターンが形成された四角形の基板パターンが複数個形成され、分割ラインに沿うように取り数に応じて極性識別マークがレジストあるいはシルク版で設けてある多面付け基板が用意される。   Here, the manufacturing process according to the present invention is summarized. First, a plurality of rectangular substrate patterns are formed on which bonding pads and electrode terminal patterns connected to the optical semiconductor bare chip mounting region and the optical semiconductor bare chip, and wiring patterns connecting them are formed. Then, a multi-sided substrate is prepared in which a polarity identification mark is provided by a resist or a silk plate according to the number of cuts along the dividing line.

次に前述の図６や図７による方法で樹脂封止工程まで実施する。
すなわち、前記多面付け回路基板に取り数に応じた数の光半導体ベアチップを前記回路基板に実装し、回路と接続するボンディング工程後に、光半導体ベアチップが搭載された前記面付け回路基板の光半導体ベアチップ実装面側に前記極性識別マークを含めて覆うように樹脂を塗布あるいは成形型により樹脂注入した後に加熱硬化する。 Next, the resin sealing process is performed by the method shown in FIGS.
That is, an optical semiconductor bare chip of the imposition circuit board on which the optical semiconductor bare chip is mounted after a bonding step of mounting the number of optical semiconductor bare chips on the multi-sided circuit board according to the number of the mounting on the circuit board and connecting to the circuit A resin is applied or the resin is injected by a mold so as to cover the mounting surface including the polarity identification mark, and then cured by heating.

次に、本発明では、前記樹脂封止工程後に多面付け状態から製品個片に分ける切断・分離工程を刃幅が異なる二つダイサーブレードにより二段階の工程に分けて行う。   Next, in the present invention, after the resin sealing step, the cutting / separation step for dividing the product into pieces from the multi-faced state is performed in two steps by two dicer blades having different blade widths.

第一の工程は溝削成工程で、刃幅の大きいダイサーブレードにより、多面付け状態の樹脂封止部にすりわり状の溝を削成する。図１０は図６による棒状の樹脂封止体６３に溝削成を行う様子を模式的に表したもので、棒状の樹脂封止体６３を一列のみ描いているが、他の列は省略している。１０２は極性識別マークである。 また、図７の封止樹脂層７６については、図示しないが、図１０に示した封止体６３と同様に刀幅の大きいダイサーブレードにより複数列（または行）の溝を形成する。   The first step is a groove cutting step, in which a slotted groove is cut in a resin-sealed portion in a multi-faceted state with a dicer blade having a large blade width. FIG. 10 schematically shows a state in which the groove is formed in the rod-shaped resin sealing body 63 according to FIG. 6, and only one row of the rod-shaped resin sealing body 63 is drawn, but the other columns are omitted. ing. Reference numeral 102 denotes a polarity identification mark. Further, although not shown, the sealing resin layer 76 in FIG. 7 is formed with a plurality of rows (or rows) of grooves by a dicer blade having a large sword width, as in the sealing body 63 shown in FIG.

溝削成は刃幅の大きい第一のダイサーブレード１０１により、前記多面付け回路基板の分割ライン１０５を位置基準として、上方からみて前記分割ラインを溝幅内に含む位置で、封止樹脂に残される厚みｔまで多面付け状態の樹脂封止体を切削加工するようにして行う。尚、封止樹脂に残される厚みｔは前記極性識別マーク１０２が透けて視認可能となる厚さ以下の値で予め定められているものである。   Groove cutting is performed by the first dicer blade 101 having a large blade width, with the dividing line 105 of the multi-sided circuit board as a position reference, and remaining in the sealing resin at a position including the dividing line within the groove width as viewed from above. The resin sealing body in a multi-faceted state is cut to a thickness t to be cut. Note that the thickness t remaining in the sealing resin is determined in advance with a value equal to or less than a thickness at which the polarity identification mark 102 can be seen through.

第二の工程は切断・分離工程で、刃幅の小さいダイサーブレードを用い、第一の工程により樹脂封止体に削成された溝と底面と樹脂部を支える前記多面付け回路基板６２を前記多面付け回路基板の分割ライン１０５上を同時に切断するものである。図１１は刃幅の小さいダイサーブレード１０６によって前記分割ライン上を切断する様子を模式的に表している。尚、図示していないが、切断後の装置各個片がバラバラにならないように、第一の溝削成工程および第二の切断・分離工程をとおして、前記多面付け回路基板は粘着シートで保持されている。   The second step is a cutting / separating step, using a dicer blade with a small blade width, and the multi-sided circuit board 62 that supports the groove, bottom surface, and resin portion cut into the resin sealing body by the first step. The multi-sided circuit board is cut along the dividing line 105 at the same time. FIG. 11 schematically shows a state in which the dividing line is cut by the dicer blade 106 having a small blade width. Although not shown, the multi-sided circuit board is held by an adhesive sheet through the first groove cutting step and the second cutting / separating step so that each piece of the device after cutting does not fall apart. Has been.

ここで図１２は分割方向からみた樹脂封止体６３の断面を示すものである。図１２に示すように、前記溝の位置は上方からみて前記回路基板６２の分割ライン１０５を溝幅内に含む位置であればよく、溝の中心線が分割ラインに一致する位置である必要はなく、前記極性識別マーク１０２の方向へ偏心していても良い。
従って、ここで用いるダイサーブレードの刃幅Ｗ１は少なくとも次の切断に使用するダイサーブレードの刃幅Ｗ２に、前記極性識別マーク１０２を視認するための薄肉部の幅Ｗ３を加えた幅（Ｗ２＋Ｗ３）以上である必要がある。
例えば、切断に用いる刃幅の小さいダイサーブレードの刃幅Ｗ２が５０μｍで前記薄肉部の幅を２５０μｍに設定すれば、溝削成に用いる刃幅の大きいダイサーブレードは３００μｍ以上の刃幅Ｗ１を持つものを使用する。
尚、ここでは図６における樹脂封止体６３を例に説明しているが、図７の封止樹脂層７６についても各ダイサーブレードの位置関係は同様な措置となる。 Here, FIG. 12 shows the cross section of the resin sealing body 63 seen from the dividing direction. As shown in FIG. 12, the position of the groove may be a position that includes the dividing line 105 of the circuit board 62 within the groove width as viewed from above, and the groove center line needs to be a position that matches the dividing line. Alternatively, it may be decentered in the direction of the polarity identification mark 102.
Therefore, the blade width W1 of the dicer blade used here is at least the width (W2 + W3) obtained by adding the width W3 of the thin portion for visually recognizing the polarity identification mark 102 to the blade width W2 of the dicer blade used for the next cutting. Need to be.
For example, if the dicer blade having a small blade width used for cutting has a blade width W2 of 50 μm and the width of the thin portion is set to 250 μm, the dicer blade having a large blade width used for groove cutting has a blade width W1 of 300 μm or more. Use things.
Here, the resin sealing body 63 in FIG. 6 is described as an example, but the positional relationship of each dicer blade is the same measure for the sealing resin layer 76 in FIG.

尚、第一の溝削成工程において前記溝の底面の表面粗さ状態は、ダイサーブレード砥粒の設定およびブレードの回転数、ブレードの送り速度などのダイシング条件により変化する。表面状態で前記極性識別マーク１０２が視認可能となる前記薄肉部厚みｔが変化するので、前記ダイシング条件は十分に管理が必要である。
もし必要であれば、第一の溝削成工程と第二の切断・分離工程の間に前記溝の底面を対象としたバフ研磨工程を挿入しても良い。 In the first groove cutting process, the surface roughness state of the bottom surface of the groove changes depending on dicing conditions such as setting of dicer blade abrasive grains, blade rotation speed, blade feed speed, and the like. Since the thickness t of the thin portion at which the polarity identification mark 102 is visible in the surface state changes, the dicing condition needs to be sufficiently managed.
If necessary, a buffing process for the bottom surface of the groove may be inserted between the first groove cutting process and the second cutting / separating process.

また図１２において、厚肉部１２４は光半導体ベアチップ接続領域を覆う部分で、極性識別マーク１０２の上に位置する薄肉部１２６は図２において帯状領域７ａとなる部分である。また薄肉部１２７は図２において帯状領域７ｂに相当する部分である。
ここで、前記第二の切断・分離工程において刃幅の小さいダイサーブレード１０６の切断位置を刃幅の大きいダイサーブレード１０１によって削成された溝の側面に面一で設定することが難しい。それ故、薄肉部１２７（帯状領域７ｂ）は薄肉部１２６（帯状領域７ａ）形成時に副次的に形成されてしまう箇所である。 In FIG. 12, a thick portion 124 is a portion that covers the optical semiconductor bare chip connection region, and a thin portion 126 that is positioned on the polarity identification mark 102 is a portion that becomes the strip region 7a in FIG. The thin portion 127 is a portion corresponding to the band-like region 7b in FIG.
Here, in the second cutting / separating step, it is difficult to set the cutting position of the dicer blade 106 having a small blade width flush with the side surface of the groove cut by the dicer blade 101 having a large blade width. Therefore, the thin portion 127 (band-like region 7b) is a portion that is formed as a secondary component when the thin-walled portion 126 (band-like region 7a) is formed.

帯状領域７ｂについては、必ずしも不要な部分とは言い切れない。それは例えば、帯状領域７ｂがないと厚肉部１２４の中心が光半導体ベアチップの位置により定まる光学中心に対してずれが生じ、配光に偏りが生じるので好ましくないという場合や、図１において該チップ型ＬＥＤが小さくなり極性識別マーク５及び薄肉箇所７ａが極小化された場合に、前記薄肉箇所７ａと７ｂとを対比することで、極性識別の判断がしやすくなるという場合があるからである。
このような場合、帯状領域７ａと帯状領域７ｂは装置の両側面にバランスよく設置されるべきであろう。 The band-like region 7b is not necessarily an unnecessary portion. For example, if the band-like region 7b is not present, the center of the thick portion 124 is not preferable because the optical center determined by the position of the optical semiconductor bare chip is shifted and the light distribution is biased. This is because when the type LED becomes small and the polarity identification mark 5 and the thin portion 7a are minimized, the thin portion 7a and 7b may be compared to facilitate determination of polarity identification.
In such a case, the belt-like region 7a and the belt-like region 7b should be installed in a balanced manner on both sides of the apparatus.

もし、例えば図１のチップ型ＬＥＤの短手寸法に制約がある場合や、ワイヤーボンディングスペースに制約がある場合のように、帯状領域７ｂが機能的に有害であれば、複数個の光半導体ベアチップ実装パターンが形成された多面付け回路基板の個々のパターン方向を工夫することで、帯状領域７ｂ部が形成されないようにすることも可能である。   If, for example, the short dimension of the chip-type LED of FIG. 1 is restricted or the wire bonding space is restricted, if the band-like region 7b is functionally harmful, a plurality of optical semiconductor bare chips By devising the individual pattern directions of the multi-sided circuit board on which the mounting pattern is formed, it is possible to prevent the belt-like region 7b from being formed.

（第三の実施形態）図１３はチップ型ＬＥＤ用の多面付け回路基板の個々のパターン方向を互い違いに配置していくことで帯状領域７ｂが形成されないようにした例である。
図１３（ａ）は前記多面付け回路基板の各ダイボンデングパッド１３３ｂにＬＥＤベアチップを戴置しワイヤー１３２にてワイヤーパッド１３３ｃに接続された様子を装置上方から樹脂１３４を透視した状態で模式的に描いたものである。ＬＥＤベアチップの搭載位置はここの装置中心に整然配置されているが、ダイボンデングパッド１３３ｂ、ワイヤーパッド１３３ｃは互い違いに両端の各電極端子パターン１３３ａに延設されていて、ワイヤー１３２も互い違いに接続方向が変えられている。また極性識別マーク１３５は一つ置きに分割ラインと極性識別マーク１３５中心が重なるように配置されている。
図１３（ｂ）は図１３（ａ）の状態における接続回路図を示したものである。各ダイオード記号がアンチパラレル状態で階段状に繰返し接続されていることになる。 (Third Embodiment) FIG. 13 shows an example in which the band-like regions 7b are not formed by arranging the individual pattern directions of the multi-sided circuit board for chip-type LEDs in an alternating manner.
FIG. 13A schematically shows a state in which an LED bare chip is placed on each die bonding pad 133b of the multi-sided circuit board and is connected to the wire pad 133c with a wire 132 in a state where the resin 134 is seen through from above the device. It is drawn. The mounting positions of the LED bare chips are regularly arranged at the center of the device, but the die bonding pad 133b and the wire pad 133c are alternately extended to the electrode terminal patterns 133a at both ends, and the wires 132 are also alternately connected in the connecting direction. Has been changed. Further, every other polarity identification mark 135 is arranged so that the division line and the center of the polarity identification mark 135 overlap.
FIG. 13 (b) shows a connection circuit diagram in the state of FIG. 13 (a). Each diode symbol is repeatedly connected in a staircase pattern in an anti-parallel state.

ここで図１３（ａ）に示す如く、溝中心が分割ライン中心と重なるように、かつ一つ置きに配置された極性識別マーク上のみにすりわり状の溝加工をすればよい。分割ラインに沿って切断・分離すれば前記帯状領域７ｂのないチップ型ＬＥＤが得られる。   Here, as shown in FIG. 13 (a), a slotted groove may be formed only on the polarity identification marks arranged so that the center of the groove overlaps with the center of the dividing line. If it cuts and isolate | separates along a division line, chip type LED without the said strip | belt-shaped area | region 7b will be obtained.

尚、ここではＬＥＤを例として説明したが、フォトダイオードの場合も同様の措置が可能である。また三端子以上の装置の場合は前述の第二の実施形態により同様な措置が可能である。また、多面付け回路基板の個々のパターン方向を互い違いに配置していく方法の他にここのパターン間隔を空けて分割を二本のラインで行うようにしても同様に帯状領域７ｂのないものが得られる。   In addition, although LED was demonstrated here as an example, the same measure is possible also in the case of a photodiode. In the case of an apparatus having three or more terminals, the same measures can be taken according to the second embodiment described above. In addition to the method in which the individual pattern directions of the multi-sided circuit board are arranged alternately, even if the division is performed with two lines with the pattern interval therebetween, there is also no band-like region 7b. can get.

（第四の実施形態）前記帯状領域は短手方向に少なくとも０．３ｍｍ以上の幅が必要であるため、特に小型化が求められるチップ型ＬＥＤの場合には、図１４（ａ）に示すように、電極端子パターン１４１の四隅に基板短手方向に幅Ｗ４の切り欠きを入れるような基板形状であってもよい。ここで前記幅Ｗ４は前記帯状領域の短手方向の幅と同程度とする。
図１４（ｂ）にプリント基板のはんだ付けパターンにマウントした状態を示す。１４５ははんだ付けパターンである。前記幅Ｗ４により、実装されるプリント基板のはんだ付けパターン長手幅Ｗ５は、２ＸＷ４分だけ短くすることができる。
一般的に面実装部品のはんだ付けパターンははんだ付け時のフィレット形成のため電極端子に対して左右両端に０．２〜０．３ｍｍ程度の余裕（クリアランス）をとるのが普通である。
従って、この措置により実装されるプリント基板への実装面積を極端に大きくすることのないチップ型ＬＥＤとすることができる。 (Fourth Embodiment) Since the band-like region needs to have a width of at least 0.3 mm or more in the short direction, as shown in FIG. Further, the substrate shape may be such that notches having a width W4 are formed at the four corners of the electrode terminal pattern 141 in the lateral direction of the substrate. Here, the width W4 is approximately the same as the width of the belt-like region in the short direction.
FIG. 14B shows a state mounted on the soldering pattern of the printed circuit board. Reference numeral 145 denotes a soldering pattern. With the width W4, the soldering pattern longitudinal width W5 of the printed circuit board to be mounted can be shortened by 2 × W4.
In general, the soldering pattern of the surface-mounted component usually has a margin of about 0.2 to 0.3 mm (clearance) at the left and right ends with respect to the electrode terminal in order to form a fillet at the time of soldering.
Therefore, it is possible to obtain a chip-type LED that does not extremely increase the mounting area on the printed board mounted by this measure.

尚、本発明における四角形の基板における四角形とは包絡的な意味をも有するものであって、上記図１４（ａ）のような形状変化を含むものである。
当業者であれば図１４（ａ）の四隅の切り欠きは例えばスルーホールによるコンジット形成により容易に作成可能と理解されるであろう。 In addition, the square in the square board | substrate in this invention also has an envelope meaning, and includes the shape change like the said Fig.14 (a).
It will be understood by those skilled in the art that the notches at the four corners in FIG. 14 (a) can be easily formed by forming a conduit with a through hole, for example.

以上述べたように、本発明によれば、不透明な樹脂により封止されたチップ型光半導体装置において、極性識別マークを封止樹脂の光入出力面に設たり、外側の電極上に配置形成したりする必要がないため、極性識別マーク形成のために樹脂封止金型や治具を複雑にせず、外側の電極部スペースを極小化でき、且つプリント基板等へ実装後も表面から識別できる極性識別マークとすることできる。   As described above, according to the present invention, in the chip type optical semiconductor device sealed with an opaque resin, the polarity identification mark is provided on the light input / output surface of the sealing resin, or disposed on the outer electrode. Therefore, it is possible to minimize the outer electrode space and to identify from the surface even after mounting on a printed circuit board, etc. It can be a polarity identification mark.

１ ＬＥＤベアチップ
３１ 受光ベアチップ
２，３２ 基板部
３，３３ 樹脂封止部
４ａ，４ｂ，３４ａ，３４ｂ 端子電極パターン
５，３５ 極性識別マーク
６ 金線
７ａ，３７ａ 帯状領域
１０１ 刃幅の大きいダイサーブレード
１０５ 分割ライン
１０６ 刃幅の大きいダイサーブレード DESCRIPTION OF SYMBOLS 1 LED bare chip 31 Light-receiving bare chip 2,32 Substrate part 3,33 Resin sealing part 4a, 4b, 34a, 34b Terminal electrode pattern 5,35 Polarity identification mark 6 Gold wire 7a, 37a Strip area 101 Dicer blade 105 with large blade width Dividing line 106 Dicer blade with large blade width

Claims (5)

一対の対向する二辺縁部の各々には表裏両面に敷設され側面を介して導通される少なくとも一つ以上の電極端子パターンと、表面中央部の光半導体ベアチップ実装領域で光半導体ベアチップに接続される複数のボンディングパッドと、前記ボンディングパッドと前記電極端子パターンの各々を繋ぐ複数の配線パターンが形成された四角形の基板と
前記光半導体ベアチップ実装領域に実装された光半導体ベアチップと、
前記光半導体ベアチップと前記光半導体ベアチップ実装領域周辺部および前記配線パターンとを覆う樹脂封止部を備えた表面実装型光半導体装置において
前記基板の表面には光半導体ベアチップ実装領域を避けて、電極端子パターン形成されていない二辺のいずれかに沿うように、レジストもしくはシルク版による短冊状パターンが形成され
前記封止樹脂部は透明樹脂に透過率低下部材が混和されており、
さらに、前記封止樹脂部における前記短冊状パターンの上の領域が、半導体ベアチップ実装領域上の領域よりも薄くした帯状に形成され、該帯状領域を通して前記短冊状パターンが視認可能であることを特徴とする表面実装型光半導体装置。 At least one electrode terminal pattern that is laid on both the front and back sides and is conducted through the side surfaces on each of a pair of two opposite edges, and is connected to the optical semiconductor bare chip at the optical semiconductor bare chip mounting region at the center of the surface. A plurality of bonding pads, a rectangular substrate on which a plurality of wiring patterns connecting the bonding pads and the electrode terminal patterns are formed, and an optical semiconductor bare chip mounted on the optical semiconductor bare chip mounting region,
In the surface-mount type optical semiconductor device having a resin-sealed portion covering the optical semiconductor bare chip, the optical semiconductor bare chip mounting region peripheral portion, and the wiring pattern, an electrode avoiding the optical semiconductor bare chip mounting region on the surface of the substrate. Along with one of the two sides where the terminal pattern is not formed, a strip-like pattern is formed by a resist or a silk plate, and the sealing resin portion is mixed with a transparent resin with a transmittance decreasing member,
Furthermore, the region above the strip-shaped pattern in the sealing resin portion is formed in a strip shape thinner than the region on the semiconductor bare chip mounting region, and the strip-shaped pattern is visible through the strip-shaped region. Surface mount type optical semiconductor device. 表面中央部の光半導体ベアチップ実装領域で光半導体ベアチップに接続されるボンディングパッドと、裏面部には電極端子パターンと、前記ボンディングパッドと裏面の前記電極端子パターンをスルーホールを介して導通させる配線パターンを複数組形成された四角形の基板と、
前記光半導体ベアチップ実装領域に実装された光半導体ベアチップと、
前記基板の表面の全面を覆う封止樹脂部を備えた表面実装型光半導体装置において
前記基板の表面には光半導体ベアチップ実装領域を避けて、四辺のいずれかに沿うように、レジストもしくはシルク版による短冊状パターンが形成され
前記封止樹脂部は透明樹脂に透過率低下部材が混和されており、
さらに、前記封止樹脂部における前記短冊状パターンの上の領域が、半導体ベアチップ実装領域上の領域よりも薄くした帯状に形成され、該帯状領域を通して前記短冊状パターンが視認可能であることを特徴とする表面実装型光半導体装置。 Bonding pads connected to the optical semiconductor bare chip in the optical semiconductor bare chip mounting area at the center of the front surface, electrode terminal patterns on the back surface, and wiring patterns for conducting the bonding pads and the electrode terminal patterns on the back surface through through holes A plurality of rectangular substrates formed,
An optical semiconductor bare chip mounted in the optical semiconductor bare chip mounting region;
In a surface mount type optical semiconductor device provided with a sealing resin portion covering the entire surface of the substrate, a resist or a silk plate is provided along one of the four sides on the surface of the substrate, avoiding an optical semiconductor bare chip mounting region. A strip-shaped pattern is formed, and the sealing resin portion is mixed with a transparent resin and a transmittance decreasing member,
Furthermore, the region above the strip-shaped pattern in the sealing resin portion is formed in a strip shape thinner than the region on the semiconductor bare chip mounting region, and the strip-shaped pattern is visible through the strip-shaped region. Surface mount type optical semiconductor device. 前記透過率低下部材は蛍光体顔料である請求項１あるいは２記載の表面実装型光半導体装置。   The surface-mount optical semiconductor device according to claim 1, wherein the transmittance decreasing member is a phosphor pigment. 前記透過率低下部材が混和された透明樹脂は可視光カット樹脂で、カットオフ波長以下の短波長側に透過率ピークが５％以下のバンドパス波長領域を有しているものであり、
前記短冊状パターンの色または前記基板の表面色のどちらかが前記バンドパス波長領域内のいずれかの波長で示される色が選択されていることを特徴とする請求項１あるいは２記載の表面実装型光半導体装置。 The transparent resin mixed with the transmittance lowering member is a visible light cut resin, and has a bandpass wavelength region having a transmittance peak of 5% or less on the short wavelength side below the cutoff wavelength,
3. The surface mounting according to claim 1, wherein a color indicated by any one of wavelengths in the bandpass wavelength region is selected as either the color of the strip pattern or the surface color of the substrate. Type optical semiconductor device. 分割ラインに沿う所定の位置に前記短冊状パターンが形成された請求項１または２における四角形の基板回路パターンが複数個形成された多面付け基板を用意する工程と、
前記多面付け基板に取り数に応じた数の光半導体ベアチップを前記回路基板に実装し、回路と接続するボンディング工程と、
光半導体ベアチップが実装された前記面付け回路基板の光半導体ベアチップ実装面側に透過率低下部材が混和された樹脂を塗布あるいは成形型により注入した後に加熱硬化させて行う樹脂封止工程と、
多面付け基板の分割ラインに重なるように前記短冊状パターンが視認可能となる樹脂厚みですりわり状の溝を削成する溝削成工程と、
前記溝の幅以下の刃幅を持つ切断機で前記溝幅内の分割ラインに沿って、前記回路基板と前記溝底面の樹脂を同時に切断した後に分離する切断・分離工程からなることを特徴とする請求項１乃至４記載の表面実装型光半導体装置の製造方法。 A step of preparing a multi-sided substrate in which a plurality of rectangular substrate circuit patterns according to claim 1 or 2 in which the strip pattern is formed at a predetermined position along a dividing line;
A bonding step of mounting a number of optical semiconductor bare chips on the multi-sided substrate according to the number to be mounted on the circuit board and connecting to the circuit;
A resin sealing step that is performed by applying a resin mixed with a transmittance lowering member to the optical semiconductor bare chip mounting surface side of the surface mounted circuit board on which the optical semiconductor bare chip is mounted, or by heat-curing after injecting by a mold;
A groove cutting step of cutting a slot-shaped groove with a resin thickness such that the strip-like pattern is visible so as to overlap the dividing line of the multi-sided substrate;
It comprises a cutting / separating step of separating the circuit board and the resin at the bottom of the groove simultaneously after being cut along a dividing line within the groove width by a cutting machine having a blade width equal to or less than the width of the groove. A method for manufacturing a surface-mounted optical semiconductor device according to claim 1.
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