JP2012111678A - 空洞筐体用の金属被覆及び非磁性密閉空洞筐体 - Google Patents
空洞筐体用の金属被覆及び非磁性密閉空洞筐体 Download PDFInfo
- Publication number
- JP2012111678A JP2012111678A JP2011145582A JP2011145582A JP2012111678A JP 2012111678 A JP2012111678 A JP 2012111678A JP 2011145582 A JP2011145582 A JP 2011145582A JP 2011145582 A JP2011145582 A JP 2011145582A JP 2012111678 A JP2012111678 A JP 2012111678A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- ceramic
- metal coating
- solderable
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00269—Bonding of solid lids or wafers to the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/10—Mounting in enclosures
- H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
- H03H9/1071—Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the SAW device
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
- B81C2203/0172—Seals
- B81C2203/019—Seals characterised by the material or arrangement of seals between parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/058—Holders; Supports for surface acoustic wave devices
- H03H9/059—Holders; Supports for surface acoustic wave devices consisting of mounting pads or bumps
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/13—Hollow or container type article [e.g., tube, vase, etc.]
- Y10T428/131—Glass, ceramic, or sintered, fused, fired, or calcined metal oxide or metal carbide containing [e.g., porcelain, brick, cement, etc.]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
- Y10T428/2495—Thickness [relative or absolute]
- Y10T428/24967—Absolute thicknesses specified
- Y10T428/24975—No layer or component greater than 5 mils thick
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/26—Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension
- Y10T428/263—Coating layer not in excess of 5 mils thick or equivalent
- Y10T428/264—Up to 3 mils
- Y10T428/265—1 mil or less
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Acoustics & Sound (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Products (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
【解決手段】セラミック10用の金属被覆30は、金属を有する基底層12と、パラジウムを含み、層厚さが0.1〜5μmの間にある接着層14と、非強磁性材質のはんだづけ可能層16と酸化保護層20とを含み、接着層14の材質がはんだづけ可能層16の材質と異なる。
【選択図】図1
Description
高分解能を得るために、MRIシステムは複数の磁性誘導コイルを用いて作動する。そこでは、各々のコイルに関するシグナルは、典型的には個別の電子回路を介してプロセスされる。この電子回路は、典型的にはMRIシステムの内部で作動するので、フィールド障害を防止するために、全ての採用される構成要素は完全に非磁性でなければならない(すなわち、強磁性材質を含んではならない)。
本発明の目的は、金属被覆と筐体技術とを開示することであり、その技術は、一方で、信頼性高く密閉可能で、例えば、SAWフィルタチップを取り付けるのに適する低コストマイクロ空洞を提供し、及び、他方で、強磁場(例、核磁気共鳴画像システム内部)で使用される場合、望ましくない干渉を引き起こす可能性のある強磁性特性を示さない低コストマイクロ空洞を提供する。
本目的は、特許請求の範囲の請求項1の特徴を有する本発明に従って解決される。有利な効果のある本発明の実施形態とその変形を従属請求項に記載する。
図1は、本発明の好ましい実施形態に従う、本発明に係る金属被覆30を有するセラミック10を示す。この実施形態によれば、金属被覆30は、タングステン又はモリブデン基底層12、その上に堆積されるパラジウム接着層14、その上に堆積されるはんだづけ可能な銅層16、その上に堆積されるパラジウム拡散障壁18、及び金表面処理20を含む。
10 セラミック
12 基底層
14 接着層
16 はんだづけ可能層
18 追加層
20 酸化保護層
22 底部
24 カバー部分
26 構成要素
28 空洞筐体
30 金属被覆
32 金属はんだ
34 ボンドワイヤ
36 プリント基板配線
38 プリント基板
40 金属はんだ
42 ガラスフリットはんだ
Claims (15)
- 金属を含む基底層(12)と、
接着層(14)と、
非強磁性材質で製造されるはんだづけ可能層(16)と、
酸化保護層(20)とを含み、
前記接着層(14)がパラジウムを含み及び前記接着層(14)の層厚さが0.1〜5.0μmであり、
前記接着層(14)の材質が前記はんだづけ可能層(16)の材質と異なる、セラミック用金属被覆(30)。 - 前記はんだづけ可能層(16)が銅で製造され及び/又は前記はんだづけ可能層(16)の層厚さが2〜15μmの間であることを特徴とする、請求項1記載の金属被覆(30)。
- 追加層(18)が前記はんだづけ可能層(16)と前記酸化保護層(20)との間に配置されることを特徴とする、請求項1又は2に記載の金属被覆(30)。
- 前記追加層(18)がパラジウムで製造され及び/又は前記追加層(18)の層厚さが0.5〜3.0μmの間であることを特徴とする、請求項3記載の金属被覆(30)。
- 前記接着層(14)がパラジウムで製造され及び層厚さが0.3〜1.3μmの間であることを特徴とする、請求項1〜4のいずれか一項に記載の金属被覆(30)。
- 前記基底層(12)が少なくとも1100℃の融点を有する金属を含むことを特徴とする、請求項1〜5のいずれか一項に記載の金属被覆(30)。
- 前記基底層(12)がタングステン/モリブデンで製造され及び/又は前記基底層(12)の層厚さが5〜20μmであることを特徴とする、請求項6記載の金属被覆(30)。
- 前記酸化保護層(20)が金で製造され及び/又は前記酸化保護層(20)の層厚さが0.3〜1.5μmであることを特徴とする、請求項1〜7のいずれか一項に記載の金属被覆(30)。
- 前記基底層(12)が前記セラミック(10)上に直接配置され、及び/又は前記接着層(14)が前記基底層(12)上に直接配置され、及び/又は前記はんだづけ可能層(16)が前記接着層(14)上に直接配置されることを特徴とする、請求項1〜8のいずれか一項に記載の金属被覆(30)。
- 前記追加層(18)又は前記酸化保護層(20)が前記はんだづけ可能層(16)上に直接配置されることを特徴とする、請求項1〜9のいずれか一項に記載の金属被覆(30)。
- 請求項1〜10のいずれか一項に記載の金属被覆(30)を含む、セラミック(10)。
- 前記セラミック(10)がHTCCセラミックであることを特徴とする、請求項11記載のセラミック(10)。
- 底部(22)とカバー部分(24)とを有し、
前記底部(22)及び/又はカバー部分(24)が、請求項11又は12に記載のセラミック(10)を含む、構成要素(26)を受け入れるための空洞筐体(28)。 - 前記構成要素(26)がSAW素子であることを特徴とする、請求項13記載の空洞筐体(28)。
- ダイボンドプロセス及び/若しくはワイヤボンドプロセスを介するか、又はフリップチップボンディングを介して構成要素26を取り付けるための、請求項11又は12に記載のセラミック(10)の使用。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102010030778 | 2010-06-30 | ||
DE102010030778.5 | 2010-06-30 | ||
DE102010024543.5 | 2010-10-15 | ||
DE102010042543.5A DE102010042543B4 (de) | 2010-06-30 | 2010-10-15 | Metallisierung für Hohlraumgehäuse und nicht-magnetisches hermetisch dichtes Hohlraumgehäuse |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012111678A true JP2012111678A (ja) | 2012-06-14 |
JP5795203B2 JP5795203B2 (ja) | 2015-10-14 |
Family
ID=44801072
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011145582A Active JP5795203B2 (ja) | 2010-06-30 | 2011-06-30 | 空洞筐体用の金属被覆及び非磁性密閉空洞筐体 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9023442B2 (ja) |
JP (1) | JP5795203B2 (ja) |
DE (1) | DE102010042543B4 (ja) |
NL (1) | NL2007028C2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017534178A (ja) * | 2014-10-31 | 2017-11-16 | ゼネラル・エレクトリック・カンパニイ | 非磁性パッケージおよび製造方法 |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10177054B2 (en) | 2011-10-27 | 2019-01-08 | Global Circuit Innovations, Inc. | Method for remapping a packaged extracted die |
US9966319B1 (en) | 2011-10-27 | 2018-05-08 | Global Circuit Innovations Incorporated | Environmental hardening integrated circuit method and apparatus |
US10147660B2 (en) | 2011-10-27 | 2018-12-04 | Global Circuits Innovations, Inc. | Remapped packaged extracted die with 3D printed bond connections |
US10109606B2 (en) | 2011-10-27 | 2018-10-23 | Global Circuit Innovations, Inc. | Remapped packaged extracted die |
US10002846B2 (en) | 2011-10-27 | 2018-06-19 | Global Circuit Innovations Incorporated | Method for remapping a packaged extracted die with 3D printed bond connections |
US9935028B2 (en) | 2013-03-05 | 2018-04-03 | Global Circuit Innovations Incorporated | Method and apparatus for printing integrated circuit bond connections |
US10128161B2 (en) | 2011-10-27 | 2018-11-13 | Global Circuit Innovations, Inc. | 3D printed hermetic package assembly and method |
US9870968B2 (en) | 2011-10-27 | 2018-01-16 | Global Circuit Innovations Incorporated | Repackaged integrated circuit and assembly method |
JP6167494B2 (ja) * | 2012-09-26 | 2017-07-26 | セイコーエプソン株式会社 | 電子デバイス用容器の製造方法、電子デバイスの製造方法、電子デバイス、電子機器及び移動体機器 |
EP2725715B1 (en) * | 2012-10-29 | 2018-12-12 | Optosys SA | Proximity sensor |
US9810751B2 (en) * | 2014-02-24 | 2017-11-07 | Northrop Grumman Systems Corporation | Customized magnetic susceptibility materials |
US10196745B2 (en) | 2014-10-31 | 2019-02-05 | General Electric Company | Lid and method for sealing a non-magnetic package |
US10115645B1 (en) | 2018-01-09 | 2018-10-30 | Global Circuit Innovations, Inc. | Repackaged reconditioned die method and assembly |
US11244876B2 (en) | 2019-10-09 | 2022-02-08 | Microchip Technology Inc. | Packaged semiconductor die with micro-cavity |
CN111933577B (zh) * | 2020-07-15 | 2022-05-31 | 中国电子科技集团公司第二十九研究所 | 一种气密封装单元局部大面积焊接板级互连集成方法 |
US11508680B2 (en) | 2020-11-13 | 2022-11-22 | Global Circuit Innovations Inc. | Solder ball application for singular die |
CN115425938A (zh) * | 2022-09-28 | 2022-12-02 | 天通瑞宏科技有限公司 | 高可靠性csp封装方法和声表面波滤波器 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002353375A (ja) * | 2001-05-25 | 2002-12-06 | Kyocera Corp | 配線基板 |
JP2003142789A (ja) * | 2001-11-02 | 2003-05-16 | Kyocera Corp | 配線基板 |
JP2005289665A (ja) * | 2004-03-31 | 2005-10-20 | Ebara Corp | セラミックスの金属被覆方法または接合方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5058799A (en) * | 1986-07-24 | 1991-10-22 | Zsamboky Kalman F | Metallized ceramic substrate and method therefor |
JPH0741159Y2 (ja) | 1988-10-07 | 1995-09-20 | 日本特殊陶業株式会社 | 気密封止型セラミックパッケージ |
JP2984068B2 (ja) * | 1991-01-31 | 1999-11-29 | 株式会社日立製作所 | 半導体装置の製造方法 |
US7253029B2 (en) | 2004-03-10 | 2007-08-07 | M/A-Com, Inc. | Non-magnetic, hermetically-sealed micro device package |
-
2010
- 2010-10-15 DE DE102010042543.5A patent/DE102010042543B4/de active Active
-
2011
- 2011-06-30 NL NL2007028A patent/NL2007028C2/nl active
- 2011-06-30 JP JP2011145582A patent/JP5795203B2/ja active Active
- 2011-06-30 US US13/173,017 patent/US9023442B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002353375A (ja) * | 2001-05-25 | 2002-12-06 | Kyocera Corp | 配線基板 |
JP2003142789A (ja) * | 2001-11-02 | 2003-05-16 | Kyocera Corp | 配線基板 |
JP2005289665A (ja) * | 2004-03-31 | 2005-10-20 | Ebara Corp | セラミックスの金属被覆方法または接合方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017534178A (ja) * | 2014-10-31 | 2017-11-16 | ゼネラル・エレクトリック・カンパニイ | 非磁性パッケージおよび製造方法 |
Also Published As
Publication number | Publication date |
---|---|
NL2007028C2 (nl) | 2013-08-08 |
DE102010042543A1 (de) | 2012-01-05 |
US9023442B2 (en) | 2015-05-05 |
US20120177853A1 (en) | 2012-07-12 |
DE102010042543B4 (de) | 2017-06-29 |
JP5795203B2 (ja) | 2015-10-14 |
NL2007028A (nl) | 2012-01-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5795203B2 (ja) | 空洞筐体用の金属被覆及び非磁性密閉空洞筐体 | |
JP4049239B2 (ja) | 表面弾性波素子を含む高周波モジュール部品の製造方法 | |
US20070267725A1 (en) | Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package | |
JP2005167969A (ja) | 弾性波素子および弾性波素子の製造方法 | |
JP2002100877A (ja) | セラミック多層基板の表面電極構造及び表面電極の製造方法 | |
JPH05206356A (ja) | 集積回路用パッケージ | |
JP2002084155A (ja) | 表面弾性波素子を含む高周波モジュール部品の製造方法 | |
JP2010045201A (ja) | 電子部品モジュール及びその製造方法 | |
JP2005039168A (ja) | セラミック容器およびそれを用いたタンタル電解コンデンサ | |
JP4582352B2 (ja) | 表面弾性波素子を含む高周波モジュール部品及びその集合体 | |
JP5537119B2 (ja) | 蓋体並びに蓋体の製造方法および電子装置の製造方法 | |
JP2013110214A (ja) | 電子部品収納用パッケージ | |
JP2005072421A (ja) | 電子部品収納用パッケージおよび電子装置 | |
JP3866128B2 (ja) | 配線基板 | |
US8358003B2 (en) | Surface mount electronic device packaging assembly | |
JP4828980B2 (ja) | 接合部材及びその製造方法ならびに接合構造体及び基体の接続方法 | |
JP2004079965A (ja) | 光半導体モジュールとその製造方法 | |
JP2004296791A (ja) | 電波吸収蓋部材およびこれを用いた高周波装置 | |
JP2004140111A (ja) | 配線基板 | |
JP6809813B2 (ja) | 半導体パッケージおよび半導体装置 | |
JP3881542B2 (ja) | 配線基板 | |
JP2015076584A (ja) | 電子部品収納用パッケージ | |
JP2685159B2 (ja) | 電子部品収納用パッケージ | |
JP3176246B2 (ja) | 半導体素子収納用パッケージ | |
JP2003303910A (ja) | 配線基板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20121011 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20131226 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140115 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140414 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20141125 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150128 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150630 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150701 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150728 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150812 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5795203 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |