JP2012084707A - Apparatus and method of silicon nitride film formation - Google Patents

Apparatus and method of silicon nitride film formation Download PDF

Info

Publication number
JP2012084707A
JP2012084707A JP2010230189A JP2010230189A JP2012084707A JP 2012084707 A JP2012084707 A JP 2012084707A JP 2010230189 A JP2010230189 A JP 2010230189A JP 2010230189 A JP2010230189 A JP 2010230189A JP 2012084707 A JP2012084707 A JP 2012084707A
Authority
JP
Japan
Prior art keywords
silicon nitride
nitride film
gas
film
film forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010230189A
Other languages
Japanese (ja)
Inventor
Yuichi Kono
雄一 河野
Toshihiko Nishimori
年彦 西森
Tadashi Shimazu
正 嶋津
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Heavy Industries Ltd
Original Assignee
Mitsubishi Heavy Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Heavy Industries Ltd filed Critical Mitsubishi Heavy Industries Ltd
Priority to JP2010230189A priority Critical patent/JP2012084707A/en
Priority to PCT/JP2011/071081 priority patent/WO2012049943A1/en
Priority to TW100134198A priority patent/TW201220400A/en
Publication of JP2012084707A publication Critical patent/JP2012084707A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C23C16/345—Silicon nitride
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/515—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using pulsed discharges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment

Abstract

PROBLEM TO BE SOLVED: To provide an apparatus and a method of silicon nitride film formation for performing implantation between fine elements without generating particles.SOLUTION: A method of silicon nitride film formation comprises the steps of supplying material gas (SiHetc.) for forming a silicon nitride film to create a plasma of the material gas when forming the silicon nitride film on a substrate, performing a deposition step of depositing the silicon nitride film by use of the plasma of the material gas, supplying only an inert gas after performing the deposition step, applying bias to the substrate to create plasma of the inert gas, performing a sputter step of bias sputtering the silicon nitride film by use of the plasma of the inert gas, and alternately performing the deposition step and the sputter step.

Description

本発明は、窒化珪素膜形成装置及び方法に関する。   The present invention relates to a silicon nitride film forming apparatus and method.

半導体デバイス等の半導体装置では、その保護膜として、酸化珪素膜や窒化珪素膜等が用いられており、プラズマＣＶＤ（Chemical Vapor Deposition）装置等を用いて形成されている。   In a semiconductor device such as a semiconductor device, a silicon oxide film, a silicon nitride film, or the like is used as a protective film, and is formed using a plasma CVD (Chemical Vapor Deposition) apparatus or the like.

特開平１１−３４０２１７号公報Japanese Patent Laid-Open No. 11-340217

半導体デバイスの素子部分には、その機能に応じて、様々な材料が用いられており、その材料の性質によっては、素子自体を保護膜で保護する必要がある。例えば、近年、記憶用の半導体デバイスとして、ＭＲＡＭ（Magnetic Random Access Memory）の開発が進められているが、その記憶素子であるＭＴＪ（Magnetic Tunnel Junction；磁気トンネル接合）には磁性体材料が使われており、この磁性体材料は水分と反応して酸化しやすいため、外部から拡散してくる水分がＭＴＪに到達しないように、防水性（耐透湿性）のある保護膜で保護する必要がある。又、保護膜は絶縁体である必要があることから、保護膜の材料としては、耐透湿性があり、絶縁性がある窒化珪素膜（ＳｉＮ膜）が一般的に使われている。   Various materials are used for an element portion of a semiconductor device depending on its function. Depending on the nature of the material, it is necessary to protect the element itself with a protective film. For example, in recent years, MRAM (Magnetic Random Access Memory) has been developed as a semiconductor device for memory, but magnetic material is used for MTJ (Magnetic Tunnel Junction) which is the memory element. Since this magnetic material is easily oxidized by reacting with moisture, it is necessary to protect the moisture diffused from the outside with a protective film having a waterproof property (moisture resistance) so that the MTJ does not reach the MTJ. . In addition, since the protective film needs to be an insulator, a silicon nitride film (SiN film) having moisture permeability resistance and insulation is generally used as the material of the protective film.

ここで、図６、図７に示すＭＲＡＭの素子構造を一例に取って、従来の成膜方法による保護膜の問題点を説明する。図６に示すように、基板３０上には、素子間距離Ｓ１を置いて、コバルト鉄等の磁性体材料からなるＭＴＪ３１が形成される。このＭＴＪ３１を保護する保護膜として、ＳｉＮ膜３２がＭＴＪ３１の段差形状を被覆するように形成される。その後、ＭＴＪ３１同士の間を埋め込むように、ＳｉＮ膜３２上に層間膜となるＳｉＯ膜３３が形成される。ＳｉＮ膜３２が形成されるときに、ＭＴＪ３１のコーナー部分にはオーバーハング部３２ａができるが、素子間距離Ｓ１が大きいときには、ボイドができることなく、ＳｉＯ膜３３を埋め込むことができる。   Here, taking the element structure of the MRAM shown in FIGS. 6 and 7 as an example, problems of the protective film by the conventional film forming method will be described. As shown in FIG. 6, an MTJ 31 made of a magnetic material such as cobalt iron is formed on the substrate 30 with an inter-element distance S1. As a protective film for protecting the MTJ 31, the SiN film 32 is formed so as to cover the step shape of the MTJ 31. Thereafter, a SiO film 33 serving as an interlayer film is formed on the SiN film 32 so as to embed between the MTJs 31. When the SiN film 32 is formed, an overhang portion 32a is formed at the corner portion of the MTJ 31, but when the inter-element distance S1 is large, the SiO film 33 can be embedded without forming a void.

近年、素子の微細化が進んできており、図７に示すように、ＭＴＪ３１同士の素子間距離Ｓ２（Ｓ２＜Ｓ１）が小さくなってきている。素子間距離Ｓ２が小さい場合（例えば、アスペクト比が１：１．５以上の場合）、従来の成膜方法では、オーバーハング部３２ａが素子間の開口部分を狭めてしまうため、ＳｉＯ膜３３で埋め込む際にボイド３４ができてしまう。その結果、素子間の絶縁性が低下し、デバイス信頼性の低下に繋がる。従って、素子間距離が小さい場合でも、ボイドなく、保護膜を形成することが求められている。   In recent years, element miniaturization has progressed, and as shown in FIG. 7, the inter-element distance S2 (S2 <S1) between the MTJs 31 is decreasing. When the inter-element distance S2 is small (for example, when the aspect ratio is 1: 1.5 or more), in the conventional film formation method, the overhang portion 32a narrows the opening between the elements. When embedding, a void 34 is formed. As a result, the insulation between elements is lowered, leading to a reduction in device reliability. Therefore, even when the distance between elements is small, it is required to form a protective film without voids.

一方、絶縁膜の埋め込み技術として、高密度プラズマＣＶＤ法により、成膜とバイアススパッタを同時に行って、ＳｉＯ膜を埋め込む成膜方法が広く使われている。この成膜方法において、原料ガスを窒素系ガスに変えれば、素子間を埋め込む膜としても、ＳｉＮ膜を用いることが可能である。   On the other hand, as a technique for embedding an insulating film, a film forming method for embedding a SiO film by simultaneously performing film formation and bias sputtering by a high density plasma CVD method is widely used. In this film forming method, if the source gas is changed to a nitrogen-based gas, it is possible to use a SiN film as a film for embedding between elements.

ここで、図８を参照して、高密度プラズマＣＶＤ法によるＳｉＮ膜の成膜方法を説明すると共に、図９を参照して、ＭＲＡＭに適用した場合の素子構造を説明する。高密度プラズマＣＶＤ法によるＳｉＮ膜の成膜方法においては、原料ガスであるＳｉＨ4ガス、窒素系ガス（例えば、Ｎ2ガス、ＮＨ3ガス等）を供給し、これらのガスを高密度のプラズマ状態とし、この状態で、基板にバイアスを印加して、ＳｉＮ膜の成膜を行っている。例えば、ＳｉＨ4ガスとバイアスのタイムチャートを示すと、図８のようになり、ＳｉＨ4ガスを供給し、バイアスを印加しているとき、成膜（デポ）とバイアススパッタが同時に行われている。つまり、成膜とバイアススパッタを同時に行うことにより、バイアススパッタによりオーバーハング部を削りながら、成膜を行っている。 Here, with reference to FIG. 8, a method of forming a SiN film by high-density plasma CVD will be described, and an element structure when applied to an MRAM will be described with reference to FIG. In a method of forming a SiN film by a high density plasma CVD method, SiH 4 gas and a nitrogen-based gas (for example, N 2 gas, NH 3 gas, etc.) that are source gases are supplied, and these gases are used as high density plasma. In this state, a SiN film is formed by applying a bias to the substrate. For example, a time chart of SiH 4 gas and bias is shown in FIG. 8, and when SiH 4 gas is supplied and bias is applied, film formation (deposition) and bias sputtering are performed simultaneously. . In other words, by performing film formation and bias sputtering at the same time, film formation is performed while removing the overhang portion by bias sputtering.

このように、成膜とバイアススパッタを同時に行うと、図９に示すように、ＭＴＪ３１同士の素子間距離Ｓ２が小さい場合でも、ボイドができることなく、素子同士の間をＳｉＮ膜３２で埋め込むことが可能である。しかしながら、この成膜方法で成膜したＳｉＮ膜は、埋め込みはできるが、膜が剥離するという問題があり、この剥離に起因して、パーティクルが発生するという問題がある。そのため、このような成膜方法は、ＳｉＮ膜の埋め込み技術として、半導体デバイスの製造に適用されていない。   In this way, when film formation and bias sputtering are performed simultaneously, as shown in FIG. 9, even when the inter-element distance S2 between the MTJs 31 is small, voids are not formed and the inter-elements are embedded with the SiN film 32. Is possible. However, although the SiN film formed by this film forming method can be embedded, there is a problem that the film is peeled off, and there is a problem that particles are generated due to the peeling. Therefore, such a film forming method is not applied to the manufacture of a semiconductor device as an SiN film embedding technique.

従って、素子間距離が小さい場合、依然として、ＳｉＮ膜の埋め込み技術は確立しておらず、素子間距離が小さい場合でも、膜剥離やパーティクルの問題を起こすことなく、ＳｉＮ膜を埋め込む技術が求められている。   Therefore, when the inter-element distance is small, the SiN film embedding technique has not yet been established, and even when the inter-element distance is small, a technique for embedding the SiN film without causing film peeling or particle problems is required. ing.

本発明は上記課題に鑑みなされたもので、パーティクルを発生させずに、微細な素子間への埋め込みを行う窒化珪素膜形成装置及び方法を提供することを目的とする。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a silicon nitride film forming apparatus and method for embedding between fine elements without generating particles.

上記課題を解決する第１の発明に係る窒化珪素膜形成装置は、
基板上に窒化珪素膜を形成する窒化珪素膜形成装置において、
前記窒化珪素膜を形成するための原料ガスと希ガスと不活性ガスとを含めて、複数のガスを供給するガス供給手段と、
前記ガスのプラズマを生成するプラズマ生成手段と、
前記基板にバイアスを印加するバイアス印加手段と、
前記ガス供給手段、前記プラズマ生成手段及び前記バイアス印加手段を制御する制御手段とを有し、
前記制御手段は、
前記ガス供給手段により、少なくとも前記原料ガスを供給し、前記プラズマ生成手段により、少なくとも前記原料ガスのプラズマを生成し、当該プラズマを用いて前記窒化珪素膜を成膜する成膜工程を実施し、
前記成膜工程の後、前記ガス供給手段により、前記希ガス又は前記不活性ガス又は前記希ガス及び前記不活性ガスを供給し、前記バイアス印加手段により前記基板へバイアスを印加し、前記プラズマ生成手段により、前記希ガス又は前記不活性ガス又は前記希ガス及び前記不活性ガスのプラズマを生成し、当該プラズマを用いて前記窒化珪素膜をバイアススパッタするスパッタ工程を実施することを特徴とする。 A silicon nitride film forming apparatus according to a first invention for solving the above-mentioned problems is
In a silicon nitride film forming apparatus for forming a silicon nitride film on a substrate,
A gas supply means for supplying a plurality of gases including a source gas, a rare gas, and an inert gas for forming the silicon nitride film;
Plasma generating means for generating plasma of the gas;
Bias applying means for applying a bias to the substrate;
Control means for controlling the gas supply means, the plasma generation means and the bias application means,
The control means includes
Supplying at least the source gas by the gas supply means, generating plasma of at least the source gas by the plasma generation means, and performing a film forming step of forming the silicon nitride film using the plasma;
After the film forming step, the gas supply means supplies the rare gas or the inert gas or the rare gas and the inert gas, the bias application means applies a bias to the substrate, and the plasma generation According to the present invention, a plasma process of generating the rare gas, the inert gas, or the rare gas and the inert gas is generated, and a sputtering process is performed in which the silicon nitride film is bias-sputtered using the plasma.

上記課題を解決する第２の発明に係る窒化珪素膜形成装置は、
上記第１の発明に記載の窒化珪素膜形成装置において、
前記制御手段は、前記成膜工程と前記スパッタ工程とを交互に複数回実施することを特徴とする。 A silicon nitride film forming apparatus according to a second invention for solving the above-mentioned problems is as follows.
In the silicon nitride film forming apparatus according to the first invention,
The control means performs the film forming step and the sputtering step alternately a plurality of times.

上記課題を解決する第３の発明に係る窒化珪素膜形成装置は、
上記第１又は第２の発明に記載の窒化珪素膜形成装置において、
前記制御手段は、
前記成膜工程において、前記基板上に成膜する第１層目の前記窒化珪素膜の膜厚をＴ（ｎｍ）とし、前記スパッタ工程において、前記基板へ印加するバイアスパワーを前記基板の面積で除算したバイアスパワー密度をＢ（Ｗ／ｃｍ2）とするとき、
［Ｂ／Ｔ≦０．０８］の条件を満たすように、前記成膜工程及び前記スパッタ工程を実施することを特徴とする。 A silicon nitride film forming apparatus according to a third invention for solving the above-mentioned problems is as follows.
In the silicon nitride film forming apparatus according to the first or second invention,
The control means includes
In the film formation step, the film thickness of the first silicon nitride film formed on the substrate is T (nm), and in the sputtering step, the bias power applied to the substrate is the area of the substrate. When the divided bias power density is B (W / cm 2 ),
The film forming step and the sputtering step are performed so as to satisfy the condition of [B / T ≦ 0.08].

上記課題を解決する第４の発明に係る窒化珪素膜形成方法は、
基板上に窒化珪素膜を形成する窒化珪素膜形成方法において、
前記窒化珪素膜を形成するための原料ガスと希ガスと不活性ガスのうち、少なくとも前記原料ガスを供給し、少なくとも前記原料ガスのプラズマを生成し、当該プラズマを用いて前記窒化珪素膜を成膜する成膜工程と、
前記成膜工程の後、前記希ガス又は前記不活性ガス又は前記希ガス及び前記不活性ガスを供給し、前記基板へバイアスを印加し、前記希ガス又は前記不活性ガス又は前記希ガス及び前記不活性ガスのプラズマを生成し、当該プラズマを用いて前記窒化珪素膜をバイアススパッタするスパッタ工程とを有することを特徴とする。 A silicon nitride film forming method according to a fourth aspect of the present invention for solving the above problem is as follows:
In a silicon nitride film forming method for forming a silicon nitride film on a substrate,
At least the source gas among the source gas, the rare gas, and the inert gas for forming the silicon nitride film is supplied, plasma of the source gas is generated at least, and the silicon nitride film is formed using the plasma. A film forming process to form a film;
After the film forming step, the rare gas or the inert gas or the rare gas and the inert gas are supplied, a bias is applied to the substrate, and the rare gas or the inert gas or the rare gas and the A sputtering step of generating an inert gas plasma and bias sputtering the silicon nitride film using the plasma.

上記課題を解決する第５の発明に係る窒化珪素膜形成方法は、
上記第４の発明に記載の窒化珪素膜形成方法において、
前記成膜工程と前記スパッタ工程とを交互に複数回実施することを特徴とする。 A silicon nitride film forming method according to a fifth invention for solving the above-described problems is as follows.
In the silicon nitride film forming method according to the fourth invention,
The film forming step and the sputtering step are alternately performed a plurality of times.

上記課題を解決する第６の発明に係る窒化珪素膜形成方法は、
上記第４又は第５の発明に記載の窒化珪素膜形成方法において、
前記成膜工程において、前記基板上に成膜する第１層目の前記窒化珪素膜の膜厚をＴ（ｎｍ）とし、前記スパッタ工程において、前記基板へ印加するバイアスパワーを前記基板の面積で除算したバイアスパワー密度をＢ（Ｗ／ｃｍ2）とするとき、
［Ｂ／Ｔ≦０．０８］の条件を満たすように、前記成膜工程及び前記スパッタ工程を実施することを特徴とする。 A silicon nitride film forming method according to a sixth invention for solving the above-described problem is
In the silicon nitride film forming method according to the fourth or fifth invention,
In the film formation step, the film thickness of the first silicon nitride film formed on the substrate is T (nm), and in the sputtering step, the bias power applied to the substrate is the area of the substrate. When the divided bias power density is B (W / cm 2 ),
The film forming step and the sputtering step are performed so as to satisfy the condition of [B / T ≦ 0.08].

第１、第２、第４、第５の発明によれば、パーティクルを発生させずに、微細な素子間への埋め込みを行うことができる。   According to the first, second, fourth, and fifth inventions, it is possible to perform embedding between fine elements without generating particles.

第３、第６の発明によれば、第１層目の窒化珪素膜の界面での剥離を抑制することができる。   According to the third and sixth inventions, peeling at the interface of the first silicon nitride film can be suppressed.

本発明に係る窒化珪素膜形成装置の実施形態の一例を示す概略構成図である。It is a schematic structure figure showing an example of an embodiment of a silicon nitride film formation device concerning the present invention. 窒化珪素膜における膜剥離やパーティクル発生の原因を説明する図である。It is a figure explaining the cause of film | membrane peeling and particle generation in a silicon nitride film. 図１に示した窒化珪素膜形成装置における絶縁膜形成方法の一例（実施例１）を示すタイムチャートである。2 is a time chart showing an example (Example 1) of an insulating film forming method in the silicon nitride film forming apparatus shown in FIG. 成膜工程とスパッタ工程とを交互に実施する場合に起こり得る問題を説明する図である。It is a figure explaining the problem which may occur when performing a film-forming process and a sputtering process alternately. 第１層目の窒化珪素膜の膜厚とバイアスパワーの条件を変えて、剥離の有無を確認した結果を示すグラフである。It is a graph which shows the result of having confirmed the presence or absence of peeling, changing the film thickness of 1st layer silicon nitride film, and the conditions of bias power. 素子間距離が大きいＭＲＡＭ素子構造において、従来の成膜方法で保護膜を形成した場合の素子断面図である。FIG. 11 is a device cross-sectional view when a protective film is formed by a conventional film formation method in an MRAM device structure having a large inter-element distance. 素子間距離が小さいＭＲＡＭ素子構造において、従来の成膜方法で保護膜を形成した場合の素子断面図である。FIG. 10 is a device cross-sectional view when a protective film is formed by a conventional film formation method in an MRAM device structure having a small inter-element distance. 高密度プラズマＣＶＤ法を用いた成膜方法を説明するタイムチャートである。It is a time chart explaining the film-forming method using a high-density plasma CVD method. 素子間距離が小さいＭＲＡＭ素子構造において、図８に示した成膜方法で保護膜を形成した場合の素子断面図である。FIG. 9 is an element cross-sectional view when a protective film is formed by the film forming method shown in FIG. 8 in an MRAM element structure having a small inter-element distance.

以下、図１〜図５を参照して、本発明に係る窒化珪素膜形成装置及び方法の実施形態について説明を行う。   Hereinafter, embodiments of a silicon nitride film forming apparatus and method according to the present invention will be described with reference to FIGS.

（実施例１）
図１は、本発明に係る窒化珪素膜形成装置の実施形態の一例を示す概略構成図である。
本実施例の窒化珪素膜形成装置は、所謂、プラズマＣＶＤ装置である。具体的には、図１に示すように、金属製の円筒状の真空チャンバ１の内部が処理室２として構成されるものであり、真空チャンバ１の上部開口部には、絶縁材料からなる円板状の天井板３が、上部開口部を閉鎖するように配設されている。又、真空チャンバ１の下部には支持台４及び支持台４を保持する下部支持台１０が備えられ、半導体材料からなる基板５（例えば、Ｓｉウェハ）が支持台４の上面に載置される。真空チャンバ１は、例えば、アルミニウム等の金属から構成されて、その内壁がアルマイト処理されており、又、天井板３は、例えば、アルミナ等のセラミクスにより構成されている。 Example 1
FIG. 1 is a schematic configuration diagram showing an example of an embodiment of a silicon nitride film forming apparatus according to the present invention.
The silicon nitride film forming apparatus of this embodiment is a so-called plasma CVD apparatus. Specifically, as shown in FIG. 1, the inside of a metal cylindrical vacuum chamber 1 is configured as a processing chamber 2, and a circular opening made of an insulating material is formed in the upper opening of the vacuum chamber 1. A plate-like ceiling board 3 is disposed so as to close the upper opening. A lower support 10 that holds the support 4 and the support 4 is provided below the vacuum chamber 1, and a substrate 5 (for example, Si wafer) made of a semiconductor material is placed on the upper surface of the support 4. . The vacuum chamber 1 is made of, for example, a metal such as aluminum, and the inner wall thereof is anodized, and the ceiling plate 3 is made of, for example, ceramics such as alumina.

天井板３の上方には、例えば、複数の円形リングからなる高周波アンテナ６が配置されており、高周波アンテナ６には整合器７を介して、数百ｋＨｚ〜数百ＭＨｚの周波数の高周波（ＲＦ）電源８が接続されている（プラズマ生成手段）。又、真空チャンバ１には、処理室２内に所望の複数のガスを導入する複数のガスノズル９が設けられている（ガス供給手段）。   A high-frequency antenna 6 composed of, for example, a plurality of circular rings is disposed above the ceiling plate 3, and a high-frequency (RF) with a frequency of several hundred kHz to several hundred MHz is connected to the high-frequency antenna 6 via a matching unit 7. ) A power source 8 is connected (plasma generating means). The vacuum chamber 1 is provided with a plurality of gas nozzles 9 for introducing a plurality of desired gases into the processing chamber 2 (gas supply means).

又、基板５を支持する支持台４には、電極部１１が設けられており、電極部１１には整合器１２を介して低周波（ＬＦ）電源１３が接続されている。低周波電源１３は、高周波電源８より低い周波数を電極部１１に印加し、基板５にバイアス電力を印加できるようになっている（バイアス印加手段）。なお、図示は省略しているが、支持台４には、静電チャック機構も設けられており、静電チャック用電源からの給電により、基板５を支持台４表面に吸着保持できるようになっている。加えて、図示は省略しているが、本実施例の窒化珪素膜形成装置は、上述したプラズマ生成手段、ガス供給手段、バイアス印加手段を制御する制御装置（制御手段）も備えている。   An electrode unit 11 is provided on the support table 4 that supports the substrate 5, and a low frequency (LF) power source 13 is connected to the electrode unit 11 via a matching unit 12. The low frequency power supply 13 is configured to apply a lower frequency than that of the high frequency power supply 8 to the electrode portion 11 and to apply a bias power to the substrate 5 (bias applying means). Although not shown, the support table 4 is also provided with an electrostatic chuck mechanism, and the substrate 5 can be attracted and held on the surface of the support table 4 by power supply from the electrostatic chuck power source. ing. In addition, although not shown, the silicon nitride film forming apparatus of this embodiment also includes a control device (control means) for controlling the above-described plasma generation means, gas supply means, and bias application means.

上記構成の窒化珪素膜形成装置では、シラン（ＳｉＨ4）、アンモニア（ＮＨ3）、窒素（Ｎ2）等のプロセスガスが、ガスノズル９を介して真空チャンバ１内に導入され、高周波アンテナ６にＲＦパワーを供給することにより、天井板３を介して電磁波が真空チャンバ１に入射され、入射された電磁波により導入されたプロセスガスがプラズマ化されている。そして、プラズマ化されたプロセスガスを用いて、基板５上にＳｉＮ膜を形成している。 In the silicon nitride film forming apparatus configured as described above, a process gas such as silane (SiH 4 ), ammonia (NH 3 ), nitrogen (N 2 ), or the like is introduced into the vacuum chamber 1 through the gas nozzle 9 and is supplied to the high-frequency antenna 6. By supplying RF power, electromagnetic waves are incident on the vacuum chamber 1 through the ceiling plate 3 and the process gas introduced by the incident electromagnetic waves is turned into plasma. Then, a SiN film is formed on the substrate 5 using a plasma process gas.

なお、上記構成の窒化珪素膜形成装置は一例であり、後述する本実施例の窒化珪素膜形成方法を実施できるプラズマＣＶＤ装置であれば、他の構成でもよく、例えば、プラズマ生成手段やガス供給手段等は様々な態様の構成が適用可能である。   The silicon nitride film forming apparatus having the above-described configuration is an example, and any other configuration may be used as long as it is a plasma CVD apparatus capable of performing the silicon nitride film forming method of the present embodiment to be described later. Various configurations can be applied to the means and the like.

ここで、本実施例の窒化珪素膜形成方法を説明する前に、ＳｉＮ膜における膜剥離やパーティクル発生の原因について説明する。ＳｉＮ膜の成膜において、基板５にバイアスを印加し、バイアススパッタしながら成膜すると、基板５の外周側において、膜中及び膜表面上のパーティクルが増加する傾向があった。本発明者等がパーティクル増加の原因を調査したところ、基板５の外周の裏面側傾斜部Ａの部分までＳｉＮ膜が形成されており（図２参照）、この裏面側傾斜部Ａに形成されたＳｉＮ膜が脆くて剥れやすいために、パーティクル源となっているという観測事実があった。一方、基板５にバイアスを印加しない場合には、裏面側傾斜部ＡにＳｉＮ膜は形成されなかった。   Here, before explaining the silicon nitride film forming method of this embodiment, the cause of film peeling and particle generation in the SiN film will be described. In the formation of the SiN film, when a bias is applied to the substrate 5 and the film is formed while performing bias sputtering, particles in the film and on the film surface tend to increase on the outer peripheral side of the substrate 5. When the present inventors investigated the cause of the increase in particles, the SiN film was formed up to the portion of the back side inclined portion A on the outer periphery of the substrate 5 (see FIG. 2), and was formed on the back side inclined portion A. There was an observation fact that the SiN film is a particle source because it is brittle and easily peeled off. On the other hand, when no bias was applied to the substrate 5, the SiN film was not formed on the back side inclined portion A.

従って、パーティクル源となる裏面側傾斜部ＡへのＳｉＮ膜の形成を防止すれば、パーティクルを低減することが可能となる。   Therefore, particles can be reduced by preventing the formation of the SiN film on the back side inclined portion A serving as a particle source.

そこで、本実施例では、上記構成の窒化珪素膜形成装置において、図３に示す窒化珪素膜形成方法を実施することで、裏面側傾斜部ＡへのＳｉＮ膜の形成を防止し、パーティクルを低減するようにしている。以下、図３のタイムチャートを参照して、本実施例の窒化珪素膜形成方法を説明する。   Therefore, in this embodiment, in the silicon nitride film forming apparatus having the above configuration, the silicon nitride film forming method shown in FIG. 3 is performed to prevent the formation of the SiN film on the back-side inclined portion A and to reduce particles. Like to do. Hereinafter, the silicon nitride film forming method of this embodiment will be described with reference to the time chart of FIG.

本実施例の窒化珪素膜形成方法においては、図３に示すように、バイアスを印加しない成膜（デポ）とバイアススパッタとを交互に行うことで、裏面側傾斜部ＡへのＳｉＮ膜の形成を防止し、裏面側傾斜部Ａからの剥離によるパーティクル発生を抑制すると共に、微細な素子間への埋め込みも可能としている。   In the silicon nitride film forming method of this embodiment, as shown in FIG. 3, the SiN film is formed on the back side inclined portion A by alternately performing film formation (deposition) without applying a bias and bias sputtering. This prevents the generation of particles due to peeling from the back-side inclined portion A, and enables embedding between fine elements.

具体的には、成膜を行う成膜工程においては、ガスノズル９を用いて、原料ガスであるＳｉＨ4ガス、窒素系ガス（例えば、Ｎ2ガス、ＮＨ3ガス等）と希ガス（例えば、Ａｒ等）とを供給し、プラズマ生成手段（高周波アンテナ６、整合器７、高周波電源８）を用いて、これらのガスを高密度のプラズマ状態とし、ＳｉＮ膜の成膜を基板５へ行っている。なお、このとき、希ガス（Ａｒ等）は供給しなくてもよく、又、基板５にバイアスは印加していないので、バイアススパッタは行われていない。 Specifically, in the film forming process for forming a film, the gas nozzle 9 is used to make the source gas SiH 4 gas, nitrogen-based gas (for example, N 2 gas, NH 3 gas, etc.), and rare gas (for example, Ar and the like, and using plasma generation means (high-frequency antenna 6, matching unit 7, high-frequency power source 8), these gases are brought into a high-density plasma state, and a SiN film is formed on the substrate 5. Yes. At this time, no rare gas (Ar or the like) may be supplied, and since no bias is applied to the substrate 5, bias sputtering is not performed.

上記成膜工程の後、スパッタ工程を実施している。スパッタ工程では、ガスノズル９を用いて、希ガス（例えば、Ａｒ等）、不活性ガス（例えば、Ｎ2ガス等）の少なくとも一方を供給し、バイアス印加手段（電極部１１、整合器１２、低周波電源１３）を用いて、基板５にバイアスを印加し、プラズマ生成手段（高周波アンテナ６、整合器７、高周波電源８）を用いて、希ガス、不活性ガスの少なくとも一方のプラズマを生成し、当該プラズマを用いて成膜工程で成膜したＳｉＮ膜のスパッタ（エッチ）、特に、オーバーハング部分のスパッタ（エッチ）を行っている。 After the film forming process, a sputtering process is performed. In the sputtering process, a gas nozzle 9 is used to supply at least one of a rare gas (for example, Ar) and an inert gas (for example, N 2 gas), and bias applying means (electrode unit 11, matching unit 12, low voltage) A bias is applied to the substrate 5 using a frequency power source 13), and at least one of a rare gas and an inert gas is generated using plasma generation means (a high-frequency antenna 6, a matching unit 7, and a high-frequency power source 8). Then, sputtering (etching) of the SiN film formed in the film forming process using the plasma, particularly, sputtering (etching) of the overhang portion is performed.

上記成膜工程、スパッタ工程について、ＳｉＨ4ガスとバイアスのタイムチャートを示すと、図３のようになる。そして、裏面側傾斜部ＡにＳｉＮ膜が形成されない成膜工程、ＳｉＮ膜のバイアススパッタを行うスパッタ工程を交互に少なくとも１回以上実施して、所望の膜厚となるＳｉＮ膜を形成することになる。なお、本実施例における各工程でのプロセス条件を例示すると、以下の表１のような条件となる。 FIG. 3 shows a time chart of the SiH 4 gas and the bias for the film forming process and the sputtering process. Then, a film forming process in which no SiN film is formed on the back side inclined portion A and a sputtering process in which bias sputtering of the SiN film is alternately performed at least once to form a SiN film having a desired film thickness. Become. In addition, if the process conditions in each process in a present Example are illustrated, it will become conditions like the following Table 1. FIG.

Figure 2012084707
Figure 2012084707

上記成膜工程により、裏面側傾斜部ＡにＳｉＮ膜が形成されることがなくなるので、剥離によるパーティクルの発生が無くなる。又、上記スパッタ工程により、成膜したＳｉＮ膜のオーバーハング部分がバイアススパッタにより削られるので、例えば、アスペクト比が１：１．５以上の微細な素子間へＳｉＮ膜を埋め込むことができる。更に、１回当たりの成膜工程におけるＳｉＮ膜の膜厚を薄くし、上記成膜工程及びスパッタ工程を複数回繰り返すことにより、より微細な素子間への埋め込みも可能となる。   Since the SiN film is not formed on the back side inclined portion A by the film forming process, generation of particles due to peeling is eliminated. In addition, since the overhang portion of the formed SiN film is removed by bias sputtering by the sputtering process, for example, the SiN film can be embedded between minute elements having an aspect ratio of 1: 1.5 or more. Further, by reducing the thickness of the SiN film in one film formation process and repeating the film formation process and the sputtering process a plurality of times, it is possible to embed between finer elements.

パーティクルに関しては、図８に示した成膜方法、即ち、成膜とバイアススパッタを同時に行うＳｉＮ膜の成膜方法では、パーティクルの数が「２１４個」であったが、表１に示すプロセス条件を用いた本実施例の成膜方法、即ち、成膜とバイアススパッタを交互に行うＳｉＮ膜の成膜方法では、パーティクルの数が「６個」と、顕著に減少した。このとき、裏面側傾斜部Ａを確認したところ、この部分にＳｉＮ膜が形成されていないことも確認できた。   Regarding the particles, in the film forming method shown in FIG. 8, that is, in the SiN film forming method in which film forming and bias sputtering are performed simultaneously, the number of particles was “214”. In the film forming method of this example using Si, that is, the SiN film forming method in which film forming and bias sputtering are alternately performed, the number of particles was remarkably reduced to “6”. At this time, when the back side inclined part A was confirmed, it was also confirmed that the SiN film was not formed in this part.

（実施例２）
本実施例は、上記実施例１を前提とするものである。従って、実施例１と重複する説明、例えば、窒化珪素膜形成装置の構成や窒化珪素膜形成方法（成膜工程、スパッタ工程）の基本的な部分等は省略して、本実施例の説明を行う。 (Example 2)
This embodiment is based on the first embodiment. Therefore, the description of the present embodiment is omitted by omitting the description overlapping with that of the first embodiment, for example, the configuration of the silicon nitride film forming apparatus and the basic portion of the silicon nitride film forming method (film forming process, sputtering process). Do.

上記実施例１のように、成膜工程とスパッタ工程とを交互に実施する場合、成膜工程で成膜したＳｉＮ膜の厚さ、そして、スパッタ工程で印加するバイアスの大きさによっては、スパッタの影響により、基板と第１層目のＳｉＮ膜との界面において、成膜工程で成膜したＳｉＮ膜が剥離を起こすおそれがある。   When the film forming process and the sputtering process are alternately performed as in the first embodiment, depending on the thickness of the SiN film formed in the film forming process and the magnitude of the bias applied in the sputtering process, the sputtering process is performed. As a result, the SiN film formed in the film forming process may peel off at the interface between the substrate and the first SiN film.

ここで、図４を参照して、成膜工程で成膜したＳｉＮ膜がスパッタ工程でのスパッタから受ける影響について説明する。   Here, with reference to FIG. 4, the influence which the SiN film formed in the film forming process receives from the sputtering in the sputtering process will be described.

上記実施例１で説明したように、本発明では、成膜工程の実施後にスパッタ工程を実施しており、基板５上にＳｉＮ膜２１を形成した後に、例えば、Ａｒ+イオンによりスパッタされる。本発明においては、微細な素子間へＳｉＮ膜を埋め込むようにするため、１回当たりの成膜工程におけるＳｉＮ膜２１の膜厚を薄くすることが望ましい。 As described in the first embodiment, in the present invention, the sputtering process is performed after the film forming process. After the SiN film 21 is formed on the substrate 5, for example, sputtering is performed with Ar + ions. In the present invention, in order to embed the SiN film between fine elements, it is desirable to reduce the film thickness of the SiN film 21 in one film forming process.

しかしながら、ＳｉＮ膜２１の膜厚が薄い場合、そして、印加するバイアスの大きさが相対的に大きい場合には、スパッタの際のＡｒ+イオンがＳｉＮ膜２１中に侵入してしまう（図４（ａ）参照）。そして、ＳｉＮ膜２１中に侵入したＡｒ+イオンが、基板５と第１層目のＳｉＮ膜２１との界面に溜まってしまう（図４（ｂ））。このような場合、最悪の場合には、界面に溜まったＡｒにより、基板５と第１層目のＳｉＮ膜２１との界面において、ＳｉＮ膜２１が剥離するおそれがある。 However, when the thickness of the SiN film 21 is thin and the applied bias is relatively large, Ar + ions at the time of sputtering enter the SiN film 21 (FIG. 4 ( a)). Then, Ar + ions that have entered the SiN film 21 accumulate at the interface between the substrate 5 and the first SiN film 21 (FIG. 4B). In such a case, in the worst case, the SiN film 21 may be peeled off at the interface between the substrate 5 and the first SiN film 21 due to Ar accumulated at the interface.

そこで、本実施例においては、図５のグラフに示すように、第１層目のＳｉＮ膜２１の膜厚とバイアスパワーの条件を変えて、剥離の有無を確認し、第１層目のＳｉＮ膜２１の膜厚とバイアスパワーの大きさの関係を規定するようにしている。なお、図５のグラフにおいて、「●」印は剥離なしを示し、「×」印は剥離有りを示している。又、横軸下側には印加したバイアスパワー（Ｗ）を示すと共に、横軸上側にはバイアスパワー密度（Ｗ／ｃｍ2）、即ち、バイアスパワーを基板５の単位面積（１ｃｍ2）当たりの密度に換算した値を示している。 Therefore, in the present embodiment, as shown in the graph of FIG. 5, the film thickness of the first layer SiN film 21 and the bias power conditions are changed to check the presence or absence of peeling, and the first layer SiN. The relationship between the film thickness of the film 21 and the magnitude of the bias power is defined. In the graph of FIG. 5, “●” indicates that there is no peeling, and “×” indicates that there is peeling. The bias power (W) applied is shown on the lower side of the horizontal axis, and the bias power density (W / cm 2 ), that is, the bias power per unit area (1 cm 2 ) of the substrate 5 is shown on the upper side of the horizontal axis. The value converted into density is shown.

図５のグラフからわかるように、バイアスパワー４００〜１５００Ｗの範囲においては、第１層目のＳｉＮ膜２１の膜厚が少なくとも３０ｎｍ以上あれば、剥離がないことを示している。一方、３０ｎｍ未満の膜厚については、膜厚が薄くなればなるほど、剥離がない場合のバイアスパワーが小さくなっていく。   As can be seen from the graph of FIG. 5, in the range of bias power of 400 to 1500 W, if the thickness of the first SiN film 21 is at least 30 nm, it indicates that there is no peeling. On the other hand, for a film thickness of less than 30 nm, the thinner the film thickness, the smaller the bias power when there is no peeling.

確認した結果を、図５の縦軸に示すように、［バイアスパワー密度（Ｗ／ｃｍ2）／第１層目の膜厚（ｎｍ）］で整理すると、剥離が発生しない許容条件としては、以下の（式１）の関係を満たす条件に規定することができる。なお、下記（式１）において、バイアスパワー密度をＢ（Ｗ／ｃｍ2）と規定し、第１層目の膜厚をＴ（ｎｍ）と規定している。
Ｂ／Ｔ≦０．０８ ・・・ （式１） As shown in the vertical axis of FIG. 5, when the confirmed result is arranged by [bias power density (W / cm 2 ) / film thickness of the first layer (nm)], as an allowable condition that peeling does not occur, It can be defined as a condition satisfying the relationship of the following (formula 1). In the following (Formula 1), the bias power density is defined as B (W / cm 2 ), and the film thickness of the first layer is defined as T (nm).
B / T ≦ 0.08 (Formula 1)

つまり、第１層目のＳｉＮ膜２１の膜厚とバイアスパワー（バイアスパワー密度）について、（式１）の条件を満たすようにすれば、スパッタによる希ガスイオンが、基板５と第１層目のＳｉＮ膜２１との界面まで届かなくなり、界面での剥離を抑制することができる。   That is, if the condition of (Formula 1) is satisfied with respect to the film thickness and bias power (bias power density) of the SiN film 21 of the first layer, the rare gas ions formed by sputtering will cause the substrate 5 and the first layer. Thus, it cannot reach the interface with the SiN film 21, and peeling at the interface can be suppressed.

なお、上記実施例１、２は、様々な半導体デバイスの素子構造に適用可能であり、前述したＭＲＡＭの素子構造に限る必要はない。   The first and second embodiments can be applied to various element structures of semiconductor devices, and need not be limited to the above-described MRAM element structures.

本発明は、半導体装置に適用するものであり、特に、素子間距離が小さい半導体装置を埋め込む窒化珪素膜として好適である。   The present invention is applied to a semiconductor device, and is particularly suitable as a silicon nitride film for embedding a semiconductor device having a small inter-element distance.

５ 基板
６ 高周波アンテナ
７ 整合器
８ 高周波電源
９ ガスノズル
１１ 電極部
１２ 整合器
１３ 低周波電源
２１ 窒化珪素膜 DESCRIPTION OF SYMBOLS 5 Board | substrate 6 High frequency antenna 7 Matching device 8 High frequency power supply 9 Gas nozzle 11 Electrode part 12 Matching device 13 Low frequency power supply 21 Silicon nitride film

Claims (6)

基板上に窒化珪素膜を形成する窒化珪素膜形成装置において、
前記窒化珪素膜を形成するための原料ガスと希ガスと不活性ガスとを含めて、複数のガスを供給するガス供給手段と、
前記ガスのプラズマを生成するプラズマ生成手段と、
前記基板にバイアスを印加するバイアス印加手段と、
前記ガス供給手段、前記プラズマ生成手段及び前記バイアス印加手段を制御する制御手段とを有し、
前記制御手段は、
前記ガス供給手段により、少なくとも前記原料ガスを供給し、前記プラズマ生成手段により、少なくとも前記原料ガスのプラズマを生成し、当該プラズマを用いて前記窒化珪素膜を成膜する成膜工程を実施し、
前記成膜工程の後、前記ガス供給手段により、前記希ガス又は前記不活性ガス又は前記希ガス及び前記不活性ガスを供給し、前記バイアス印加手段により前記基板へバイアスを印加し、前記プラズマ生成手段により、前記希ガス又は前記不活性ガス又は前記希ガス及び前記不活性ガスのプラズマを生成し、当該プラズマを用いて前記窒化珪素膜をバイアススパッタするスパッタ工程を実施することを特徴とする窒化珪素膜形成装置。 In a silicon nitride film forming apparatus for forming a silicon nitride film on a substrate,
A gas supply means for supplying a plurality of gases including a source gas, a rare gas, and an inert gas for forming the silicon nitride film;
Plasma generating means for generating plasma of the gas;
Bias applying means for applying a bias to the substrate;
Control means for controlling the gas supply means, the plasma generation means and the bias application means,
The control means includes
Supplying at least the source gas by the gas supply means, generating plasma of at least the source gas by the plasma generation means, and performing a film forming step of forming the silicon nitride film using the plasma;
After the film forming step, the gas supply means supplies the rare gas or the inert gas or the rare gas and the inert gas, the bias application means applies a bias to the substrate, and the plasma generation Means for generating a plasma of the rare gas, the inert gas, or the rare gas and the inert gas, and performing a sputtering step of bias sputtering the silicon nitride film using the plasma. Silicon film forming apparatus. 請求項１に記載の窒化珪素膜形成装置において、
前記制御手段は、前記成膜工程と前記スパッタ工程とを交互に複数回実施することを特徴とする窒化珪素膜形成装置。 The silicon nitride film forming apparatus according to claim 1,
The said control means implements the said film-forming process and the said sputtering process several times alternately, The silicon nitride film forming apparatus characterized by the above-mentioned. 請求項１又は請求項２に記載の窒化珪素膜形成装置において、
前記制御手段は、
前記成膜工程において、前記基板上に成膜する第１層目の前記窒化珪素膜の膜厚をＴ（ｎｍ）とし、前記スパッタ工程において、前記基板へ印加するバイアスパワーを前記基板の面積で除算したバイアスパワー密度をＢ（Ｗ／ｃｍ2）とするとき、
［Ｂ／Ｔ≦０．０８］の条件を満たすように、前記成膜工程及び前記スパッタ工程を実施することを特徴とする窒化珪素膜形成装置。 In the silicon nitride film forming apparatus according to claim 1 or 2,
The control means includes
In the film formation step, the film thickness of the first silicon nitride film formed on the substrate is T (nm), and in the sputtering step, the bias power applied to the substrate is the area of the substrate. When the divided bias power density is B (W / cm 2 ),
The silicon nitride film forming apparatus, wherein the film forming step and the sputtering step are performed so as to satisfy a condition of [B / T ≦ 0.08]. 基板上に窒化珪素膜を形成する窒化珪素膜形成方法において、
前記窒化珪素膜を形成するための原料ガスと希ガスと不活性ガスのうち、少なくとも前記原料ガスを供給し、少なくとも前記原料ガスのプラズマを生成し、当該プラズマを用いて前記窒化珪素膜を成膜する成膜工程と、
前記成膜工程の後、前記希ガス又は前記不活性ガス又は前記希ガス及び前記不活性ガスを供給し、前記基板へバイアスを印加し、前記希ガス又は前記不活性ガス又は前記希ガス及び前記不活性ガスのプラズマを生成し、当該プラズマを用いて前記窒化珪素膜をバイアススパッタするスパッタ工程とを有することを特徴とする窒化珪素膜形成方法。 In a silicon nitride film forming method for forming a silicon nitride film on a substrate,
At least the source gas among the source gas, the rare gas, and the inert gas for forming the silicon nitride film is supplied, plasma of the source gas is generated at least, and the silicon nitride film is formed using the plasma. A film forming process to form a film;
After the film forming step, the rare gas or the inert gas or the rare gas and the inert gas are supplied, a bias is applied to the substrate, and the rare gas or the inert gas or the rare gas and the A method of forming a silicon nitride film, comprising: generating a plasma of an inert gas and performing a bias sputtering of the silicon nitride film using the plasma. 請求項４に記載の窒化珪素膜形成方法において、
前記成膜工程と前記スパッタ工程とを交互に複数回実施することを特徴とする窒化珪素膜形成方法。 In the silicon nitride film forming method according to claim 4,
The method for forming a silicon nitride film, wherein the film forming step and the sputtering step are alternately performed a plurality of times. 請求項４又は請求項５に記載の窒化珪素膜形成方法において、
前記成膜工程において、前記基板上に成膜する第１層目の前記窒化珪素膜の膜厚をＴ（ｎｍ）とし、前記スパッタ工程において、前記基板へ印加するバイアスパワーを前記基板の面積で除算したバイアスパワー密度をＢ（Ｗ／ｃｍ2）とするとき、
［Ｂ／Ｔ≦０．０８］の条件を満たすように、前記成膜工程及び前記スパッタ工程を実施することを特徴とする窒化珪素膜形成方法。 In the silicon nitride film forming method according to claim 4 or 5,
In the film formation step, the film thickness of the first silicon nitride film formed on the substrate is T (nm), and in the sputtering step, the bias power applied to the substrate is the area of the substrate. When the divided bias power density is B (W / cm 2 ),
The silicon nitride film forming method, wherein the film forming step and the sputtering step are performed so as to satisfy a condition of [B / T ≦ 0.08].
JP2010230189A 2010-10-13 2010-10-13 Apparatus and method of silicon nitride film formation Pending JP2012084707A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2010230189A JP2012084707A (en) 2010-10-13 2010-10-13 Apparatus and method of silicon nitride film formation
PCT/JP2011/071081 WO2012049943A1 (en) 2010-10-13 2011-09-15 Silicon nitride film-forming device and method
TW100134198A TW201220400A (en) 2010-10-13 2011-09-22 Silicon nitride film-forming device and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010230189A JP2012084707A (en) 2010-10-13 2010-10-13 Apparatus and method of silicon nitride film formation

Publications (1)

Publication Number Publication Date
JP2012084707A true JP2012084707A (en) 2012-04-26

Family

ID=45938176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010230189A Pending JP2012084707A (en) 2010-10-13 2010-10-13 Apparatus and method of silicon nitride film formation

Country Status (3)

Country Link
JP (1) JP2012084707A (en)
TW (1) TW201220400A (en)
WO (1) WO2012049943A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016066794A (en) * 2014-09-24 2016-04-28 ラム リサーチ コーポレーションＬａｍ Ｒｅｓｅａｒｃｈ Ｃｏｒｐｏｒａｔｉｏｎ Methods and apparatuses for uniform reduction of in-feature wet etch rate of silicon nitride film formed by ald
US10658172B2 (en) 2017-09-13 2020-05-19 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
US10804099B2 (en) 2014-11-24 2020-10-13 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
WO2020247531A1 (en) * 2019-06-06 2020-12-10 Applied Materials, Inc. Methods of post treating silicon nitride based dielectric films with high energy low dose plasma
US11404275B2 (en) 2018-03-02 2022-08-02 Lam Research Corporation Selective deposition using hydrolysis

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0352232A (en) * 1989-07-20 1991-03-06 Fuji Electric Co Ltd Step covering method with insulating film
JPH05129276A (en) * 1991-11-06 1993-05-25 Fuji Electric Co Ltd Manufacture of insulating film

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04245628A (en) * 1991-01-31 1992-09-02 Hitachi Ltd Forming method of insulating film
JPH08288285A (en) * 1995-04-18 1996-11-01 Sony Corp Forming method of insulating film

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0352232A (en) * 1989-07-20 1991-03-06 Fuji Electric Co Ltd Step covering method with insulating film
JPH05129276A (en) * 1991-11-06 1993-05-25 Fuji Electric Co Ltd Manufacture of insulating film

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016066794A (en) * 2014-09-24 2016-04-28 ラム リサーチ コーポレーションＬａｍ Ｒｅｓｅａｒｃｈ Ｃｏｒｐｏｒａｔｉｏｎ Methods and apparatuses for uniform reduction of in-feature wet etch rate of silicon nitride film formed by ald
US10804099B2 (en) 2014-11-24 2020-10-13 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
US10658172B2 (en) 2017-09-13 2020-05-19 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
US11404275B2 (en) 2018-03-02 2022-08-02 Lam Research Corporation Selective deposition using hydrolysis
WO2020247531A1 (en) * 2019-06-06 2020-12-10 Applied Materials, Inc. Methods of post treating silicon nitride based dielectric films with high energy low dose plasma

Also Published As

Publication number Publication date
WO2012049943A1 (en) 2012-04-19
TW201220400A (en) 2012-05-16

Similar Documents

Publication Publication Date Title
KR20190040082A (en) Deposition of thick tungsten hardmask films on high compression / tensile warp wafers
TWI324026B (en) Plasma producing method and apparatus as well as plasma processing apparatus
US8662010B2 (en) Plasma processing apparatus, plasma processing method, plasma film deposition apparatus, and plasma film deposition method
US7972946B2 (en) Plasma treatment method and plasma treatment device
CN102396052A (en) Plasma processing apparatus, plasma processing method, and method of manufacturing chip provided with processed substrate
JP2005302848A (en) Semiconductor manufacturing equipment and semiconductor manufacturing method
WO2012049943A1 (en) Silicon nitride film-forming device and method
KR101846049B1 (en) Method of forming copper wiring, and storage medium
US8835296B2 (en) Electronic component manufacturing method including step of embedding metal film
JP2007531997A (en) Substrate processing method
US11319630B2 (en) Deposition apparatus and deposition method
US10577689B2 (en) Sputtering showerhead
TWI632716B (en) Manufacturing method of organic component, manufacturing device of organic component, and organic component
JP4123428B2 (en) Etching method
WO2012043250A1 (en) Method and device for forming insulation film
JP2003059918A (en) Method and apparatus for plasma treatment and manufacturing method for semiconductor device
JP5649441B2 (en) Method of manufacturing electronic component having step of embedding metal film
US20200357643A1 (en) Deposition of metal silicide layers on substrates and chamber components
JP3116904B2 (en) Semiconductor device film forming apparatus, semiconductor device manufacturing method, and semiconductor thin film forming method
US20070082466A1 (en) High density plasma chemical vapor deposition apparatus, operating method thereof, and method of manufacturing semiconductor device
US11562925B2 (en) Method of depositing multilayer stack including copper over features of a device structure
JPWO2007077718A1 (en) Substrate processing method and substrate processing apparatus
JP2021521326A (en) Solving spontaneous arcs during thick film deposition of high temperature amorphous carbon deposits
JP2008182001A (en) Manufacturing method for semiconductor device
JP2005248222A (en) Sputtering method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130802

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140916

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20141113

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150106

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20151006