JP2012079765A - Electronic component mounting substrate - Google Patents
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- JP2012079765A JP2012079765A JP2010221028A JP2010221028A JP2012079765A JP 2012079765 A JP2012079765 A JP 2012079765A JP 2010221028 A JP2010221028 A JP 2010221028A JP 2010221028 A JP2010221028 A JP 2010221028A JP 2012079765 A JP2012079765 A JP 2012079765A
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Abstract
Description
本発明は、配線パターンが形成された基板を、絶縁樹脂層を間に介装して複数積層した多層配線基板の表面に、はんだ接合により電子部品が実装される電子部品実装基板に関するものである。 The present invention relates to an electronic component mounting substrate in which electronic components are mounted by solder bonding on the surface of a multilayer wiring substrate in which a plurality of substrates on which wiring patterns are formed are stacked with an insulating resin layer interposed therebetween. .
従来、プリント基板上に電子部品を実装する場合には、基板上に形成された配線パターンに、錫−鉛の共晶はんだを用いたはんだ付けによって、上記電子部品を接合する方法が採用されていた。この錫−鉛の共晶はんだは、融点が低く、しかも柔軟性があるため、伸びと強度のバランスが良く、はんだ付けの際に、プリント基板と電子部品端子との間の熱膨張係数の違いによるストレスを吸収することができる。また、自らが劣化すること（粒径の粗大化）により、急激な破壊または破断を防止し、一種の緩衝剤として作用するため、はんだ付け接合部に高い信頼性を与えていた。 Conventionally, when an electronic component is mounted on a printed circuit board, a method of joining the electronic component to a wiring pattern formed on the substrate by soldering using a tin-lead eutectic solder has been employed. It was. This tin-lead eutectic solder has a low melting point and is flexible, so there is a good balance between elongation and strength. The difference in thermal expansion coefficient between the printed circuit board and the electronic component terminals during soldering Can absorb the stress caused by. Moreover, since it deteriorates itself (coarse particle size), it prevents rapid breakage or breakage and acts as a kind of buffering agent, thus giving the soldered joint high reliability.
しかしながら、鉛は人体に有害な金属である。そのため、地球環境の保護や有害物質の使用を回避しようとする国際的な要求の高まりに応じて、鉛を含有しない鉛フリーはんだの研究および開発が進められてきている。 However, lead is a metal harmful to the human body. For this reason, research and development of lead-free solders that do not contain lead have been promoted in response to increasing international demands to protect the global environment and avoid the use of harmful substances.
現在、最も一般的に使用されている無鉛はんだは、３元系の錫−銀−銅の合金である。この代表的な組成として、Ｓｎ−３．５Ａｇ−０．７Ｃｕ、Ｓｎ−３．０Ａｇ−０．５Ｃｕ等が実用化されている。これ以外にも、３元系のＳｎ−Ａｇ−Ｂｉ、Ｓｎ−Ｃｕ−Ｎｉ（Ｎｉは微量添加物）、４元系のＳｎ−Ａｇ−Ｃｕ−Ｂｉ、５元系のＳｎ−Ａｇ−Ｃｕ−Ｂｉ−Ｇｅ等の無鉛はんだ等が発表されている。 Currently, the most commonly used lead-free solder is a ternary tin-silver-copper alloy. As this typical composition, Sn-3.5Ag-0.7Cu, Sn-3.0Ag-0.5Cu, etc. are put into practical use. In addition, ternary Sn-Ag-Bi, Sn-Cu-Ni (Ni is a trace additive), quaternary Sn-Ag-Cu-Bi, quinary Sn-Ag-Cu- Lead-free solder such as Bi-Ge has been announced.
しかし、これらの鉛フリーはんだ材料は、鉛含有はんだに比べて上記ストレスの吸収作用が小さいことが知られている。そのため、通電時の温度上昇において、基板と電子部品との熱膨張率が異なるために生じるストレスを完全に吸収することができず、微小な塑性歪みが蓄積されてしまう。 However, it is known that these lead-free solder materials have a smaller effect of absorbing the stress than lead-containing solder. For this reason, when the temperature rises during energization, the stress generated due to the different coefficients of thermal expansion between the substrate and the electronic component cannot be completely absorbed, and minute plastic strain is accumulated.
また、電子部品実装基板では、使用のたびに自身や周囲の部品からの発熱による熱歪みが発生し、各部材間の熱歪み差に起因して発生する応力が、はんだ部にも及んでしまう。このため、鉛フリーはんだにおいては、発熱のたびに塑性歪みが蓄積されて、ある時点において接合部内部にクラックが発生し、さらに使用を続けていくと、クラックは成長して接合部の断裂を起こし、電気的な接続が保てなくなるという問題がある。 In addition, in electronic component mounting boards, thermal distortion occurs due to heat generation from itself and surrounding components every time it is used, and the stress generated due to the thermal strain difference between each member also reaches the solder part. . For this reason, in lead-free solder, plastic strain accumulates every time heat is generated, and cracks are generated inside the joint at a certain point in time, and as the use continues further, the crack grows and breaks the joint. There is a problem that the electrical connection cannot be maintained.
さらに、電子部品の小型化に伴う搭載部品の高密度化、配線の複雑化が進む今日では、局所的に強度の低下した部分が現れやすく、高度な設計・製造技術が必要になっている。特に、図５に示すような配線パターン４が形成された基板１を、絶縁樹脂層５を間に介装して複数積層した多層配線基板２の表面に、はんだ７により電子部品８の端子と配線パターン４である接合部９とが接合されて実装される電子部品実装基板３においては、電子部品８の通電時の発熱による熱歪みによって、はんだ７の接合部の疲労寿命が低下する傾向があり、鉛フリーはんだの機械特性の改善やはんだ接合量・位置の最適化、使用部材の選定などによる対応では望みの信頼性を得られないケースが多くある。そのため、熱歪みの小さい高価な基板材料への変更など、コストの増加によって信頼性を維持させている現実がある。 Furthermore, as the density of mounted components and the complexity of wiring increase with the downsizing of electronic components, parts with reduced strength tend to appear locally, and advanced design and manufacturing techniques are required. In particular, the terminals of the electronic component 8 are connected to the surface of the multilayer wiring substrate 2 in which a plurality of substrates 1 having the wiring pattern 4 as shown in FIG. In the electronic component mounting board 3 that is mounted by being bonded to the joint portion 9 that is the wiring pattern 4, the fatigue life of the joint portion of the solder 7 tends to decrease due to heat distortion due to heat generation when the electronic component 8 is energized. There are many cases in which the desired reliability cannot be obtained by improving the mechanical properties of lead-free solder, optimizing the amount and position of solder joints, and selecting the materials used. Therefore, there is a reality that reliability is maintained by an increase in cost, such as a change to an expensive substrate material with a small thermal strain.
すなわち、熱歪みが発生した場合に起こる破壊の原因は、基板１と電子部品８との熱膨張率が異なるために現れる基板、の反りにある。例えば、チップ抵抗器やインダクタで多く利用されているセラミック焼結体やフェライト焼結体、ＩＣ部品の主要材料であるシリコン素子は、概ね３〜８×１０-6／℃程度の熱膨張率を示す。 That is, the cause of the destruction that occurs when thermal distortion occurs is the warpage of the substrate that appears because the thermal expansion coefficients of the substrate 1 and the electronic component 8 are different. For example, a ceramic sintered body, a ferrite sintered body, and a silicon element that is a main material of IC components, which are widely used in chip resistors and inductors, have a thermal expansion coefficient of about 3 to 8 × 10 −6 / ° C. Show.
一方、基板１は金属またはガラスをベースに樹脂含浸したものや、紙をベースに樹脂が含浸したものなど種類が多い。しかし、ほとんど熱膨張率は１４〜３０×１０-6／℃の範囲に収まっている。このような部品構成において、高温または低温に移行すると、電子部品８と基板１の熱膨張率の差からストレスが発生し、はんだ７に歪みが蓄積される。また同時に基板１、が変形して反りが発生し、搭載する電子部品８に様々な応力が生じる。 On the other hand, there are many types of substrates 1 such as a metal or glass base impregnated with resin and a paper base base impregnated with resin. However, the thermal expansion coefficient is almost in the range of 14 to 30 × 10 −6 / ° C. In such a component configuration, when the temperature shifts to a high temperature or a low temperature, a stress is generated due to a difference in coefficient of thermal expansion between the electronic component 8 and the substrate 1, and distortion is accumulated in the solder 7. At the same time, the substrate 1 is deformed and warps, causing various stresses on the electronic component 8 to be mounted.
このような熱歪みは、内部に多数の金属配線を含む多層基板において、問題がより顕著になり、はんだの疲労寿命が大きく劣化するという問題がある。これは、配線材料として銅が最も頻繁に使用されるが、銅の熱膨張率は１６．７×１０-6／℃程度であり、熱膨張率は搭載部品に比べて大きく、かつ剛性は樹脂基板に比べて著しく高いため、大きな熱歪みの発生源となっているためである。そのため、金属の内層数が増えるとともに疲労寿命は大きく劣化する傾向があり、大きな問題となっている。 Such a thermal strain becomes more problematic in a multilayer substrate including a large number of metal wirings therein, and there is a problem that the fatigue life of the solder is greatly deteriorated. This is because copper is most frequently used as a wiring material, but the coefficient of thermal expansion of copper is about 16.7 × 10 −6 / ° C., the coefficient of thermal expansion is larger than that of the mounted components, and the rigidity is resin. This is because it is significantly higher than the substrate and is a source of large thermal strain. Therefore, as the number of inner layers of metal increases, the fatigue life tends to deteriorate greatly, which is a big problem.
この問題について種々に研究した結果、金属の内部配線パターンが熱歪みの原因となるのは部品の直下近傍にある配線のみであることが分かった。これは、配線パターンにより発生した熱歪みが基板の中で緩和されていくためである。また、部品の直下に金属配線がない場合も、部品と金属配線との熱歪みの差が発生しにくい状況になるため、はんだ接合部への負担は小さくなることが判明した。これにより、問題となる部品の周囲に金属配線が存在しないように設計段階において、留意することにより熱歪みを防止する方法がある。 As a result of various researches on this problem, it has been found that the metal internal wiring pattern causes only the wiring in the immediate vicinity of the component to cause thermal distortion. This is because the thermal strain generated by the wiring pattern is alleviated in the substrate. In addition, it has been found that even when there is no metal wiring directly under the part, a difference in thermal strain between the part and the metal wiring hardly occurs, so that the burden on the solder joint portion is reduced. Thus, there is a method for preventing thermal distortion by paying attention in the design stage so that metal wiring does not exist around the component in question.
しかし、高密度化された現代の電子部品では、基板の放熱性を高めるために内層される銅の残銅率は高い方が好ましい。また、基板内部の配線パターンが、搭載部品の直下部を回避するために、複雑な形状になると放射ノイズの発生原因になるという問題がある。この放射ノイズは、搭載部品の正常動作を妨げることがあり、特に信号の受発信や処理を行う部品や回路を搭載した基板では重大な問題になる。さらに、高密度化を行う上では、配線パターンの制約が大きくなるため、設計開発コストが嵩むという問題もある。 However, in modern electronic components with high density, it is preferable that the copper remaining in the inner layer is high in order to increase the heat dissipation of the substrate. In addition, there is a problem that radiation noise is generated when the wiring pattern inside the substrate becomes a complicated shape in order to avoid a portion directly below the mounted component. This radiation noise may interfere with the normal operation of the mounted components, and becomes a serious problem especially on a substrate on which components and circuits for receiving and transmitting signals and processing are mounted. Furthermore, when the density is increased, there is a problem that the design and development costs increase because the restrictions on the wiring pattern increase.
本発明は、かかる事情に鑑みてなされたもので、多層配線基板の表面に、実装された電子部品の発熱による熱歪みの影響によって起こるはんだ接合部の破損を減少させ、信頼性の高い電子部品実装基板を提供することを課題とするものである。 The present invention has been made in view of such circumstances, and reduces damage to solder joints caused by the effect of thermal distortion due to heat generation of electronic components mounted on the surface of a multilayer wiring board, and has high reliability. It is an object to provide a mounting substrate.
上記課題を解決するために、請求項１に記載の発明は、配線パターンが形成された基板を絶縁樹脂層を間に介装して複数積層した多層配線基板の表面に、はんだ接合により電子部品が実装される電子部品実装基板において、上記多層配線基板は、最表層の上記基板と上記電子部品との間に緩衝部が形成されているとともに、上記基板の上記配線パターンと導通し、かつ上記緩衝部の外表面に露出して上記電子部品が上記はんだにより接合される接続部が形成されていることを特徴とするものである。 In order to solve the above-mentioned problems, an invention according to claim 1 is directed to an electronic component by solder bonding to a surface of a multilayer wiring board in which a plurality of substrates on which a wiring pattern is formed are stacked with an insulating resin layer interposed therebetween. In the electronic component mounting substrate on which is mounted, the multilayer wiring substrate has a buffer portion formed between the substrate on the outermost layer and the electronic component, and is electrically connected to the wiring pattern on the substrate. A connection portion is formed which is exposed on the outer surface of the buffer portion and is joined to the electronic component by the solder.
また、請求項２に記載の発明は、請求項１に記載の発明において、上記緩衝部は、上記多層配線基板の最表層の上記基板の全面を覆う層状に形成されていることを特徴とするものである。 According to a second aspect of the present invention, in the first aspect of the present invention, the buffer portion is formed in a layer shape covering the entire surface of the substrate as the outermost layer of the multilayer wiring substrate. Is.
さらに、請求項３に記載の発明は、請求項１または２に記載の発明において、上記緩衝部は、上記絶縁樹脂層と同質材により形成されていることを特徴とするものである。 Further, the invention described in claim 3 is characterized in that, in the invention described in claim 1 or 2, the buffer portion is formed of the same material as the insulating resin layer.
また、請求項４に記載の発明は、請求項１〜３のいずれかに記載の発明において、上記緩衝部は、０．０５ｍｍ〜１．０ｍｍの厚さ寸法により形成されていることを特徴とするものである。 The invention according to claim 4 is the invention according to any one of claims 1 to 3, wherein the buffer portion is formed with a thickness of 0.05 mm to 1.0 mm. To do.
請求項１〜４に記載の本発明によれば、配線パターンが形成された基板を、絶縁樹脂層を間に介装して複数積層した多層配線基板は、最表層の上記基板と電子部品との間に緩衝部が形成されているため、当該緩衝部部において、上記電子部品の通電時の発熱を遮断して、熱膨張率および剛性が高い銅材料からなる上記配線パターンに熱を伝わりにくくするとともに、上記電子部品の通電時の発熱によって、上記配線パターンに熱歪みが生じた場合には、その熱歪みを吸収することができる。これにより、上記基板の上記配線パターンと上記電子部品とを接合している上記はんだに、上記熱歪みによるストレスの蓄積が抑制され、鉛フリーはんだの破損を防止することができるとともに、電子部品実装基板の使用寿命や信頼性を向上させることができる。 According to the first to fourth aspects of the present invention, a multilayer wiring board obtained by stacking a plurality of substrates on which a wiring pattern is formed with an insulating resin layer interposed therebetween includes the substrate and the electronic component on the outermost layer. Since the buffer portion is formed between the two, the heat generated during energization of the electronic component is blocked in the buffer portion, and it is difficult to transfer heat to the wiring pattern made of a copper material having a high coefficient of thermal expansion and rigidity. In addition, in the case where thermal distortion occurs in the wiring pattern due to heat generated when the electronic component is energized, the thermal distortion can be absorbed. As a result, accumulation of stress due to the thermal strain is suppressed in the solder that joins the wiring pattern of the substrate and the electronic component, and damage to the lead-free solder can be prevented. The service life and reliability of the substrate can be improved.
また、上記電子部品を高密度化されて実装する場合でも、上記多層配線基板の内層において、上記配線パターンの無理な設計変更などを行う必要がなく、残銅率を高くすることができ、放熱性を向上させることができるとともに、上記配線パターンを複雑な形状にすることがないため、放射ノイズの発生を抑えることができる。 In addition, even when the electronic parts are mounted with a high density, it is not necessary to make an unfortunate design change of the wiring pattern in the inner layer of the multilayer wiring board, and the residual copper ratio can be increased, and heat dissipation can be achieved. And the generation of radiation noise can be suppressed because the wiring pattern does not have a complicated shape.
そして、上記緩衝部の外表面に露出して上記電子部品を上記はんだにより接合する接続部が形成されているため、最表層の上記基板と上記電子部品との間に形成された上記緩衝部を絶縁性のある材質により形成しても、上記基板に形成された上記配線パターンと簡便に導通させることができる。 And since the connection part which is exposed to the outer surface of the said buffer part and joins the said electronic component with the said solder is formed, the said buffer part formed between the said board | substrate of the outermost layer and the said electronic component is formed. Even if it is made of an insulating material, it can be easily conducted to the wiring pattern formed on the substrate.
請求項２に記載の発明によれば、上記緩衝部が、上記多層配線基板の最表層の上記基板の全面を覆う層状に形成されているため、上記接続部(配線パターン)などを自由にレイアウトすることができるとともに、搭載する上記電子部品のマウント性やはんだによる接合性を損なうことがない。 According to the second aspect of the present invention, since the buffer portion is formed in a layer shape covering the entire surface of the outermost layer of the multilayer wiring board, the connection portion (wiring pattern) and the like can be freely laid out. In addition, the mountability of the electronic component to be mounted and the bondability by soldering are not impaired.
また、上記多層配線基板を製造する際に、上記配線パターンが形成された上記基板や上記絶縁樹脂層と共に、一括して成型することができる。この結果、容易に製造することができるとともに、新たな工程を追加することがなく製造コストを抑えることができる。 Moreover, when manufacturing the said multilayer wiring board, it can shape | mold collectively with the said board | substrate with which the said wiring pattern was formed, and the said insulating resin layer. As a result, it can be manufactured easily, and the manufacturing cost can be reduced without adding a new process.
請求項３に記載の発明によれば、上記緩衝部が、上記絶縁樹脂層と同じ材質により形成されているため、機械特性や熱膨張率を等しくすることができる。これにより、上記緩衝部が新たなストレスや反りの発生源になることがないとともに、良好な信頼性を持たせることができる。 According to invention of Claim 3, since the said buffer part is formed with the same material as the said insulating resin layer, a mechanical characteristic and a thermal expansion coefficient can be made equal. As a result, the buffer section does not become a source of new stress or warpage, and can have good reliability.
また、上記多層配線基板を製造する際に、新たな工程を追加することなく、従来の製造工程において、一括して製造することができる。この結果、容易に製造することができるとともに、製造コストを抑えることができる。 Moreover, when manufacturing the said multilayer wiring board, it can manufacture collectively in the conventional manufacturing process, without adding a new process. As a result, it can be easily manufactured and the manufacturing cost can be suppressed.
請求項４に記載の発明によれば、上記緩衝部の厚さ寸法が、０．０５〜１．０ｍｍであるため、上記電子部品の通電時の発熱による上記配線パターンの材料の熱歪みの影響を少なくすることができるとともに、上記緩衝部を含む上記多層配線基板の内部残銅率の厚み方向の偏りによる反りの発生を防ぐことができる。 According to invention of Claim 4, since the thickness dimension of the said buffer part is 0.05-1.0mm, the influence of the thermal distortion of the material of the said wiring pattern by the heat_generation | fever at the time of electricity supply of the said electronic component And the occurrence of warpage due to the deviation in the thickness direction of the internal copper ratio of the multilayer wiring board including the buffer portion can be prevented.
（第１の実施形態）
図１に示すように、本発明に係る電子部品実装基板３の一実施形態は、配線パターン４が両面に形成された４枚の基板１を、絶縁樹脂層５を間に介装して積層し多層配線基板２が形成され、この多層配線基板２の最表層の基板１ａと、電子部品８との間に緩衝部６が形成されているとともに、基板１の配線パターン４と導通し、かつ緩衝部６の外表面６ａに露出した接続部９に、電子部品８の端子部がはんだ７により接合され概略構成されている。
(First embodiment)
As shown in FIG. 1, in one embodiment of an electronic component mounting board 3 according to the present invention, four boards 1 each having a wiring pattern 4 formed on both sides are laminated with an insulating resin layer 5 interposed therebetween. A multilayer wiring board 2 is formed, and a buffer portion 6 is formed between the outermost substrate 1a of the multilayer wiring board 2 and the electronic component 8, and is electrically connected to the wiring pattern 4 of the board 1. The terminal part of the electronic component 8 is joined to the connection part 9 exposed on the outer surface 6 a of the buffer part 6 by the solder 7, and is schematically configured.
ここで、基板１は、０．０２〜０．０５ｍｍのリジッド基板が用いられ、その組成の種類から、 紙にフェノール樹脂を含浸させた紙フェノール基板、 紙にエポキシ樹脂を含浸させた紙エポキシ基板、切り揃えたガラス繊維を重ねエポキシ樹脂を含浸させたガラスコンポジット基板、 ガラス繊維製の布（クロス）を重ねたものに、エポキシ樹脂を含浸させたガラスエポキシ基板などが用いられる。 Here, a rigid substrate having a thickness of 0.02 to 0.05 mm is used as the substrate 1. From the type of composition, a paper phenol substrate in which paper is impregnated with phenol resin, and a paper epoxy substrate in which paper is impregnated with epoxy resin A glass composite substrate in which cut glass fibers are laminated and impregnated with an epoxy resin, a glass epoxy substrate in which an epoxy resin is impregnated on a glass fiber cloth (cloth), and the like are used.
また、配線パターン４は、その主成分に銅が用いられ、基板１の両面に配線パターンが印刷されて形成されている。そして、絶縁樹脂層５は、熱硬化性樹脂組成物及び高弾性基材からなる熱硬化性接着材料である。そして、絶縁樹脂層５は、４枚の基板１の間に積層され、加熱加圧されることにより、４枚の基板１が接着されるとともに、基板１上の配線パターン４が埋設され多層配線基板２が形成されている。 The wiring pattern 4 is formed by using copper as a main component and printing the wiring pattern on both surfaces of the substrate 1. And the insulating resin layer 5 is a thermosetting adhesive material which consists of a thermosetting resin composition and a highly elastic base material. The insulating resin layer 5 is laminated between the four substrates 1 and heated and pressed to bond the four substrates 1 and embed the wiring pattern 4 on the substrate 1 so that the multilayer wiring is provided. A substrate 2 is formed.
さらに、緩衝部６は、基板１より熱伝導率が低く、絶縁性があり、弾性係数が小さい合成樹脂などの材質により形成されている。また、絶縁樹脂層５と同質の材料である熱硬化性樹脂組成物及び高弾性基材からなる熱硬化性接着材料を用いることもできる。そして、緩衝部６が多層配線基板２の最表層の基板１ａに加熱加圧されることにより接着されている。また、緩衝部６は、厚さ寸法が０．０５〜１．０ｍｍに形成されている。 Further, the buffer portion 6 is made of a material such as a synthetic resin having a lower thermal conductivity than the substrate 1, an insulating property, and a small elastic coefficient. Also, a thermosetting resin composition made of the same material as the insulating resin layer 5 and a thermosetting adhesive material made of a highly elastic base material can be used. The buffer 6 is bonded to the outermost substrate 1a of the multilayer wiring board 2 by being heated and pressed. Moreover, the buffer part 6 has a thickness dimension of 0.05 to 1.0 mm.
また、接続部９は、導体にめっきを施したものであり、緩衝部６を貫通して、最表層の基板１ａの配線パターン４に導通し、かつ外表面６ａに露出して形成されている。そして、緩衝部６の外表面６ａに露出した接続部９に、はんだ７により電子部品８の端子部が接合され、電子部品実装基板３が形成されている。 The connecting portion 9 is formed by plating the conductor, penetrates the buffer portion 6, is electrically connected to the wiring pattern 4 of the outermost substrate 1a, and is exposed to the outer surface 6a. . And the terminal part of the electronic component 8 is joined to the connection part 9 exposed to the outer surface 6a of the buffer part 6 with the solder 7, and the electronic component mounting board 3 is formed.
なお、はんだ７は、無鉛はんだが用いられている。この無鉛はんだは、３元系の錫−銀−銅の合金である。そして、その組成としては、Ｓｎ−３．５Ａｇ−０．７Ｃｕ、Ｓｎ−３．０Ａｇ−０．５Ｃｕ等がある。またこれ以外にも、３元系のＳｎ−Ａｇ−Ｂｉ、Ｓｎ−Ｃｕ−Ｎｉ（Ｎｉは微量添加物）、４元系のＳｎ−Ａｇ−Ｃｕ−Ｂｉ、５元系のＳｎ−Ａｇ−Ｃｕ−Ｂｉ−Ｇｅ等の無鉛はんだがある。 The solder 7 is lead-free solder. This lead-free solder is a ternary tin-silver-copper alloy. And as the composition, there are Sn-3.5Ag-0.7Cu, Sn-3.0Ag-0.5Cu, and the like. In addition, ternary Sn—Ag—Bi, Sn—Cu—Ni (Ni is a trace additive), quaternary Sn—Ag—Cu—Bi, quinary Sn—Ag—Cu -There are lead-free solders such as Bi-Ge.
（第２の実施形態）
図２は、本発明に係る電子部品実装基板３の第２の実施形態を示すものであり、図３および図４は、その変形例を示すものである。
なお、これらの図において、第１の実施形態に示したものと同一構成部分については、同一符号を付してその説明を簡略化する。
(Second Embodiment)
FIG. 2 shows a second embodiment of the electronic component mounting board 3 according to the present invention, and FIGS. 3 and 4 show a modification thereof.
In these drawings, the same components as those shown in the first embodiment are denoted by the same reference numerals and the description thereof is simplified.
図２（ｂ）に示すように、電子部品実装基板３は、配線パターン４が形成された４枚の基板１を、絶縁樹脂層５を間に介装して多層配線基板２を形成し、その最表層の基板１ａと、電子部品８との間に層状をなす緩衝部６が、最表層の基板１ａの全面を覆って形成されているとともに、基板１の配線パターン４と導通し、かつ緩衝部６の外表面６ａに露出した接続部９に、電子部品８の端子部がはんだ７により接合され概略構成されている。 As shown in FIG. 2 (b), the electronic component mounting board 3 forms the multilayer wiring board 2 with the insulating resin layer 5 interposed between the four boards 1 on which the wiring patterns 4 are formed, A buffer portion 6 that forms a layer between the outermost substrate 1a and the electronic component 8 is formed so as to cover the entire surface of the outermost substrate 1a, and is electrically connected to the wiring pattern 4 of the substrate 1. The terminal part of the electronic component 8 is joined to the connection part 9 exposed on the outer surface 6 a of the buffer part 6 by the solder 7, and is schematically configured.
ここで、基板１は、両面に配線パターン４が印刷されて形成されている。そして、絶縁樹脂層５が、４枚の基板１の間に積層され、加熱加圧されることにより、４枚の基板１が接着されるとともに、基板１上の配線パターン４が埋設され多層配線基板２が形成されている。 Here, the board | substrate 1 is formed by printing the wiring pattern 4 on both surfaces. Then, the insulating resin layer 5 is laminated between the four substrates 1 and heated and pressed to bond the four substrates 1 and embed the wiring pattern 4 on the substrate 1 so that the multilayer wiring is provided. A substrate 2 is formed.
さらに、緩衝部６が多層配線基板２の最表層の基板１ａの全面に加熱加圧されることにより接着される。そして、緩衝部６の外表面６ａに露出した接続部９に、はんだ７により電子部品８の端子部が接合され、電子部品実装基板３が形成されている。 Further, the buffer section 6 is bonded to the entire surface of the outermost substrate 1a of the multilayer wiring board 2 by being heated and pressurized. And the terminal part of the electronic component 8 is joined to the connection part 9 exposed to the outer surface 6a of the buffer part 6 with the solder 7, and the electronic component mounting board 3 is formed.
また、図３（ａ）の変形例では、４枚の基板１を絶縁樹脂層５を間に介装して多層配線基板２が形成され、この多層配線基板２の最表層の基板１ａと、電子部品８との間に層状をなす緩衝部６が、最表層の基板１ａの全面を覆って形成され、さらに層状をなす緩衝部６が下面側の最表層の基板１ｂの全面を覆って形成されているとともに、基板１の配線パターン４と導通し、かつ緩衝部６の外表面６ａに露出した接続部９に、電子部品８の端子部がはんだ７により接合され概略構成されている。 Further, in the modification of FIG. 3A, a multilayer wiring board 2 is formed by interposing four substrates 1 with an insulating resin layer 5 interposed therebetween, and a substrate 1a as the outermost layer of the multilayer wiring board 2; A buffer portion 6 that forms a layer with the electronic component 8 is formed so as to cover the entire surface of the outermost substrate 1a, and further, a buffer portion 6 that forms a layer covers the entire surface of the substrate 1b on the lowermost layer. In addition, the terminal portion of the electronic component 8 is joined to the connection portion 9 that is electrically connected to the wiring pattern 4 of the substrate 1 and exposed to the outer surface 6 a of the buffer portion 6 by the solder 7.
さらに、図３（ｂ）の変形例では、基板１、配線パターン４，絶縁樹脂層５、緩衝部６の構成を図２に示す電子部品実装基板３と同一にし、緩衝部６の厚さ寸法を図２に示す緩衝部６より大きくしするとともに、絶縁樹脂層５の厚さ寸法を図２に示す絶縁樹脂層５より小さくすることにより、電子部品８の直下に配設され配線パターン４との距離を大きくし、断熱効果を高めるとともに、配線パターン４の熱歪みを吸収し易くするように形成されている。 Further, in the modification of FIG. 3B, the configuration of the substrate 1, the wiring pattern 4, the insulating resin layer 5, and the buffer portion 6 is the same as that of the electronic component mounting substrate 3 shown in FIG. 2 is made larger than the buffer portion 6 shown in FIG. 2, and the thickness dimension of the insulating resin layer 5 is made smaller than that of the insulating resin layer 5 shown in FIG. The distance is increased to increase the heat insulation effect and to easily absorb the thermal distortion of the wiring pattern 4.
また、図４（ａ）の変形例では、３枚の基板１を絶縁樹脂層５を間に介装して多層配線基板２が形成され、この多層配線基板２の最表層の基板１ａと、電子部品８との間に層状をなす緩衝部６が、最表層の基板１ａの全面を覆って形成され、さらに層状をなす緩衝部６が下面側の最表層の基板１ｂの全面を覆って形成されているとともに、基板１の配線パターン４と導通し、かつ緩衝部６の外表面６ａに露出した接続部９に、電子部品８の端子部がはんだ７により接合され概略構成されている。なお、この変形例では、緩衝部６の外表面６ａに接続部９を形成し、この接続部９を配線パターン４とすることにより、基板１の積層数を減らすことができ、絶縁樹脂層５を厚さ寸法を大きくすることができる。 4A, a multilayer wiring board 2 is formed by interposing three substrates 1 with an insulating resin layer 5 interposed therebetween, and a substrate 1a as the outermost layer of the multilayer wiring board 2, A buffer portion 6 that forms a layer with the electronic component 8 is formed so as to cover the entire surface of the outermost substrate 1a, and further, a buffer portion 6 that forms a layer covers the entire surface of the substrate 1b on the lowermost layer. In addition, the terminal portion of the electronic component 8 is joined to the connection portion 9 that is electrically connected to the wiring pattern 4 of the substrate 1 and exposed to the outer surface 6 a of the buffer portion 6 by the solder 7. In this modification, the connection portion 9 is formed on the outer surface 6 a of the buffer portion 6, and the connection portion 9 is used as the wiring pattern 4, whereby the number of stacked substrates 1 can be reduced, and the insulating resin layer 5. The thickness dimension can be increased.
そして、図４（ｂ）の変形例では、図４（ａ）に示す電子部品実装基板３と同様に、３枚の基板１を絶縁樹脂層５を間に介装して多層配線基板２が形成され、この多層配線基板２の最表層の基板１ａと、電子部品８との間に層状をなす緩衝部６が、最表層の基板１ａの全面を覆って形成され、さらに層状をなす緩衝部６が下面側の最表層の基板１ｂの全面を覆って形成されているとともに、基板１の配線パターン４と導通し、かつ緩衝部６の外表面６ａに露出した接続部９に、電子部品８の端子部がはんだ７により接合され概略構成されている。この変形例では、図４（ａ）の電子部品実装基板３の緩衝部６よりも、厚さ寸法を大きくするとともに、絶縁樹脂層５の厚さ寸法を小さくして形成し、さらに、緩衝部６の外表面６ａに形成された接続部９を配線パターン４とすることによって、基板１の積層数を減らすことができ、さらに絶縁樹脂層５の厚さ寸法を小さくすることにより、多層配線基板２全体の厚さ寸法を小さくすることができる。 4B, similarly to the electronic component mounting board 3 shown in FIG. 4A, the multilayer wiring board 2 includes three substrates 1 with an insulating resin layer 5 interposed therebetween. A buffer portion 6 formed and formed between the outermost substrate 1a of the multilayer wiring board 2 and the electronic component 8 is formed so as to cover the entire surface of the outermost substrate 1a. 6 is formed so as to cover the entire surface of the lowermost substrate 1b on the lower surface side, is electrically connected to the wiring pattern 4 of the substrate 1, and is connected to the connection portion 9 exposed on the outer surface 6a of the buffer portion 6 with the electronic component 8 These terminal portions are joined together by solder 7 so as to be roughly configured. In this modification, the thickness is made larger than that of the buffer portion 6 of the electronic component mounting substrate 3 of FIG. 4A, and the thickness of the insulating resin layer 5 is made smaller. By using the connection portion 9 formed on the outer surface 6a of the wiring 6 as the wiring pattern 4, the number of stacked substrates 1 can be reduced, and by further reducing the thickness dimension of the insulating resin layer 5, a multilayer wiring board can be obtained. The thickness dimension of 2 whole can be made small.
以上の構成による電子部品実装基板を用いることにより、多層配線基板２の最表層の基板１の表面に形成した緩衝部６が、耐熱疲労性の改善に効果的があることを発明者らが行った実験を用いて説明する。 By using the electronic component mounting substrate having the above configuration, the inventors have performed that the buffer portion 6 formed on the surface of the outermost substrate 1 of the multilayer wiring substrate 2 is effective in improving the heat fatigue resistance. This will be explained using the experiment.
＜実施例＞
今回の実験では、図６に示すように、ある電子部品８をはんだ７で多層配線基板２に接続した有限要素解析形状モデルを用いて解析を行った。
なお、このモデルで想定した温度サイクル条件及び各部の構成などの解析条件については、以下の通りである。
<Example>
In this experiment, as shown in FIG. 6, an analysis was performed using a finite element analysis shape model in which a certain electronic component 8 was connected to the multilayer wiring board 2 with solder 7.
The temperature cycling conditions assumed in this model and the analysis conditions such as the configuration of each part are as follows.
１．温度サイクルは、１２５℃〜-−５５℃におけるはんだ接合部に蓄積される塑性歪みを計算した。
２．チップ部品はセラミック、チップの電極部と基板配線部は銅、はんだはＳｎ−３．０Ａｇ−０．５Ｃｕ合金
３．基板の物性値はガラスコンポジット基板（ＣＥＭ−３）を想定
４．チップ部品サイズ２．０×１．０ｍｍ、部品厚さ０．４８ｍｍ、チップ部品と-基板の間隔０．０８ｍｍ
５．チップ電極の厚さ０．０１５ｍｍ、基板電極部の厚さ０．０５ｍｍ
６．基板の厚み１．２ｍｍ、内部配線パターンの厚み３５μｍ、コア基板の厚み３０μｍ
７．配線パターンの層数８層
８．本発明で提案する歪み抑制体（セラミックシート）の設置状況を以下の４通りで解析する。
（ａ）絶縁樹脂層５の厚みを２６７μｍに設定、緩衝部６の設置無し（従来の多層基板構成） 図６（ａ）
（ｂ）絶縁樹脂層５の厚みを９０μｍ、緩衝部６を厚み２６５μｍで上下に設置（両面実装を想定） 図６（ｂ）
（ｃ）絶縁樹脂層５の厚みを９０μｍ、緩衝部６の厚み５３０μｍ（片面実装を想定した構成） 図６（ｃ）
（ｄ）内部配線パターンの存在しない構成(単層基板) 図無し
1. For the temperature cycle, the plastic strain accumulated in the solder joint at 125 ° C. to −55 ° C. was calculated.
2. 2. Chip component is ceramic, chip electrode and substrate wiring are copper, solder is Sn-3.0Ag-0.5Cu alloy The physical properties of the substrate are assumed to be a glass composite substrate (CEM-3)
4). Chip component size 2.0 x 1.0 mm, component thickness 0.48 mm, distance between chip component and substrate-0.08 mm
5. Chip electrode thickness 0.015 mm, substrate electrode thickness 0.05 mm
6). Substrate thickness 1.2 mm, internal wiring pattern thickness 35 μm, core substrate thickness 30 μm
7). 7. Number of wiring pattern layers 8 The installation state of the strain suppression body (ceramic sheet) proposed in the present invention is analyzed in the following four ways.
(A) The thickness of the insulating resin layer 5 is set to 267 μm, and the buffer section 6 is not installed (conventional multilayer board configuration).
(B) The insulating resin layer 5 has a thickness of 90 μm and the buffer 6 has a thickness of 265 μm and is installed vertically (assuming double-sided mounting).
(C) The thickness of the insulating resin layer 5 is 90 μm, and the thickness of the buffer portion 6 is 530 μm (configuration assuming single-sided mounting).
(D) Configuration without internal wiring pattern (single layer board)
上記の条件により解析した結果、電子部品８側面の下側のコーナー部近傍のはんだ部に強い応力集中が発生した。この応力集中の度合いは（ａ）、（ｂ）、（ｃ）、（ｄ）の順に小さくなった。解析結果より得られるコーナー部のはんだに蓄積される塑性歪み量（非線形歪み振幅）と実際の温度サイクル試験結果の相関をとることで、類似構成での破断発生サイクル数などを予測することができる。例えば図６（ａ）に示す本発明を用いない標準的な部品構成では、温度サイクル１２５℃〜−５５℃における破断サイクル数は、約４８０回となった。同様に計算結果より各構成での破断サイクル数を予測すると図６（ｂ）の構成において、７３８回、（ｃ）の構成で１１３０回、（ｄ）の構成において、１２２０回となった。 As a result of analysis under the above conditions, strong stress concentration occurred in the solder portion near the lower corner of the side surface of the electronic component 8. The degree of stress concentration decreased in the order of (a), (b), (c), and (d). By correlating the amount of plastic strain (nonlinear strain amplitude) accumulated in the solder at the corner obtained from the analysis results and the actual temperature cycle test results, the number of cycles at which fracture occurs in a similar configuration can be predicted. . For example, in the standard component structure not using the present invention shown in FIG. 6A, the number of fracture cycles at a temperature cycle of 125 ° C. to −55 ° C. is about 480 times. Similarly, when the number of fracture cycles in each configuration is predicted from the calculation results, it was 738 in the configuration of FIG. 6B, 1130 in the configuration of (c), and 1220 in the configuration of (d).
すなわち、いずれも同じ厚みの多層配線基板２でありながら、片面実装では疲労寿命が２．４倍、両面実装でも１．５倍の寿命向上効果が得られることが分かった。同型のチップサイズ・はんだ形状、同材質の基板を用いた条件では、図６（ａ）に示す構成では、上記に述べた通り寿命増加効果が得られることは殆どない。しかし、図６（ｂ）および（ｃ）において、極めて高い効果が得られていることが分かった。特に図６（ｃ）においては、内部配線パターンのない基板構造（ｄ）と殆ど同じ値にまで疲労寿命が回復している。 That is, it was found that although both were multilayer wiring boards 2 having the same thickness, fatigue life was improved 2.4 times in single-sided mounting and 1.5 times in double-sided mounting. Under the conditions using the same type of chip size / solder shape and substrate of the same material, the configuration shown in FIG. 6 (a) hardly provides the effect of increasing the life as described above. However, in FIGS. 6B and 6C, it was found that an extremely high effect was obtained. In particular, in FIG. 6C, the fatigue life has recovered to almost the same value as the substrate structure (d) having no internal wiring pattern.
また、緩衝部６の厚みが０．５ｍｍ程度あれば、応力緩和の効果がほぼ最大限に得られていることが分かった。図６（ｂ）においては、緩衝部６の厚みが薄いため、そこまでの効果はないが、図６（ａ）に比べると明らかに高い疲労寿命を持ち、緩衝部６による寿命向上の効果の高いことが分かる。 Further, it was found that if the thickness of the buffer portion 6 is about 0.5 mm, the effect of stress relaxation is almost maximized. In FIG. 6 (b), since the thickness of the buffer portion 6 is thin, there is no effect so far. However, compared with FIG. I understand that it is expensive.
上述の実施形態による電子部品実装基板３によれば、多層配線基板２は、最表層の基板１ａと電子部品８との間に緩衝部６が形成されているため、電子部品８の通電時の発熱を遮断して、熱膨張率および剛性が高い銅材料からなる配線パターン４に熱を伝わりにくくするとともに、電子部品８の通電時の発熱によって、配線パターン４に熱歪みが生じた場合には、その熱歪みを吸収することができる。これにより、上記実施例に示す実験結果から分かるように、基板１に電子部品８を接合しているはんだ７に、熱歪みによるストレスの蓄積が抑制され、鉛フリーはんだの破損を防止することができ、電子部品実装基板３の使用寿命や信頼性を向上させることができる。 According to the electronic component mounting substrate 3 according to the above-described embodiment, the multilayer wiring substrate 2 has the buffer portion 6 formed between the outermost layer substrate 1a and the electronic component 8, and therefore when the electronic component 8 is energized. When heat generation is interrupted to make it difficult for heat to be transmitted to the wiring pattern 4 made of a copper material having a high coefficient of thermal expansion and rigidity, and when heat distortion occurs in the wiring pattern 4 due to heat generation when the electronic component 8 is energized. The heat distortion can be absorbed. As a result, as can be seen from the experimental results shown in the above-described embodiment, accumulation of stress due to thermal strain is suppressed in the solder 7 joining the electronic component 8 to the substrate 1, and damage to the lead-free solder can be prevented. The service life and reliability of the electronic component mounting board 3 can be improved.
また、電子部品８を高密度化されて実装する場合でも、多層配線基板２の内層において、配線パターン４の無理な設計変更などを行う必要がなく、残銅率を高くすることができ、放熱性を向上させることができるとともに、配線パターン４を複雑な形状にすることがないため、放射ノイズの発生を抑えることができる。 Even when the electronic component 8 is mounted with a high density, there is no need to forcibly change the design of the wiring pattern 4 in the inner layer of the multilayer wiring board 2, and the residual copper ratio can be increased, and heat dissipation can be achieved. In addition, the wiring pattern 4 does not have a complicated shape, and generation of radiation noise can be suppressed.
そして、緩衝部６の外表面６ａに露出して上記電子部品を上記はんだ７により接合する接続部９が形成されているため、最表層の基板１ａと電子部品８との間にに形成された緩衝部６を絶縁性のある材質により形成しても、基板１に形成された配線パターン４と簡便に導通させることができる。 And since the connection part 9 which is exposed to the outer surface 6a of the buffer part 6 and joins the said electronic component with the said solder 7 is formed, it was formed between the board | substrate 1a of the outermost layer, and the electronic component 8. Even if the buffer portion 6 is formed of an insulating material, it can be easily conducted to the wiring pattern 4 formed on the substrate 1.
さらに、緩衝部６が、多層配線基板２の最表層の基板１ａの全面を覆う層状に形成されているとともに、絶縁樹脂層５と同じ材質により形成されているため、接続部９などを自由にレイアウトすることができるとともに、機械特性や熱膨張率を等しくすることができる。これにより、緩衝部６が新たなストレスや反りの発生源になることがないとともに、良好な信頼性を持たせることができる。 Further, since the buffer portion 6 is formed in a layer covering the entire surface of the outermost substrate 1a of the multilayer wiring board 2 and is formed of the same material as the insulating resin layer 5, the connection portion 9 and the like can be freely set. In addition to being able to lay out, mechanical characteristics and thermal expansion coefficient can be made equal. Thereby, the buffer part 6 does not become a source of new stress and warpage, and can have good reliability.
また、多層配線基板２を製造する際に、配線パターン４が形成された基板１や絶縁樹脂層５と共に、一括して成型することができる。この結果、容易に製造することができるとともに、新たな工程を追加することがなく製造コストを抑えることができる。 Further, when the multilayer wiring substrate 2 is manufactured, it can be molded together with the substrate 1 on which the wiring pattern 4 is formed and the insulating resin layer 5. As a result, it can be manufactured easily, and the manufacturing cost can be reduced without adding a new process.
そして、図４（ａ）および（ｂ）に示すように、接続部９が、緩衝部６の外表面６ａに形成されている場合には、この接続部９を配線パターン４として用いることができる。これにより、多層配線基板２に積層する配線パターン４を形成した基板１の積層する枚数を減らすことができる。これにより、多層配線基板２全体の厚さ寸法を小さくすることができるとともに、多層配線基板２全体の厚さ寸法を大きくすることなく、緩衝部６の厚さ寸法を大きくすることができる。 4A and 4B, when the connecting portion 9 is formed on the outer surface 6a of the buffer portion 6, this connecting portion 9 can be used as the wiring pattern 4. . Thereby, the number of stacked substrates 1 on which the wiring pattern 4 to be stacked on the multilayer wiring substrate 2 is formed can be reduced. Thereby, the thickness dimension of the entire multilayer wiring board 2 can be reduced, and the thickness dimension of the buffer portion 6 can be increased without increasing the thickness dimension of the entire multilayer wiring board 2.
さらに、緩衝部６を０．０５〜１．０ｍｍの厚さ寸法により形成しているため、電子部品８の通電時の発熱による配線パターン４の銅の熱歪みの影響を少なくすることができるとともに、多層配線基板２の内部残銅率の厚み方向の偏りによって起こる反りの発生を防ぐことができる。 Furthermore, since the buffer part 6 is formed with a thickness of 0.05 to 1.0 mm, the influence of the thermal distortion of the copper of the wiring pattern 4 due to heat generated when the electronic component 8 is energized can be reduced. Further, it is possible to prevent the occurrence of warpage caused by the deviation of the internal copper ratio of the multilayer wiring board 2 in the thickness direction.
なお、上記実施の形態において、配線パターン４が形成された基板１において、配線パターンを両面に形成した基板１を用いる場合のみ説明したが、これに限定されるものではなく、例えば、片面に配線パターンが形成された基板１でも対応可能である。 In the above embodiment, the substrate 1 on which the wiring pattern 4 is formed is described only when the substrate 1 having the wiring pattern formed on both surfaces is used. However, the present invention is not limited to this. The substrate 1 on which a pattern is formed can also be handled.
配線パターンが形成された基板を、絶縁樹脂層を間に介装して複数積層した多層配線基板に利用することができる。 A substrate on which a wiring pattern is formed can be used for a multilayer wiring substrate in which a plurality of layers are stacked with an insulating resin layer interposed therebetween.
１ 基板
１ａ 最表層の基板
１ｂ 最表層の基板
２ 多層配線基板
３ 電子部品実装基板
４ 配線パターン
５ 絶縁樹脂層
６ 緩衝部
７ はんだ
８ 電子部品
９ 接続部
1 substrate 1a outermost layer substrate 1b outermost layer substrate 2 multilayer wiring substrate 3 electronic component mounting substrate 4 wiring pattern 5 insulating resin layer 6 buffer portion 7 solder 8 electronic component 9 connection portion
Claims (4)
上記多層配線基板は、最表層の上記基板と上記電子部品との間に緩衝部が形成されているとともに、上記基板の上記配線パターンと導通し、かつ上記緩衝部の外表面に露出して上記電子部品が上記はんだにより接合される接続部が形成されていることを特徴とする電子部品実装基板。 In an electronic component mounting substrate in which electronic components are mounted by solder bonding on the surface of a multilayer wiring substrate in which a plurality of substrates on which a wiring pattern is formed are laminated with an insulating resin layer interposed therebetween,
The multilayer wiring board has a buffer portion formed between the substrate on the outermost layer and the electronic component, is electrically connected to the wiring pattern of the substrate, and is exposed on the outer surface of the buffer portion. An electronic component mounting board characterized in that a connection portion to which the electronic component is joined by the solder is formed.
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| JP2010221028A JP2012079765A (en) | 2010-09-30 | 2010-09-30 | Electronic component mounting substrate |
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| JP2010221028A JP2012079765A (en) | 2010-09-30 | 2010-09-30 | Electronic component mounting substrate |
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|---|---|
| JP2012079765A true JP2012079765A (en) | 2012-04-19 |
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