JP2012069713A - Interposer, semiconductor device with chip mounting interposer, manufacturing methods of the interposer and semiconductor device - Google Patents

Interposer, semiconductor device with chip mounting interposer, manufacturing methods of the interposer and semiconductor device Download PDF

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JP2012069713A
JP2012069713A JP2010212971A JP2010212971A JP2012069713A JP 2012069713 A JP2012069713 A JP 2012069713A JP 2010212971 A JP2010212971 A JP 2010212971A JP 2010212971 A JP2010212971 A JP 2010212971A JP 2012069713 A JP2012069713 A JP 2012069713A
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interposer
resin
semiconductor device
silicon wafer
protective layer
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JP5577988B2 (en
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Ichiro Kono
一郎 河野
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Casio Computer Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof

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Abstract

PROBLEM TO BE SOLVED: To provide an interposer which prevents cracks and chips on a side surface of a semiconductor substrate, to provide a semiconductor device in which a chip is mounted on the interposer, and to provide manufacturing methods of the interposer and the semiconductor device.SOLUTION: An interposer 10A comprises: a semiconductor substrate 11 having an upper surface on which a conductor circuit 19 is formed; and a protective layer 20A covering a side surface of the semiconductor substrate 11. The semiconductor substrate 11 is made of silicon. The upper surface of the semiconductor substrate is covered with a first insulation film 13 and a lower surface and a side surface are covered with the protective layer 20A. The semiconductor chips 1 and 2 are connected with electric wiring 19 (conductor circuit) of the interposer 10A by solder terminals 3 and 4 and fixed to the upper surface of the interposer 10A by the underfill 5 and 6.

Description

本発明は、インターポーザー、インターポーザーにチップを実装した半導体装置、インターポーザーの製造方法及び半導体装置の製造方法に関する。   The present invention relates to an interposer, a semiconductor device in which a chip is mounted on the interposer, an interposer manufacturing method, and a semiconductor device manufacturing method.

近年、デジタル機器の高機能化、高性能化の要求に応えるために、論理回路とメモリー回路との間のデータ転送速度の向上や、メモリー容量の増加が必要とされている。従来の汎用ＤＲＡＭやＡＳＩＣをＰＣＢ実装する手法では、消費電力や実装面積が大きい。このため、近年、ＤＲＡＭやＡＳＩＣをシリコンインターポーザーに実装する例が報告されつつある（例えば、特許文献１参照）。   In recent years, in order to meet the demand for higher functionality and higher performance of digital devices, it is necessary to improve the data transfer speed between the logic circuit and the memory circuit and increase the memory capacity. In the conventional method of mounting a general-purpose DRAM or ASIC on a PCB, power consumption and mounting area are large. For this reason, in recent years, an example in which a DRAM or ASIC is mounted on a silicon interposer is being reported (for example, see Patent Document 1).

シリコンインターポーザーは、シリコンをベース材料とし、半導体チップと熱膨張係数が同じである。このため、半導体チップをフリップチップ実装しても電気特性がよく、高速・高周波領域でも動作特性がよい。樹脂インターポーザー（ＰＣＢ基板）よりも微細な配線やバンプ形成が可能になる。   The silicon interposer is based on silicon and has the same thermal expansion coefficient as that of the semiconductor chip. For this reason, the electrical characteristics are good even if the semiconductor chip is flip-chip mounted, and the operating characteristics are good even in the high speed / high frequency region. Finer wiring and bumps can be formed than the resin interposer (PCB substrate).

ただし、シリコンインターポーザーはベース材料がシリコン基板なので、裏面や側面で割れや欠けなど発生しやすく、取り扱いは非常にデリケートである。シリコンの割れや欠けを防ぐために、シリコンの裏面を補強することも行われている（例えば、特許文献２、３参照）   However, since the base material of a silicon interposer is a silicon substrate, cracks and chips are likely to occur on the back and side surfaces, and handling is very delicate. In order to prevent cracking and chipping of silicon, the back surface of silicon is also reinforced (see, for example, Patent Documents 2 and 3).

特開２００６−２８６８５３号公報JP 2006-286853 A 特開平５−２３４９７２号公報JP-A-5-234972 特開２００５−１５８９２９号公報JP 2005-158929 A

しかし、シリコンの裏面を補強するのみでは、シリコンの側面における割れや欠けを防ぐことができない。   However, it is not possible to prevent cracks and chips on the side surfaces of the silicon by simply reinforcing the back surface of the silicon.

本発明の課題は、半導体基板の側面における割れや欠けを防ぐことができるインターポーザー、インターポーザーにチップを実装した半導体装置、インターポーザーの製造方法及び半導体装置の製造方法を提供することである。   An object of the present invention is to provide an interposer that can prevent cracks and chips on the side surface of a semiconductor substrate, a semiconductor device in which a chip is mounted on the interposer, a method for manufacturing the interposer, and a method for manufacturing the semiconductor device.

以上の課題を解決するため、本発明の第１の態様によれば、半導体を有するインターポーザー基板と、少なくとも前記インターポーザー基板の側面を被覆する保護層と、を備えることを特徴とするインターポーザーが提供される。   In order to solve the above problems, according to the first aspect of the present invention, an interposer comprising: an interposer substrate having a semiconductor; and a protective layer covering at least a side surface of the interposer substrate. Is provided.

好ましくは、前記保護層は、前記半導体基板の下面を被覆する。
好ましくは、前記インターポーザー基板の上面側に導体回路が設けられ、前記導体回路に集積回路チップが接続されている。 Preferably, the protective layer covers the lower surface of the semiconductor substrate.
Preferably, a conductor circuit is provided on the upper surface side of the interposer substrate, and an integrated circuit chip is connected to the conductor circuit.

本発明の他の態様によれば、シリコンウェハの上面を溝加工することによりダイシングストリートを形成する工程と、前記ダイシングストリートに未硬化の樹脂を充填し硬化させる工程と、硬化された前記樹脂が露出するまで前記シリコンウェハの下面を研削する工程と、前記ダイシングストリートの部分で前記樹脂を切断して、切断された前記樹脂が側面に残るように前記シリコンウェハを分離する工程と、を含むことを特徴とするインターポーザーの製造方法が提供される。   According to another aspect of the present invention, a step of forming a dicing street by grooving an upper surface of a silicon wafer, a step of filling and curing an uncured resin in the dicing street, and the cured resin Grinding the lower surface of the silicon wafer until it is exposed, and cutting the resin at a portion of the dicing street, and separating the silicon wafer so that the cut resin remains on the side surface. An interposer manufacturing method is provided.

本発明の他の態様によれば、シリコンウェハの上面を溝加工することによりダイシングストリートを形成する工程と、前記ダイシングストリートに未硬化の樹脂を充填し硬化させる工程と、硬化された前記樹脂が露出するまで前記シリコンウェハの下面を研削する工程と、前記シリコンウェハの下面に樹脂を形成する工程と、前記ダイシングストリートの部分で前記樹脂を切断して、切断された前記樹脂が側面に残るように前記シリコンウェハを分離する工程と、を含むことを特徴とするインターポーザーの製造方法が提供される。   According to another aspect of the present invention, a step of forming a dicing street by grooving an upper surface of a silicon wafer, a step of filling and curing an uncured resin in the dicing street, and the cured resin Grinding the lower surface of the silicon wafer until it is exposed; forming a resin on the lower surface of the silicon wafer; and cutting the resin at a portion of the dicing street so that the cut resin remains on the side surface And a step of separating the silicon wafer. The method for manufacturing an interposer is provided.

本発明の他の態様によれば、前記インターポーザーの製造方法により製造されたインターポーザーの上面側に設けられた導体回路に、集積回路チップを接続することを特徴とする半導体装置の製造方法が提供される。   According to another aspect of the present invention, there is provided a semiconductor device manufacturing method, wherein an integrated circuit chip is connected to a conductor circuit provided on an upper surface side of an interposer manufactured by the interposer manufacturing method. Provided.

本発明によれば、半導体基板の側面における割れや欠けを防ぐことができるインターポーザー、インターポーザーにチップを実装した半導体装置、インターポーザーの製造方法及び半導体装置の製造方法を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the interposer which can prevent the crack and notch | chip in the side surface of a semiconductor substrate, the semiconductor device which mounted the chip | tip on the interposer, the manufacturing method of an interposer, and the manufacturing method of a semiconductor device can be provided.

本発明の第１実施形態に係る半導体装置１Ａを示す平面図である。1 is a plan view showing a semiconductor device 1A according to a first embodiment of the present invention. 図１のII−II矢視断面図である。It is II-II arrow sectional drawing of FIG. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ａの製造方法の説明図である。It is explanatory drawing of the manufacturing method of 1 A of semiconductor devices. 半導体装置１Ｂの断面図である。It is sectional drawing of the semiconductor device 1B. 半導体装置１Ｃの断面図である。It is sectional drawing of 1 C of semiconductor devices.

〔第１実施形態〕
図１は本発明の第１実施形態に係るインターポーザー１０Ａを用いた半導体装置１Ａを示す平面図であり、図２は図１のII−II矢視断面図である。図１、図２に示すように、半導体装置１Ａは、複数の集積回路チップ１、２と、インターポーザー１０Ａと、等を備える。 [First Embodiment]
FIG. 1 is a plan view showing a semiconductor device 1A using an interposer 10A according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II in FIG. As shown in FIGS. 1 and 2, the semiconductor device 1 </ b> A includes a plurality of integrated circuit chips 1 and 2, an interposer 10 </ b> A, and the like.

集積回路チップ１、２は、半田端子３、４によりインターポーザー１０Ａの配線１９（導体回路）に接続されるとともに、アンダーフィル５、６によりインターポーザー１０Ａの上面に固定されている。集積回路チップ１、２は、例えばＤＲＡＭ、ＡＳＩＣ等である。   The integrated circuit chips 1 and 2 are connected to the wiring 19 (conductor circuit) of the interposer 10 </ b> A by the solder terminals 3 and 4, and are fixed to the upper surface of the interposer 10 </ b> A by the underfills 5 and 6. The integrated circuit chips 1 and 2 are, for example, a DRAM or an ASIC.

インターポーザー１０Ａは、図２に示すように、半導体基板１１と、第１絶縁膜１３と、配線１９（導体回路）と、第２絶縁膜１４と、保護層２０Ａと、等からなる。   As shown in FIG. 2, the interposer 10A includes a semiconductor substrate 11, a first insulating film 13, a wiring 19 (conductor circuit), a second insulating film 14, a protective layer 20A, and the like.

半導体基板１１はシリコン等からなり、上面を第１絶縁膜５で被覆されるとともに、下面及び側面を保護層２０Ａで被覆されている。
第１絶縁膜１３及び第２絶縁膜１４はポリイミド（ＰＩ）、ポリベンゾオキサゾール（ＰＢＯ）、等の高機能プラスチック材料、エポキシ系、フェノール系、シリコン系等のプラスチック材料、またはこれらの複合材料等からなる。第１絶縁膜１３の上面には、配線１９及び第２絶縁膜１４が形成される。 The semiconductor substrate 11 is made of silicon or the like, and has an upper surface covered with the first insulating film 5 and a lower surface and side surfaces covered with the protective layer 20A.
The first insulating film 13 and the second insulating film 14 are high-functional plastic materials such as polyimide (PI) and polybenzoxazole (PBO), plastic materials such as epoxy, phenol, and silicon, or composite materials thereof. Consists of. A wiring 19 and a second insulating film 14 are formed on the upper surface of the first insulating film 13.

第２絶縁膜１４は、第１絶縁膜１３とともに配線１９を絶縁するものである。第２絶縁膜１４には、配線１９の両端部を露出させる開口１４ａ、１４ｂが設けられている。
配線１９は銅等の導電性材料からなり、開口１４ａ、１４ｂの部分を除き、上面及び側面を第２絶縁膜１４により被覆されている。配線１９の両端部は第２絶縁膜１４の開口１４ａ、１４ｂにより露出されており、配線１９の開口１４ａ、１４ｂから露出した部分がそれぞれ端子１９ａ、１９ｂとなる。図１、図２に示すように、端子１９ａは、半田端子３、４を介して集積回路チップ１、２と接続される。また、端子１９ｂは、半導体装置１Ａの上面外周部に設けられており、他の電子回路と接続される。配線１９により、集積回路チップ１、２や他の電子回路が相互に接続される。 The second insulating film 14 insulates the wiring 19 together with the first insulating film 13. The second insulating film 14 is provided with openings 14 a and 14 b that expose both ends of the wiring 19.
The wiring 19 is made of a conductive material such as copper, and the upper surface and side surfaces thereof are covered with the second insulating film 14 except for the openings 14a and 14b. Both ends of the wiring 19 are exposed through the openings 14a and 14b of the second insulating film 14, and portions exposed from the openings 14a and 14b of the wiring 19 become terminals 19a and 19b, respectively. As shown in FIGS. 1 and 2, the terminal 19 a is connected to the integrated circuit chips 1 and 2 via the solder terminals 3 and 4. The terminal 19b is provided on the outer peripheral portion of the upper surface of the semiconductor device 1A and is connected to other electronic circuits. The integrated circuit chips 1 and 2 and other electronic circuits are connected to each other by the wiring 19.

保護層２０Ａは、半導体基板１１、第１絶縁膜１３及び第２絶縁膜１４の側面と、半導体基板１１の下面とを被覆している。保護層２０Ａは、半導体基板１１を衝撃による割れやひび等から保護する。保護層２０Ａには、耐熱性の樹脂材料を用いることができる。例えば、エポキシ系樹脂、フェノール樹脂、ポリイミド、ポリパラフェニレンベンゾビスオキサゾール（ＰＢＯ）樹脂、ベンゾシクロブテン（ＢＣＢ）樹脂等を用いることができる。   The protective layer 20 </ b> A covers the side surfaces of the semiconductor substrate 11, the first insulating film 13, and the second insulating film 14 and the lower surface of the semiconductor substrate 11. The protective layer 20A protects the semiconductor substrate 11 from cracks and cracks caused by impact. A heat-resistant resin material can be used for the protective layer 20A. For example, epoxy resin, phenol resin, polyimide, polyparaphenylene benzobisoxazole (PBO) resin, benzocyclobutene (BCB) resin, or the like can be used.

次に、インターポーザー１０Ａの保護層２０Ａの製造方法について図３〜図１１を用いて説明する。
図３は半導体基板１１となるダイシング前のシリコンウェハ３１の平面図であり、図４は図３のIV−IV矢視断面図である。なお、図示しないが、シリコンウェハ３１の上面には、第１絶縁膜１３、配線１９、第２絶縁膜１４等が形成される。 Next, the manufacturing method of 20 A of protective layers of 10 A of interposers is demonstrated using FIGS.
FIG. 3 is a plan view of the silicon wafer 31 before dicing to be the semiconductor substrate 11, and FIG. 4 is a cross-sectional view taken along arrows IV-IV in FIG. Although not shown, the first insulating film 13, the wiring 19, the second insulating film 14, and the like are formed on the upper surface of the silicon wafer 31.

まず、シリコンウェハ３１の上面に、第１絶縁膜１３、配線１９、第２絶縁膜１４等を形成する。
次に、図３、図４に示すように、シリコンウェハ３１の上面に、ダイシングストリート３１ａとなる部分を除き、レジスト３２を形成し、ダイシングストリート３１ａとなる部分を溝加工する。溝加工は、レーザー法、ドライエッチング法、ウェットエッチング法等の任意の方法により行うことができる。ダイシングストリート３１ａの幅は１００〜２０００μｍ、深さはシリコンウェハ３１の厚さの１／３〜２／３程度である。 First, the first insulating film 13, the wiring 19, the second insulating film 14, etc. are formed on the upper surface of the silicon wafer 31.
Next, as shown in FIGS. 3 and 4, a resist 32 is formed on the upper surface of the silicon wafer 31 except for the portion that becomes the dicing street 31 a, and the portion that becomes the dicing street 31 a is grooved. The groove processing can be performed by an arbitrary method such as a laser method, a dry etching method, or a wet etching method. The width of the dicing street 31 a is 100 to 2000 μm, and the depth is about 1/3 to 2/3 of the thickness of the silicon wafer 31.

次に、図５に示すように、溝加工により形成されたダイシングストリート３１ａに保護層２０Ａとなる樹脂３３を充填し、硬化（熱硬化、UV硬化等）させる。
次に、図６に示すように、レジスト３２を除去する。
次に、図７に示すように、シリコンウェハ３１の上面にバックグラインドテープ３４を貼り付ける。
次に、図８に示すように、グラインダーにてシリコンウェハ３１の下面を研削し、樹脂３３を露出させる。これにより、シリコンウェハ３１のダイシングストリート３１ａに囲まれた部分が半導体基板１１となる。 Next, as shown in FIG. 5, a dicing street 31a formed by grooving is filled with a resin 33 to be the protective layer 20A and cured (thermal curing, UV curing, etc.).
Next, as shown in FIG. 6, the resist 32 is removed.
Next, as shown in FIG. 7, a back grind tape 34 is attached to the upper surface of the silicon wafer 31.
Next, as shown in FIG. 8, the lower surface of the silicon wafer 31 is ground by a grinder to expose the resin 33. As a result, the portion surrounded by the dicing street 31 a of the silicon wafer 31 becomes the semiconductor substrate 11.

次に、図９に示すように、シリコンウェハ３１の下面に保護層２０Ａとなる樹脂３５を塗布し、硬化（熱硬化、UV硬化等）させる。これにより、保護層２０Ａとなる樹脂３３、３５が一体化する。
次に、図１０に示すように、バックグラインドテープ３４を剥がす。
その後、図１１に示すように、樹脂３３、３５をダイシングする。以上により、インターポーザー１０Ａが完成する。その後、インターポーザー１０Ａ上に集積回路チップ１、２を載置し、リフロー法により半田端子３、４と配線１９とを接続するとともに、アンダーフィル５、６により集積回路チップ１、２を固定する。以上により、半導体装置１Ａが完成する。 Next, as shown in FIG. 9, a resin 35 serving as the protective layer 20 </ b> A is applied to the lower surface of the silicon wafer 31 and cured (thermal curing, UV curing, etc.). Thereby, the resins 33 and 35 to be the protective layer 20A are integrated.
Next, as shown in FIG. 10, the back grind tape 34 is peeled off.
Thereafter, as shown in FIG. 11, the resins 33 and 35 are diced. Thus, the interposer 10A is completed. Thereafter, the integrated circuit chips 1 and 2 are mounted on the interposer 10A, the solder terminals 3 and 4 and the wiring 19 are connected by the reflow method, and the integrated circuit chips 1 and 2 are fixed by the underfills 5 and 6. . Thus, the semiconductor device 1A is completed.

このように、本発明によれば、保護層２０Ａにより半導体基板１１の下面及び側面を被覆することで、半導体基板１１を衝撃による割れやひび等から保護することができる。また、シリコンウェハ３１のダイシングストリート３１ａに保護層２０Ａとなる樹脂３３を充填し、硬化（熱硬化、UV硬化等）させた後にダイシングを行うため、半導体基板１１の下面及び側面を被覆する保護層２０Ａを一括形成することができる。   Thus, according to the present invention, the semiconductor substrate 11 can be protected from cracks and cracks due to impact by covering the lower surface and side surfaces of the semiconductor substrate 11 with the protective layer 20A. In addition, since the dicing street 31a of the silicon wafer 31 is filled with the resin 33 serving as the protective layer 20A and cured (thermal curing, UV curing, etc.), the dicing is performed, so that the protective layer that covers the lower surface and side surfaces of the semiconductor substrate 11 is used. 20A can be collectively formed.

〔第２実施形態〕
図１２は本発明の第２実施形態に係るインターポーザー１０Ｂを用いた半導体装置１Ｂを示す図２と同様の断面図である。なお、第１実施形態と同様の構成については、同符号を付して説明を割愛する。
本実施形態においては、半導体基板１１、第１絶縁膜１３及び第２絶縁膜１４の側面を被覆する保護層２０Ｂのみが設けられている。
インターポーザー１０Ｂの製造方法は、第１実施形態のインターポーザー１０Ａの製造方法において、樹脂３５の塗布プロセスを省略すればよい。 [Second Embodiment]
FIG. 12 is a cross-sectional view similar to FIG. 2 showing a semiconductor device 1B using an interposer 10B according to a second embodiment of the present invention. In addition, about the structure similar to 1st Embodiment, the same code | symbol is attached | subjected and description is omitted.
In the present embodiment, only the protective layer 20B that covers the side surfaces of the semiconductor substrate 11, the first insulating film 13, and the second insulating film 14 is provided.
The interposer 10B may be manufactured by omitting the application process of the resin 35 in the manufacturing method of the interposer 10A of the first embodiment.

本実施形態においても、第１実施形態と同様に、保護層２０Ｂにより半導体基板１１の側面を被覆することで、半導体基板１１を衝撃による割れやひび等から保護することができる。また、シリコンウェハ３１のダイシングストリート３１ａに保護層２０Ａとなる樹脂３３を充填し、硬化（熱硬化、UV硬化等）させた後にダイシングを行うため、半導体基板１１の側面を被覆する保護層２０Ｂを一括形成することができる。さらに、半導体基板１１の下面を被覆しないため、保護層との熱膨張率の差による半導体基板１１の反りを防ぐことができる。   In the present embodiment, similarly to the first embodiment, by covering the side surface of the semiconductor substrate 11 with the protective layer 20B, the semiconductor substrate 11 can be protected from cracks and cracks due to impact. In addition, since the dicing street 31a of the silicon wafer 31 is filled with the resin 33 serving as the protective layer 20A and cured (thermal curing, UV curing, etc.), the dicing is performed, so that the protective layer 20B covering the side surface of the semiconductor substrate 11 is provided. Batch formation is possible. Furthermore, since the lower surface of the semiconductor substrate 11 is not covered, it is possible to prevent the semiconductor substrate 11 from warping due to a difference in thermal expansion coefficient with the protective layer.

〔第３実施形態〕
図１３は本発明の第３実施形態に係るインターポーザー１０Ｃを用いた半導体装置１Ｃを示す図２と同様の断面図である。なお、第１実施形態と同様の構成については、同符号を付して説明を割愛する。
本実施形態においては、半導体基板１１の下面を被覆する保護層２０Ｃのみが設けられている。
インターポーザー１０Ｃの製造方法は、第１実施形態のインターポーザー１０Ａの製造方法において、樹脂３３の塗布プロセスを省略すればよい。 [Third Embodiment]
FIG. 13 is a cross-sectional view similar to FIG. 2, showing a semiconductor device 1C using an interposer 10C according to a third embodiment of the present invention. In addition, about the structure similar to 1st Embodiment, the same code | symbol is attached | subjected and description is omitted.
In the present embodiment, only the protective layer 20 </ b> C that covers the lower surface of the semiconductor substrate 11 is provided.
The manufacturing method of the interposer 10C may omit the application process of the resin 33 in the manufacturing method of the interposer 10A of the first embodiment.

本実施形態においても、第１実施形態と同様に、保護層２０Ｃにより半導体基板１１の下面を被覆することで、半導体基板１１を衝撃による割れやひび等から保護することができる。   Also in the present embodiment, as in the first embodiment, the semiconductor substrate 11 can be protected from cracks and cracks due to impact by covering the lower surface of the semiconductor substrate 11 with the protective layer 20C.

なお、以上の実施形態においては、保護層を樹脂から形成したが、本発明はこれに限らず、金属からなる保護層を形成してもよい。例えば、シリコンウェハ３１の下面に樹脂３５を塗布する代わりに、Ｃｕ、Ａｌ等の金属層や、ＳｉＯ２、ＳｉＮ等の絶縁層を保護層として形成してもよい。金属層や絶縁層は例えばスパッタ法により形成することができる。   In the above embodiment, the protective layer is formed from a resin. However, the present invention is not limited to this, and a protective layer made of metal may be formed. For example, instead of applying the resin 35 to the lower surface of the silicon wafer 31, a metal layer such as Cu or Al, or an insulating layer such as SiO2 or SiN may be formed as a protective layer. The metal layer and the insulating layer can be formed by sputtering, for example.

１Ａ、１Ｂ、１Ｃ 半導体装置
１０Ａ、１０Ｂ、１０Ｃ インターポーザー
１１ 半導体基板
２０Ａ、２０Ｂ、２０Ｃ 保護層
３１ シリコンウェハ
３１ａ ダイシングストリート
３３、３５ 樹脂 1A, 1B, 1C Semiconductor devices 10A, 10B, 10C Interposer 11 Semiconductor substrate 20A, 20B, 20C Protective layer 31 Silicon wafer 31a Dicing street 33, 35 Resin

Claims (6)

半導体を有するインターポーザー基板と、
少なくとも前記インターポーザー基板の側面を被覆する保護層と、を備えることを特徴とするインターポーザー。 An interposer substrate having a semiconductor;
A protective layer covering at least a side surface of the interposer substrate. 前記保護層は、前記半導体基板の下面を被覆することを特徴とする請求項１に記載のインターポーザー。   The interposer according to claim 1, wherein the protective layer covers a lower surface of the semiconductor substrate. 請求項１または２に記載のインターポーザーの前記インターポーザー基板の上面側に導体回路が設けられ、前記導体回路に集積回路チップが接続されていることを特徴とする半導体装置。   3. A semiconductor device, wherein a conductor circuit is provided on an upper surface side of the interposer substrate of the interposer according to claim 1 and an integrated circuit chip is connected to the conductor circuit. シリコンウェハの上面を溝加工することによりダイシングストリートを形成する工程と、
前記ダイシングストリートに未硬化の樹脂を充填し硬化させる工程と、
硬化された前記樹脂が露出するまで前記シリコンウェハの下面を研削する工程と、
前記ダイシングストリートの部分で前記樹脂を切断して、切断された前記樹脂が側面に残るように前記シリコンウェハを分離する工程と、
を含むことを特徴とするインターポーザーの製造方法。 Forming a dicing street by grooving the upper surface of the silicon wafer;
Filling and curing the uncured resin in the dicing street;
Grinding the lower surface of the silicon wafer until the cured resin is exposed;
Cutting the resin at a portion of the dicing street, and separating the silicon wafer so that the cut resin remains on the side surface;
A process for producing an interposer, comprising: シリコンウェハの上面を溝加工することによりダイシングストリートを形成する工程と、
前記ダイシングストリートに未硬化の樹脂を充填し硬化させる工程と、
硬化された前記樹脂が露出するまで前記シリコンウェハの下面を研削する工程と、
前記シリコンウェハの下面に樹脂を形成する工程と、
前記ダイシングストリートの部分で前記樹脂を切断して、切断された前記樹脂が側面に残るように前記シリコンウェハを分離する工程と、
を含むことを特徴とするインターポーザーの製造方法。 Forming a dicing street by grooving the upper surface of the silicon wafer;
Filling and curing the uncured resin in the dicing street;
Grinding the lower surface of the silicon wafer until the cured resin is exposed;
Forming a resin on the lower surface of the silicon wafer;
Cutting the resin at a portion of the dicing street, and separating the silicon wafer so that the cut resin remains on the side surface;
A process for producing an interposer, comprising: 請求項４または５に記載のインターポーザーの製造方法により製造されたインターポーザーの上面側に設けられた導体回路に、集積回路チップを接続する工程を含むことを特徴とする半導体装置の製造方法。   6. A method for manufacturing a semiconductor device, comprising a step of connecting an integrated circuit chip to a conductor circuit provided on an upper surface side of an interposer manufactured by the method for manufacturing an interposer according to claim 4 or 5.
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