JP2012042281A - Semiconductor integrated circuit, and method of gate screening test of semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit, and method of gate screening test of semiconductor integrated circuit Download PDF

Info

Publication number
JP2012042281A
JP2012042281A JP2010182369A JP2010182369A JP2012042281A JP 2012042281 A JP2012042281 A JP 2012042281A JP 2010182369 A JP2010182369 A JP 2010182369A JP 2010182369 A JP2010182369 A JP 2010182369A JP 2012042281 A JP2012042281 A JP 2012042281A
Authority
JP
Japan
Prior art keywords
circuit
gate
type semiconductor
screening test
mos type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2010182369A
Other languages
Japanese (ja)
Other versions
JP5382544B2 (en
Inventor
Takasato Oe
崇智 大江
Naoki Kumagai
直樹 熊谷
Tomoyuki Yamazaki
智幸 山崎
Takahiro Mori
貴浩 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2010182369A priority Critical patent/JP5382544B2/en
Publication of JP2012042281A publication Critical patent/JP2012042281A/en
Application granted granted Critical
Publication of JP5382544B2 publication Critical patent/JP5382544B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, in which a plurality of MOS type semiconductor elements are integrated, for efficiently performing a gate screening test.SOLUTION: An IC 400 is an integrated circuit in which four channels of a MOS type semiconductor element MOSFET and its control circuit are provided in one chip. Voltage level shift circuits 405-408 are connected to gate electrodes of power MOSFETs 401-404, and control circuits 409-412 are connected to the respective voltage level shift circuits. All of the gate electrodes from the MOSFETs are connected to a reverse current preventing circuit 413, and one gate screening test terminal G is connected to the end of the reverse current preventing circuit 413. Input terminals IN1-IN4 are connected to inputs of control circuits 409-412, drain terminals D1-D4 are connected to a power source, source terminals S1-S4 are connected to the ground. Source electrodes of the power MOSFETs 401-404 are connected to the source terminals S1-S4, and their drain electrodes are connected to the drain terminals D1-D4.

Description

本発明は、半導体集積回路および半導体集積回路に対するゲートスクリーニング試験の方法に関し、より詳細には、複数のＭＯＳ型半導体素子が集積された半導体集積回路および当該半導体集積回路に対するゲートスクリーニング試験の方法に関する。   The present invention relates to a semiconductor integrated circuit and a gate screening test method for the semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which a plurality of MOS type semiconductor elements are integrated and a gate screening test method for the semiconductor integrated circuit.

近年、パワーＭＯＳＦＥＴや絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ）等のＭＯＳ型半導体素子を出力段とする半導体集積回路（ＩＣ）が開発されている。このような半導体集積回路の信頼性を高めるために、ＭＯＳ型半導体素子のゲートに対してゲートスクリーニング試験が行われる。ウェーハプロセスを終了した時点でチップを試験し、欠陥を有する製品が排除される。   In recent years, semiconductor integrated circuits (ICs) using MOS type semiconductor elements such as power MOSFETs and insulated gate bipolar transistors (IGBTs) as an output stage have been developed. In order to increase the reliability of such a semiconductor integrated circuit, a gate screening test is performed on the gate of the MOS type semiconductor device. At the end of the wafer process, the chip is tested and defective products are eliminated.

特許文献１には、ＭＯＳ型半導体素子と当該ＭＯＳ型半導体素子の制御回路とを同一半導体基体に集積したＩＣにおいて、ＭＯＳ型半導体素子よりも低耐圧である制御回路に悪影響を及ぼすことなく、ＭＯＳ型半導体素子のゲート酸化膜周辺の異常品を低チップ温度、短時間の試験で除去する技術が開示されている。図１は、特許文献１に開示された発明に係るＩＣを示しており、ＭＯＳ型半導体素子であるＭＯＳＦＥＴ１と、ＭＯＳＦＥＴ１の制御回路２と、ＭＯＳＦＥＴ１のゲート電極１６に接続された試験用ゲート端子Ｇと、ＭＯＳＦＥＴ１と制御回路２との間に接続された電圧レベルシフト回路６とを備える。ＭＯＳＦＥＴ１のゲート電極１６に試験用ゲート端子Ｇを接続したことにより、高いゲート電圧をゲート電極１６に印加することができ、低耐圧の制御回路２が一緒に集積化されていないＭＯＳＦＥＴ単体の場合と同様に、低チップ温度で短時間にゲート酸化膜周辺の異常部を破壊させることができる。高印加電圧の制御回路２に対する悪影響を抑えるために、制御回路２とＭＯＳＦＥＴ１との間に電圧レベルシフト回路６が設けられており、電圧レベルシフト回路６は、試験用ゲート端子Ｇに与えられた高電圧を制御回路２の側へ低くシフトする。   Patent Document 1 discloses that in an IC in which a MOS type semiconductor element and a control circuit for the MOS type semiconductor element are integrated on the same semiconductor substrate, the MOS circuit does not adversely affect the control circuit having a lower breakdown voltage than the MOS type semiconductor element. A technique for removing abnormal products around the gate oxide film of a type semiconductor element by a test at a low chip temperature for a short time is disclosed. FIG. 1 shows an IC according to the invention disclosed in Patent Document 1, which is a MOSFET 1 that is a MOS type semiconductor element, a control circuit 2 of the MOSFET 1, and a test gate terminal G connected to the gate electrode 16 of the MOSFET 1. And a voltage level shift circuit 6 connected between the MOSFET 1 and the control circuit 2. By connecting the test gate terminal G to the gate electrode 16 of the MOSFET 1, a high gate voltage can be applied to the gate electrode 16, and in the case of a single MOSFET in which the low breakdown voltage control circuit 2 is not integrated together, Similarly, the abnormal part around the gate oxide film can be destroyed in a short time at a low chip temperature. In order to suppress the adverse effect of the high applied voltage on the control circuit 2, a voltage level shift circuit 6 is provided between the control circuit 2 and the MOSFET 1, and the voltage level shift circuit 6 is supplied to the test gate terminal G. The high voltage is shifted down to the control circuit 2 side.

図２は、図１の構成を１チップ内に４チャンネル設けたＩＣの例を示している。パワーＭＯＳＦＥＴ１０１、１０２、１０３、１０４のゲート電極に電圧レベルシフト回路１０５、１０６、１０７、１０８が接続され、電圧レベルシフト回路１０５、１０６、１０７、１０８に制御回路（駆動・検出・保護回路）１０９、１１０、１１１、１１２が接続されている。パワーＭＯＳＦＥＴ１０１、１０２、１０３、１０４のゲート電極に、ゲートスクリーニング試験端子（または端子パッド）Ｇ１、Ｇ２、Ｇ３、Ｇ４が接続されている。制御回路１０９、１１０、１１１、１１２の入力には入力端子（または端子パッド）ＩＮ１、ＩＮ２、ＩＮ３、ＩＮ４、電源にはドレイン端子（または端子パッド）Ｄ１、Ｄ２、Ｄ３、Ｄ４、グランドにはソース端子（または端子パッド）Ｓ１、Ｓ２、Ｓ３、Ｓ４が接続されている。パワーＭＯＳＦＥＴ１０１、１０２、１０３、１０４のソース電極は、ソース端子Ｓ１、Ｓ２、Ｓ３、Ｓ４に、ドレイン電極は、ドレイン端子Ｄ１、Ｄ２、Ｄ３、Ｄ４に接続されている。図３は、図２のＩＣの上面図であり、チップの端子（端子パッド）のみを示す。電圧レベルシフト回路の詳細については特許文献１に説明されており、本明細書では説明しない。   FIG. 2 shows an example of an IC in which the configuration of FIG. 1 is provided in four channels in one chip. The voltage level shift circuits 105, 106, 107, 108 are connected to the gate electrodes of the power MOSFETs 101, 102, 103, 104, and a control circuit (drive / detection / protection circuit) 109 is connected to the voltage level shift circuits 105, 106, 107, 108. , 110, 111, 112 are connected. Gate screening test terminals (or terminal pads) G1, G2, G3, G4 are connected to the gate electrodes of the power MOSFETs 101, 102, 103, 104. Input terminals (or terminal pads) IN1, IN2, IN3, and IN4 are input to the control circuits 109, 110, 111, and 112, drain terminals (or terminal pads) are D1, D2, D3, and D4 as power sources, and sources are as grounds. Terminals (or terminal pads) S1, S2, S3, and S4 are connected. The source electrodes of the power MOSFETs 101, 102, 103, and 104 are connected to the source terminals S1, S2, S3, and S4, and the drain electrodes are connected to the drain terminals D1, D2, D3, and D4. FIG. 3 is a top view of the IC of FIG. 2, showing only the terminals (terminal pads) of the chip. Details of the voltage level shift circuit are described in Patent Document 1 and will not be described in this specification.

図２の例のように、１チップに複数のＭＯＳＦＥＴを有する場合、ＭＯＳＦＥＴ毎にゲートスクリーニング試験端子パッドを設けてゲートスクリーニング試験を実施していたため、ゲートスクリーニング端子パッドの分だけチップサイズが拡大してしまう。また、ゲートスクリーニング試験時間の長時間化により生産能力の低下を招いていた。   As shown in the example of FIG. 2, when a plurality of MOSFETs are provided on one chip, a gate screening test terminal pad is provided for each MOSFET and a gate screening test is performed. Therefore, the chip size is increased by the gate screening terminal pad. End up. In addition, the prolongation of the gate screening test time has led to a decrease in production capacity.

１チップ上にある複数のＭＯＳ型半導体素子のゲートスクリーニングを一度に済ませるためには入力の共通化が考えられ、特許文献２において、バーンインテスト（ＢＴ）時のＩＣに対する外付け回路部品を簡略化する技術が開示されている。特許文献２の技術では、ＤＵＴ（Ｄｅｖｉｃｅ Ｕｎｄｅｒ Ｔｅｓｔ）の特定の入力端子３の電圧によりＢＴがどうかを判断し、ＢＴであると判断されたら、ＤＵＴ内の複数の被試験素子に対する入力を全てＤＵＴの電源電圧ＶＤＤにしてしまうことで入力の共通化を図り、ＢＴ時に必要な入力配線等の部品点数を削減することができる。   In order to complete the gate screening of a plurality of MOS type semiconductor devices on one chip at a time, common input is conceivable. In Patent Document 2, the external circuit components for the IC during the burn-in test (BT) are simplified. Techniques to do this are disclosed. In the technique of Patent Document 2, it is determined whether or not a BT is based on the voltage of a specific input terminal 3 of a DUT (Device Under Test). By using the power supply voltage VDD, it is possible to share inputs and reduce the number of components such as input wiring necessary for BT.

特開平７−２８３３７０号公報JP-A-7-283370 特開平６−１０９８１５号公報JP-A-6-109815

しかしながら、特許文献２のＩＣまたはゲートスクリーニング試験方法には、次のような問題点がある。まず、高電圧検出回路２０が必要である。加えて、高電圧検出回路２０が接続されている素子Ｇ３には通常動作時に自由に入力することができない。また、特許文献２の技術は、ＢＴ時に被試験素子を構成するＭＯＳＦＥＴのゲートがオープンにならないようにすることが目的なので被試験素子の入力が電源電圧ＶＤＤに限定されていて、電源電圧ＶＤＤを超えた電圧を印加した状態でゲートスクリーニングを実施することができない。   However, the IC or gate screening test method of Patent Document 2 has the following problems. First, the high voltage detection circuit 20 is necessary. In addition, the element G3 to which the high voltage detection circuit 20 is connected cannot be freely input during normal operation. In addition, since the technique of Patent Document 2 is intended to prevent the gate of the MOSFET constituting the device under test from being open during BT, the input of the device under test is limited to the power supply voltage VDD. Gate screening cannot be performed with a voltage exceeding the voltage applied.

本発明は、このような問題点に鑑みてなされたものであり、その目的は、複数のＭＯＳ型半導体素子が集積された半導体集積回路であって、ゲートスクリーニング試験を効率的に実施することのできる半導体集積回路を提供することにある。また、本発明の他の目的は、複数のＭＯＳ型半導体素子が集積された半導体集積回路に対して、ゲートスクリーニング試験を効率的に実施する方法を提供することにある。   The present invention has been made in view of such problems, and an object of the present invention is a semiconductor integrated circuit in which a plurality of MOS semiconductor elements are integrated, and an efficient gate screening test is performed. An object of the present invention is to provide a semiconductor integrated circuit that can be used. Another object of the present invention is to provide a method for efficiently performing a gate screening test on a semiconductor integrated circuit in which a plurality of MOS type semiconductor elements are integrated.

このような目的を達成するために、本発明の第１の態様は、複数のＭＯＳ型半導体素子が集積された半導体集積回路において、複数のＭＯＳ型半導体素子と、それぞれが各ＭＯＳ型半導体素子のための制御回路である複数の制御回路と、それぞれが、各ＭＯＳ型半導体素子のゲート電極と、前記各ＭＯＳ型半導体素子のための各制御回路との間に接続されている複数の電圧レベルシフト回路と、各ＭＯＳ型半導体素子のゲート電極が接続された逆流防止回路と、前記逆流防止回路に接続された単一のゲートスクリーニング試験端子と
を備えることを特徴とする。 In order to achieve such an object, according to a first aspect of the present invention, there is provided a semiconductor integrated circuit in which a plurality of MOS type semiconductor elements are integrated. A plurality of control circuits, each of which is connected between a gate electrode of each MOS type semiconductor element and each control circuit for each of the MOS type semiconductor elements The circuit includes a backflow prevention circuit to which a gate electrode of each MOS semiconductor element is connected, and a single gate screening test terminal connected to the backflow prevention circuit.

また、本発明の第２の態様は、第１の態様において、前記逆流防止回路が、前記複数のＭＯＳ型半導体素子に対応する数のＭＯＳＦＥＴが並列に接続された回路であることを特徴とする。   According to a second aspect of the present invention, in the first aspect, the backflow prevention circuit is a circuit in which a number of MOSFETs corresponding to the plurality of MOS type semiconductor elements are connected in parallel. .

また、本発明の第３の態様は、第１の態様において、前記逆流防止回路が、前記複数のＭＯＳ型半導体素子に対応する数のダイオードが並列に接続された回路であることを特徴とする。   According to a third aspect of the present invention, in the first aspect, the backflow prevention circuit is a circuit in which a number of diodes corresponding to the plurality of MOS semiconductor elements are connected in parallel. .

また、本発明の第４の態様は、複数のＭＯＳ型半導体素子が集積された半導体集積回路に対するゲートスクリーニング試験の方法において、単一のゲートスクリーニング試験端子に電圧を印加して、前記単一のゲートスクリーニング試験端子から逆流防止回路を介して前記複数のＭＯＳ型半導体素子のゲート電極に電圧を印加するステップを含むことを特徴とする。   According to a fourth aspect of the present invention, there is provided a gate screening test method for a semiconductor integrated circuit in which a plurality of MOS type semiconductor elements are integrated, by applying a voltage to a single gate screening test terminal. The method includes a step of applying a voltage from the gate screening test terminal to the gate electrodes of the plurality of MOS semiconductor devices through a backflow prevention circuit.

本発明によれば、複数のＭＯＳ型半導体素子が集積された半導体集積回路において、各ＭＯＳ型半導体素子のゲート電極が接続された逆流防止回路と、当該逆流防止回路に接続された単一のゲートスクリーニング試験端子と備えることにより、ゲートスクリーニング試験を効率的に実施することができる。   According to the present invention, in a semiconductor integrated circuit in which a plurality of MOS type semiconductor elements are integrated, a backflow prevention circuit to which the gate electrode of each MOS type semiconductor element is connected, and a single gate connected to the backflow prevention circuit By providing with a screening test terminal, a gate screening test can be performed efficiently.

特許文献１に開示された発明に係るＩＣを示す図である。It is a figure which shows IC which concerns on the invention disclosed by patent document 1. FIG. 図１の構成を１チップ内に４チャンネル設けたＩＣの例を示す図である。FIG. 2 is a diagram illustrating an example of an IC in which the configuration of FIG. 1 is provided with four channels in one chip. 図２のＩＣの上面図である。FIG. 3 is a top view of the IC of FIG. 2. 本発明の実施形態に係るＩＣを示す図である。It is a figure which shows IC which concerns on embodiment of this invention. 図４のＩＣの上面図である。It is a top view of IC of FIG. ＭＯＳＦＥＴのゲート端子とソース端子に電圧を印加したときのゲート・ソース間電圧に対する破壊電圧値の分布図である。It is a distribution map of the breakdown voltage value with respect to the gate-source voltage when a voltage is applied to the gate terminal and source terminal of MOSFET. 逆流防止回路の実施例を示す図である。It is a figure which shows the Example of a backflow prevention circuit. 逆流防止回路の実施例を示す図である。It is a figure which shows the Example of a backflow prevention circuit.

以下、本発明の実施形態を詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail.

図４に、本発明の実施形態に係るＩＣを示す。図２のＩＣと、ゲートスクリーニング試験端子Ｇの周辺以外は同様である。ＩＣ４００は、ＭＯＳ型半導体素子であるＭＯＳＦＥＴとその制御回路とを１チップ内に４チャンネル設けたＩＣであり、パワーＭＯＳＦＥＴ４０１、４０２、４０３、４０４のゲート電極に電圧レベルシフト回路４０５、４０６、４０７、４０８が接続され、電圧レベルシフト回路４０５、４０６、４０７、４０８に制御回路（駆動・検出・保護回路）４０９、４１０、４１１、４１２が接続されている。パワーＭＯＳＦＥＴ４０１、４０２、４０３、４０４のゲート電極がすべて逆流防止回路４１３に接続され、その先にゲートスクリーニング試験端子（または端子パッド）Ｇが１つ接続される。制御回路４０９、４１０、４１１、４１２の入力には入力端子（または端子パッド）ＩＮ１、ＩＮ２、ＩＮ３、ＩＮ４、電源にはドレイン端子（または端子パッド）Ｄ１、Ｄ２、Ｄ３、Ｄ４、グランドにはソース端子（または端子パッド）Ｓ１、Ｓ２、Ｓ３、Ｓ４が接続されている。パワーＭＯＳＦＥＴ４０１、４０２、４０３、４０４のソース電極は、ソース端子Ｓ１、Ｓ２、Ｓ３、Ｓ４に、ドレイン電極は、ドレイン端子Ｄ１、Ｄ２、Ｄ３、Ｄ４に接続されている。   FIG. 4 shows an IC according to an embodiment of the present invention. The IC of FIG. 2 is the same except for the periphery of the gate screening test terminal G. The IC 400 is an IC in which a MOSFET which is a MOS type semiconductor element and its control circuit are provided in four channels in one chip. The voltage level shift circuits 405, 406, 407, 408, and control circuits (drive / detection / protection circuits) 409, 410, 411, and 412 are connected to the voltage level shift circuits 405, 406, 407, and 408, respectively. The gate electrodes of the power MOSFETs 401, 402, 403, and 404 are all connected to the backflow prevention circuit 413, and one gate screening test terminal (or terminal pad) G is connected to the end thereof. Input terminals (or terminal pads) IN1, IN2, IN3, IN4 for the inputs of the control circuits 409, 410, 411, 412, drain terminals (or terminal pads) D1, D2, D3, D4 for the power source, and sources for the ground Terminals (or terminal pads) S1, S2, S3, and S4 are connected. The source electrodes of the power MOSFETs 401, 402, 403, and 404 are connected to the source terminals S1, S2, S3, and S4, and the drain electrodes are connected to the drain terminals D1, D2, D3, and D4.

図４のゲートスクリーニング試験端子Ｇに電圧ｄを印加することにより、複数のパワーＭＯＳＦＥＴのゲートスクリーニング試験を一度に実施することができる。ただし、実使用時、あるパワーＭＯＳＦＥＴのゲート電位が高電位、別のパワーＭＯＳＦＥＴのゲート電位が低電位の場合、低電位側へ電流が流れ込むので、逆流防止のために逆流防止回路４１３を接続する。本発明では、ゲートスクリーニング試験端子数の低減によりチップサイズを縮小することができる。また、ゲートスクリーニング試験時間の短時間化により生産能力の向上が図れる。図５は、図４のＩＣの上面図である。   By applying the voltage d to the gate screening test terminal G of FIG. 4, a gate screening test for a plurality of power MOSFETs can be performed at once. However, in actual use, when the gate potential of one power MOSFET is high and the gate potential of another power MOSFET is low, current flows into the low potential side, so that a backflow prevention circuit 413 is connected to prevent backflow. . In the present invention, the chip size can be reduced by reducing the number of gate screening test terminals. In addition, the production capacity can be improved by shortening the gate screening test time. FIG. 5 is a top view of the IC of FIG.

ここで、特許文献２の技術との比較を行うと、本発明のＩＣ４００は、ゲート・ソース間に電源電圧より高い電圧を印加してスクリーニングすることでＢＴ試験によるスクリーニングを不要にすることを目的としていて、逆流防止回路４１３という追加の回路が必要ではあるものの、特許文献２の技術のように高電圧検出回路２０に加えてＢＴ試験を必要とするものではなく、ＢＴ試験費が不要というメリットがある。また、特許文献２の技術では、インバータＧ３（特許文献２図１参照）に対しては、通常動作でも電源電圧ＶＤＤまでの電圧は印加されるので、電源電圧ＶＤＤ以下の電圧を高電圧と判定すると実動作にならなくなるため、ＶＨ＞ＶＤＤとする必要がある。これを実現するためには、ＶＨをレベルシフトして電源電圧ＶＤＤ以下にするレベルシフト回路と、レベルシフト回路の出力が高いか低いかを判定する回路が必要となる。例えば、抵抗による分圧回路、コンパレータ、基準電圧、といった無視できない規模の回路となる。従い、特許文献２の技術のように高電圧検出回路２０を設けるということは、相当規模のチップサイズ増大につながることになる。これに対し、本発明の逆流防止回路は単純なダイオードやＭＯＳＦＥＴで構成することができるので、チップサイズ、すなわちコストに与える影響は小さなものになり、パッド数の削減の効果によって全体としてコスト削減を図ることができる。   Here, when compared with the technique of Patent Document 2, the IC 400 of the present invention aims to eliminate screening by the BT test by applying a voltage higher than the power supply voltage between the gate and the source for screening. However, although an additional circuit called a backflow prevention circuit 413 is required, it does not require a BT test in addition to the high voltage detection circuit 20 as in the technique of Patent Document 2, and the BT test cost is unnecessary. There is. In the technique of Patent Document 2, since the voltage up to the power supply voltage VDD is applied to the inverter G3 (see FIG. 1 of Patent Document 2) even in normal operation, the voltage below the power supply voltage VDD is determined as a high voltage. Then, since actual operation is not performed, it is necessary to satisfy VH> VDD. To achieve this, a level shift circuit that shifts VH to a level equal to or lower than the power supply voltage VDD and a circuit that determines whether the output of the level shift circuit is high or low are required. For example, it becomes a circuit of a non-negligible scale such as a voltage dividing circuit using resistors, a comparator, and a reference voltage. Accordingly, the provision of the high voltage detection circuit 20 as in the technique of Patent Document 2 leads to a considerable increase in chip size. On the other hand, since the backflow prevention circuit of the present invention can be configured with a simple diode or MOSFET, the influence on the chip size, that is, the cost is small, and the overall cost reduction is achieved by the effect of reducing the number of pads. Can be planned.

また、特許文献２の技術では、ＢＴ時の要請により被試験素子の入力が電源電圧ＶＤＤに限定されていて、電源電圧ＶＤＤを超えた電圧を印加した状態でゲートスクリーニングを実施することができないが、本発明はＢＴ試験をベースとしたものではなく、むしろＢＴ試験を避けるためのものであるため、印加電圧ｄが電源電圧Ｄに限定されない。従い、積極的に印加電圧ｄを電源電圧ＶＤＤ以上とすることにより、試験を加速することができる。   In the technique of Patent Document 2, the input of the device under test is limited to the power supply voltage VDD due to a request at the time of BT, and gate screening cannot be performed in a state where a voltage exceeding the power supply voltage VDD is applied. The present invention is not based on the BT test, but rather is for avoiding the BT test, so that the applied voltage d is not limited to the power supply voltage D. Therefore, the test can be accelerated by positively setting the applied voltage d to the power supply voltage VDD or higher.

印加電圧ｄの好ましい値について図６を参照して説明する。図６（特許文献１図４に対応）は、ＭＯＳＦＥＴのゲート端子とソース端子に電圧を印加したときのゲート・ソース間電圧に対する破壊電圧値の分布図である。印加電圧ｄを、電圧ｃと電圧ｂの間にある値として一定時間だけ印加し、電圧ａ及びｂ付近に分布する素子のゲート酸化膜等を破壊するのが好ましい。   A preferable value of the applied voltage d will be described with reference to FIG. FIG. 6 (corresponding to FIG. 4 of Patent Document 1) is a distribution diagram of breakdown voltage values with respect to the gate-source voltage when a voltage is applied to the gate terminal and the source terminal of the MOSFET. It is preferable to apply the applied voltage d as a value between the voltage c and the voltage b for a certain period of time to destroy the gate oxide film of the elements distributed in the vicinity of the voltages a and b.

図７及び８に、逆流防止回路の実施例を示す。図７は、ＭＯＳＦＥＴ７０１、７０２、７０３、７０４を利用する例であり、図８は、ダイオード８０１、８０２、８０３、８０４を利用する例である。いずれも、ＭＯＳＦＥＴ４０１〜４０４に対応する数のＭＯＳＦＥＴ又はダイオードが並列に接続されている。   7 and 8 show an embodiment of the backflow prevention circuit. FIG. 7 shows an example in which MOSFETs 701, 702, 703, and 704 are used, and FIG. 8 shows an example in which diodes 801, 802, 803, and 804 are used. In either case, the number of MOSFETs or diodes corresponding to the MOSFETs 401 to 404 are connected in parallel.

なお、本発明は、パワーＭＯＳＦＥＴやＩＧＢＴのＭＯＳ型半導体素子が集積された出力段用のＩＣのゲートスクリーニング試験の他に、複数のＭＯＳ型半導体素子がその出力段として集積された完結した回路（例えばスイッチング電源装置用の制御回路等）のゲートスクリーニング試験にも適用可能である。   In addition to the gate screening test of an output stage IC in which power MOSFETs and IGBT MOS type semiconductor elements are integrated, the present invention is a complete circuit in which a plurality of MOS type semiconductor elements are integrated as an output stage ( For example, the present invention can also be applied to a gate screening test of a control circuit for a switching power supply device.

４００ ＩＣ
４０１〜４０４ ＭＯＳＦＥＴ（「ＭＯＳ型半導体素子」に対応）
４０５〜４０８ 電圧レベルシフト回路
４０９〜４１２ 制御回路
４１３ 逆流防止回路
ＩＮ１〜ＩＮ４ 入力端子
Ｓ１〜Ｓ４ ソース端子
Ｄ１〜Ｄ４ ドレイン端子 400 IC
401-404 MOSFET (corresponding to "MOS type semiconductor device")
405 to 408 Voltage level shift circuit 409 to 412 Control circuit 413 Backflow prevention circuit IN1 to IN4 Input terminal S1 to S4 Source terminal D1 to D4 Drain terminal

Claims (4)

複数のＭＯＳ型半導体素子が集積された半導体集積回路において、
複数のＭＯＳ型半導体素子と、
それぞれが各ＭＯＳ型半導体素子のための制御回路である複数の制御回路と、
それぞれが、各ＭＯＳ型半導体素子のゲート電極と、前記各ＭＯＳ型半導体素子のための各制御回路との間に接続されている複数の電圧レベルシフト回路と、
各ＭＯＳ型半導体素子のゲート電極が接続された逆流防止回路と、
前記逆流防止回路に接続された単一のゲートスクリーニング試験端子と
を備えることを特徴とする半導体集積回路。 In a semiconductor integrated circuit in which a plurality of MOS type semiconductor elements are integrated,
A plurality of MOS type semiconductor elements;
A plurality of control circuits each of which is a control circuit for each MOS type semiconductor element;
A plurality of voltage level shift circuits each connected between the gate electrode of each MOS type semiconductor element and each control circuit for each MOS type semiconductor element;
A backflow prevention circuit to which the gate electrode of each MOS semiconductor element is connected;
A semiconductor integrated circuit comprising a single gate screening test terminal connected to the backflow prevention circuit. 前記逆流防止回路は、前記複数のＭＯＳ型半導体素子に対応する数のＭＯＳＦＥＴが並列に接続された回路であることを特徴とする請求項１記載の半導体集積回路。   2. The semiconductor integrated circuit according to claim 1, wherein the backflow prevention circuit is a circuit in which a number of MOSFETs corresponding to the plurality of MOS type semiconductor elements are connected in parallel. 前記逆流防止回路は、前記複数のＭＯＳ型半導体素子に対応する数のダイオードが並列に接続された回路であることを特徴とする請求項１記載の半導体集積回路。   2. The semiconductor integrated circuit according to claim 1, wherein the backflow prevention circuit is a circuit in which a number of diodes corresponding to the plurality of MOS type semiconductor elements are connected in parallel. 複数のＭＯＳ型半導体素子が集積された半導体集積回路に対するゲートスクリーニング試験の方法において、
単一のゲートスクリーニング試験端子に電圧を印加して、前記単一のゲートスクリーニング試験端子から逆流防止回路を介して前記複数のＭＯＳ型半導体素子のゲート電極に電圧を印加するステップを含むことを特徴とするゲートスクリーニング試験の方法。 In a gate screening test method for a semiconductor integrated circuit in which a plurality of MOS semiconductor elements are integrated,
Applying a voltage to a single gate screening test terminal and applying a voltage from the single gate screening test terminal to the gate electrodes of the plurality of MOS type semiconductor devices via a backflow prevention circuit. And the method of gate screening test.
JP2010182369A 2010-08-17 2010-08-17 Semiconductor integrated circuit and gate screening test method for semiconductor integrated circuit Active JP5382544B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010182369A JP5382544B2 (en) 2010-08-17 2010-08-17 Semiconductor integrated circuit and gate screening test method for semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010182369A JP5382544B2 (en) 2010-08-17 2010-08-17 Semiconductor integrated circuit and gate screening test method for semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JP2012042281A true JP2012042281A (en) 2012-03-01
JP5382544B2 JP5382544B2 (en) 2014-01-08

Family

ID=45898789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010182369A Active JP5382544B2 (en) 2010-08-17 2010-08-17 Semiconductor integrated circuit and gate screening test method for semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JP5382544B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10002807B2 (en) 2012-11-06 2018-06-19 Denso Corporation Semiconductor device
US10725087B2 (en) 2017-06-23 2020-07-28 Fuji Electric Co., Ltd. Semiconductor integrated device and gate screening test method of the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06109815A (en) * 1992-09-29 1994-04-22 Nec Corp Semiconductor integrated circuit
JPH06130131A (en) * 1992-10-14 1994-05-13 Mitsubishi Electric Corp Hybrid integrated circuit device
JPH07283370A (en) * 1994-02-17 1995-10-27 Fuji Electric Co Ltd Semiconductor integrated circuit device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06109815A (en) * 1992-09-29 1994-04-22 Nec Corp Semiconductor integrated circuit
JPH06130131A (en) * 1992-10-14 1994-05-13 Mitsubishi Electric Corp Hybrid integrated circuit device
JPH07283370A (en) * 1994-02-17 1995-10-27 Fuji Electric Co Ltd Semiconductor integrated circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10002807B2 (en) 2012-11-06 2018-06-19 Denso Corporation Semiconductor device
US10725087B2 (en) 2017-06-23 2020-07-28 Fuji Electric Co., Ltd. Semiconductor integrated device and gate screening test method of the same

Also Published As

Publication number Publication date
JP5382544B2 (en) 2014-01-08

Similar Documents

Publication Publication Date Title
JP2018504818A (en) High voltage switch
US20080062596A1 (en) Distributed electrostatic discharge protection circuit with varying clamp size
JP5397571B2 (en) Control device
US20150207429A1 (en) Power conversion device
JP4623659B2 (en) Semiconductor device
CN105575960B (en) Method and circuit for on-chip electrostatic discharge protection scheme
JP5382544B2 (en) Semiconductor integrated circuit and gate screening test method for semiconductor integrated circuit
US9520880B2 (en) Configurable analog front ends for circuits with substantially gate enclosed inner electrode MOSFET switch
JP2016032043A (en) Semiconductor device, semiconductor wafer, and method for evaluating semiconductor device
JP5050628B2 (en) Semiconductor device
JPH11327500A (en) Load driving device
JP2006115472A (en) Integrated circuit device for driving power semiconductor switch
JP4516294B2 (en) Semiconductor device and manufacturing method of semiconductor device
US7164277B2 (en) Method for circuit inspection
JP6461842B2 (en) Semiconductor integrated circuit
US20180061822A1 (en) Semiconductor integrated circuit
US10263622B2 (en) Semiconductor apparatus and method of controlling MOS transistor
US7456656B2 (en) Semiconductor device and method of manufacturing the same
JP2005175054A (en) Semiconductor device and method for manufacturing the same
JP2021082879A (en) Logic circuit and circuit chip
WO2009098738A1 (en) Semiconductor device and method for resetting the same
JP5590507B2 (en) Semiconductor integrated circuit
JP6608990B2 (en) Test apparatus and test method with spike protection
JP2011075334A (en) Semiconductor integrated circuit and method of testing the same
JP2005261076A (en) Power converter

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20121015

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130617

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130621

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130820

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130906

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130919

R150 Certificate of patent or registration of utility model

Ref document number: 5382544

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250