JP2012015313A - Semiconductor device having semiconductor element - Google Patents

Semiconductor device having semiconductor element Download PDF

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JP2012015313A
JP2012015313A JP2010150214A JP2010150214A JP2012015313A JP 2012015313 A JP2012015313 A JP 2012015313A JP 2010150214 A JP2010150214 A JP 2010150214A JP 2010150214 A JP2010150214 A JP 2010150214A JP 2012015313 A JP2012015313 A JP 2012015313A
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layer
pure
semiconductor element
alloy
semiconductor
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Takeshi Tachibana
武史 橘
Yasushi Goto
裕史 後藤
Hiroyuki Okuno
博行 奥野
Takeaki Maeda
剛彰 前田
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Kobe Steel Ltd
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Kobe Steel Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with high reliability by reducing a strain stress due to thermal expansion occurring between semiconductor elements or between a semiconductor element and a circuit board.SOLUTION: A semiconductor device comprises at least one configuration in which a circuit board 1 and a semiconductor element 2 having an electrode 3 are bonded via a joint member. The joint member is composed of a stacked structure of an Al alloy layer 5 and a pure Al layer 6. The Al alloy layer is disposed at the electrode side of the semiconductor element and the pure Al layer is disposed at the circuit board side.

Description

本発明は、半導体素子を有する半導体装置に関し、詳細には耐熱性に優れ、長期信頼性を高めることが可能な半導体素子を有する半導体装置に関する。   The present invention relates to a semiconductor device having a semiconductor element, and more particularly to a semiconductor device having a semiconductor element that has excellent heat resistance and can improve long-term reliability.

半導体装置は、論理回路、ＣＰＵなどの様々な用途で使用されると共に、これらを組み込んだ電子機器は多岐に亘る。近年、電子機器の小型、軽量化や高性能化が求められており、半導体としてもＳｉよりもバンドギャップが大きいＳｉＣ、ＧａＮ、ダイヤモンドなどのワイドギャップ半導体（パワー半導体）が注目されている。これらＳｉＣなどのワイドギャップ半導体はＳｉ半導体に比べて耐電圧性能が高く、また電力損失が少なく、高温動作性にも優れていることから、様々な分野での使用が検討されている。   Semiconductor devices are used in various applications such as logic circuits and CPUs, and a wide variety of electronic devices incorporate them. In recent years, there has been a demand for smaller, lighter, and higher performance electronic devices. As semiconductors, wide gap semiconductors (power semiconductors) such as SiC, GaN, and diamond, which have a larger band gap than Si, have attracted attention. These wide-gap semiconductors such as SiC have higher withstand voltage performance than Si semiconductors, have less power loss, and are excellent in high-temperature operability, and are therefore being studied for use in various fields.

例えば高電圧、大電流の用途に用いられる大電力用半導体装置にワイドギャップ半導体を用いると、半導体素子の高集積化による高性能化やインバータなどの電力変換装置の小型化や低損失化が期待できることから、近年開発が進められている。もっとも、半導体装置の大電流化や半導体素子の高集積化に伴い、半導体素子からの発熱量も増大する傾向にある。発熱量が一定以上に達すると、半導体素子や回路基板などが熱膨張するが、熱膨張係数差に起因して、歪応力が残留し、その影響で半導体素子の特性の変動が発生するという問題が生じ、長期信頼性の確保が問題となっていた。   For example, if a wide-gap semiconductor is used in a high-power semiconductor device used for high-voltage and large-current applications, high performance due to high integration of semiconductor elements and miniaturization and low loss of power conversion devices such as inverters are expected. Because of this, development has been promoted in recent years. However, the amount of heat generated from the semiconductor element tends to increase as the current of the semiconductor device increases and the integration of the semiconductor element increases. When the calorific value reaches a certain level, the semiconductor elements and circuit boards thermally expand, but due to the difference in coefficient of thermal expansion, the strain stress remains, which causes fluctuations in the characteristics of the semiconductor elements. As a result, ensuring long-term reliability has been a problem.

また近年、ブルーレイディスクなどの高密度光ディスクの記録や読み出し用のレーザーや、ＬＥＤ照明などにもワイドギャップ半導体が用いられるようになっている。レーザーやＬＥＤ照明などの用途では、さらなる発光強度の向上が要求されているが、電流量を増大させて発光強度を高めると発熱を伴うため、上記残留歪の影響で、波長や偏光特性にばらつきが発生し、長期信頼性が低下するという問題が生じていた。   In recent years, wide gap semiconductors have also been used for lasers for recording and reading high density optical disks such as Blu-ray discs, LED lighting, and the like. In applications such as laser and LED lighting, further improvement in light emission intensity is required, but increasing the light emission intensity by increasing the amount of current is accompanied by heat generation, so the wavelength and polarization characteristics vary due to the effects of residual strain. Has occurred, and the long-term reliability has deteriorated.

このように半導体装置の大電流化や半導体素子の集積化に伴い、半導体素子の発熱量は増大する傾向にあり、またＳｉＣやＧａＮなど、Ｓｉより高い温度で動作可能な半導体素子の実用化によって、使用時の耐熱温度として、更に高い温度が要求されるようになっている。   Thus, with the increase in current of semiconductor devices and the integration of semiconductor elements, the amount of heat generated by semiconductor elements tends to increase, and the practical use of semiconductor elements that can operate at temperatures higher than Si, such as SiC and GaN. As a heat-resistant temperature at the time of use, a higher temperature is required.

このような問題の対策として、従来からファンや冷却フィンなどの冷却装置によって温度の低減が図られているが、ワイドギャップ半導体などのように従来よりも高温となる場合には、冷却装置では十分に冷却することができない。   As countermeasures against such problems, the temperature has been conventionally reduced by cooling devices such as fans and cooling fins. However, if the temperature is higher than that of conventional devices such as wide gap semiconductors, the cooling device is sufficient. Can not be cooled to.

また半導体素子同士や半導体素子と回路基板との接合に用いるはんだ材料としてＰｂ系はんだを用いると、はんだに上記歪応力が残留しやすく、熱膨張と熱収縮の繰り返しによって、はんだ接合部に亀裂が生じたり、高温によってはんだが溶融してしまい、接合が外れるというがあった。   In addition, when Pb-based solder is used as a solder material used for bonding between semiconductor elements or between a semiconductor element and a circuit board, the above-mentioned strain stress tends to remain in the solder, and cracks are generated in the solder joint due to repeated thermal expansion and contraction. It was generated or the solder was melted due to a high temperature, and the joint was disconnected.

そこで、Ｐｂ系はんだよりも融点の高いＡｕ合金系はんだを用いることが提案されている。しかしワイドギャップ半導体の使用可能温度はＡｕ合金系はんだの融点よりも高いため、Ａｕ合金系はんだが溶融したり、歪応力の残留によってはんだ接合部に亀裂が生じるという問題がある。またＡｕ合金系はんだは高価であり、製造コストの面からも汎用的に使用することは難しい。   Thus, it has been proposed to use Au alloy solder having a higher melting point than Pb solder. However, since the usable temperature of the wide gap semiconductor is higher than the melting point of the Au alloy solder, there is a problem that the Au alloy solder melts or cracks occur in the solder joints due to residual strain stress. In addition, Au alloy solder is expensive and difficult to use for general purposes from the viewpoint of manufacturing cost.

上記歪応力を緩和する技術として特許文献１には半導体素子と回路基板との間にエポキシ樹脂などの応力緩和層を設ける技術が開示されているが、樹脂は塑性変形性に優れているものの、融点が低いため、上記Ａｕ合金系はんだと同様、高温時に溶融するという問題がある。   As a technique for relaxing the strain stress, Patent Document 1 discloses a technique for providing a stress relaxation layer such as an epoxy resin between a semiconductor element and a circuit board, although the resin is excellent in plastic deformability, Since the melting point is low, there is a problem that it melts at a high temperature like the Au alloy solder.

特開２００９−１０４３６号公報JP 2009-10436 A

本発明は上記のような問題点に鑑みてなされたもので、その目的は、半導体素子間や半導体素子と回路基板との間で生じる熱膨張による歪応力を緩和し、長時間使用（５００時間以上）しても該歪応力の影響によって半導体素子の電極に亀裂が生じるのを抑制したり、歪応力による半導体素子の特性の変動を抑制することによって、長期間にわたって高い信頼性を有する半導体装置を提供することにある。   The present invention has been made in view of the above-described problems, and its purpose is to relieve strain stress due to thermal expansion generated between semiconductor elements or between a semiconductor element and a circuit board, and can be used for a long time (500 hours). The semiconductor device having high reliability over a long period of time by suppressing the generation of cracks in the electrodes of the semiconductor element due to the influence of the strain stress and suppressing the fluctuation of the characteristics of the semiconductor element due to the strain stress. Is to provide.

上記課題を達成し得た本発明は、電極を有する半導体素子と、回路基板とが、接合部材を介して接合された構成を１以上含む半導体装置であって、前記接合部材は、Ａｌ合金層と純Ａｌ層との積層構造からなり、前記Ａｌ合金層は、前記半導体素子の電極側に配置され、前記純Ａｌ層は、前記回路基板側に配置されていることに要旨を有する。   The present invention that has achieved the above object is a semiconductor device including one or more configurations in which a semiconductor element having an electrode and a circuit board are bonded via a bonding member, the bonding member comprising an Al alloy layer The Al alloy layer is arranged on the electrode side of the semiconductor element, and the pure Al layer is arranged on the circuit board side.

本発明では、前記電極の一部または全部が、前記接合部材で構成されていることも好ましい実施態様である。   In the present invention, it is also a preferred embodiment that part or all of the electrode is constituted by the joining member.

また前記純Ａｌ層のＡｌ純度が９９．５％以上であることも好ましい実施態様である。   It is also a preferred embodiment that the Al purity of the pure Al layer is 99.5% or more.

更に前記Ａｌ合金は、Ｎｉ、Ｃｏ、Ｆｅ、およびＭｎよりなる群から選ばれる少なくとも１種を合計で０．１〜１０原子％含有すると共に、Ｎｄ、Ｌａ、およびＰｒよりなる群から選ばれる少なくとも１種を合計で０．１〜６原子％含有するものであることも好ましい実施態様である。   The Al alloy further contains at least one selected from the group consisting of Ni, Co, Fe, and Mn in a total amount of 0.1 to 10 atomic%, and at least selected from the group consisting of Nd, La, and Pr. It is also a preferred embodiment that one type is contained in a total of 0.1 to 6 atomic%.

本発明によれば半導体素子間や、半導体素子と回路基板は、純ＡｌとＡｌ合金の積層構造からなる接合部材を介して接合させているため、稼働時に発生する歪応力は、該接合部材が塑性変形することによって緩和できる。したがって本発明の半導体装置は、半導体素子や回路基板にかかるストレスを小さくできるため、残留した歪応力による半導体素子の特性の変動が抑制されており、従来よりも優れた長期信頼性を有する。   According to the present invention, between the semiconductor elements and between the semiconductor element and the circuit board are joined via a joining member having a laminated structure of pure Al and an Al alloy, strain stress generated during operation is It can be relaxed by plastic deformation. Therefore, the semiconductor device of the present invention can reduce the stress applied to the semiconductor element and the circuit board. Therefore, the fluctuation of the characteristics of the semiconductor element due to the remaining strain stress is suppressed, and the long-term reliability is superior to that of the conventional device.

図１は、本発明の半導体装置一例を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor device of the present invention. 図２は、本発明の他の半導体装置一例を示す概略断面図である。FIG. 2 is a schematic sectional view showing an example of another semiconductor device of the present invention. 図３は、実施例１で使用したＬＥＤ半導体装置を示す概略断面図である。FIG. 3 is a schematic cross-sectional view showing the LED semiconductor device used in Example 1. 図４は、実施例２で使用した絶縁ゲート型バイポーラ・トランジスタを示す概略断面図である。FIG. 4 is a schematic sectional view showing the insulated gate bipolar transistor used in the second embodiment. 図５は、亀裂密度とＮｉ、Ｃｏ含有量の関係を示すグラフである。FIG. 5 is a graph showing the relationship between crack density and Ni / Co content.

本発明者らは上記課題を解決すべく、鋭意研究を重ねてきた。その結果、半導体素子間、或いは半導体素子と基板を、純ＡｌとＡｌ合金との積層構造からなる接合部材を介して接合することによって、上記課題を解決できることを見出し、本発明に至った。   The inventors of the present invention have made extensive studies to solve the above problems. As a result, the present inventors have found that the above-described problems can be solved by joining between semiconductor elements or between a semiconductor element and a substrate via a joining member having a laminated structure of pure Al and an Al alloy.

以下、図面を参照しながら、本発明の半導体装置の好ましい実施形態を説明するが、本発明はこれに限定されない。   Hereinafter, preferred embodiments of the semiconductor device of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.

図１は、本発明に係る半導体装置の好ましい実施形態を説明する概略断面説明図である。図１は、電極３を有する半導体素子２と、回路基板１に形成された回路（図示せず）とが、接合部材４を介して接合された構成を１以上含む半導体装置である。具体的には、接合部材４は、純Ａｌ層６とＡｌ合金層５との積層構造からなり、Ａｌ合金層５は、半導体素子２の電極３側に配置され、純Ａｌ層６は、回路基板１側に配置されている。   FIG. 1 is a schematic cross-sectional explanatory view illustrating a preferred embodiment of a semiconductor device according to the present invention. FIG. 1 shows a semiconductor device including one or more configurations in which a semiconductor element 2 having an electrode 3 and a circuit (not shown) formed on a circuit board 1 are bonded via a bonding member 4. Specifically, the bonding member 4 has a laminated structure of a pure Al layer 6 and an Al alloy layer 5, the Al alloy layer 5 is disposed on the electrode 3 side of the semiconductor element 2, and the pure Al layer 6 is a circuit. Arranged on the substrate 1 side.

本発明では接合部材４を純Ａｌ層６とＡｌ合金層５からなる積層構造とすることにより、熱伝導性に優れ柔軟性の高い純Ａｌ層６によって稼働時の発熱によって生じる半導体素子間（後記図２参照）や半導体素子２と回路基板１との間の熱膨張係数差に起因する歪応力を緩和・吸収させると共に、純Ａｌに比べて耐熱性の高いＡｌ合金層５によって純Ａｌ層６と半導体素子２の電極３との接続性を確保することができる。   In the present invention, the joining member 4 has a laminated structure composed of a pure Al layer 6 and an Al alloy layer 5, so that the pure Al layer 6 having excellent thermal conductivity and high flexibility can be used to generate heat between semiconductor elements (described later). 2) and the strained stress caused by the difference in thermal expansion coefficient between the semiconductor element 2 and the circuit board 1 is relaxed and absorbed, and the pure Al layer 6 is formed by the Al alloy layer 5 having higher heat resistance than pure Al. And the electrode 3 of the semiconductor element 2 can be secured.

また図２は本発明の他の好ましい実施形態であり、複数の半導体素子をアレイ状に集積させた半導体装置の概略説明図である。図２は、電極３ａを有する第１の半導体素子２ａと電極３ｂを有する第２の半導体素子２ｂとが、接合部材４を介して接合された構成を１以上含む半導体装置である。具体的には、上記図１と同様、接合部材４を構成するＡｌ合金層５は、第１の半導体素子２ａの電極３ａ側に配置され、純Ａｌ層６は、基板側に配置されている。   FIG. 2 shows another preferred embodiment of the present invention, and is a schematic explanatory view of a semiconductor device in which a plurality of semiconductor elements are integrated in an array. FIG. 2 shows a semiconductor device including one or more configurations in which a first semiconductor element 2 a having an electrode 3 a and a second semiconductor element 2 b having an electrode 3 b are bonded via a bonding member 4. Specifically, as in FIG. 1, the Al alloy layer 5 constituting the bonding member 4 is disposed on the electrode 3a side of the first semiconductor element 2a, and the pure Al layer 6 is disposed on the substrate side. .

このように接合部材４を介して複数の半導体素子間を接合させれば、上記図１の場合と同様、接合部材を構成する純Ａｌ層６によって稼働時の発熱によって生じる半導体素子間の熱膨張係数差に起因する歪応力を緩和・吸収することができると共に、Ａｌ合金層５によって純Ａｌ層６と半導体素子の電極との接続性を確保することができる。   If a plurality of semiconductor elements are bonded through the bonding member 4 in this way, as in the case of FIG. 1, the thermal expansion between the semiconductor elements caused by heat generated during operation by the pure Al layer 6 constituting the bonding member. The strain stress resulting from the coefficient difference can be relaxed and absorbed, and the Al alloy layer 5 can ensure the connectivity between the pure Al layer 6 and the electrode of the semiconductor element.

なお、複数の半導体素子を集積させる場合、本発明では図２に限定されず、更に多くの半導体素子と接合部材が接合されていてもよく、その場合の基本的な構造は図２と同じである。   In the case where a plurality of semiconductor elements are integrated, the present invention is not limited to FIG. 2, and more semiconductor elements and bonding members may be bonded, and the basic structure in that case is the same as FIG. is there.

また本発明では、上記半導体素子の電極や回路の電極の一部または全部が、上記接合部材で構成されていてもよい。即ち、半導体素子の電極の一部または全部がＡｌ合金で構成されていてもよく、また回路基板の電極の一部または全部が純Ａｌで構成されていてもよい。なお、本発明では、基板に設けられた配線であっても、上記純Ａｌとの接合部分は、電極に含まれる。   In the present invention, some or all of the electrodes of the semiconductor element and the electrodes of the circuit may be constituted by the bonding member. That is, some or all of the electrodes of the semiconductor element may be made of an Al alloy, and some or all of the electrodes of the circuit board may be made of pure Al. In the present invention, even if the wiring is provided on the substrate, the junction with pure Al is included in the electrode.

このように半導体素子や回路の電極の一部または全部を上記接合部材で構成することによって、接合部材のみを純ＡｌとＡｌ合金とした場合に比べて、夫々の上記効果をより高めることができるからである。   As described above, by forming a part or all of the electrodes of the semiconductor element and the circuit with the above-mentioned joining member, the above-described effects can be further enhanced as compared with the case where only the joining member is made of pure Al and Al alloy. Because.

以下、本発明の純Ａｌ層とＡｌ合金層からなる接合部材について説明する。   Hereinafter, the joining member consisting of a pure Al layer and an Al alloy layer of the present invention will be described.

まず、本発明者らは熱膨張係数差に起因する歪応力の影響によって半導体素子の特性が低下するという上記問題を解消するために、半導体素子間、あるいは半導体素子と回路基板との間に該応力を吸収できる熱応力緩和層（接合部材４）を設けることとし、最適な材料について調べたところ、純Ａｌが有効であることを見出した。   First, in order to solve the above-mentioned problem that the characteristics of a semiconductor element deteriorate due to the influence of strain stress caused by a difference in thermal expansion coefficient, the present inventors have found that the semiconductor element or between a semiconductor element and a circuit board When a thermal stress relaxation layer (bonding member 4) capable of absorbing stress was provided and an optimum material was examined, it was found that pure Al was effective.

純Ａｌは、Ｐｂ系はんだやＡｕ合金系はんだよりも融点が高く、また熱伝導性が高く、放熱効果に優れているため、ＳｉＣなどのワイドギャップ半導体を使用した半導体素子の稼働時の発熱温度でも溶融することがない。また半導体装置の稼働によって発生する温度において純Ａｌ層が軟化するため、熱膨張係数差によって発生する歪応力を、純Ａｌ層が柔軟に変形することによって、吸収、緩和できる。   Pure Al has a higher melting point than Pb-based solder and Au alloy-based solder, has high thermal conductivity, and is excellent in heat dissipation. But it does not melt. Further, since the pure Al layer is softened at the temperature generated by the operation of the semiconductor device, the strain stress generated by the difference in thermal expansion coefficient can be absorbed and relaxed by flexibly deforming the pure Al layer.

もっとも、このような歪応力に対する吸収、緩和効果を発揮するためには、純Ａｌ層にある程度の厚みを持たせることが望ましい。純Ａｌ層の厚みが薄すぎると、歪応力を十分に吸収、緩和できず、上記効果を発揮できないことがある。純Ａｌ層の厚みは、半導体素子の形状、素材や、稼働時の温度、熱膨張係数などに応じて適宜決定すればよいが、好ましくは半導体素子を構成する主要母材の厚さよりも厚くするのがよく、例えば好ましくは２倍以上、より好ましくは３倍以上とする。一方、純Ａｌ層の厚みを増大させすぎても、上記熱応力緩和層の効果は飽和すると共に、半導体装置の厚みが増すことから、好ましくは１０倍以下、より好ましく５倍以下とすることが望ましい。   However, in order to exhibit such an effect of absorbing and relaxing strain stress, it is desirable that the pure Al layer has a certain thickness. If the thickness of the pure Al layer is too thin, strain stress cannot be sufficiently absorbed and relaxed, and the above effects may not be exhibited. The thickness of the pure Al layer may be appropriately determined according to the shape, material, operating temperature, thermal expansion coefficient, etc. of the semiconductor element, but is preferably thicker than the thickness of the main base material constituting the semiconductor element. For example, it is preferably 2 times or more, more preferably 3 times or more. On the other hand, even if the thickness of the pure Al layer is increased too much, the effect of the thermal stress relaxation layer is saturated and the thickness of the semiconductor device is increased. Therefore, the thickness is preferably 10 times or less, more preferably 5 times or less. desirable.

なお、半導体素子を構成する主要母材の厚さとは、半導体素子を構成する半導体（例えばＳｉ、ＳｉＣなど）の厚さをノギスやマイクロメータ、或いはレーザー干渉法によって測定されるマザーウエハの厚さをいう。   The thickness of the main base material constituting the semiconductor element refers to the thickness of the semiconductor (eg, Si, SiC, etc.) constituting the semiconductor element and the thickness of the mother wafer measured by a caliper, micrometer, or laser interferometry. Say.

また本発明で用いる純Ａｌとは、純度９９．５％以上のＡｌであることが好ましい。本発明では上記の通り、純Ａｌ層は歪応力を吸収、緩和する層としての役割を果たすが、Ａｌ層の柔軟性はＡｌの純度が低下するほど失われる。したがって純Ａｌ層が２５０℃以上の高温下で柔軟に変形して歪応力を吸収、緩和する効果を十分に発揮させるためには、Ａｌの純度は高い方が望ましい。具体的に純度は９９．５％以上のＡｌが好ましく、より好ましく純度９９．９％以上のＡｌ、更に好ましくは純度９９．９５％以上のＡｌである。なお、残部は不可避不純物である。   The pure Al used in the present invention is preferably Al having a purity of 99.5% or more. In the present invention, as described above, the pure Al layer serves as a layer that absorbs and relieves strain stress, but the flexibility of the Al layer is lost as the purity of Al decreases. Therefore, in order for the pure Al layer to flexibly deform at a high temperature of 250 ° C. or higher to sufficiently absorb and relax the strain stress, it is desirable that the purity of Al is high. Specifically, Al having a purity of 99.5% or more is preferable, Al having a purity of 99.9% or more is more preferable, and Al having a purity of 99.95% or more is more preferable. The balance is inevitable impurities.

本発明では、半導体素子側の電極と、上記純Ａｌ層との接合を高めるために、該電極と純Ａｌ層の間にＡｌ合金の層を設ける。Ａｌ合金層を設けることによって、純Ａｌ層では十分な耐熱性が得られない２００℃以上の温度域でも優れた耐熱性を発揮できる。   In the present invention, in order to enhance the bonding between the electrode on the semiconductor element side and the pure Al layer, an Al alloy layer is provided between the electrode and the pure Al layer. By providing the Al alloy layer, excellent heat resistance can be exhibited even in a temperature range of 200 ° C. or higher where sufficient heat resistance cannot be obtained with a pure Al layer.

このように、Ａｌ合金層は純Ａｌ層の欠点を補完するために設けられたものであり、純Ａｌ層とＡｌ合金層からなる積層構造を接合部材として用いることによって、熱膨張係数差による熱応力の緩和と高い耐熱性を兼ね備えた接合部材を得ることができる。   As described above, the Al alloy layer is provided to compensate for the shortcomings of the pure Al layer. By using a laminated structure composed of the pure Al layer and the Al alloy layer as a joining member, heat due to a difference in thermal expansion coefficient can be obtained. A joining member having both relaxation of stress and high heat resistance can be obtained.

また本発明に用いるＡｌ合金層に添加する合金元素としては、次の観点から約３００℃程度の熱履歴によって導電性の高い析出物が形成可能な元素であることが望ましい。   The alloy element added to the Al alloy layer used in the present invention is desirably an element that can form a highly conductive precipitate with a thermal history of about 300 ° C. from the following viewpoint.

まず、３００℃程度としたのは、半導体素子の稼働時の温度がおおむね３００℃程度となることがあり、この温度域での耐熱性を確保し、半導体素子と純Ａｌ層との接合を維持する必要があるからである。   First, the temperature of about 300 ° C. is that the operating temperature of the semiconductor element is about 300 ° C. The heat resistance in this temperature range is ensured and the bonding between the semiconductor element and the pure Al layer is maintained. Because it is necessary to do.

また、Ａｌ合金層に３００℃程度の熱履歴が加えられた場合に、合金成分が析出することが望ましいとしたのは、３００℃程度の熱履歴が加えられた際に、Ａｌ合金層内部で合金元素を析出させれば、この析出物によって半導体素子の電極と純Ａｌ層との導電性を維持しつつ、Ａｌ合金層に歪応力による亀裂等が生じるのを防ぐことができるため、接合部材を介して半導体素子同士、あるいは半導体素子と回路基板との接合を維持できるからである。このようにＡｌ合金層内部で析出物を析出させることによって、本発明の熱緩和部材が、高温下でも優れた安定性を発揮できる。   In addition, it is desirable that the alloy component is precipitated when a heat history of about 300 ° C. is applied to the Al alloy layer, when the heat history of about 300 ° C. is applied inside the Al alloy layer. If the alloy element is deposited, it is possible to prevent the Al alloy layer from being cracked due to strain stress while maintaining the conductivity between the electrode of the semiconductor element and the pure Al layer. This is because the bonding between the semiconductor elements or between the semiconductor element and the circuit board can be maintained via the. Thus, by depositing precipitates in the Al alloy layer, the heat relaxation member of the present invention can exhibit excellent stability even at high temperatures.

なお、本発明において３００℃の熱履歴には、製造工程において加えられる３００℃以上の熱に限らず、使用に伴う発熱によって３００℃以上に達する場合も含む。   In the present invention, the heat history of 300 ° C. includes not only the heat of 300 ° C. or higher applied in the manufacturing process, but also the case of reaching 300 ° C. or higher due to heat generated by use.

このような性質を付与する合金元素（Ｘ）として、Ｎｉ、Ｃｏ、Ｆｅ、Ｍｎなどの遷移金属を添加すると、耐熱性を高めることができるので望ましい。またＮｉ、Ｃｏ、Ｆｅ、およびＭｎは、Ａｌ合金層と、このＡｌ合金層に直接接触する半導体素子の電極との接触電気抵抗を低減するのに有効な元素である。これらの中でも、特に好ましい合金元素はＮｉやＣｏである。ＮｉやＣｏは熱処理によって界面に導電性のＮｉ含有析出物などが形成され、絶縁性酸化アルミニウム等の生成が抑制されるため、接触電気抵抗を低く抑えることができる。これらの合金元素（Ｘ）は単独で添加してもよいし、併用してもよい。   It is desirable to add a transition metal such as Ni, Co, Fe, or Mn as the alloying element (X) that imparts such properties because heat resistance can be improved. Ni, Co, Fe, and Mn are effective elements for reducing the contact electric resistance between the Al alloy layer and the electrode of the semiconductor element that is in direct contact with the Al alloy layer. Among these, particularly preferable alloy elements are Ni and Co. Since Ni or Co forms a conductive Ni-containing precipitate or the like at the interface by heat treatment and suppresses the production of insulating aluminum oxide or the like, the contact electrical resistance can be kept low. These alloy elements (X) may be added alone or in combination.

またこれら合金元素（Ｘ）の含有量は合計量（単独の場合は単独量）で、０．１〜１０原子％とすることが好ましい。０．１原子％を下回ると合金元素（Ｘ）による上記耐熱性向上効果が十分に得られないことがある。より好ましい合金元素（Ｘ）の添加量の下限は０．２原子％、更に好ましくは０．５原子％である。一方、合金元素（Ｘ）の含有量が１０原子％を超えると、Ａｌ合金の柔軟性が失われて、高温下で使用した場合に歪応力の影響によってＡｌ合金層に亀裂が生じることがある。より好ましい合金元素（Ｘ）の添加量の上限は６原子％、更に好ましくは２原子％である。   Further, the content of these alloy elements (X) is a total amount (single amount in the case of single), and is preferably 0.1 to 10 atomic%. If it is less than 0.1 atomic%, the effect of improving the heat resistance by the alloy element (X) may not be sufficiently obtained. The lower limit of the addition amount of the alloy element (X) is more preferably 0.2 atomic%, still more preferably 0.5 atomic%. On the other hand, if the content of the alloy element (X) exceeds 10 atomic%, the flexibility of the Al alloy is lost, and cracks may occur in the Al alloy layer due to the influence of strain stress when used at high temperatures. . The upper limit of the addition amount of the alloy element (X) is more preferably 6 atomic%, and further preferably 2 atomic%.

また上記合金元素（Ｘ）と共に、希土類元素（Ｙ）を添加することが望ましい。３００℃近傍の高温下では、ヒロックと呼ばれる微細な突起が電極を構成する配線膜等の表面に形成されて、半導体装置としての性能が低下する場合があるが、希土類元素は、加熱による結晶粒の成長、拡散を抑制して、耐ヒロック性の向上に有用だからである。   Moreover, it is desirable to add rare earth elements (Y) together with the alloy element (X). Under a high temperature of about 300 ° C., fine protrusions called hillocks are formed on the surface of a wiring film or the like that constitutes the electrode, and the performance as a semiconductor device may be deteriorated. This is because it is useful for improving the hillock resistance by suppressing the growth and diffusion of the metal.

希土類元素（Ｙ）として、Ｎｄ、Ｌａ、Ｐｒなどの高融点希土類元素を添加すると、これら希土類元素が、大電流通電時の断線防止という効果を発揮することができるので望ましい。これらの中でも、特に好ましい希土類元素（Ｙ）としてはＮｄやＬａである。これらの希土類元素（Ｙ）は単独で添加してもよいし、併用してもよい。   It is desirable to add refractory rare earth elements such as Nd, La, Pr and the like as the rare earth elements (Y) because these rare earth elements can exhibit the effect of preventing disconnection when a large current is applied. Among these, particularly preferable rare earth elements (Y) are Nd and La. These rare earth elements (Y) may be added alone or in combination.

本発明で用いるＡｌ合金は好ましくは上記合金元素を含み、残部Ａｌ及び不可避不純物である。   The Al alloy used in the present invention preferably contains the above alloy elements, with the balance being Al and inevitable impurities.

またこれら希土類元素（Ｙ）の含有量は合計量（単独の場合は単独量）で、０．１〜６原子％とすることが好ましい。希土類元素（Ｙ）が０．１原子％を下回ると希土類元素（Ｙ）による上記断線防止効果が十分に得られないことがある。より好ましい希土類元素（Ｙ）の添加量の下限は０．２５原子％、更に好ましくは０．３５原子％である。一方、希土類元素（Ｙ）の含有量が６原子％を超えると、希土類元素を起因とする膜割れや剥離が生じることがある。より好ましい希土類元素（Ｙ）の添加量の上限は３原子％、更に好ましくは２原子％である。なお上記Ａｌ合金層の厚みは特に限定されない。   Further, the content of these rare earth elements (Y) is preferably the total amount (single amount in the case of single use) of 0.1 to 6 atomic%. If the rare earth element (Y) is less than 0.1 atomic%, the disconnection preventing effect by the rare earth element (Y) may not be sufficiently obtained. The lower limit of the addition amount of the rare earth element (Y) is more preferably 0.25 atomic%, still more preferably 0.35 atomic%. On the other hand, when the content of the rare earth element (Y) exceeds 6 atomic%, film cracking or peeling due to the rare earth element may occur. The upper limit of the addition amount of the rare earth element (Y) is more preferably 3 atomic%, further preferably 2 atomic%. The thickness of the Al alloy layer is not particularly limited.

以上、本発明の積層構造について説明した。   The laminated structure of the present invention has been described above.

次に本発明の半導体素子の製造方法について説明する。   Next, the manufacturing method of the semiconductor element of this invention is demonstrated.

回路基板としては特に限定されず、各種用途に用いられる電子回路等が例示される。また回路基板に形成される電極や配線材料等についても特に限定されない。本発明の接合部材を構成する純Ａｌ層は、回路基板の電極や配線など所望の位置に形成すればよい。   It does not specifically limit as a circuit board, The electronic circuit etc. which are used for various uses are illustrated. Also, the electrodes and wiring materials formed on the circuit board are not particularly limited. The pure Al layer constituting the bonding member of the present invention may be formed at a desired position such as an electrode or wiring of a circuit board.

接合部材を構成する純Ａｌ層を形成するにあたっては、成膜方法は特に限定されず、例えば公知のスパッタリング法や溶射法で成膜してもよい。   In forming the pure Al layer constituting the joining member, the film forming method is not particularly limited, and for example, the film may be formed by a known sputtering method or thermal spraying method.

次に、接合部材を構成するＡｌ合金層を、上記純Ａｌ層上に形成する。Ａｌ合金層を形成するにあたっては、成膜が容易であることからスパッタリング法によることが好ましい。   Next, an Al alloy layer constituting the joining member is formed on the pure Al layer. In forming the Al alloy layer, it is preferable to use a sputtering method because film formation is easy.

スパッタリング法の条件としては上記純Ａｌ層と同様の条件でもよい。また使用するターゲット材は、Ａｌ合金層と同じ組成のものをもちいればよい。   The conditions for the sputtering method may be the same as those for the pure Al layer. The target material to be used may be the same composition as the Al alloy layer.

このようにして形成した接合部材のＡｌ合金側に、半導体素子の電極を接地させるが、公知の方法により、接地させればよい。   The electrode of the semiconductor element is grounded on the Al alloy side of the joining member formed as described above, but may be grounded by a known method.

なお、本発明で用いることができる半導体素子としては特に限定されず、各種トランジスタ、サイリスタ（ＳＣＲ）、ダイオード（整流器）、発光ダイオード（ＬＥＤ）等が例示される。   In addition, it does not specifically limit as a semiconductor element which can be used by this invention, Various transistors, a thyristor (SCR), a diode (rectifier), a light emitting diode (LED) etc. are illustrated.

以上のようにして、半導体素子は接合部材を介して回路基板と接合することができる。   As described above, the semiconductor element can be bonded to the circuit board via the bonding member.

また本発明では、半導体素子を個別部品（単体チップ）として上記のように接合部材を介して回路基板に接合させる場合に限らず、複数の半導体素子を用いて集積回路とする場合にも適用できる。特に複数の半導体素子を積層させアレイ状の集積回路とする場合は、半導体素子間に上記接合部材を介在させればよい。   Further, the present invention is not limited to the case where the semiconductor element is bonded to the circuit board as a separate component (single chip) via the bonding member as described above, but can also be applied to a case where an integrated circuit is formed using a plurality of semiconductor elements. . In particular, when a plurality of semiconductor elements are stacked to form an arrayed integrated circuit, the bonding member may be interposed between the semiconductor elements.

以下、実施例を挙げて本発明をより具体的に説明するが、本発明はもとより下記実施例によって制限を受けるものではなく、前・後記の趣旨に適合し得る範囲で適当に変更を加えて実施することも勿論可能であり、それらはいずれも本発明の技術的範囲に包含される。   EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples. However, the present invention is not limited by the following examples, but may be appropriately modified within a range that can meet the purpose described above and below. Of course, it is possible to implement them, and they are all included in the technical scope of the present invention.

（実施例１）
半導体素子としてＧａＮ系ＬＥＤ（シチズン電子製：ＬＣ−Ｌ２３０−ＣＩＯＮ−Ａ）を用いて図３に示すような電極部を作製して、１００時間の通電試験と５００時間の通電試験を行ない、夫々の試験における亀裂発生の有無を調べた。 Example 1
Using a GaN-based LED (manufactured by Citizen Electronics: LC-L230-CION-A) as a semiconductor element, an electrode portion as shown in FIG. 3 is produced, and a 100-hour energization test and a 500-hour energization test are performed. The presence or absence of cracks in this test was examined.

回路基板（材質：アルミナ）上にまず、純度９９．９％のＡｌ膜（純Ａｌ層：厚さ６００ｎｍ）をスパッタリング法で成膜した後、２原子％Ｎｉ−Ａｌ合金膜（Ａｌ合金層：厚さ３００ｎｍ）をスパッタリング法で成膜し、接合部材（純Ａｌ／Ａｌ合金）を形成した。次いでＡｌ合金層にＬＥＤ（半導体素子）の電極面（図示せず）を接地させた。なお、半導体素子を構成する主要母材の厚さ（１００ｎｍ）は、レーザー干渉法によって測定した。また純Ａｌ層、Ａｌ合金層の厚みは触針式膜厚計によって測定した。各膜の成分についてはＩＣＰ（Ｉｎｄｕｃｔｉｖｅｌｙ Ｃｏｕｐｌｅｄ Ｐｌａｓｍａ：誘導結合プラズマ）発光分析法によって測定した。   First, an Al film (pure Al layer: thickness 600 nm) having a purity of 99.9% is formed on a circuit board (material: alumina) by sputtering, and then a 2 atomic% Ni—Al alloy film (Al alloy layer: (Thickness 300 nm) was formed by sputtering to form a bonding member (pure Al / Al alloy). Next, the electrode surface (not shown) of the LED (semiconductor element) was grounded to the Al alloy layer. In addition, the thickness (100 nm) of the main base material constituting the semiconductor element was measured by a laser interference method. The thicknesses of the pure Al layer and Al alloy layer were measured with a stylus type film thickness meter. The components of each film were measured by ICP (Inductively Coupled Plasma) emission spectrometry.

また回路基板の片面には、基板側から順に約１５０ｎｍ厚のＮｉ層および約１００ｎｍ厚のＡｕ層が形成された配線膜が形成されているが（図示しない）、上記純Ａｌ層とＡｌ合金層は図示しないオーミック層とバリア層との間に形成されている。   On one side of the circuit board is formed a wiring film (not shown) in which an Ni layer of about 150 nm thickness and an Au layer of about 100 nm thickness are formed in order from the substrate side. Is formed between an ohmic layer (not shown) and a barrier layer.

ＬＥＤ（半導体素子）のｐ側電極は、３ｎｍ厚のＮｉ層と約１５０ｎｍ厚のＡｕ層の積層構造とした。また拡散防止層は、約３０ｎｍ厚のＴｉ層と約３００ｎｍ厚のＡｕ層の積層構造とした。   The p-side electrode of the LED (semiconductor element) has a laminated structure of a Ni layer having a thickness of 3 nm and an Au layer having a thickness of about 150 nm. The diffusion preventing layer has a laminated structure of a Ti layer having a thickness of about 30 nm and an Au layer having a thickness of about 300 nm.

比較例として、上記接合部材（純Ａｌ層とＡｌ合金層）に代えて２０原子％Ｓｎ−Ａｕ（比較例１）、１０原子％Ｇｅ−Ａｕ（比較例２）を用いてはんだ付けした以外は実施例１と同様にしてＬＥＤ半導体装置を作製した。なお、はんだ条件は２９０℃で６０秒間、加圧着した。   As a comparative example, instead of the joining member (pure Al layer and Al alloy layer), soldering was performed using 20 atomic% Sn—Au (Comparative Example 1) and 10 atomic% Ge—Au (Comparative Example 2). An LED semiconductor device was produced in the same manner as in Example 1. Note that the soldering condition was 290 ° C. for 60 seconds.

試験条件
ＬＥＤ半導体装置に定格電流密度比＋１５％の条件で、１００時間、５００時間通電させた後、ＬＥＤ（半導体素子）のｐ側電極を光学顕微鏡（倍率３０〜１００倍）で観察して、亀裂の有無を調べた。亀裂が観察された場合を×、観察されなかった場合を○と評価した。結果を表１に示す。 Test conditions After the LED semiconductor device was energized for 100 hours and 500 hours under the condition of the rated current density ratio + 15%, the p-side electrode of the LED (semiconductor element) was observed with an optical microscope (magnification 30 to 100 times). The presence or absence of cracks was examined. The case where cracks were observed was evaluated as x, and the case where cracks were not observed was evaluated as ◯. The results are shown in Table 1.

表１に示すように、本発明の要件を満たす純Ａｌと、２原子％Ｎｉ−Ａｌ合金膜からなる積層構造の接合部材を用いた場合は、１００時間通電のみならず、５００時間もの長時間通電させてもｐ側電極に亀裂は生じておらず、高温状態で稼働させても半導体素子の長期信頼性を確保できたと共に、長時間に亘って電流密度を高めてＬＥＤの発光効率を維持することができた。   As shown in Table 1, when a joining member having a laminated structure composed of pure Al that satisfies the requirements of the present invention and a 2 atomic% Ni—Al alloy film is used, not only energization for 100 hours but also a long time of 500 hours The p-side electrode is not cracked even when energized, and the long-term reliability of the semiconductor element was ensured even when operated at a high temperature, and the light emission efficiency of the LED was maintained by increasing the current density over a long period of time. We were able to.

なお、Ａｌ合金層、純Ａｌ層、基板についても光学顕微鏡で観察したが亀裂は発生していなかった。   In addition, although the Al alloy layer, the pure Al layer, and the substrate were also observed with an optical microscope, no cracks were generated.

一方、比較例１では、１００時間通電後は良好な結果だったが、５００時間通電試験後の半導体素子の電極に亀裂が観察された。また比較例２では１００時間通電試験後の半導体素子の電極に亀裂が観察され、高温状態で稼働させると半導体素子の信頼性が低下することが分かった。
（実施例２）
図４に示すような絶縁ゲート型バイポーラ・トランジスタ（ＩＧＢＴ）が実装された半導体装置（応力緩和層を有する半導体装置と半導体素子の集合体）を作製した。 On the other hand, in Comparative Example 1, although good results were obtained after energization for 100 hours, cracks were observed in the electrodes of the semiconductor elements after the energization test for 500 hours. Further, in Comparative Example 2, cracks were observed in the electrodes of the semiconductor element after the 100-hour energization test, and it was found that the reliability of the semiconductor element was lowered when operated at a high temperature.
(Example 2)
A semiconductor device (an assembly of a semiconductor device having a stress relaxation layer and a semiconductor element) on which an insulated gate bipolar transistor (IGBT) as shown in FIG. 4 was mounted was manufactured.

具体的には、まず、回路基板（材質：ＡｌＮ）上に純度９９．５％のＡｌ膜（純Ａｌ層）を溶射した後、図５に示す各種合金膜（Ａｌ合金層：厚さ１００ｎｍ）をスパッタリング法で成膜し、接合部材（純Ａｌ／Ａｌ合金）を形成した。次いでＡｌ合金膜上に半導体素子（ＩＧＢＴ）の電極面を接地させた。なお、半導体素子の接地は、不溶性ガス中で６００℃の加熱を１時間保持しておこなった。また半導体素子を構成する主要母材の厚さは２００ｎｍであり、純Ａｌ層の厚さは３５０ｎｍであった。なお、図５における各種合金膜（Ａｌ−ｘ原子％Ｎｉ−５原子％Ｎｄ、Ａｌ−ｘ原子％Ｎｉ−３原子％Ｌａ、Ａｌ−ｘ原子％Ｃｏ−６原子％Ｎｄ、Ａｌ−ｘ原子％Ｃｏ−３原子％Ｌａ）はＮｉとＣｏの含有量（ｘ）を変化させたものである。   Specifically, first, after spraying a 99.5% pure Al film (pure Al layer) on a circuit board (material: AlN), various alloy films (Al alloy layer: thickness 100 nm) shown in FIG. Was formed by sputtering to form a bonding member (pure Al / Al alloy). Next, the electrode surface of the semiconductor element (IGBT) was grounded on the Al alloy film. The grounding of the semiconductor element was performed by maintaining heating at 600 ° C. in an insoluble gas for 1 hour. The main base material constituting the semiconductor element had a thickness of 200 nm, and the pure Al layer had a thickness of 350 nm. In addition, various alloy films in FIG. 5 (Al-x atom% Ni-5 atom% Nd, Al-x atom% Ni-3 atom% La, Al-x atom% Co-6 atom% Nd, Al-x atom% Co-3 atomic% La) is obtained by changing the content (x) of Ni and Co.

このような半導体装置に、電子情報技術産業規格（ＪＥＩＴＡ：ＥＤ−４７０１）に準拠して信頼性試験を実施した。具体的には、熱衝撃試験（１００℃で５分間保持した後、０℃で５分間保持するサイクルを１０サイクル）と温度サイクル試験（−４０℃で６０分保持した後、１５５℃で６０分保持するサイクルは１００サイクル繰り返し）を実施した。その後、回路基板を分解し、Ａｌ合金層を透過Ｘ線で観察し、線状コントラストが観察された場合、該線状コントラストを亀裂密度として計測した。具体的には、マイクロフォーカス機能付きのＸ線顕微鏡でＡｌ合金層の透過像を観察した。この際、管電圧を２０〜３０ｋＶとすると共に、等倍撮影したデータを２〜１０倍に拡大して線状コントラストを確認した。結果を図５に示す。   A reliability test was performed on such a semiconductor device in accordance with the Electronic Information Technology Industry Standard (JEITA: ED-4701). Specifically, thermal shock test (10 cycles of holding at 100 ° C. for 5 minutes and then holding at 0 ° C. for 5 minutes) and temperature cycle test (holding at −40 ° C. for 60 minutes, then at 155 ° C. for 60 minutes) The holding cycle was repeated 100 cycles). Thereafter, the circuit board was disassembled, the Al alloy layer was observed with transmitted X-rays, and when a linear contrast was observed, the linear contrast was measured as a crack density. Specifically, a transmission image of the Al alloy layer was observed with an X-ray microscope with a microfocus function. At this time, the tube voltage was set to 20 to 30 kV, and the data taken at the same magnification was magnified 2 to 10 times to confirm the linear contrast. The results are shown in FIG.

図５に示すように、Ａｌ合金層が本発明で規定する範囲内の添加量のＡｌ合金を用いた場合、優れた効果を発揮した。   As shown in FIG. 5, when the Al alloy layer was used in an addition amount within the range specified by the present invention, an excellent effect was exhibited.

１ 回路基板
２、２ａ、２ｂ、２ｃ、２ｄ 半導体素子
３、３ａ、３ｂ 電極
４ 接合部材
５ Ａｌ合金層
６ 純Ａｌ層 DESCRIPTION OF SYMBOLS 1 Circuit board 2, 2a, 2b, 2c, 2d Semiconductor element 3, 3a, 3b Electrode 4 Joining member 5 Al alloy layer 6 Pure Al layer

Claims (4)

電極を有する半導体素子と、回路基板とが、接合部材を介して接合された構成を１以上含む半導体装置であって、
前記接合部材は、Ａｌ合金層と純Ａｌ層との積層構造からなり、
前記Ａｌ合金層は、前記半導体素子の電極側に配置され、
前記純Ａｌ層は、前記回路基板側に配置されていることを特徴とする半導体装置。 A semiconductor device including one or more configurations in which a semiconductor element having an electrode and a circuit board are bonded via a bonding member,
The joining member has a laminated structure of an Al alloy layer and a pure Al layer,
The Al alloy layer is disposed on the electrode side of the semiconductor element,
The pure Al layer is arranged on the circuit board side. 前記電極の一部または全部が、前記接合部材で構成されている請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein a part or all of the electrode is configured by the bonding member. 前記純Ａｌ層のＡｌ純度が９９．５％以上である請求項１または２に記載の半導体装置。   The semiconductor device according to claim 1, wherein an Al purity of the pure Al layer is 99.5% or more. 前記Ａｌ合金は、Ｎｉ、Ｃｏ、Ｆｅ、およびＭｎよりなる群から選ばれる少なくとも１種を合計で０．１〜１０原子％含有すると共に、Ｎｄ、Ｌａ、およびＰｒよりなる群から選ばれる少なくとも１種を合計で０．１〜６原子％含有するものである請求項１〜３のいずれかに記載の半導体装置。   The Al alloy contains at least one selected from the group consisting of Ni, Co, Fe, and Mn in a total amount of 0.1 to 10 atomic%, and at least one selected from the group consisting of Nd, La, and Pr. The semiconductor device according to any one of claims 1 to 3, wherein the seed contains 0.1 to 6 atomic percent in total.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015115665A1 (en) * 2014-02-03 2015-08-06 国立大学法人大阪大学 Bonded structure and method for producing bonded structure
WO2016093276A1 (en) * 2014-12-09 2016-06-16 国立大学法人大阪大学 Bonded structure and method for producing bonded structure
WO2018100932A1 (en) * 2016-11-30 2018-06-07 株式会社コベルコ科研 Aluminum alloy sputtering target

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015115665A1 (en) * 2014-02-03 2015-08-06 国立大学法人大阪大学 Bonded structure and method for producing bonded structure
JPWO2015115665A1 (en) * 2014-02-03 2017-03-23 国立大学法人大阪大学 Junction structure and manufacturing method of junction structure
US10332853B2 (en) 2014-02-03 2019-06-25 Osaka University Bonding structure and method for producing bonding structure
WO2016093276A1 (en) * 2014-12-09 2016-06-16 国立大学法人大阪大学 Bonded structure and method for producing bonded structure
JP2016111259A (en) * 2014-12-09 2016-06-20 国立大学法人大阪大学 Junction structure and manufacturing method of the same
WO2018100932A1 (en) * 2016-11-30 2018-06-07 株式会社コベルコ科研 Aluminum alloy sputtering target

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