JP2011248222A - Display device - Google Patents
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- JP2011248222A JP2011248222A JP2010123023A JP2010123023A JP2011248222A JP 2011248222 A JP2011248222 A JP 2011248222A JP 2010123023 A JP2010123023 A JP 2010123023A JP 2010123023 A JP2010123023 A JP 2010123023A JP 2011248222 A JP2011248222 A JP 2011248222A
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- 239000000758 substrate Substances 0.000 claims abstract description 115
- 239000010409 thin film Substances 0.000 claims abstract description 62
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 238000013459 approach Methods 0.000 claims description 2
- 102100036464 Activated RNA polymerase II transcriptional coactivator p15 Human genes 0.000 abstract description 32
- 101000713904 Homo sapiens Activated RNA polymerase II transcriptional coactivator p15 Proteins 0.000 abstract description 32
- 229910004444 SUB1 Inorganic materials 0.000 abstract description 32
- 230000001629 suppression Effects 0.000 abstract description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 22
- 239000013256 coordination polymer Substances 0.000 description 13
- 239000010408 film Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 229910004438 SUB2 Inorganic materials 0.000 description 5
- 101100311330 Schizosaccharomyces pombe (strain 972 / ATCC 24843) uap56 gene Proteins 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 101150018444 sub2 gene Proteins 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
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- 238000009825 accumulation Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4092—Integral conductive tabs, i.e. conductive parts partly detached from the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10128—Display
- H05K2201/10136—Liquid Crystal display [LCD]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/361—Assembling flexible printed circuits with other printed circuits
- H05K3/363—Assembling flexible printed circuits with other printed circuits by soldering
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
- Wire Bonding (AREA)
Abstract
Description
本発明は、表示装置に関する。 The present invention relates to a display device.
コンピュータ等の情報通信端末やテレビ受像機の表示デバイスとして、液晶表示装置や有機ＥＬ表示装置などの表示装置が広く用いられている。例えば、液晶表示装置は、電界を変化させることにより、薄膜トランジスタ（ＴＦＴ：Thin Film Transistor）基板と対向基板の間に封じ込められた液晶組成物の配向を変え、２つの基板と液晶組成物を通過する光の透過度合いを制御することにより画像を表示させる液晶表示パネルを用いた装置である。この電界の変化は、液晶表示パネル内に複数形成された画素ごとに行われる。 Display devices such as liquid crystal display devices and organic EL display devices are widely used as display devices for information communication terminals such as computers and television receivers. For example, a liquid crystal display device changes the orientation of a liquid crystal composition contained between a thin film transistor (TFT) substrate and a counter substrate by changing an electric field, and passes through the two substrates and the liquid crystal composition. It is an apparatus using a liquid crystal display panel that displays an image by controlling the degree of light transmission. This change in the electric field is performed for each of a plurality of pixels formed in the liquid crystal display panel.
画素ごとに電界を変化させるために、液晶表示パネルの薄膜トランジスタ基板には、複数の映像信号線と複数の走査信号線が形成され、各画素に配置された薄膜トランジスタに、それぞれ映像信号線と走査信号線が接続される。 In order to change the electric field for each pixel, a plurality of video signal lines and a plurality of scanning signal lines are formed on the thin film transistor substrate of the liquid crystal display panel, and the video signal lines and the scanning signals are respectively formed on the thin film transistors arranged in each pixel. The line is connected.
そして、映像信号線には、液晶表示パネルの表示領域の外側に設置されたドレインドライバから、各画素の階調値に対応する映像信号が出力され、走査信号線には、表示領域の外側に設置されたゲートドライバから、映像信号を各画素に入力するタイミング信号（ゲート信号）が出力される。各画素に供給された映像信号は、薄膜トランジスタを介して画素電極に印加される。 A video signal corresponding to the gradation value of each pixel is output to the video signal line from the drain driver installed outside the display area of the liquid crystal display panel, and the scanning signal line is provided outside the display area. A timing signal (gate signal) for inputting a video signal to each pixel is output from the installed gate driver. The video signal supplied to each pixel is applied to the pixel electrode through the thin film transistor.
上記ドレインドライバやゲートドライバ（本明細書において、駆動回路ともいう）は、例えば、ＣＯＦ（Chip On Film）のような、半導体チップを搭載したフィルム状のパッケージとして形成されて、映像信号線や走査信号線が形成された薄膜トランジスタ基板に接続される。 The drain driver and the gate driver (also referred to as a drive circuit in the present specification) are formed as a film-like package on which a semiconductor chip is mounted, such as a COF (Chip On Film), and are used for video signal lines and scanning. It is connected to a thin film transistor substrate on which signal lines are formed.
薄膜トランジスタ基板は、上記映像信号線や走査信号線と上記ＣＯＦの接続を行う端子部を有する。このような構造を示す一例として、例えば特開２００９−３６８７１（特許文献１）がある。 The thin film transistor substrate has a terminal portion for connecting the video signal line or the scanning signal line to the COF. As an example showing such a structure, for example, there is JP-A-2009-36871 (Patent Document 1).
ここで、図７Ａおよび図７Ｂに、従来の薄膜トランジスタ基板ＳＵＢ１における端子部とＣＯＦの接続領域の拡大図を示す。図７Ａは、薄膜トランジスタ基板ＳＵＢ１の映像信号線に接続される端子ＴＲに、フレキシブル基板ＦＢ上の配線ＬＳが重なって接続される様子を示す上面図である。配線ＬＳにより、フレキシブル基板ＦＢに搭載された半導体チップと端子ＴＲとが電気的に接続される。なお、ＣＯＦのフレキシブル基板ＦＢ上には、例えばソルダーレジストによって、絶縁保護膜としての樹脂膜ＳＲ（ソルダーレジスト膜）が形成される。 Here, FIGS. 7A and 7B are enlarged views of a connection region between the terminal portion and the COF in the conventional thin film transistor substrate SUB1. FIG. 7A is a top view showing a state in which the wiring LS on the flexible substrate FB is connected to the terminal TR connected to the video signal line of the thin film transistor substrate SUB1. The semiconductor chip mounted on the flexible substrate FB and the terminal TR are electrically connected by the wiring LS. On the COF flexible substrate FB, a resin film SR (solder resist film) as an insulating protective film is formed by, for example, a solder resist.
図７Ｂは、図７ＡのVIIＢ−VIIＢにおける断面図である。図７Ｂにおいては、薄膜トランジスタ基板ＳＵＢ１の端子部とフレキシブル基板ＦＢとの間の異方性導電膜（ＡＣＦ：Anisotropic Conductive Film）の図示を省略している。 7B is a cross-sectional view taken along the line VIIB-VIIB in FIG. 7A. In FIG. 7B, illustration of an anisotropic conductive film (ACF) between the terminal portion of the thin film transistor substrate SUB1 and the flexible substrate FB is omitted.
図７Ｂで示されるように、従来のフレキシブル基板ＦＢ上の配線ＬＳは、等方溶解性を有するエッチング液による製造方法によってテーパー状に形成されて、フレキシブル基板ＦＢ側の幅が広くなる。具体的には、端子ＴＲが均等のピッチｐで並ぶ場合に、配線ＬＳのフレキシブル基板ＦＢ側の幅Ｘ１は、通常、略ｐ／２となるように形成され、端子ＴＲ側の幅Ｙ１は、略ｐ／３となるように形成される。また、薄膜トランジスタ基板ＳＵＢ１の各端子ＴＲの幅Ｗは、このようなテーパー形状の配線ＬＳの断面形状及び幅を踏まえて、最適化した値に設定される。 As shown in FIG. 7B, the wiring LS on the conventional flexible substrate FB is formed into a tapered shape by a manufacturing method using an isotropically soluble etching solution, and the width on the flexible substrate FB side is widened. Specifically, when the terminals TR are arranged at an equal pitch p, the width X1 of the wiring LS on the flexible substrate FB side is normally formed to be approximately p / 2, and the width Y1 on the terminal TR side is It is formed so as to be approximately p / 3. In addition, the width W of each terminal TR of the thin film transistor substrate SUB1 is set to an optimized value in consideration of the cross-sectional shape and width of the tapered wiring LS.
近年の原価低減に対する技術的取組みの結果、ＣＯＦに搭載される半導体チップの加工技術は微細化し、フレキシブル基板ＦＢ上の配線形成技術の向上も進展している。 As a result of technical efforts for cost reduction in recent years, the processing technology of semiconductor chips mounted on the COF has been miniaturized, and the improvement of the wiring formation technology on the flexible substrate FB is also progressing.
ここで例えば、フレキシブル基板ＦＢ上の配線形成に、異方性エッチングおよび積層方式を適用する場合には、図７Ｂに示すようなテーパー状の断面形状ではなく、配線の底部と上面の幅が同等となる矩形状の断面となる。 Here, for example, when anisotropic etching and a lamination method are applied to the wiring formation on the flexible substrate FB, the widths of the bottom and top surfaces of the wiring are not the same, as shown in FIG. 7B. It becomes a rectangular cross section.
図８は、このような場合を示す図であり、図７と同様に、薄膜トランジスタ基板ＳＵＢの端子部と、ＣＯＦとの接続領域の拡大図を示している。ここで、配線ＬＳの幅Ｘ２をｐ／３程度に細く設定する場合には、各配線ＬＳの間隔に余裕が生じるため、ショートなどの不具合が生じにくくなる。しかしながら、薄膜トランジスタ基板ＳＵＢ１の端部ＥＧ付近から外側に引き出される配線ＬＳの断面積が減少するため、配線ＬＳの機械的強度が低下して断線する可能性が高くなる。 FIG. 8 is a diagram showing such a case, and similarly to FIG. 7, shows an enlarged view of a connection region between the terminal portion of the thin film transistor substrate SUB and the COF. Here, when the width X2 of the wiring LS is set to be as thin as about p / 3, there is a margin in the interval between the wirings LS, so that problems such as a short circuit are less likely to occur. However, since the cross-sectional area of the wiring LS drawn out from the vicinity of the end portion EG of the thin film transistor substrate SUB1 is reduced, the mechanical strength of the wiring LS is lowered and the possibility of disconnection is increased.
一方、配線ＬＳの幅Ｘ２をｐ／２程度に太く設定する場合には、機械的強度が向上するものの、配線ＬＳの端子ＴＲと重なる部分の幅も広くなり、ショートなどの不具合が発生しやすくなる。 On the other hand, when the width X2 of the wiring LS is set to be as thick as about p / 2, the mechanical strength is improved, but the width of the portion overlapping the terminal TR of the wiring LS is also widened, and a problem such as a short circuit is likely to occur. Become.
以上のように、フレキシブル基板上の配線が微細化するのに伴い、フレキシブル基板上の配線の機械的強度を確保しつつ、表示パネルとフレキシブル基板の接続部における電気的な不具合を抑制するのが困難になる。 As described above, with the miniaturization of the wiring on the flexible substrate, the electrical strength at the connection portion between the display panel and the flexible substrate is suppressed while ensuring the mechanical strength of the wiring on the flexible substrate. It becomes difficult.
本発明は、上記課題に鑑みて、薄膜トランジスタ基板の端子部とフレキシブル基板の配線の接続部における不具合の抑制と、フレキシブル基板上の配線の機械的強度の確保を両立した表示装置を提供することを目的とする。 In view of the above problems, the present invention provides a display device that achieves both suppression of defects in the connection portion between the terminal portion of the thin film transistor substrate and the wiring of the flexible substrate and securing of the mechanical strength of the wiring on the flexible substrate. Objective.
本発明に係る表示装置は、上記課題に鑑みて、複数の端子を含む端子部を薄膜トランジスタ基板上に備えた表示パネルと、前記端子部に接続される駆動回路と、を有する表示装置であって、前記駆動回路は、フレキシブル基板と、当該フレキシブル基板に搭載される半導体チップと、を有し、前記フレキシブル基板は、前記半導体チップ及び前記複数の端子の間をそれぞれ接続する複数の配線を備え、前記配線は、前記端子に重なる第１配線部分と、前記第１配線部分と前記半導体チップとの間に位置する第２配線部分と、を有し、前記第１配線部分は、前記第２配線部分よりも細い、ことを特徴とする。 In view of the above problems, a display device according to the present invention is a display device having a display panel including a terminal portion including a plurality of terminals on a thin film transistor substrate, and a drive circuit connected to the terminal portion. The drive circuit includes a flexible substrate and a semiconductor chip mounted on the flexible substrate, and the flexible substrate includes a plurality of wirings respectively connecting the semiconductor chip and the plurality of terminals. The wiring includes a first wiring portion that overlaps with the terminal, and a second wiring portion that is positioned between the first wiring portion and the semiconductor chip, and the first wiring portion includes the second wiring portion. It is thinner than the part.
また、本発明に係る表示装置の一態様では、前記複数の端子は、前記薄膜トランジスタ基板の端部から離れて内側に配置される、ことを特徴としてもよい。 In the display device according to one aspect of the present invention, the plurality of terminals may be disposed on the inner side away from the end portion of the thin film transistor substrate.
また、本発明に係る表示装置の一態様では、前記フレキシブル基板の一部は、前記端子部を含む前記薄膜トランジスタ基板の一部と重なり、前記配線は、前記第１配線部分と前記第２配線部分の間に位置する第３配線部分をさらに有し、前記第３配線部分は、前記薄膜トランジスタ基板の前記端部と前記端子との間の領域と重なるとともに、前記第２配線部分に近づくにつれて徐々に線幅が太くなる、ことを特徴としてもよい。 In the display device according to the aspect of the invention, a part of the flexible substrate may overlap a part of the thin film transistor substrate including the terminal portion, and the wiring may include the first wiring part and the second wiring part. And a third wiring portion that overlaps with a region between the end of the thin film transistor substrate and the terminal and gradually approaches the second wiring portion. The line width may be increased.
また、本発明に係る表示装置の一態様では、前記第２配線部分は、前記薄膜トランジスタ基板の前記端部と重複する、ことを特徴としてもよい。 In the display device according to the aspect of the invention, the second wiring portion may overlap the end portion of the thin film transistor substrate.
また、本発明に係る表示装置の一態様では、前記複数の端子は、所定のピッチで配置されて、前記配線は、断面が矩形状に形成されて、前記第１配線部分は、前記ピッチの０．３倍以上であって０．４倍以下の線幅となる、ことを特徴としてもよい。 In the display device according to the aspect of the invention, the plurality of terminals may be arranged at a predetermined pitch, the wiring may have a rectangular cross section, and the first wiring portion may have the pitch. The line width may be 0.3 times or more and 0.4 times or less.
また、本発明に係る表示装置の一態様では、前記複数の端子は、前記薄膜トランジスタ基板の端部に沿って所定のピッチで配置されて、前記複数の配線のそれぞれは、前記薄膜トランジスタ基板の前記端部とほぼ垂直に交差して、前記複数の端子のそれぞれと重なる、ことを特徴としてもよい。 In the display device according to the aspect of the invention, the plurality of terminals are arranged at a predetermined pitch along an end portion of the thin film transistor substrate, and each of the plurality of wirings is connected to the end of the thin film transistor substrate. It may also be characterized in that it intersects each of the plurality of terminals and overlaps each of the plurality of terminals.
本発明によれば、薄膜トランジスタ基板の端子部とフレキシブル基板の接続部における不具合の抑制と、フレキシブル基板上の配線の機械的強度の確保とを両立した表示装置を提供することが出来る。 ADVANTAGE OF THE INVENTION According to this invention, the display apparatus which can suppress the malfunction in the terminal part of a thin-film transistor substrate and the connection part of a flexible substrate, and ensuring the mechanical strength of the wiring on a flexible substrate can be provided.
以下、図面を用いて本発明の一実施形態について説明する。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
［第１の実施形態］
図１は、本実施形態に係る表示装置の概略平面図である。本実施形態における表示装置は、液晶表示装置であって、液晶表示パネルＰＮＬは、液晶（図示せず）を介在させて対向配置される薄膜トランジスタ基板ＳＵＢ１および対向基板ＳＵＢ２を含んで構成されている。
[First Embodiment]
FIG. 1 is a schematic plan view of a display device according to the present embodiment. The display device in the present embodiment is a liquid crystal display device, and the liquid crystal display panel PNL includes a thin film transistor substrate SUB1 and a counter substrate SUB2 that are arranged to face each other with a liquid crystal (not shown) interposed therebetween.
また液晶は、薄膜トランジスタ基板ＳＵＢ１に対する対向基板ＳＵＢ２の固定を兼ねるシール材ＳＬによって封止され、該シール材ＳＬで囲まれた領域が、画像を表示する表示領域ＡＲとして構成されている。 The liquid crystal is sealed by a sealing material SL that also serves to fix the counter substrate SUB2 to the thin film transistor substrate SUB1, and an area surrounded by the sealing material SL is configured as a display area AR that displays an image.
表示領域ＡＲでは、薄膜トランジスタ基板ＳＵＢ１側に、図中ｘ方向に延在しｙ方向に並設される複数のゲート信号線ＧＬ、および、図中ｙ方向に延在しｘ方向に並設される複数のドレイン信号線ＤＬが形成されている。 In the display area AR, on the thin film transistor substrate SUB1 side, a plurality of gate signal lines GL extending in the x direction in the drawing and arranged in parallel in the y direction, and extending in the y direction in the drawing and arranged in parallel in the x direction. A plurality of drain signal lines DL are formed.
表示領域ＡＲにおいては、互いに隣接する２本のゲート信号線ＧＬと、互いに隣接する２本のドレイン信号線ＤＬとで囲まれる領域（画素領域ＰＩＸ）がマトリックス状に配置される。画素領域ＰＩＸの等価回路は、たとえば図中実線丸枠で示すように、薄膜トランジスタＴＦＴと、画素電極ＰＸと、容量素子Ｃａｄｄを備えている。画素領域ＰＩＸでは、薄膜トランジスタＴＦＴに、ゲート信号線ＧＬからの走査信号が入力され、画素電極ＰＸに、薄膜トランジスタＴＦＴを介してドレイン信号線ＤＬからの映像信号が供給される。そして、容量素子Ｃａｄｄは、画素電極ＰＸと、隣接する画素領域にゲート信号を出力するゲート信号線ＧＬとの間に接続されて、当該画素電極ＰＸに映像信号が供給された際にその電荷を比較的長く蓄積させるために備えられる。また、対向基板ＳＵＢ２の液晶側の面には、各画素領域に共通に設けられた対向電極（図示せず）が備えられ、画素電極ＰＸとの間に電界が印加されることにより、液晶が駆動するようになっている。 In the display area AR, an area (pixel area PIX) surrounded by two adjacent gate signal lines GL and two adjacent drain signal lines DL is arranged in a matrix. The equivalent circuit of the pixel region PIX includes, for example, a thin film transistor TFT, a pixel electrode PX, and a capacitor element Cadd, as shown by a solid circle in the drawing. In the pixel region PIX, the scanning signal from the gate signal line GL is input to the thin film transistor TFT, and the video signal from the drain signal line DL is supplied to the pixel electrode PX via the thin film transistor TFT. The capacitive element Cadd is connected between the pixel electrode PX and a gate signal line GL that outputs a gate signal to an adjacent pixel region, and the charge is supplied when a video signal is supplied to the pixel electrode PX. Provided for relatively long accumulation. In addition, a counter electrode (not shown) provided in common to each pixel region is provided on the liquid crystal side surface of the counter substrate SUB2, and an electric field is applied between the counter electrode SUB2 and the pixel electrode PX. It comes to drive.
ゲート信号線ＧＬは、たとえば図中左側の一端において、シール材ＳＬを越えて延在され、薄膜トランジスタ基板ＳＵＢ１の左側周辺に配置される複数のゲートドライバＶＣ１、ＶＣ２、・・・、ＶＣｎに接続されている。これらゲートドライバＶＣ１、ＶＣ２、・・・、ＶＣｎの駆動によって、各ゲート信号線ＧＬに走査信号が順次供給される。 The gate signal line GL, for example, extends beyond the seal material SL at one end on the left side in the figure, and is connected to a plurality of gate drivers VC1, VC2,..., VCn disposed around the left side of the thin film transistor substrate SUB1. ing. By driving these gate drivers VC1, VC2,..., VCn, scanning signals are sequentially supplied to the gate signal lines GL.
また、ドレイン信号線ＤＬは、たとえば図中上側の一端において、シール材ＳＬを越えて延在され、薄膜トランジスタ基板ＳＵＢ１の上側周辺に配置される複数のドレインドライバＨＣ１、ＨＣ２、・・・、ＨＣｍに接続されている。これらドレインドライバＨＣ１、ＨＣ２、・・・、ＨＣｍの駆動によって、各ドレイン信号線ＤＬに映像信号が供給される。この場合の映像信号の供給は、ゲートドライバＶＣ１、ＶＣ２、・・・、ＶＣｎによる各ゲート信号線ＧＬへの走査信号の供給のタイミングに合わせてなされるようになっている。 Further, the drain signal line DL extends, for example, at one end on the upper side in the figure beyond the seal material SL, and is connected to a plurality of drain drivers HC1, HC2,..., HCm arranged on the upper periphery of the thin film transistor substrate SUB1. It is connected. By driving these drain drivers HC1, HC2,..., HCm, a video signal is supplied to each drain signal line DL. In this case, the video signal is supplied in accordance with the supply timing of the scanning signal to each gate signal line GL by the gate drivers VC1, VC2,..., VCn.
ゲートドライバＶＣ１、ＶＣ２、・・・、ＶＣｎは、後に説明するフレキシブル基板上にドライバチップが搭載された、いわゆるチップオンフィルム（ＣＯＦ）方式で形成された駆動回路ＳＣＮとして構成されている。 The gate drivers VC1, VC2,..., VCn are configured as a drive circuit SCN formed by a so-called chip on film (COF) system in which a driver chip is mounted on a flexible substrate described later.
また、ドレインドライバＨＣ１、ＨＣ２、・・・、ＨＣｍも、ゲートドライバＶＣ１、ＶＣ２、・・・、ＶＣｎと同様に、ＣＯＦ方式で形成された駆動回路ＳＣＮとして構成され、液晶表示パネルＰＮＬに近接して配置されるプリント基板ＰＣＢｈ１、ＰＣＢｈ２との間に跨って配置されている。 The drain drivers HC1, HC2,..., HCm are also configured as a drive circuit SCN formed by the COF method, similar to the gate drivers VC1, VC2,..., VCn, and are close to the liquid crystal display panel PNL. The printed circuit boards PCBh1 and PCBh2 are arranged so as to straddle.
また、プリント基板ＰＣＢｈ１、ＰＣＢｈ２には、図示しない制御回路（Ｔ−ｃｏｎ）からの信号Ｓｈが供給されるようになっており、該プリント基板ＰＣＢｈ１、ＰＣＢｈ２を介してドレインドライバＨＣ１、ＨＣ２、・・・、ＨＣｍに信号Ｓｈが入力されるようになっている。 Further, a signal Sh from a control circuit (T-con) (not shown) is supplied to the printed circuit boards PCBh1, PCBh2, and the drain drivers HC1, HC2,... Via the printed circuit boards PCBh1, PCBh2. The signal Sh is input to HCm.
上記のような液晶表示パネルＰＮＬは、たとえばバックライト等とともに、フレームによって固定されてモジュール化されるようになっている。 The liquid crystal display panel PNL as described above is fixed to a module by a frame together with, for example, a backlight.
次に、駆動回路ＳＣＮについて説明する。図２Ａおよび図２Ｂは、本実施形態における駆動回路ＳＣＮの概略的構成を示す図であり、図１におけるドレインドライバＨＣ１をその一例として示している。 Next, the drive circuit SCN will be described. 2A and 2B are diagrams showing a schematic configuration of the drive circuit SCN in the present embodiment, and the drain driver HC1 in FIG. 1 is shown as an example.
上述したように、駆動回路ＳＣＮは、ＣＯＦ方式によって形成され、樹脂材からなるフレキシブル基板ＦＢのほぼ中央にドライバＩＣである半導体チップＣＰが搭載される。フレキシブル基板ＦＢには、薄膜トランジスタ基板ＳＵＢ１と半導体チップＣＰとを接続するための複数の配線Ｌａと、プリント基板ＰＣＢｈ１に接続するための入力端子ＩＴと、入力端子ＩＴと半導体チップＣＰとの間を接続するための配線Ｌｂとが形成されている。 As described above, the drive circuit SCN is formed by the COF method, and the semiconductor chip CP, which is a driver IC, is mounted almost at the center of the flexible substrate FB made of a resin material. The flexible substrate FB is connected to a plurality of wirings La for connecting the thin film transistor substrate SUB1 and the semiconductor chip CP, an input terminal IT for connecting to the printed circuit board PCBh1, and a connection between the input terminal IT and the semiconductor chip CP. Wiring Lb is formed.
図２Ｂは、図２ＡにおけるIIB−IIBの概略断面を示す図である。図２Ｂで示すように、入力端子ＩＴ、配線Ｌａ、Ｌｂは、フレキシブル基板ＦＢのたとえば半導体チップＣＰの搭載される側と反対側の面にそれぞれが形成されている。 FIG. 2B is a diagram showing a schematic cross section of IIB-IIB in FIG. 2A. As shown in FIG. 2B, the input terminal IT and the wirings La and Lb are formed on the surface of the flexible substrate FB opposite to the side on which the semiconductor chip CP is mounted, for example.
フレキシブル基板ＦＢの半導体チップＣＰが搭載される領域には、透孔ＴＨが形成されている。そして、入力端子ＩＴのそれぞれに接続される配線Ｌｂの先端は、透孔ＴＨ内に突出して形成され、これら突出部は、半導体チップＣＰの各入力バンプＩＢＰに接続される端子ＴＭ１を構成するようになっている。また、配線Ｌａも同様に、透孔ＴＨ内に突出して形成され、これら突出部は、半導体チップＣＰの各出力バンプＯＢＰに接続される端子ＴＭ２を構成するようになっている。 A through hole TH is formed in a region of the flexible substrate FB where the semiconductor chip CP is mounted. The tips of the wirings Lb connected to the respective input terminals IT are formed so as to protrude into the through holes TH, and these protruding parts constitute terminals TM1 connected to the respective input bumps IBP of the semiconductor chip CP. It has become. Similarly, the wiring La is formed so as to protrude into the through hole TH, and these protruding portions constitute terminals TM2 connected to the output bumps OBP of the semiconductor chip CP.
半導体チップＣＰは、フレキシブル基板ＦＢの入力端子ＩＴ、配線Ｌａ、配線Ｌｂが形成された面と反対側から搭載され、たとえば半田を介して、その入力バンプＩＢＰは配線Ｌｂの端子ＴＭ１に接続され、出力バンプＯＢＰは配線Ｌａの端子ＴＭ２に接続されるようになっている。 The semiconductor chip CP is mounted from the side opposite to the surface on which the input terminal IT, the wiring La, and the wiring Lb of the flexible substrate FB are formed. For example, the input bump IBP is connected to the terminal TM1 of the wiring Lb via solder. The output bump OBP is connected to the terminal TM2 of the wiring La.
なお、半導体チップＣＰが搭載される側のフレキシブル基板ＦＢには該半導体チップＣＰを被って樹脂材（ソルダーレジスト膜）が塗布されているが、図５においては、その樹脂材は図示していない。 Note that a resin material (solder resist film) is applied to the flexible substrate FB on the side where the semiconductor chip CP is mounted so as to cover the semiconductor chip CP, but the resin material is not shown in FIG. .
さらに、図３Ａ及び図３Ｂは、駆動回路ＳＣＮのフレキシブル基板ＦＢが、プリント基板ＰＣＢｈ１と薄膜トランジスタ基板ＳＵＢ１とに接続された状態を概略的に示す図である。図３Ａは上面図であり、図３Ｂは、図３ＡのIIIB−IIIB線における断面図を示している。フレキシブル基板ＦＢの入力端子ＩＴと、プリント基板ＰＣＢｈ１の出力端子ＯＴＭとがそれぞれ対向するように、プリント基板ＰＣＢｈ１、異方性導電膜ＡＣＦ、フレキシブル基板ＦＢが順次積層配置されている。この積層配置は、液晶表示パネルＰＮＬ側でもほぼ同様であり、フレキシブル基板ＦＢと薄膜トランジスタ基板ＳＵＢ１の間に異方性導電膜ＡＣＦが介在している。 3A and 3B are diagrams schematically showing a state in which the flexible substrate FB of the drive circuit SCN is connected to the printed circuit board PCBh1 and the thin film transistor substrate SUB1. 3A is a top view, and FIG. 3B is a cross-sectional view taken along line IIIB-IIIB in FIG. 3A. The printed circuit board PCBh1, the anisotropic conductive film ACF, and the flexible circuit board FB are sequentially stacked so that the input terminal IT of the flexible circuit board FB and the output terminal OTM of the printed circuit board PCBh1 face each other. This stacked arrangement is substantially the same on the liquid crystal display panel PNL side, and an anisotropic conductive film ACF is interposed between the flexible substrate FB and the thin film transistor substrate SUB1.
ここで、図４〜図６に、本実施形態の薄膜トランジスタ基板ＳＵＢ１とフレキシブル基板ＦＢの接続部を拡大した様子を示す。図４は、当該接続部の上面を示す拡大図であり、図５および図６は、図４におけるV−V断面およびVI−VI断面を示す図である。 Here, FIGS. 4 to 6 show an enlarged view of the connecting portion between the thin film transistor substrate SUB1 and the flexible substrate FB of the present embodiment. FIG. 4 is an enlarged view showing the upper surface of the connecting portion, and FIGS. 5 and 6 are views showing a VV cross section and a VI-VI cross section in FIG.
まず、薄膜トランジスタ基板ＳＵＢ１は、ドレイン信号線ＤＬやゲート信号線ＧＬと駆動回路との接続を行うための、複数の端子ＴＲを含む端子部を有する。本実施形態における複数の端子ＴＲのそれぞれは、図４で示すように、薄膜トランジスタ基板ＳＵＢ１上に長方形状に形成される。各端子ＴＲは、薄膜トランジスタ基板ＳＵＢ１の端部ＥＧに沿って所定のピッチｐで並んで配置されており、各端子ＴＲの長辺は、端部ＥＧに対してほぼ垂直となるように配置されている。また、薄膜トランジスタ基板ＳＵＢ１の端部ＥＧは、マザーガラスから切断する際の端面（切断端）である。なお、本実施形態における端子部は、複数の端子ＴＲのそれぞれの短辺を結び、両端の端子ＴＲの長辺によって確定される部分をいうものとする。 First, the thin film transistor substrate SUB1 has a terminal portion including a plurality of terminals TR for connecting the drain signal line DL and the gate signal line GL to the driving circuit. As shown in FIG. 4, each of the plurality of terminals TR in the present embodiment is formed in a rectangular shape on the thin film transistor substrate SUB1. The terminals TR are arranged side by side at a predetermined pitch p along the end portion EG of the thin film transistor substrate SUB1, and the long sides of the terminals TR are arranged so as to be substantially perpendicular to the end portion EG. Yes. The end portion EG of the thin film transistor substrate SUB1 is an end surface (cut end) when cutting from the mother glass. In addition, the terminal part in this embodiment shall say the part which connects each short side of several terminal TR, and is decided by the long side of terminal TR of both ends.
次に、フレキシブル基板ＦＢは、図４（あるいは図１等）で示されるように、薄膜トランジスタ基板ＳＵＢ１と一部が重なるように固定される。さらに本実施形態では、フレキシブル基板ＦＢは、複数の端子ＴＲのそれぞれを上側から完全に覆っており、フレキシブル基板ＦＢと薄膜トランジスタ基板ＳＵＢ１との間に異方性導電膜ＡＣＦ（図４において不図示）が介在して固定される。また、フレキシブル基板ＦＢと薄膜トランジスタ基板ＳＵＢ１とが接着されるのりしろ寸法に対して、薄膜トランジスタ基板ＳＵＢ１上の端子ＴＲは小さく設定されている。 Next, as shown in FIG. 4 (or FIG. 1 or the like), the flexible substrate FB is fixed so as to partially overlap the thin film transistor substrate SUB1. Further, in this embodiment, the flexible substrate FB completely covers each of the plurality of terminals TR from above, and an anisotropic conductive film ACF (not shown in FIG. 4) is provided between the flexible substrate FB and the thin film transistor substrate SUB1. Is fixed by intervening. In addition, the terminal TR on the thin film transistor substrate SUB1 is set to be small with respect to a margin dimension to which the flexible substrate FB and the thin film transistor substrate SUB1 are bonded.
また、フレキシブル基板ＦＢが薄膜トランジスタ基板ＳＵＢ１上で固定される際には、フレキシブル基板ＦＢの複数の配線Ｌａが、複数の端子ＴＲとそれぞれ重なるようにして固定される。そして複数の配線Ｌａは、複数の端子ＴＲのそれぞれから直線状に延伸し、薄膜トランジスタ基板ＳＵＢ１の端部ＥＧとほぼ垂直に交差して（図３Ａ参照）、半導体チップＣＰに接続されるようにそれぞれ引き回されるようなレイアウトになっている。 When the flexible substrate FB is fixed on the thin film transistor substrate SUB1, the plurality of wirings La of the flexible substrate FB are fixed so as to overlap with the plurality of terminals TR, respectively. The plurality of wirings La extend linearly from each of the plurality of terminals TR, intersect the end EG of the thin film transistor substrate SUB1 substantially perpendicularly (see FIG. 3A), and are connected to the semiconductor chip CP. The layout is drawn around.
そして特に、図４、および、図５と図６の対比からもわかるように、フレキシブル基板ＦＢに形成された配線Ｌａの配線幅が部分的に異なっている。具体的には、フレキシブル基板ＦＢ上の配線Ｌａは、端子ＴＲと重なる第１配線部分Ｌａ１と、第１配線部分Ｌａ１と半導体チップＣＰの間に位置する第２配線部分Ｌａ２を有しており、第１配線部分Ｌａ１が有する第１の線幅ＷＴ１は、第２配線部分Ｌａ２が有する第２の線幅ＷＴ２よりも細くなる。これにより、端子ＴＲの幅に対して配線間ショートを起こしづらくするとともに、配線Ｌａの機械的強度を向上することができる。 In particular, as can be seen from FIG. 4 and the comparison between FIG. 5 and FIG. 6, the wiring width of the wiring La formed on the flexible substrate FB is partially different. Specifically, the wiring La on the flexible substrate FB includes a first wiring portion La1 that overlaps the terminal TR, and a second wiring portion La2 that is positioned between the first wiring portion La1 and the semiconductor chip CP. The first line width WT1 included in the first wiring portion La1 is narrower than the second line width WT2 included in the second wiring portion La2. As a result, it is difficult to cause a short circuit between wirings with respect to the width of the terminal TR, and the mechanical strength of the wiring La can be improved.
また、各端子ＴＲは、薄膜トランジスタ基板ＳＵＢ１の端部ＥＧから内側（表示領域ＡＲ側）に離れて配置される。端部ＥＧでは、フレキシブル基板ＦＢの湾曲等により応力が生じやすいが、端部ＥＧから離れて線幅の細い第１配線部分Ｌａ１が配置されることで、第１配線部分Ｌａ１が破損されにくくなる。 Further, each terminal TR is arranged away from the end EG of the thin film transistor substrate SUB1 on the inner side (display area AR side). In the end portion EG, stress is likely to occur due to the curvature of the flexible substrate FB, etc., but the first wiring portion La1 having a narrow line width away from the end portion EG is less likely to damage the first wiring portion La1. .
また、さらに、図４で示すように、この各端子ＴＲと薄膜トランジスタ基板ＳＵＢ１の端部ＥＧとの間には、第３配線部分Ｌａ３が介在して、配線幅の拡大が行われている。すなわち、第３配線部分Ｌａ３は、第１配線部分Ｌａ１と第２配線部分Ｌａ２との間に位置する部分であり、第３配線部分Ｌａ３は、薄膜トランジスタ基板ＳＵＢ１の端部ＥＧと端子ＴＲとの間の領域と重複して、かつ、第２配線部分Ｌａ２に向かうにつれて線幅がＷＴ１からＷＴ２へと徐々に太くなる。このように第３配線部分Ｌａ３において線幅が徐々に変化することにより、応力集中等の影響が緩和され、さらに、第３配線部分Ｌａ３が端部ＥＧの内側に存在することで、第２配線部分Ｌａ２以下の線幅となる第３配線部分Ｌａ３の機械的強度が補われる。 Furthermore, as shown in FIG. 4, the third wiring portion La3 is interposed between each terminal TR and the end portion EG of the thin film transistor substrate SUB1, thereby increasing the wiring width. That is, the third wiring portion La3 is a portion located between the first wiring portion La1 and the second wiring portion La2, and the third wiring portion La3 is between the end portion EG of the thin film transistor substrate SUB1 and the terminal TR. The line width gradually increases from WT1 to WT2 as it goes to the second wiring portion La2. As described above, the line width gradually changes in the third wiring portion La3, thereby mitigating the influence of stress concentration and the like. Further, the third wiring portion La3 exists inside the end portion EG. The mechanical strength of the third wiring portion La3 having a line width equal to or smaller than the portion La2 is supplemented.
また、本実施形態では、図４で示すように、複数の第２配線部分Ｌａ２および複数の第３配線部分Ｌａ３が端子部のピッチｐと同様のピッチで直線状に敷設されて、第２配線部分Ｌａ２と端部ＥＧとが垂直に交差している。第２配線部分Ｌａ２は、第３配線部分Ｌａ３が終了する位置から開始しており、その開始位置から樹脂膜ＳＲに覆われて保護されている。この第２配線部分Ｌａ２は、図４で示すように、端子ＴＲを基準として端部ＥＧよりも近い位置で開始して、端部ＥＧと重複する位置を含んでフレキシブル基板ＦＢ上に敷設されているのが望ましい。換言すれば、第２配線部分Ｌａ２と端子ＴＲとの間の距離が、端部ＥＧと端子ＴＲ間の距離よりも短くなるのが望ましい。これにより、フレキシブル基板ＦＢの湾曲等が生じ易い端部ＥＧにおいて機械的強度がさらに確保される。 Further, in the present embodiment, as shown in FIG. 4, the plurality of second wiring portions La2 and the plurality of third wiring portions La3 are laid in a straight line at a pitch similar to the pitch p of the terminal portion, and the second wiring The portion La2 and the end portion EG intersect each other vertically. The second wiring portion La2 starts from a position where the third wiring portion La3 ends, and is covered and protected by the resin film SR from the starting position. As shown in FIG. 4, the second wiring portion La2 starts at a position closer to the end portion EG with respect to the terminal TR, and is laid on the flexible substrate FB including a position overlapping the end portion EG. It is desirable. In other words, it is desirable that the distance between the second wiring portion La2 and the terminal TR is shorter than the distance between the end portion EG and the terminal TR. Thereby, the mechanical strength is further ensured at the end portion EG where the flexible substrate FB is likely to be bent.
なお、本実施形態では、図４で示すように、端子ＴＲと重なる位置に、第１配線部分Ｌａ１が配置され、端子ＴＲと重ならず薄膜トランジスタ基板ＳＵＢ１と重なる位置に、第３配線部分Ｌａ３が配置される。しかしながら、フレキシブル基板ＦＢを端子部に接着する際の誤差により、第１配線部分Ｌａ１等がずれて配置されることも想定される。したがって、例えば、第１配線部分Ｌａ１が端子ＴＲの端部ＥＧ側の短辺に至らず、第３配線部分Ｌａ３が、端部ＥＧ及び端子ＴＲ間の領域と重複しつつさらに端子ＴＲと重複してもよく、端子ＴＲと重複する位置から線幅の拡大が開始するのであっても良い。また、第１配線部分Ｌａ１が端子ＴＲの端部ＥＧ側の短辺を超えて第３配線部分Ｌａ３とつながり、端部ＥＧを基準として端子ＴＲよりも近い位置から線幅の拡大が開始するのであってもよい。また、例えば、第１配線部分Ｌａ１が端子ＴＲの端部ＥＧ側の短辺を超えて固定されるようなレイアウトで設計されてもよく、これらの場合も、本発明の範囲内となることはいうまでもない。 In the present embodiment, as shown in FIG. 4, the first wiring portion La1 is arranged at a position overlapping the terminal TR, and the third wiring portion La3 is positioned not overlapping the terminal TR but overlapping the thin film transistor substrate SUB1. Be placed. However, it is also assumed that the first wiring portion La1 and the like are shifted from each other due to an error in bonding the flexible substrate FB to the terminal portion. Therefore, for example, the first wiring portion La1 does not reach the short side of the terminal TR on the end EG side, and the third wiring portion La3 overlaps with the region between the end EG and the terminal TR while further overlapping with the terminal TR. Alternatively, the expansion of the line width may be started from a position overlapping with the terminal TR. Also, since the first wiring portion La1 is connected to the third wiring portion La3 beyond the short side on the end EG side of the terminal TR, and the line width starts to increase from a position closer to the terminal TR with respect to the end EG. There may be. Further, for example, the layout may be designed such that the first wiring portion La1 is fixed beyond the short side on the end portion EG side of the terminal TR, and these cases are also within the scope of the present invention. Needless to say.
なお、本実施形態では、図５及び図６で示されるように、フレキシブル基板ＦＢ上の配線Ｌａは、異方性エッチングおよび積層方式を用いて形成されて、断面が矩形状になっている。断面が矩形状になっている場合には、第１配線部分Ｌａ１における第１の線幅ＷＴ１は、端子ＴＲが配置されるピッチｐの０．３倍以上０．４倍以下とするのが望ましい。またさらに、この場合における第２配線部分Ｌａ２における第２の線幅ＷＴ２は、当該ピッチｐの０．４５倍以上０．５５倍以下とするのが望ましく、薄膜トランジスタ基板ＳＵＢ１上の端子ＴＲの幅は、第２の線幅ＷＴ２よりも太くしてよい。 In the present embodiment, as shown in FIGS. 5 and 6, the wiring La on the flexible substrate FB is formed using anisotropic etching and a lamination method, and has a rectangular cross section. When the cross section is rectangular, the first line width WT1 in the first wiring portion La1 is preferably 0.3 to 0.4 times the pitch p at which the terminals TR are arranged. . Furthermore, in this case, the second line width WT2 in the second wiring portion La2 is preferably 0.45 times to 0.55 times the pitch p, and the width of the terminal TR on the thin film transistor substrate SUB1 is , It may be thicker than the second line width WT2.
なお、本実施形態では、配線Ｌａの断面が矩形状になっているが、必ずしも断面を厳密な矩形とする必要はなく、断面が矩形状にならない場合であっても、本発明を適用できるものとする。 In this embodiment, the cross section of the wiring La is rectangular. However, the cross section is not necessarily a strict rectangle, and the present invention can be applied even when the cross section is not rectangular. And
なお、上記実施形態において、図４等で示されるフレキシブル基板ＦＢを有する駆動回路ＳＣＮは、ドレインドライバＨＣであってもよいし、ゲートドライバＶＣであってもよく、いずれにも適用可能である。 In the above embodiment, the drive circuit SCN having the flexible substrate FB shown in FIG. 4 or the like may be the drain driver HC or the gate driver VC, and can be applied to both.
なお、第３配線部分Ｌａ３は、上記の実施形態のように幅が線形的に変化するのが望ましいが、複数の段数を有する階段状の変化等であってもよい。 Note that the width of the third wiring portion La3 is preferably linearly changed as in the above embodiment, but may be a step-like change having a plurality of steps.
なお、上記の実施形態では、図４に示されるように、３本の配線Ｌａのそれぞれが、第１の線幅ＷＴ１を有する第１配線部分Ｌａ１と、第２の線幅ＷＴ２を有する第２配線部分Ｌａ２とを含んでいる。しかし、例えば、複数の配線Ｌａのうちの一本のみが、このような第１配線部分Ｌａ１と第２配線部分Ｌａ２とを含む場合であっても、電気的な不具合が抑制されつつ機械的強度が確保される。 In the above embodiment, as shown in FIG. 4, each of the three wirings La has a first wiring portion La1 having a first line width WT1 and a second wiring width WT2. The wiring part La2 is included. However, for example, even if only one of the plurality of wirings La includes such a first wiring part La1 and the second wiring part La2, the mechanical strength is suppressed while suppressing electrical problems. Is secured.
なお、上記実施形態では、液晶表示装置の場合について説明をしているが、有機ＥＬ表示装置等の他の表示装置についても同様に本発明を適用することが出来る。また、本発明が適用できる液晶表示装置としては、その画素の構成として上述したものに限定されることはなく、たとえば、基板ＳＵＢ１側の画素領域に画素電極と対向電極とが形成され、これら各電極の間に発生する電界によって液晶を駆動させるいわゆる横電界方式と称される画素構成であってもよいし、他の画素構成の液晶表示装置であっても良い。 Although the liquid crystal display device is described in the above embodiment, the present invention can be similarly applied to other display devices such as an organic EL display device. The liquid crystal display device to which the present invention can be applied is not limited to the above-described configuration of the pixel. For example, a pixel electrode and a counter electrode are formed in the pixel region on the substrate SUB1 side. A pixel configuration called a so-called horizontal electric field method in which liquid crystal is driven by an electric field generated between electrodes may be used, or a liquid crystal display device having another pixel configuration may be used.
ＰＮＬ 液晶表示パネル、ＳＵＢ１ 薄膜トランジスタ基板、ＳＵＢ２ 対向基板、ＡＲ 表示領域、ＧＬ ゲート信号線、ＤＬ ドレイン信号線、ＳＬ シール材、ＰＣＢｈ１，ＰＣＢｈ２ プリント基板、ＡＣＦ 異方性導電膜、ＳＲ 樹脂膜、ＶＣ ゲートドライバ、ＨＣ ドレインドライバ、ＳＣＮ 駆動回路、ＦＢ フレキシブル基板、ＣＰ 半導体チップ、ＩＮ 入力端子、ＯＴＭ 出力端子、Ｌａ 配線、Ｌａ１ 第１配線部分、Ｌａ２ 第２配線部分、Ｌａ３ 第３配線部分、ＴＲ 端子、ＥＧ 端部（切断端）。 PNL liquid crystal display panel, SUB1 thin film transistor substrate, SUB2 counter substrate, AR display area, GL gate signal line, DL drain signal line, SL seal material, PCBh1, PCBh2 printed circuit board, ACF anisotropic conductive film, SR resin film, VC gate Driver, HC drain driver, SCN drive circuit, FB flexible board, CP semiconductor chip, IN input terminal, OTM output terminal, La wiring, La1 first wiring part, La2 second wiring part, La3 third wiring part, TR terminal, EG end (cut end).
Claims (6)
前記端子部に接続される駆動回路と、を有する表示装置であって、
前記駆動回路は、
フレキシブル基板と、当該フレキシブル基板に搭載される半導体チップと、を有し、
前記フレキシブル基板は、前記半導体チップ及び前記複数の端子の間をそれぞれ接続する複数の配線を備え、
前記配線は、
前記端子に重なる第１配線部分と、
前記第１配線部分と前記半導体チップとの間に位置する第２配線部分と、を有し、
前記第１配線部分は、前記第２配線部分よりも細い、
ことを特徴とする表示装置。 A display panel including a terminal portion including a plurality of terminals on a thin film transistor substrate;
A display device having a drive circuit connected to the terminal portion,
The drive circuit is
A flexible substrate and a semiconductor chip mounted on the flexible substrate;
The flexible substrate includes a plurality of wirings that connect the semiconductor chip and the plurality of terminals, respectively.
The wiring is
A first wiring portion overlapping the terminal;
A second wiring portion located between the first wiring portion and the semiconductor chip,
The first wiring portion is thinner than the second wiring portion;
A display device characterized by that.
前記複数の端子は、前記薄膜トランジスタ基板の端部から離れて内側に配置される、
ことを特徴とする表示装置。 The display device according to claim 1,
The plurality of terminals are disposed on an inner side away from an end of the thin film transistor substrate.
A display device characterized by that.
前記フレキシブル基板の一部は、前記端子部を含む前記薄膜トランジスタ基板の一部と重なり、
前記配線は、
前記第１配線部分と前記第２配線部分の間に位置する第３配線部分をさらに有し、
前記第３配線部分は、前記薄膜トランジスタ基板の前記端部と前記端子との間の領域と重なるとともに、前記第２配線部分に近づくにつれて徐々に線幅が太くなる、
ことを特徴とする表示装置。 A display device according to claim 2,
A portion of the flexible substrate overlaps a portion of the thin film transistor substrate including the terminal portion,
The wiring is
A third wiring portion located between the first wiring portion and the second wiring portion;
The third wiring portion overlaps with a region between the end of the thin film transistor substrate and the terminal, and the line width gradually increases as it approaches the second wiring portion.
A display device characterized by that.
前記第２配線部分は、前記薄膜トランジスタ基板の前記端部と重複する、
ことを特徴とする表示装置。 A display device according to any one of claims 2 and 3,
The second wiring portion overlaps the end of the thin film transistor substrate;
A display device characterized by that.
前記複数の端子は、所定のピッチで配置されて、
前記配線は、断面が矩形状に形成されて、
前記第１配線部分は、前記ピッチの０．３倍以上であって０．４倍以下の線幅となる、
ことを特徴とする表示装置。 The display device according to claim 1,
The plurality of terminals are arranged at a predetermined pitch,
The wiring is formed in a rectangular cross section,
The first wiring portion has a line width of not less than 0.3 times the pitch and not more than 0.4 times.
A display device characterized by that.
前記複数の端子は、前記薄膜トランジスタ基板の端部に沿って所定のピッチで配置されて、
前記複数の配線のそれぞれは、前記薄膜トランジスタ基板の前記端部とほぼ垂直に交差して、前記複数の端子のそれぞれと重なる、
ことを特徴とする表示装置。 The display device according to claim 1,
The plurality of terminals are arranged at a predetermined pitch along an end of the thin film transistor substrate,
Each of the plurality of wirings intersects the end of the thin film transistor substrate substantially perpendicularly and overlaps each of the plurality of terminals;
A display device characterized by that.
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| JP2010123023A JP5528906B2 (en) | 2010-05-28 | 2010-05-28 | Display device |
| US13/115,131 US8902394B2 (en) | 2010-05-28 | 2011-05-25 | Display device comprising a flexible board including a first wiring portion that is narrower than a second wiring portion and wherein the second wiring portion does not overlap a terminal portion |
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| JP2010123023A JP5528906B2 (en) | 2010-05-28 | 2010-05-28 | Display device |
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| JP2018049193A (en) * | 2016-09-23 | 2018-03-29 | 株式会社ジャパンディスプレイ | Display device |
| KR102578051B1 (en) | 2018-06-01 | 2023-09-14 | 삼성전자주식회사 | Film type package and display apparatus having the same |
| CN115866879A (en) | 2019-09-10 | 2023-03-28 | 群创光电股份有限公司 | Electronic device |
| KR20210060718A (en) * | 2019-11-18 | 2021-05-27 | 삼성디스플레이 주식회사 | Display device and method of manufacturing display device |
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