JP2011192733A - Method of manufacturing photovoltaic device - Google Patents

Method of manufacturing photovoltaic device Download PDF

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JP2011192733A
JP2011192733A JP2010056117A JP2010056117A JP2011192733A JP 2011192733 A JP2011192733 A JP 2011192733A JP 2010056117 A JP2010056117 A JP 2010056117A JP 2010056117 A JP2010056117 A JP 2010056117A JP 2011192733 A JP2011192733 A JP 2011192733A
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heat treatment
semiconductor layer
substrate
layer
intrinsic semiconductor
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JP5268976B2 (en
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Masa Sakai
雅 酒井
Takehiko Sato
剛彦 佐藤
Shuichi Hiza
秀一 檜座
Shigeru Matsuno
繁 松野
Makoto Konagai
誠 小長井
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Mitsubishi Electric Corp
Tokyo Institute of Technology NUC
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Tokyo Institute of Technology NUC
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a photovoltaic device which has good characteristics by improving interface characteristics of a crystalline silicon substrate and an intrinsic semiconductor layer. <P>SOLUTION: The method includes; a process (S101) for forming a second conductive type first semiconductor layer different from a first conductive type on a light receiving surface side of a first conductive type silicon semiconductor substrate; a process (S105) for forming the intrinsic semiconductor layer on a surface opposite to the light receiving surface of the silicon semiconductor substrate; a process (S106, S107) for carrying out first thermal treatment after forming the intrinsic semiconductor layer; a process (S108) for forming a first conductive type second semiconductor layer with higher impurity density than the silicon semiconductor substrate on a surface opposite to the intrinsic semiconductor layer after the first thermal treatment; and a process (S109) for carrying out second thermal treatment after forming the second semiconductor layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、太陽電池などの光起電力装置の製造方法に関し、特に、結晶シリコン系太陽電池において高効率化が可能なヘテロ接合太陽電池の製造方法に関する。   The present invention relates to a method for manufacturing a photovoltaic device such as a solar cell, and more particularly to a method for manufacturing a heterojunction solar cell capable of increasing efficiency in a crystalline silicon solar cell.

現在の多結晶シリコン太陽電池は、厚さが２００μｍ程度のｐ型多結晶シリコン基板を用い、光吸収率を高める表面テクスチャー、ｎ型拡散層、反射防止膜及び表面電極（例えば、櫛型Ａｇ電極）を当該基板の受光面側に順次形成し、また、裏面電極（例えば、Ａｌ電極）をスクリーン印刷によって当該基板の非受光面側に形成した後、これらを焼成することによって一般に製造されている。   A current polycrystalline silicon solar cell uses a p-type polycrystalline silicon substrate having a thickness of about 200 μm, and has a surface texture, an n-type diffusion layer, an antireflection film, and a surface electrode (for example, a comb-shaped Ag electrode) that increase the light absorption rate. ) Are sequentially formed on the light-receiving surface side of the substrate, and a back electrode (for example, an Al electrode) is formed on the non-light-receiving surface side of the substrate by screen printing, and then is generally manufactured by firing them. .

かかる焼成では、表面電極及び裏面電極の溶媒分が揮発すると共に、当該基板の受光面側において櫛型Ａｇ電極が反射防止膜を突き破ってｎ型拡散層に接続され、また、当該基板の非受光面側においてＡｌ電極の一部のＡｌが当該基板に拡散して裏面電界層（ＢＳＦ：Back Surface Field）を形成する。   In such firing, the solvent content of the front electrode and the back electrode is volatilized, and the comb-shaped Ag electrode penetrates the antireflection film on the light receiving surface side of the substrate and is connected to the n-type diffusion layer. On the surface side, a part of Al of the Al electrode diffuses into the substrate to form a back surface field layer (BSF).

このＢＳＦ層は、当シリコン基板との接合面で内部電界を形成してＢＳＦ層近傍で発生した少数キャリアをシリコン基板内部へ押し戻し、Ａｌ電極近傍でのキャリア再結合を抑制するため、開放電圧を高くすることができる。   This BSF layer forms an internal electric field at the bonding surface with the silicon substrate, pushes minority carriers generated near the BSF layer back into the silicon substrate, and suppresses carrier recombination near the Al electrode. Can be high.

既に、結晶シリコン基板に薄い真性半導体層を介して不純物ドープシリコン層からなる接合或いはＢＳＦ層を形成するヘテロ接合太陽電池に関する発明が開示されている（特許文献１〜３参照）。   An invention relating to a heterojunction solar cell in which a junction made of an impurity-doped silicon layer or a BSF layer is formed on a crystalline silicon substrate via a thin intrinsic semiconductor layer has already been disclosed (see Patent Documents 1 to 3).

不純物ドープ層を薄膜で形成することにより不純物ドープ層の濃度分布を自由に設定でき、また不純物層が薄いため膜中でのキャリアの再結合を抑制することができる。また、間に挿入した真性半導体層は接合間の不純物拡散を抑制し、急峻な不純物プロファイルをもつ接合を形成することができるため、良好な接合界面形成により高い開放電圧を得ることができる。   By forming the impurity doped layer as a thin film, the concentration distribution of the impurity doped layer can be freely set, and since the impurity layer is thin, carrier recombination in the film can be suppressed. In addition, since the intrinsic semiconductor layer inserted between them can suppress impurity diffusion between the junctions and form a junction having a steep impurity profile, a high open-circuit voltage can be obtained by forming a good junction interface.

さらに真性半導体層、不純物ドープ層は２００℃程度の低温で形成できるため、基板の厚みが薄くても熱により基板に生じるストレスや、基板の反りを低減することができる。また、熱により劣化しやすい多結晶シリコン基板に対しても基板品質の低下を抑制できることが期待できる。   Further, since the intrinsic semiconductor layer and the impurity doped layer can be formed at a low temperature of about 200 ° C., stress generated in the substrate due to heat and warpage of the substrate can be reduced even if the substrate is thin. In addition, it can be expected that deterioration of the substrate quality can be suppressed even for a polycrystalline silicon substrate that is easily deteriorated by heat.

ヘテロ接合太陽電池の変換効率を向上させる方法としては、太陽電池セルの集電極を形成した後に高温で熱処理することが開示されている（特許文献４、５参照）。   As a method for improving the conversion efficiency of the heterojunction solar cell, it is disclosed that heat treatment is performed at a high temperature after the collector electrode of the solar cell is formed (see Patent Documents 4 and 5).

高温で熱処理を行うことにより、シリコン基板と膜の界面や、真性半導体層と不純物層の界面、透明導電膜と不純物層との界面などの、太陽電池セル内部の各界面特性が改善する効果と共に、不純物ドープ層の比抵抗が小さくなり、直列抵抗成分が抑えられて太陽電池の変換効率が向上する効果がある。   Along with the effect of improving each interface property inside the solar cell, such as the interface between the silicon substrate and the film, the interface between the intrinsic semiconductor layer and the impurity layer, the interface between the transparent conductive film and the impurity layer, by performing the heat treatment at a high temperature. The specific resistance of the impurity doped layer is reduced, the series resistance component is suppressed, and the conversion efficiency of the solar cell is improved.

特許文献４では、集電極形成後の熱処理の温度、時間を最適にすることにより太陽電池の特性が改善する方法が開示されている。特許文献５では、裏面電極と接する所定領域の不純物ドープ層とシリコン基板との間に、シリコン酸化膜を挟むことによって、熱処理で変質した不純物ドープ層がシリコン基板へ直接の影響を与えない方法が開示されている。   Patent Document 4 discloses a method of improving the characteristics of a solar cell by optimizing the temperature and time of heat treatment after the collector electrode is formed. In Patent Document 5, there is a method in which a silicon oxide film is sandwiched between an impurity doped layer in a predetermined region in contact with a back electrode and a silicon substrate so that the impurity doped layer altered by heat treatment does not directly affect the silicon substrate. It is disclosed.

特許第２１３２５２７号公報Japanese Patent No. 2132527 特許第２６１４５６１号公報Japanese Patent No. 2614561 特許第３４６９７２９号公報Japanese Patent No. 3469729 特開２００７−２９４８３０号公報JP 2007-294830 A 特開平９−９７９１６号公報JP-A-9-97916

結晶シリコン基板に薄い真性半導体層を介して不純物ドープシリコン層からなる接合或いはＢＳＦ層を形成するヘテロ接合太陽電池に関して、集電極形成後に一括して熱処理を行うと、結晶シリコンと真性半導体層の界面特性を改善する熱処理温度と、不純物ドープ層の耐熱温度が異なるため、一括熱処理では十分な太陽電池の特性が得られなかった。   With respect to a heterojunction solar cell in which a junction made of an impurity-doped silicon layer or a BSF layer is formed on a crystalline silicon substrate via a thin intrinsic semiconductor layer, when the heat treatment is performed after the collector electrode is formed, the interface between the crystalline silicon and the intrinsic semiconductor layer Since the heat treatment temperature for improving the characteristics is different from the heat resistance temperature of the impurity-doped layer, sufficient solar cell characteristics cannot be obtained by the collective heat treatment.

これは、結晶シリコンと真性半導体層の界面特性を改善する熱処理温度が、不純物ドープシリコン層の耐熱温度に比べて、高温側に存在するためと思われる。集電極形成後の一括した熱処理温度を、結晶シリコンと真性半導体層の界面特性を改善する熱処理温度に合わせると、不純物ドープシリコン層の耐熱温度に対しては高すぎる温度になるため、不純物ドープ層の膜質が劣化し、良好な太陽電池の特性を十分得ることができない。   This is probably because the heat treatment temperature for improving the interface characteristics between the crystalline silicon and the intrinsic semiconductor layer exists on the higher temperature side than the heat resistance temperature of the impurity-doped silicon layer. When the heat treatment temperature after forming the collector electrode is adjusted to the heat treatment temperature for improving the interface characteristics between the crystalline silicon and the intrinsic semiconductor layer, the temperature becomes too high for the heat resistance temperature of the impurity doped silicon layer. As a result, the quality of the solar cell is deteriorated and sufficient solar cell characteristics cannot be obtained.

また、熱処理温度を不純物ドープ層の耐熱温度に合わせると、結晶シリコンと真性半導体層の界面特性を改善する熱処理温度に対して、低すぎる温度になるため、結晶シリコン基板と真性半導体層の界面特性を十分に改善することができないという問題があった。   In addition, when the heat treatment temperature is adjusted to the heat resistance temperature of the impurity doped layer, the temperature is too low for the heat treatment temperature to improve the interface characteristics between the crystalline silicon and the intrinsic semiconductor layer, and thus the interface characteristics between the crystalline silicon substrate and the intrinsic semiconductor layer. There was a problem that could not be improved sufficiently.

また、集電極形成後に一括して熱処理を行うと、熱処理により真性半導体層から不純物ドープ層への水素の拡散、脱離が起こり、シリコン基板と真性半導体層の界面のパッシベーション効果が低下する問題があった。   Also, if heat treatment is performed collectively after the collector electrode is formed, hydrogen diffuses and desorbs from the intrinsic semiconductor layer to the impurity doped layer due to the heat treatment, and the passivation effect at the interface between the silicon substrate and the intrinsic semiconductor layer is reduced. there were.

さらに、真性半導体層は結晶シリコン基板へエピタキシャル成長し易いため、その後形成する不純物ドープ層もエピタキシャル成長し易く、この場合、粒界形成による欠陥が不純物ドープ層内に形成され、パッシベーション効果が低下する問題があった。   Further, since the intrinsic semiconductor layer is easily grown epitaxially on the crystalline silicon substrate, the impurity doped layer to be formed thereafter is also easily grown epitaxially. In this case, defects due to grain boundary formation are formed in the impurity doped layer, and the passivation effect is lowered. there were.

本発明は、上記に鑑みてなされたものであって、結晶シリコン基板と真性半導体層の界面特性を改善してキャリアの再結合を抑制することで良好な特性を持つ光起電力装置を形成でき、また、真性半導体層製膜が良好な界面特性を得ることができ、さらに、真性半導体層の後に形成する不純物ドープ層の粒界形成による欠陥の形成を防ぐことができる光起電力装置の製造方法を得ることを目的とする。   The present invention has been made in view of the above, and can improve the interface characteristics between a crystalline silicon substrate and an intrinsic semiconductor layer to suppress carrier recombination, thereby forming a photovoltaic device having good characteristics. In addition, it is possible to produce a photovoltaic device in which intrinsic semiconductor layer deposition can obtain good interface characteristics, and furthermore, formation of defects due to grain boundary formation of an impurity doped layer formed after the intrinsic semiconductor layer can be prevented. The purpose is to obtain a method.

上述した課題を解決し、目的を達成するために、本発明は、第１の導電型のシリコン半導体基板の受光面側に第１の導電型とは異なる第２の導電型の第１半導体層を形成する工程と、前記シリコン半導体基板の前記受光面と反対側の面に真性半導体層を形成する工程と、前記真性半導体層の形成後に第１熱処理を行う工程と、前記第１熱処理の後に、前記真性半導体層の前記反対側の面上に前記シリコン半導体基板より不純物濃度が高い第１の導電型の第２半導体層を形成する工程と、前記第２半導体層の形成後に第２熱処理を行う工程とを具備することを特徴とする。   In order to solve the above-described problems and achieve the object, the present invention provides a first semiconductor layer of a second conductivity type different from the first conductivity type on the light receiving surface side of the first conductivity type silicon semiconductor substrate. Forming an intrinsic semiconductor layer on a surface opposite to the light receiving surface of the silicon semiconductor substrate, performing a first heat treatment after the formation of the intrinsic semiconductor layer, and after the first heat treatment Forming a second semiconductor layer of a first conductivity type having an impurity concentration higher than that of the silicon semiconductor substrate on the opposite surface of the intrinsic semiconductor layer, and performing a second heat treatment after the formation of the second semiconductor layer. And performing the process.

本発明によれば、結晶シリコン基板と真性半導体層の界面特性が改善されてキャリアの再結合が抑制されることにより、良好な特性を持つ光起電力装置を形成することができるという効果を奏する。   According to the present invention, the interface characteristic between the crystalline silicon substrate and the intrinsic semiconductor layer is improved and the recombination of carriers is suppressed, so that it is possible to form a photovoltaic device having good characteristics. .

図１は、本発明の実施の形態１にかかる製造方法で形成した光起電力装置のセル構造を示す断面図である。FIG. 1 is a cross-sectional view showing a cell structure of a photovoltaic device formed by the manufacturing method according to the first embodiment of the present invention. 図２は、実施の形態１にかかる光起電力装置の製造方法のフローチャートを示す図である。FIG. 2 is a flowchart of the method for manufacturing the photovoltaic device according to the first embodiment. 図３は、実施の形態１の製造方法で形成した太陽電池と比較例の製造方法で形成した太陽電池と比較した図である。FIG. 3 is a diagram comparing the solar cell formed by the manufacturing method of Embodiment 1 and the solar cell formed by the manufacturing method of the comparative example.

以下に、本発明にかかる光起電力装置の製造方法の実施の形態を図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。   Embodiments of a method for manufacturing a photovoltaic device according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

実施の形態１．
図１は、本発明の実施の形態１にかかる製造方法で形成した光起電力装置のセル構造を示す断面図である。図２は、本実施の形態にかかる光起電力装置の製造方法のフローチャートである。以下に、本実施の形態にかかる光起電力装置の製造方法を図１及び図２を用いて説明する。 Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a cell structure of a photovoltaic device formed by the manufacturing method according to the first embodiment of the present invention. FIG. 2 is a flowchart of the method for manufacturing the photovoltaic device according to the present embodiment. Below, the manufacturing method of the photovoltaic apparatus concerning this Embodiment is demonstrated using FIG.1 and FIG.2.

まず、1Ωcmのｐ型単結晶シリコンを基板（第１の導電型のシリコン半導体基板）１とし、アルカリ溶液中でスライス時のワイヤーソーダメージを除去し、続けてアルカリ溶液による異方性エッチングによりテクスチャーを形成した（図２のステップＳ１００、図１に示さず）。   First, 1Ωcm p-type single crystal silicon is used as the substrate (first conductive silicon semiconductor substrate) 1 to remove wire saw damage at the time of slicing in an alkaline solution, and then textured by anisotropic etching with an alkaline solution. (Step S100 in FIG. 2, not shown in FIG. 1).

その後、ＰＯＣｌ３ガス雰囲気下で熱処理することにより基板１と逆導電型であるｎ型の接合層（第１半導体層）としてリン拡散層（第２の導電型の不純物ドープ層）２を形成し（ステップＳ１０１）、表面に形成されたリンガラスを除去した。 Thereafter, a phosphorus diffusion layer (second conductivity type impurity doped layer) 2 is formed as an n-type bonding layer (first semiconductor layer) having a conductivity type opposite to that of the substrate 1 by heat treatment in a POCl 3 gas atmosphere. (Step S101), the phosphorus glass formed on the surface was removed.

さらに受光面側に反射防止膜としてシランとアンモニアを原料とするプラズマＣＶＤでＳｉＮ反射防止膜３を形成した。その後受光面側のＳｉＮ反射防止膜３を保護し、リン拡散層２をもつシリコン基板１の裏面（ｎ型拡散層）を５μｍ程度フッ硝酸により除去した（ステップＳ１０２）。   Further, an SiN antireflection film 3 was formed on the light receiving surface side by plasma CVD using silane and ammonia as raw materials as an antireflection film. Thereafter, the SiN antireflection film 3 on the light-receiving surface side was protected, and the back surface (n-type diffusion layer) of the silicon substrate 1 having the phosphorous diffusion layer 2 was removed by about 5 μm with hydrofluoric acid (step S102).

そして受光面側ＳｉＮ反射防止膜３上にＡｇの電極ペーストを用いたスクリーン印刷によりくし型電極４を形成し、約８００℃で焼成することにより表面電極４を形成した（ステップＳ１０３）。   Then, the comb-shaped electrode 4 was formed on the light-receiving surface side SiN antireflection film 3 by screen printing using an Ag electrode paste, and the surface electrode 4 was formed by baking at about 800 ° C. (step S103).

その後、シリコン基板１の裏面をＲＣＡ洗浄によりクリーニングする（ステップＳ１０４）とともに、希フッ酸での酸化膜除去を施し、２７．５６ＭＨｚのＶＨＦプラズマＣＶＤチャンバで約４ｎｍの真性半導体層となるｉ型非晶質シリコン膜５を形成した（ステップＳ１０５）。   Thereafter, the back surface of the silicon substrate 1 is cleaned by RCA cleaning (step S104), and the oxide film is removed with dilute hydrofluoric acid to form an intrinsic semiconductor layer of about 4 nm in a 27.56 MHz VHF plasma CVD chamber. A crystalline silicon film 5 was formed (step S105).

ｉ型非晶質シリコン膜５はＲＦ出力５０ｍＷ／ｃｍ２、基板温度２００℃、ガス圧５００Ｐａの雰囲気下で、シラン３０ｓｃｃｍ、および水素５００ｓｃｃｍを流して成膜を行なった。 The i-type amorphous silicon film 5 was formed by flowing silane at 30 sccm and hydrogen at 500 sccm in an atmosphere with an RF output of 50 mW / cm 2 , a substrate temperature of 200 ° C., and a gas pressure of 500 Pa.

その後、酸素を含んだガス雰囲気(酸素２０％)中で２００℃５分間の熱処理（第１前半熱処理）を行った（ステップＳ１０６）後、フォーミングガス(水素５％含有の不活性ガス雰囲気)中で３８５℃１０分間の熱処理（第１後半熱処理）を行った（ステップＳ１０７）。第１前半熱処理（ステップＳ１０６）と第１後半熱処理（ステップＳ１０７）とを合わせて第１熱処理とする。   Thereafter, heat treatment (first first half heat treatment) at 200 ° C. for 5 minutes was performed in a gas atmosphere containing oxygen (oxygen 20%) (step S106), and then in forming gas (inert gas atmosphere containing 5% hydrogen) Then, a heat treatment (first second heat treatment) at 385 ° C. for 10 minutes was performed (step S107). The first first half heat treatment (step S106) and the first second half heat treatment (step S107) are combined to form a first heat treatment.

その後、ｉ型非晶質シリコン膜５の上に（基板１の裏面方向に）、２７．５６ＭＨｚのプラズマＣＶＤチャンバで約１００ｎｍのｐ型微結晶シリコン膜（第１の導電型の高濃度不純物ドープ層）６を形成した（ステップＳ１０８）。   Thereafter, on the i-type amorphous silicon film 5 (in the direction of the back surface of the substrate 1), a p-type microcrystalline silicon film (first conductivity type high-concentration impurity doping) of about 100 nm in a 27.56 MHz plasma CVD chamber. Layer) 6 was formed (step S108).

成膜条件は基板温度１４０℃、ガス圧５００Paの雰囲気下で、１００ｍＷ／ｃｍ２、シラン１０ｓｃｃｍ、水素１０００ｓｃｃｍ、０．１％に水素希釈したジボラン２０ｓｃｃｍとした。ここで形成されたｐ型微結晶シリコン膜（第２半導体層）６の不純物濃度は、シリコン半導体基板１より高くなっている。 Deposition conditions were 100 mW / cm 2 , 10 sccm of silane, 1000 sccm of hydrogen, and 20 sccm of diborane diluted to 0.1% with hydrogen in an atmosphere of a substrate temperature of 140 ° C. and a gas pressure of 500 Pa. The impurity concentration of the p-type microcrystalline silicon film (second semiconductor layer) 6 formed here is higher than that of the silicon semiconductor substrate 1.

その後、フォーミングガス(水素５％含有の不活性ガス雰囲気)中で３２５℃１０分間の熱処理（第２熱処理）を行った（ステップＳ１０９）。第２熱処理（ステップＳ１０９）は、第１熱処理とは異なる温度で行う。即ち、第１熱処理の後半である第１後半熱処理（ステップＳ１０７）の温度は、第２熱処理の最高温度である３２５℃より高い温度になっている。   Thereafter, a heat treatment (second heat treatment) was performed at 325 ° C. for 10 minutes in a forming gas (inert gas atmosphere containing 5% hydrogen) (step S109). The second heat treatment (step S109) is performed at a temperature different from that of the first heat treatment. That is, the temperature of the first second heat treatment (step S107), which is the latter half of the first heat treatment, is higher than the maximum temperature of 325 ° C. of the second heat treatment.

その後、真空蒸着により裏面にＡｌ電極（非受光面側電極）７を形成し（ステップＳ１１０）、フォーミングガス（水素５％含有の不活性ガス雰囲気）中で２００℃３０分間の熱処理を行なった（ステップＳ１１１）。   Thereafter, an Al electrode (non-light-receiving surface side electrode) 7 was formed on the back surface by vacuum deposition (Step S110), and heat treatment was performed at 200 ° C. for 30 minutes in a forming gas (inert gas atmosphere containing 5% hydrogen) ( Step S111).

比較のため、上記プロセスにて作製した太陽電池と同じ結晶、同じ特性をもつ基板を用いて、ｉ型非晶質シリコン膜形成後の酸素を含んだガス雰囲気中での熱処理（ステップＳ１０６）の有無、及びｉ型非晶質酸化シリコン膜形成後のフォーミングガス中での熱処理（ステップＳ１０７）の有無を変え、それ以外はすべて同じプロセスによって太陽電池を作製した。   For comparison, heat treatment (step S106) in a gas atmosphere containing oxygen after forming the i-type amorphous silicon film using a substrate having the same crystal and the same characteristics as the solar cell manufactured by the above process. The solar cells were fabricated by the same process except for the presence or absence and the presence or absence of the heat treatment (Step S107) in the forming gas after forming the i-type amorphous silicon oxide film.

それらを、図３に示すように比較例１、２として本実施の形態によるプロセスで作成した太陽電池と共に、ＡＭ１．５のソーラーシミュレータにて電流−電圧特性を評価した。   As shown in FIG. 3, the current-voltage characteristics were evaluated by a solar simulator of AM1.5 together with the solar cells produced by the process according to the present embodiment as Comparative Examples 1 and 2.

その結果、ｉ型非晶質シリコン膜形成後に酸素を含んだガス雰囲気で熱処理（ステップＳ１０６）したのち、フォーミングガス中で熱処理（ステップＳ１０７）を施した本実施の形態のサンプルにおいて、標準プロセスである比較例１のサンプルより約４ｍＶ高い開放電圧を得ることができた。   As a result, in the sample of this embodiment, after the heat treatment (step S106) in the gas atmosphere containing oxygen after the i-type amorphous silicon film is formed, the sample of this embodiment is subjected to the heat treatment (step S107) in the forming gas. An open circuit voltage about 4 mV higher than that of a sample of Comparative Example 1 could be obtained.

本実施の形態においては、ｉ型非晶質シリコン膜形成（ステップＳ１０５）後にｐ型微結晶シリコン膜形成（ステップＳ１０８）後の熱処理温度の最高温度より高い温度で熱処理することにより、シリコン基板とｉ型非晶質シリコン膜との界面特性の改善が可能となった。   In the present embodiment, after the formation of the i-type amorphous silicon film (step S105), heat treatment is performed at a temperature higher than the maximum heat treatment temperature after the formation of the p-type microcrystalline silicon film (step S108). The interface characteristics with the i-type amorphous silicon film can be improved.

すなわち、ｐ型微結晶膜形成後に界面特性改善を狙った熱処理を一括して行う従来技術の場合、ｐ型微結晶膜の耐熱温度が真性半導体層／基板の界面特性を改善する最適温度より低いため、ｐ型微結晶膜の耐熱温度に合わせる必要がある。その場合、真性半導体層と基板界面のパッシベーション効果が十分得られなかった。   That is, in the case of the conventional technique in which heat treatment aiming at improving the interface characteristics is performed after forming the p-type microcrystalline film, the heat resistance temperature of the p-type microcrystalline film is lower than the optimum temperature for improving the interface characteristics of the intrinsic semiconductor layer / substrate. Therefore, it is necessary to match the heat resistance temperature of the p-type microcrystalline film. In that case, a sufficient passivation effect between the intrinsic semiconductor layer and the substrate interface could not be obtained.

本実施の形態においては、真性半導体層の製膜後とｐ型微結晶膜の製膜後とで、それぞれ異なる最適な温度で熱処理をすることにより、パッシベーション効果を高めることが可能となる。   In this embodiment, the passivation effect can be enhanced by performing heat treatment at different optimum temperatures after the intrinsic semiconductor layer is formed and after the p-type microcrystalline film is formed.

さらにｉ型非晶質シリコン膜５形成後に酸素を含んだガス雰囲気で熱処理（ステップＳ１０６）することによって、ｉ型非晶質シリコン膜５の最表面に酸化層が形成され、そのあとのより高温な熱処理によるｉ型非晶質シリコン膜中からの水素の脱理を抑制するキャップ層として機能する。   Further, by performing heat treatment in a gas atmosphere containing oxygen after forming the i-type amorphous silicon film 5 (step S106), an oxide layer is formed on the outermost surface of the i-type amorphous silicon film 5, and a higher temperature thereafter. It functions as a cap layer that suppresses hydrogen from being removed from the i-type amorphous silicon film by an appropriate heat treatment.

このため、シリコン基板１とｉ型非晶質シリコン膜５の界面を良好に保つことが可能となる。即ち、界面パッシベーション効果を十分得ることができ太陽電池特性を向上させる。   For this reason, the interface between the silicon substrate 1 and the i-type amorphous silicon film 5 can be kept good. That is, a sufficient interface passivation effect can be obtained and the solar cell characteristics are improved.

また、ｉ型非晶質シリコン膜５がシリコン基板１に対してエピタキシャル成長している場合でも、酸化層の存在により、その後形成されるｐ型微結晶シリコン膜６のエピタキシャル成長が抑制されるため、膜中に粒界や転位のない品質の良好なｐ型微結晶シリコン膜６の形成が可能となる。   Even when the i-type amorphous silicon film 5 is epitaxially grown on the silicon substrate 1, the presence of the oxide layer suppresses the epitaxial growth of the p-type microcrystalline silicon film 6 to be formed thereafter. It is possible to form a p-type microcrystalline silicon film 6 having good quality without grain boundaries or dislocations.

本実施の形態では、単結晶基板を用いたが、多結晶基板を用いてもよい。また、本実施の形態では酸素を含まない半導体層を用いたが、酸素、窒素、或いは炭素を含む半導体層を用いてもよい。ｉ型非晶質シリコン膜５の場合、酸素が含まれることにより結晶シリコン基板１に対してエピタキシャル成長が抑制され、良好な界面特性が得られる。   Although a single crystal substrate is used in this embodiment mode, a polycrystalline substrate may be used. Further, although a semiconductor layer not containing oxygen is used in this embodiment mode, a semiconductor layer containing oxygen, nitrogen, or carbon may be used. In the case of the i-type amorphous silicon film 5, by containing oxygen, epitaxial growth is suppressed with respect to the crystalline silicon substrate 1, and good interface characteristics are obtained.

また、本実施の形態においては、フォーミンガス(水素５％含有の不活性ガス)を用いたが、酸素、窒素、アルゴン等を含んだ雰囲気ガスを用いてもよい。ただ、水素を含んだガスは、結晶シリコン基板１とｉ型非晶質シリコン膜５との界面を水素終端することによりパッシベーション効果を高め、また、膜中の欠陥も水素により修復されるため、水素を含んだガスを用いるのが望ましい。   In this embodiment, foaming gas (inert gas containing 5% hydrogen) is used, but atmospheric gas containing oxygen, nitrogen, argon, or the like may be used. However, since the gas containing hydrogen enhances the passivation effect by terminating the interface between the crystalline silicon substrate 1 and the i-type amorphous silicon film 5 with hydrogen, and defects in the film are also repaired by hydrogen. It is desirable to use a gas containing hydrogen.

また、酸素を含む雰囲気での熱処理（ステップＳ１０６）において、酸素濃度が５％より低いと、酸化層の形成が不十分で水素脱理を抑制するキャップ層としての機能が十分得られず、さらにｐ型微結晶層６のエピタキシャル成長を抑制できない。   In addition, in the heat treatment in an atmosphere containing oxygen (step S106), if the oxygen concentration is lower than 5%, the formation of an oxide layer is insufficient and a function as a cap layer for suppressing hydrogen removal cannot be obtained sufficiently. The epitaxial growth of the p-type microcrystalline layer 6 cannot be suppressed.

逆に、酸素濃度が５０％より高いと、ｉ型非晶質シリコン膜５の全体が酸化されるため、導電性が低くなるため直列抵抗が高くなってしまう。従って、上述した効果を適切に得るためには、ステップＳ１０６における酸素濃度は５〜５０％程度であることが望ましい。   On the contrary, if the oxygen concentration is higher than 50%, the entire i-type amorphous silicon film 5 is oxidized, so that the conductivity becomes low and the series resistance becomes high. Therefore, in order to appropriately obtain the above-described effect, it is desirable that the oxygen concentration in step S106 is about 5 to 50%.

一導電型の結晶シリコンを基板とし、光受光面側に真性半導体層、基板と逆の導電型の不純物ドープシリコン層、透明導電膜、集電極をもつか、或いは光受光面と反対側の基板表面に真性半導体層、基板と同じ導電型の不純物ドープシリコン層、透明導電膜、裏面電極をもつか、或いはその両方の構造をもつ光起電力装置においても、上記と同様な工程が実施可能である。   Crystal substrate of one conductivity type is used as substrate, intrinsic light semiconductor layer on the light receiving surface side, impurity doped silicon layer of opposite conductivity type to substrate, transparent conductive film, collector electrode, or substrate opposite to light receiving surface The same process as above can be carried out in a photovoltaic device having an intrinsic semiconductor layer on the surface, an impurity-doped silicon layer of the same conductivity type as the substrate, a transparent conductive film, a back electrode, or both structures. is there.

すなわち、真性半導体層形成後、不純物ドープシリコン層形成後のそれぞれにおいて、最適な異なる温度で熱処理を行うと同時に、真性半導体層形成後の熱処理においては、最初に酸素を含んだ雰囲気で熱処理をおこなえば、同様な効果が得られる。   That is, after the formation of the intrinsic semiconductor layer and after the formation of the impurity-doped silicon layer, the heat treatment is performed at different optimum temperatures. At the same time, the heat treatment after the formation of the intrinsic semiconductor layer can be performed in an atmosphere containing oxygen first. The same effect can be obtained.

本実施の形態によれば、真性半導体層製膜後、不純物ドープ層製膜後のそれぞれにおいて、最適な異なる温度で熱処理を行うことにより、結晶シリコン基板と真性半導体層の界面特性が改善され、キャリアの再結合が抑制されることにより良好な特性を持つ光起電力装置を形成することができる。   According to the present embodiment, the interface characteristics between the crystalline silicon substrate and the intrinsic semiconductor layer are improved by performing the heat treatment at an optimum different temperature after the intrinsic semiconductor layer deposition and after the impurity doped layer deposition, By suppressing recombination of carriers, a photovoltaic device having good characteristics can be formed.

また、真性半導体層製膜後の熱処理において、最初に酸素を含んだ雰囲気で熱処理を行うことにより、真性半導体層の表面に酸化層が形成されるので、その後の熱処理による水素の膜からの脱離を防ぐキャップ層として機能し良好な界面特性を得ることができる。   In addition, in the heat treatment after the formation of the intrinsic semiconductor layer, an oxide layer is formed on the surface of the intrinsic semiconductor layer by first performing the heat treatment in an atmosphere containing oxygen, so that the hydrogen is removed from the film by the subsequent heat treatment. It functions as a cap layer that prevents separation, and good interface characteristics can be obtained.

さらに、真性半導体層が結晶シリコン基板に対してエピタキシャル成長した場合においても、その後形成する不純物ドープ層は、真性半導体層表面の酸化層によって、真性半導体層へのエピタキシャル成長が抑制され、粒界形成による欠陥の形成を防ぐことができる。   Furthermore, even when the intrinsic semiconductor layer is epitaxially grown on the crystalline silicon substrate, the impurity doped layer to be formed thereafter is suppressed by the oxide layer on the surface of the intrinsic semiconductor layer, so that the epitaxial growth on the intrinsic semiconductor layer is suppressed, and defects due to grain boundary formation occur. Can be prevented.

さらに、本願発明は上記実施の形態に限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で種々に変形することが可能である。また、上記実施の形態には種々の段階の発明が含まれており、開示される複数の構成要件における適宜な組み合わせにより種々の発明が抽出されうる。例えば、実施の形態に示される全構成要件からいくつかの構成要件が削除されても、発明が解決しようとする課題の欄で述べた課題が解決でき、発明の効果の欄で述べられている効果が得られる場合には、この構成要件が削除された構成が発明として抽出されうる。更に、異なる実施の形態にわたる構成要素を適宜組み合わせてもよい。   Furthermore, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent requirements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. When an effect is obtained, a configuration from which this configuration requirement is deleted can be extracted as an invention. Furthermore, the constituent elements over different embodiments may be appropriately combined.

以上のように、本発明にかかる光起電力装置の製造方法は、光起電力素子の製造に有用であり、特に、太陽電池の製造に適している。   As described above, the method for manufacturing a photovoltaic device according to the present invention is useful for manufacturing a photovoltaic device, and is particularly suitable for manufacturing a solar cell.

１ 第１の導電型のシリコン半導体基板
２ 第２の導電型の不純物ドープ層
３ ＳｉＮ反射防止膜
４ 受光面側くし型Ａｇ電極
５ ｉ型アモルファスシリコン層
６ 第１の導電型の高濃度不純物ドープ層
７ 非受光面側電極 DESCRIPTION OF SYMBOLS 1 1st conductivity type silicon semiconductor substrate 2 2nd conductivity type impurity doped layer 3 SiN antireflection film 4 Light-receiving surface side comb-type Ag electrode 5 i-type amorphous silicon layer 6 High concentration impurity doping of 1st conductivity type Layer 7 Non-light-receiving surface side electrode

Claims (6)

第１の導電型のシリコン半導体基板の受光面側に第１の導電型とは異なる第２の導電型の第１半導体層を形成する工程と、
前記シリコン半導体基板の前記受光面と反対側の面に真性半導体層を形成する工程と、
前記真性半導体層の形成後に第１熱処理を行う工程と、
前記第１熱処理の後に、前記真性半導体層の前記反対側の面上に前記シリコン半導体基板より不純物濃度が高い第１の導電型の第２半導体層を形成する工程と、
前記第２半導体層の形成後に第２熱処理を行う工程とを具備する
ことを特徴とする光起電力装置の製造方法。 Forming a first semiconductor layer of a second conductivity type different from the first conductivity type on the light-receiving surface side of the silicon semiconductor substrate of the first conductivity type;
Forming an intrinsic semiconductor layer on a surface opposite to the light receiving surface of the silicon semiconductor substrate;
Performing a first heat treatment after forming the intrinsic semiconductor layer;
Forming a second semiconductor layer of a first conductivity type having an impurity concentration higher than that of the silicon semiconductor substrate on the opposite surface of the intrinsic semiconductor layer after the first heat treatment;
And a step of performing a second heat treatment after the formation of the second semiconductor layer. A method for manufacturing a photovoltaic device, comprising: 前記第１熱処理の温度が、前記第２熱処理の最高温度よりも高くなる
ことを特徴とする請求項１に記載の光起電力装置の製造方法。 The method for manufacturing a photovoltaic device according to claim 1, wherein a temperature of the first heat treatment is higher than a maximum temperature of the second heat treatment. 前記第１熱処理を行う工程は、第１前半熱処理を行う工程とそれに引き続く第１後半熱処理を行う工程を含み、
前記第１前半熱処理は、酸素を含む雰囲気で行われる
ことを特徴とする、請求項１または２に記載の光起電力装置の製造方法。 The step of performing the first heat treatment includes a step of performing a first first half heat treatment and a step of performing a first second half heat treatment subsequent thereto,
The method for manufacturing a photovoltaic device according to claim 1, wherein the first first-half heat treatment is performed in an atmosphere containing oxygen. 前記第１後半熱処理の温度が、前記第２熱処理の最高温度よりも高くなる
ことを特徴とする請求項３に記載の光起電力装置の製造方法。 The method for manufacturing a photovoltaic device according to claim 3, wherein a temperature of the first second heat treatment is higher than a maximum temperature of the second heat treatment. 前記酸素を含む雰囲気の酸素濃度が、５〜５０％である
ことを特徴とする請求項３または４に記載の光起電力装置の製造方法。 The method for producing a photovoltaic device according to claim 3 or 4, wherein the oxygen concentration in the atmosphere containing oxygen is 5 to 50%. 前記第１後半熱処理と前記第２熱処理は、水素、酸素、窒素のいずれかを含む雰囲気であることを特徴とする、請求項３〜５のいずれか１つに記載の光起電力装置の製造方法。   The photovoltaic device according to any one of claims 3 to 5, wherein the first second heat treatment and the second heat treatment are an atmosphere containing any of hydrogen, oxygen, and nitrogen. Method.
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