JP2011114057A - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 42
- 230000000903 blocking effect Effects 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 88
- 229920005591 polysilicon Polymers 0.000 claims description 86
- 230000006870 function Effects 0.000 claims description 76
- 239000007769 metal material Substances 0.000 claims description 46
- 230000014759 maintenance of location Effects 0.000 abstract description 33
- 230000005641 tunneling Effects 0.000 abstract description 11
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
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- 230000008901 benefit Effects 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 230000008878 coupling Effects 0.000 description 8
- 238000010168 coupling process Methods 0.000 description 8
- 238000005859 coupling reaction Methods 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 5
- 101000648265 Homo sapiens Thymocyte selection-associated high mobility group box protein TOX Proteins 0.000 description 4
- 102100028788 Thymocyte selection-associated high mobility group box protein TOX Human genes 0.000 description 4
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- 229910005883 NiSi Inorganic materials 0.000 description 2
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- 238000000151 deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
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- 239000012528 membrane Substances 0.000 description 2
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- 101000679555 Homo sapiens TOX high mobility group box family member 2 Proteins 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
【解決手段】半導体記憶装置は、基板101と、基板上に形成され、FNトンネル膜として機能する第1のゲート絶縁膜111と、第1のゲート絶縁膜上に形成された第1の浮遊ゲート112と、第1の浮遊ゲート上に形成され、FNトンネル膜として機能する第2のゲート絶縁膜113と、第2のゲート絶縁膜上に形成された第2の浮遊ゲート114と、第2の浮遊ゲート上に形成されており、電荷ブロック膜として機能するゲート間絶縁膜115と、ゲート間絶縁膜上に形成された制御ゲート116とを備え、第1及び第2の浮遊ゲートの少なくともいずれかは、メタル層を含んでいる。
【選択図】図2
Description
図1は、第1実施形態の半導体記憶装置の構成を概略的に示す平面図である。図1の半導体記憶装置は、NAND型フラッシュメモリとなっている。
第2実施形態については、第1実施形態と同様、図2を参照して説明する。
第3実施形態については、第1及び第2実施形態と同様、図2を参照して説明する。
図8は、第4実施形態の半導体記憶装置の構成を示す側方断面図である。
第5実施形態については、図2を参照して説明する。
第6実施形態については、図2を参照して説明する。
第7実施形態については、図2を参照して説明する。
図2を参照して、第8実施形態の第1から第3の例について説明する。
111 第1のトンネル絶縁膜
112 第1の浮遊ゲート
113 第2のトンネル絶縁膜
114 第2の浮遊ゲート
115 IPD膜
116 制御ゲート
121 素子分離絶縁膜
122 層間絶縁膜
131 ソースドレイン拡散層
211 第1絶縁膜
212 第1電極層
213 第2絶縁膜
214 第2電極層
215 第3絶縁膜
216 第3電極層
301 第1のマスク層
302 第2のマスク層
Claims (5)
- 基板と、
前記基板上に形成され、FN(Fowler-Nordheim)トンネル膜として機能する第1のゲート絶縁膜と、
前記第1のゲート絶縁膜上に形成された第1の浮遊ゲートと、
前記第1の浮遊ゲート上に形成され、FNトンネル膜として機能する第2のゲート絶縁膜と、
前記第2のゲート絶縁膜上に形成された第2の浮遊ゲートと、
前記第2の浮遊ゲート上に形成されており、電荷ブロック膜として機能するゲート間絶縁膜と、
前記ゲート間絶縁膜上に形成された制御ゲートとを備え、
前記第1及び第2の浮遊ゲートの少なくともいずれかは、メタル層を含んでいることを特徴とする半導体記憶装置。 - 前記第1の浮遊ゲートは、メタル材料で形成されており、前記第2の浮遊ゲートは、ポリシリコンで形成されていることを特徴とする請求項1に記載の半導体記憶装置。
- 前記第1の浮遊ゲートは、ポリシリコンで形成されており、前記第2の浮遊ゲートは、メタル材料で形成されていることを特徴とする請求項1に記載の半導体記憶装置。
- 前記第1の浮遊ゲートは、複数の層を含んでおり、
前記第1の浮遊ゲートの最上位層は、メタル材料で形成されていることを特徴とする請求項1に記載の半導体記憶装置。 - 前記第2の浮遊ゲートは、複数の層を含んでおり、
前記第2の浮遊ゲートの最下位層は、メタル材料で形成されていることを特徴とする請求項1に記載の半導体記憶装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009267236A JP5537130B2 (ja) | 2009-11-25 | 2009-11-25 | 半導体記憶装置 |
US12/719,193 US8354706B2 (en) | 2009-11-25 | 2010-03-08 | Semiconductor memory device |
KR1020100024200A KR20110058631A (ko) | 2009-11-25 | 2010-03-18 | 반도체 메모리 장치 |
Applications Claiming Priority (1)
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JP2009267236A JP5537130B2 (ja) | 2009-11-25 | 2009-11-25 | 半導体記憶装置 |
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JP2011114057A true JP2011114057A (ja) | 2011-06-09 |
JP5537130B2 JP5537130B2 (ja) | 2014-07-02 |
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JP2009267236A Expired - Fee Related JP5537130B2 (ja) | 2009-11-25 | 2009-11-25 | 半導体記憶装置 |
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US (1) | US8354706B2 (ja) |
JP (1) | JP5537130B2 (ja) |
KR (1) | KR20110058631A (ja) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013201254A (ja) * | 2012-03-23 | 2013-10-03 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2014036048A (ja) * | 2012-08-07 | 2014-02-24 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
JP2014063883A (ja) * | 2012-09-21 | 2014-04-10 | Toshiba Corp | 半導体記憶装置 |
US8803219B2 (en) | 2012-06-20 | 2014-08-12 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of manufacturing |
US9029933B2 (en) | 2012-09-11 | 2015-05-12 | Kabushiki Kaisha Toshiba | Non-volatile memory device and method for manufacturing same |
US9379200B2 (en) | 2013-12-13 | 2016-06-28 | Kabushiki Kaisha Toshiba | Memory with a silicide charge trapping layer |
WO2016139725A1 (ja) * | 2015-03-02 | 2016-09-09 | 株式会社 東芝 | 半導体記憶装置及びその製造方法 |
US10910401B2 (en) | 2019-03-15 | 2021-02-02 | Toshiba Memory Corporation | Semiconductor device and method of manufacturing the same |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5039116B2 (ja) * | 2009-11-24 | 2012-10-03 | 株式会社東芝 | 半導体記憶装置 |
US8575678B2 (en) * | 2011-01-13 | 2013-11-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor memory device with floating gate |
US9001564B2 (en) | 2011-06-29 | 2015-04-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and a method for driving the same |
JP2014049731A (ja) * | 2012-09-04 | 2014-03-17 | Toshiba Corp | 半導体装置 |
US9123822B2 (en) * | 2013-08-02 | 2015-09-01 | Silicon Storage Technology, Inc. | Split gate non-volatile flash memory cell having a silicon-metal floating gate and method of making same |
US9768270B2 (en) * | 2014-06-25 | 2017-09-19 | Sandisk Technologies Llc | Method of selectively depositing floating gate material in a memory device |
CN105514105B (zh) | 2014-09-26 | 2019-08-06 | 联华电子股份有限公司 | 集成电路与其形成方法 |
US11133226B2 (en) | 2018-10-22 | 2021-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | FUSI gated device formation |
CN110634875A (zh) * | 2019-09-24 | 2019-12-31 | 上海华力微电子有限公司 | 一种存储单元、nand闪存架构及其形成方法 |
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JP2013201254A (ja) * | 2012-03-23 | 2013-10-03 | Toshiba Corp | 半導体装置及びその製造方法 |
US8803219B2 (en) | 2012-06-20 | 2014-08-12 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of manufacturing |
JP2014036048A (ja) * | 2012-08-07 | 2014-02-24 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
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US9379200B2 (en) | 2013-12-13 | 2016-06-28 | Kabushiki Kaisha Toshiba | Memory with a silicide charge trapping layer |
WO2016139725A1 (ja) * | 2015-03-02 | 2016-09-09 | 株式会社 東芝 | 半導体記憶装置及びその製造方法 |
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US11785774B2 (en) | 2019-03-15 | 2023-10-10 | Kioxia Corporation | Semiconductor device and method of manufacturing the same |
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Publication number | Publication date |
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US20110121381A1 (en) | 2011-05-26 |
US8354706B2 (en) | 2013-01-15 |
KR20110058631A (ko) | 2011-06-01 |
JP5537130B2 (ja) | 2014-07-02 |
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