JP2011077468A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

Info

Publication number
JP2011077468A
JP2011077468A JP2009230215A JP2009230215A JP2011077468A JP 2011077468 A JP2011077468 A JP 2011077468A JP 2009230215 A JP2009230215 A JP 2009230215A JP 2009230215 A JP2009230215 A JP 2009230215A JP 2011077468 A JP2011077468 A JP 2011077468A
Authority
JP
Japan
Prior art keywords
insulating film
film
semiconductor device
opening
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2009230215A
Other languages
Japanese (ja)
Inventor
Nobuyoshi Kosaka
宜吉 小坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Priority to JP2009230215A priority Critical patent/JP2011077468A/en
Priority to PCT/JP2010/001165 priority patent/WO2011039898A1/en
Publication of JP2011077468A publication Critical patent/JP2011077468A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a void from forming in a connection plug when forming embedded wiring of copper and the connection plug, using a dual-damascene method. <P>SOLUTION: After a connection hole 19a which serves as a plug is formed in an interlayer insulating film comprising Low-k films 13, 15, an ELK film 14, and a TEOS film 16, an altered layer 20 is formed through oxygen plasma processing, and selectively removed through chemical processing to taper a side wall 21 of the ELK film 14 at an angle larger than those of the Low-k films 13, 15, etc., caused by the ELK film being porous. Then a groove for wiring burying is formed to have its bottom surface inside the ELK film 14; and after an entrance of a plug opening is widened, a copper film is embedded. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、特にデュアルダマシン法を用いる半導体装置の配線形成工程において、配線に電気的接続するためのアスペクト比の高い接続孔へ金属などの導電性材料を良好に埋め込むことができる製造方法に関するものである。   The present invention relates to a manufacturing method capable of satisfactorily embedding a conductive material such as a metal in a connection hole having a high aspect ratio for electrical connection to a wiring, particularly in a wiring formation process of a semiconductor device using a dual damascene method. It is.

半導体集積回路装置の高集積化に際し、半導体素子パターンの微細加工精度に対する要求はますます厳しいものとなってきている。特に多層配線の採用が進み、８層ないし９層の配線構造がとられている近年のシステムＬＳＩなどのデバイスにおいては、デュアルダマシン（Ｄｕａｌ Ｄａｍａｓｃｅｎｅ）法をはじめとした、絶縁膜の溝に配線を埋め込む埋め込み配線技術が採用されている。デュアルダマシン法とは上層と下層の配線層間を電気的に結ぶための接続孔と配線を埋め込む配線溝とを層間絶縁膜に形成した後、これら双方に同時に配線材料を埋め込み、ＣＭＰ（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ）法で接続孔および配線溝の外側に存在する余分な配線材料を削り、表面が平坦化された配線および配線接続用プラグを同時に形成する技術である。このデュアルダマシン配線技術によると、配線とプラグとを１回の工程で形成することができるので、大幅なプロセスコストの低減を図ることができる。   With the high integration of semiconductor integrated circuit devices, the demand for fine processing accuracy of semiconductor element patterns has become increasingly severe. In recent years, devices such as dual damascene (Dual Damascene) method are used for wiring in insulating films in devices such as system LSIs in recent years, where the adoption of multilayer wiring has progressed and 8-layer to 9-layer wiring structures have been adopted. An embedded wiring technique is employed. In the dual damascene method, a connection hole for electrically connecting the upper and lower wiring layers and a wiring groove for embedding the wiring are formed in the interlayer insulating film, and then a wiring material is simultaneously buried in both of them, and CMP (Chemical Mechanical Polishing) is performed. In this technique, excess wiring material existing outside the connection hole and the wiring groove is shaved by the method, and the wiring having a flat surface and the wiring connection plug are simultaneously formed. According to this dual damascene wiring technique, the wiring and the plug can be formed in a single process, so that the process cost can be greatly reduced.

図７〜図１０は従来のデュアルダマシン法による配線構造の製造方法を工程順に示す断面図である。製造方法を説明すると、まず図７（ａ）に示すように、半導体基板（図示省略）上に層間絶縁膜３０、層間絶縁膜３０に被覆された各種半導体素子（図示省略）、および層間絶縁膜３０に埋め込まれた下層配線３１を形成する。次に層間絶縁膜３０上にシリコン窒化膜（ＳｉＮ膜）からなるエッチングストッパー膜３２を形成し、その上に低誘電率の層間絶縁膜（ＳｉＯＣ膜）３３、シリコン酸化膜であるＴＥＯＳ膜３４を形成する。ＴＥＯＳ膜３４は、ＴＥＯＳを原材料ガスとしてＣＶＤ法で堆積される膜であり、後の工程で形成され、配線構造の一部となるバリアメタル膜から層間絶縁膜３３への汚染を防ぐためのキャップ絶縁膜として作用する。次にＴＥＯＳ膜３４上に一般にＢＡＲＣ膜と呼ばれる反射防止膜３５を塗布し、その上にリソグラフィ技術により接続孔パターンを開口したレジスト膜３６を形成する。   7 to 10 are sectional views showing a method of manufacturing a wiring structure by a conventional dual damascene method in the order of steps. The manufacturing method will be described. First, as shown in FIG. 7A, an interlayer insulating film 30, various semiconductor elements (not shown) covered with the interlayer insulating film 30, and an interlayer insulating film are formed on a semiconductor substrate (not shown). A lower layer wiring 31 embedded in 30 is formed. Next, an etching stopper film 32 made of a silicon nitride film (SiN film) is formed on the interlayer insulating film 30, and a low dielectric constant interlayer insulating film (SiOC film) 33 and a TEOS film 34 which is a silicon oxide film are formed thereon. Form. The TEOS film 34 is a film deposited by a CVD method using TEOS as a raw material gas, and is a cap that is formed in a later process and prevents contamination from the barrier metal film that becomes a part of the wiring structure to the interlayer insulating film 33. Acts as an insulating film. Next, an antireflection film 35 generally called a BARC film is applied on the TEOS film 34, and a resist film 36 having connection hole patterns opened thereon is formed thereon by lithography.

次に図７（ｂ）に示す工程で、レジスト膜３６をマスクにして反射防止膜３５、ＴＥＯＳ膜３４および層間絶縁膜３３を、エッチングストッパー膜３２の表面が露出するまでエッチングし、接続孔３７ａを形成する。次に図８（ａ）に示す工程で、接続孔３７ａにレジスト３８を埋め込む。そしてＴＥＯＳ膜３４上に反射防止膜３９を塗布し、その上に配線溝パターンを開口したレジスト膜４０を形成する。次に図８（ｂ）に示す工程で、レジスト膜４０をマスクとして反射防止膜３９、ＴＥＯＳ膜３４をエッチング除去し、さらに層間絶縁膜３３を所定の深さまでエッチングすることによって配線溝４１ａを形成する。その後レジスト膜４０、反射防止膜３９およびレジスト３８をプラズマアッシングとウェット洗浄により除去する。   Next, in the step shown in FIG. 7B, the antireflection film 35, the TEOS film 34, and the interlayer insulating film 33 are etched using the resist film 36 as a mask until the surface of the etching stopper film 32 is exposed, thereby connecting holes 37a. Form. Next, in the step shown in FIG. 8A, a resist 38 is embedded in the connection hole 37a. Then, an antireflection film 39 is applied on the TEOS film 34, and a resist film 40 having a wiring groove pattern opened thereon is formed thereon. Next, in the step shown in FIG. 8B, the antireflection film 39 and the TEOS film 34 are removed by etching using the resist film 40 as a mask, and the interlayer insulating film 33 is further etched to a predetermined depth to form a wiring groove 41a. To do. Thereafter, the resist film 40, the antireflection film 39 and the resist 38 are removed by plasma ashing and wet cleaning.

次に図９（ａ）に示すように、最初の接続孔３７ａの底面に露出していたエッチングストッパー膜３２を除去すると、最初の底面がさらに下方へエッチングされた接続孔３７ｂと配線溝４１ｂとなる。次に図９（ｂ）に示すように、接続孔３７ｂおよび配線溝４１ｂの内部にバリア膜４２を堆積し、さらに電解メッキ用のシード膜として薄い銅膜４３を堆積した後、銅膜４３上に電解メッキ法により厚い銅膜４４を形成する。次に図１０に示すように、接続孔および配線溝の外部の銅膜４３、４４およびバリア膜４２、さらにＴＥＯＳ膜３４を例えばＣＭＰ法を用いて除去し、層間絶縁膜３３の表面を露出させることにより、銅膜４３、４４およびバリア膜４２からなる上層配線とそれに接続するプラグを形成する。このようして、デュアルダマシン法による銅の埋め込み多層配線構造を有する半導体装置が製造される（特許文献１参照）。   Next, as shown in FIG. 9A, when the etching stopper film 32 exposed on the bottom surface of the first connection hole 37a is removed, the connection hole 37b and the wiring groove 41b in which the first bottom surface is etched further downward. Become. Next, as shown in FIG. 9B, a barrier film 42 is deposited inside the connection hole 37b and the wiring groove 41b, and a thin copper film 43 is deposited as a seed film for electrolytic plating. A thick copper film 44 is formed by electrolytic plating. Next, as shown in FIG. 10, the copper films 43 and 44 and the barrier film 42 outside the connection holes and wiring trenches, and the TEOS film 34 are removed by using, for example, a CMP method to expose the surface of the interlayer insulating film 33. As a result, an upper wiring composed of the copper films 43 and 44 and the barrier film 42 and a plug connected thereto are formed. Thus, a semiconductor device having a copper buried multilayer wiring structure by a dual damascene method is manufactured (see Patent Document 1).

特開２００７−８４８９１号公報JP 2007-84891 A

しかしながら一般にデュアルダマシン法では図９（ａ）、（ｂ）に示されるように、配線溝の内部と接続孔の内部とに配線材料を同時に埋め込む。このため従来から、配線溝の底面からさらに下方へ掘り下げられ、横方向寸法の微小化を進めることによってアスペクト比が高くなった接続孔内部には配線材料が埋め込まれ難いという問題があった。   However, in general, in the dual damascene method, as shown in FIGS. 9A and 9B, a wiring material is simultaneously embedded in the wiring groove and the connection hole. For this reason, conventionally, there has been a problem that it is difficult to embed the wiring material inside the connection hole that has been dug further downward from the bottom surface of the wiring groove and the aspect ratio has been increased by miniaturizing the lateral dimension.

図１１は従来のデュアルダマシン法で配線構造を形成するときに生じる問題点を示す断面図である。図１１に示すように、従来の製造方法では、配線溝の底面に形成された接続孔の入口を含むコーナー部の側壁が垂直となりやすく、微細化が進むと接続孔の開口上部が一層狭くなる。このため例えばスパッタリングによって成膜されるバリアメタル膜４３、電解メッキシード膜としての銅膜４４は接続孔のコーナー部でオーバーハング４７を生じ、接続孔の開口上部寸法あるいは直径がバリア膜４３、銅膜４４の堆積でさらに狭くなる。こうした状態で銅膜４５を電解メッキ法で埋め込むと、オーバーハング４７に起因して接続孔内部にボイド４６が発生し易く、銅からなるプラグ部分の抵抗増加を招くとともにある場合にはプラグの導電性不良となる確率が高くなり、結果的に半導体集積回路装置の製造歩留まりや信頼性を低下させる。   FIG. 11 is a cross-sectional view showing problems that occur when a wiring structure is formed by a conventional dual damascene method. As shown in FIG. 11, in the conventional manufacturing method, the side wall of the corner portion including the entrance of the connection hole formed on the bottom surface of the wiring groove is likely to be vertical, and as the miniaturization progresses, the upper opening portion of the connection hole becomes narrower. . Therefore, for example, the barrier metal film 43 formed by sputtering and the copper film 44 as the electrolytic plating seed film cause an overhang 47 at the corner of the connection hole, and the upper dimension or diameter of the connection hole is the barrier film 43, copper The film 44 is further narrowed by deposition. When the copper film 45 is embedded by the electrolytic plating method in such a state, a void 46 is likely to be generated inside the connection hole due to the overhang 47, leading to an increase in resistance of the plug portion made of copper, and in some cases, the conductivity of the plug. As a result, the manufacturing yield and reliability of the semiconductor integrated circuit device are lowered.

本発明は上記課題を解決するものであり、接続孔と配線溝とに金属のような配線用導電材料を埋め込む場合、配線層が微細化されてもボイドを形成することなく容易に埋め込みできるデュアルダマシン法を用いた配線構造形成方法を提供することを目的とするものである。   The present invention solves the above-described problem. When a conductive material for wiring such as metal is embedded in a connection hole and a wiring groove, a dual that can be easily embedded without forming a void even if the wiring layer is miniaturized. It is an object of the present invention to provide a wiring structure forming method using the damascene method.

上記従来の課題を解決するための本発明に係る半導体装置の製造方法は、基板上に設けられた下層配線の上にエッチングストッパー膜を堆積する工程と、前記エッチングストッパー膜の上に第１絶縁膜、第２絶縁膜および第３絶縁膜を順次堆積する工程と、前記第３絶縁膜、前記第２絶縁膜および前記第１絶縁膜を順次選択的にエッチングし、前記第３絶縁膜および前記第２絶縁膜を貫通して前記第１絶縁膜まで延びる開口を形成する工程と、前記開口の内部にガスのプラズマ処理を施す工程と、前記プラズマ処理工程の後、前記開口の内部に薬液処理を施す工程と、前記第３絶縁膜および前記第２絶縁膜の前記開口を含む領域を選択的にエッチングし、前記第２絶縁膜内で前記エッチングを停止して溝を形成する工程と、前記溝および前記開口内部に導電膜を埋め込む工程とを備えており、
少なくとも前記第２絶縁膜の膜密度を前記第１絶縁膜の膜密度より小さく設定することを特徴とするものである。 A method of manufacturing a semiconductor device according to the present invention for solving the above-described conventional problems includes a step of depositing an etching stopper film on a lower wiring provided on a substrate, and a first insulation on the etching stopper film. Sequentially depositing a film, a second insulating film, and a third insulating film; and sequentially etching the third insulating film, the second insulating film, and the first insulating film sequentially; and A step of forming an opening extending through the second insulating film to the first insulating film, a step of performing a plasma treatment of a gas inside the opening, and a chemical treatment inside the opening after the plasma treatment step A step of selectively etching a region including the opening of the third insulating film and the second insulating film, stopping the etching in the second insulating film, and forming a groove; Groove and said And a step of embedding a conductive film in the mouth portion,
At least the film density of the second insulating film is set smaller than the film density of the first insulating film.

さらに上記製造方法の一形態として、前記第３絶縁膜および前記第２絶縁膜をエッチングして前記溝を形成する工程は、前記第３絶縁膜の前記開口を含む領域を選択的にエッチングし、前記第３絶縁膜内で前記エッチングを停止して溝部を形成する工程と、前記溝部の底面部においてさらに前記第３絶縁膜および前記第２絶縁膜を選択的にエッチングするとともに、前記開口の下の前記エッチングストッパー膜を選択的にエッチングして、前記下層配線の表面を露出させる工程とを含む。   Furthermore, as one form of the manufacturing method, the step of etching the third insulating film and the second insulating film to form the groove selectively etches a region including the opening of the third insulating film, Stopping the etching in the third insulating film to form a groove, selectively etching the third insulating film and the second insulating film on the bottom surface of the groove, and under the opening Selectively etching the etching stopper film to expose the surface of the lower layer wiring.

本発明に係る製造方法においては、前記第２絶縁膜の比誘電率が前記第１絶縁膜の比誘電率より小さいものとすることができる。また、前記第２絶縁膜はその内部に微細な空孔を多数有し、前記第１絶縁膜は前記空孔を有していないものとすることができる。あるいはまた、前記第１絶縁膜および前記第２絶縁膜がその内部に微細な空孔を多数有し、前記第２絶縁膜の空孔密度が前記第１絶縁膜の空孔密度より大きいものとすることができる。そして前記第１絶縁膜の比誘電率として２．８〜３．５、前記第２絶縁膜の比誘電率として２．８以下となる材料膜を選ぶことができる。   In the manufacturing method according to the present invention, the relative dielectric constant of the second insulating film may be smaller than the relative dielectric constant of the first insulating film. The second insulating film may have a number of fine holes therein, and the first insulating film may not have the holes. Alternatively, the first insulating film and the second insulating film have many fine holes therein, and the hole density of the second insulating film is larger than the hole density of the first insulating film. can do. A material film having a relative dielectric constant of 2.8 to 3.5 and a relative dielectric constant of the second insulating film of 2.8 or less can be selected.

また、本発明に係る製造方法においては、前記プラズマ処理は酸素を含むガスのプラズマ処理とすることが望ましく、前記薬液処理はＨＦを含む薬液による処理とすることが望ましい。   In the manufacturing method according to the present invention, the plasma treatment is preferably a plasma treatment of a gas containing oxygen, and the chemical treatment is preferably a treatment with a chemical solution containing HF.

次に上記従来の課題を解決するための本発明に係る半導体装置は、基板上に設けられた下層配線と、前記下層配線上に、下から順にそれぞれ積層された第１絶縁膜、第２絶縁膜および第３絶縁膜と、前記第３絶縁膜および前記第２絶縁膜に形成され、前記第２絶縁膜中に底面を有する溝と、前記溝の底面から前記第２絶縁膜および前記第１絶縁膜を貫通し、前記下層配線に達する開口と、前記溝および前記開口内に埋め込まれた導電膜とを備え、少なくとも前記第２絶縁膜の膜密度は前記第１絶縁膜の膜密度より小さく、前記開口の上部の寸法は下部の寸法より大きいことを特徴とする構成を有する。   Next, a semiconductor device according to the present invention for solving the above-described conventional problems includes a lower layer wiring provided on a substrate, a first insulating film and a second insulating layer stacked on the lower layer wiring in order from the bottom. A film, a third insulating film, a groove formed in the third insulating film and the second insulating film, and having a bottom surface in the second insulating film; and the second insulating film and the first from the bottom surface of the groove An opening that penetrates the insulating film and reaches the lower layer wiring; and a conductive film embedded in the groove and the opening. At least a film density of the second insulating film is smaller than a film density of the first insulating film. The size of the upper portion of the opening is larger than the size of the lower portion.

本発明に係る半導体装置においては、前記第２絶縁膜の比誘電率を前記第１絶縁膜の比誘電率より小さいものとすることができる。また、前記第２絶縁膜はその内部に微細な空孔を多数有し、前記第１絶縁膜は前記空孔を有していないものとすることができる。あるいはまた、前記第１絶縁膜および前記第２絶縁膜はその内部に微細な空孔を多数有し、前記第２絶縁膜の空孔密度は前記第１絶縁膜の空孔密度より大きいものとすることができる。そして前記第１絶縁膜の比誘電率として２．８〜３．５、前記第２絶縁膜の比誘電率として２．８以下となる材料を選ぶことができる。   In the semiconductor device according to the present invention, the relative dielectric constant of the second insulating film may be smaller than the relative dielectric constant of the first insulating film. The second insulating film may have a number of fine holes therein, and the first insulating film may not have the holes. Alternatively, the first insulating film and the second insulating film have a large number of fine holes therein, and the hole density of the second insulating film is larger than the hole density of the first insulating film. can do. A material having a relative dielectric constant of 2.8 to 3.5 and a relative dielectric constant of the second insulating film of 2.8 or less can be selected.

また本発明に係る半導体装置において、前記開口内部における前記第２絶縁膜の側壁面の、水平面に対する角度は、前記第１絶縁膜の側壁面の角度より小さいことが望ましく、 さらにその第２絶縁膜の側壁面の前記角度を４５°〜８０°にすることが望ましい。   In the semiconductor device according to the present invention, an angle of the side wall surface of the second insulating film inside the opening is preferably smaller than an angle of the side wall surface of the first insulating film, and the second insulating film It is desirable that the angle of the side wall surface is set to 45 ° to 80 °.

本発明に係る半導体装置の製造方法では、上に述べたように、第１、第２および第３絶縁膜からなる積層絶縁膜のうち、少なくとも第２絶縁膜の膜密度を第１絶縁膜の膜密度より小さく設定し、かつ積層絶縁膜に設けられた開口の内部にガスのプラズマ処理と、その後の薬液処理を施す工程を行う。このことにより第２絶縁膜の側壁面に特に大きいテーパーを付けることができるか、あるいは第２絶縁膜と第１絶縁膜にまたがる側壁面を階段状にできる。従って完成時の半導体装置において、導電膜を埋め込んで配線とするための溝の下に形成されて接続孔となる前記開口上部の寸法が下部より大きくなって開口の入口が広がる。このため、開口内へ埋め込まれる導電膜にボイドなどの埋め込み不良が発生せず導電性不良が防止され、デュアルダマシン法による配線形成工程が採用される半導体集積回路装置の製造歩留まりや信頼性を向上できる。   In the method of manufacturing a semiconductor device according to the present invention, as described above, at least the second insulating film density of the first, second, and third insulating films is made to be the same as that of the first insulating film. A step of performing gas plasma treatment and subsequent chemical treatment on the inside of the opening provided in the laminated insulating film is set to be smaller than the film density. Accordingly, the side wall surface of the second insulating film can be particularly tapered, or the side wall surface extending over the second insulating film and the first insulating film can be stepped. Accordingly, in the completed semiconductor device, the size of the upper part of the opening, which is formed under the trench for filling the conductive film to form a wiring and becomes a connection hole, is larger than the lower part, and the entrance of the opening is widened. For this reason, voids or other defects in the conductive film embedded in the opening do not occur, preventing the conductivity defects, and improving the manufacturing yield and reliability of the semiconductor integrated circuit device employing the dual damascene method. it can.

また第２の絶縁膜としてその内部に微細な空孔を多数有する多孔質膜、または比誘電率が２．８以下の膜を用いると開口側壁面のテーパーや階段形状を容易に形成することができる。   Further, when a porous film having a large number of fine pores therein or a film having a relative dielectric constant of 2.8 or less is used as the second insulating film, a taper or a step shape of the opening side wall surface can be easily formed. it can.

本発明の実施形態による配線構造の製造方法を示す工程断面図。Process sectional drawing which shows the manufacturing method of the wiring structure by embodiment of this invention. 本発明の実施形態による配線構造の製造方法を示す工程断面図。Process sectional drawing which shows the manufacturing method of the wiring structure by embodiment of this invention. 本発明の実施形態による配線構造の製造方法を示す工程断面図。Process sectional drawing which shows the manufacturing method of the wiring structure by embodiment of this invention. 本発明の実施形態による配線構造の製造方法を示す工程断面図。Process sectional drawing which shows the manufacturing method of the wiring structure by embodiment of this invention. 本発明の実施形態による配線構造の製造方法を示す工程断面図。Process sectional drawing which shows the manufacturing method of the wiring structure by embodiment of this invention. Ｌｏｗ−ｋ膜とＥＬＫ膜に対するＴＤＳ法による脱離ガス分析結果を示す図。The figure which shows the desorption gas analysis result by TDS method with respect to a Low-k film | membrane and an ELK film | membrane. 配線構造の従来の製造方法を示す工程断面図。Process sectional drawing which shows the conventional manufacturing method of wiring structure. 配線構造の従来の製造方法を示す工程断面図。Process sectional drawing which shows the conventional manufacturing method of wiring structure. 配線構造の従来の製造方法を示す工程断面図。Process sectional drawing which shows the conventional manufacturing method of wiring structure. 配線構造の従来の製造方法を示す工程断面図。Process sectional drawing which shows the conventional manufacturing method of wiring structure. 従来の製造方法における問題点を説明する図。The figure explaining the problem in the conventional manufacturing method.

図１〜図５は本発明の実施形態によるデュアルダマシン法を用いた、半導体集積回路における多層配線構造の製造方法を示す工程断面図であり、以下これら図面を参照して上記実施形態による製造方法を説明する。まず図１（ａ）に示すように、シリコンなどの半導体基板（図示省略）上に各種半導体素子（図示省略）を形成し、その半導体素子を被覆するように酸化シリコン系の材料からなる層間絶縁膜１０および層間絶縁膜１０に埋め込まれた銅からなる下層配線１１形成する。上記層間絶縁膜１０および下層配線１１の表面は同一高さとなるように平坦化されている。   1 to 5 are process sectional views showing a method of manufacturing a multilayer wiring structure in a semiconductor integrated circuit using a dual damascene method according to an embodiment of the present invention. The manufacturing method according to the above embodiment will be described below with reference to these drawings. Will be explained. First, as shown in FIG. 1A, various semiconductor elements (not shown) are formed on a semiconductor substrate (not shown) such as silicon, and an interlayer insulation made of a silicon oxide-based material so as to cover the semiconductor elements. A lower layer wiring 11 made of copper embedded in the film 10 and the interlayer insulating film 10 is formed. The surfaces of the interlayer insulating film 10 and the lower layer wiring 11 are planarized so as to have the same height.

次にＳｉXＣYＮZ（以下、簡単にＳｉＣＮという）膜で構成されるとともに、後に配線への接続孔１９ａを形成するためのエッチング工程においてエッチングストッパーとして作用するエッチングストッパー膜１２を層間絶縁膜１０の全面を覆うように形成する。この膜は例えばプラズマＣＶＤ法で堆積される。続いて例えば直鎖型分子構造を有するトリメチルシランやテトラメチルシランを原料として、低誘電率絶縁膜（以下Ｌｏｗ−ｋ膜という）１３をプラズマＣＶＤ法によりエッチングストッパー膜１２上に、例えば１５０ｎｍ程度形成する。Ｌｏｗ−ｋ膜１３はＳｉXＯYＣZ（以下簡単にＳｉＯＣ膜という）という形の酸化シリコン系の膜あるいは有機・無機ハイブリッド膜と称せられ、その比誘電率は少なくともＳｉＯ2膜（比誘電率３．９〜４）より小さく普通２．８〜３．５である。 Next, the insulating film is formed of a Si x C y N z (hereinafter simply referred to as SiCN) film, and an etching stopper film 12 that acts as an etching stopper in an etching process for forming a connection hole 19a to the wiring later is interlayer-insulated. It forms so that the whole surface of the film | membrane 10 may be covered. This film is deposited by, for example, a plasma CVD method. Subsequently, using, for example, trimethylsilane or tetramethylsilane having a linear molecular structure as a raw material, a low dielectric constant insulating film (hereinafter referred to as “low-k film”) 13 is formed on the etching stopper film 12 by, for example, about 150 nm by plasma CVD. To do. The low-k film 13 is called a silicon oxide film or an organic / inorganic hybrid film in the form of Si x O y C z (hereinafter simply referred to as SiOC film), and has a relative dielectric constant of at least a SiO 2 film (relative dielectric). The ratio is smaller than 3.9-4) and is usually 2.8-3.5.

次にＬｏｗ−ｋ膜１３上に、例えば前記のトリメチルシランやテトラメチルシランと、いわゆるポロジェンと呼ばれるＳｉ−Ｏ結合などから構成される環状分子構造を含む有機化合物（例えば環状型シロキサン）とを混在させた材料を原料とし、ＳｉＯＣ系のシリコン酸化膜をプラズマＣＶＤ法によりＬｏｗ−ｋ膜１３と同じく成膜する。その後この膜に紫外線照射し多孔質低誘電率絶縁膜（Ｐｏｒｕｓ−Ｌｏｗ−ｋ膜）（以下ＥＬＫ膜（Ｅｘｔｒｅｍｅ Ｌｏｗ−ｋ膜）という）１４に変化させる。このＥＬＫ膜１４の堆積膜厚は例えば１０〜１００ｎｍ程度である。ＥＬＫ膜１４は膜中に比誘電率が真空に近い空隙を多数有する多孔質構造をとることによって２．２〜２．８という非常に小さい比誘電率を示す。   Next, on the low-k film 13, for example, the above-mentioned trimethylsilane or tetramethylsilane and an organic compound (for example, cyclic siloxane) having a cyclic molecular structure composed of a so-called porogen called Si—O bond are mixed. Using the material made as a raw material, a SiOC-based silicon oxide film is formed in the same manner as the low-k film 13 by plasma CVD. Thereafter, the film is irradiated with ultraviolet rays to be changed into a porous low dielectric constant insulating film (Porus-Low-k film) (hereinafter referred to as ELK film (Extreme Low-k film)) 14. The deposited film thickness of the ELK film 14 is, for example, about 10 to 100 nm. The ELK film 14 exhibits a very small relative dielectric constant of 2.2 to 2.8 by taking a porous structure having a large number of voids with a relative dielectric constant close to vacuum in the film.

次にＥＬＫ膜１４上にＬｏｗ−ｋ膜１３と同一の形成方法を用い、同一の物性を有する低誘電率絶縁膜（Ｌｏｗ−Ｋ膜またはＳｉＯＣ膜）１５を例えば１００ｎｍ程度形成する。 次に例えば減圧ＣＶＤ法によりテトラエトキソオキソシラン（ＴＥＯＳ）を原料として酸化シリコン系のＴＥＯＳ膜１６を例えば１００ｎｍ程度の厚さに形成する。このＴＥＯＳ膜１６は、後の工程で形成されるバリアメタル膜中の金属原子がＬｏｗ−ｋ膜１５へ侵入し、汚染するのを防止するため形成されるものである。次にＴＥＯＳ膜１６上に有機系の反射防止膜１７を塗布し、さらにその上にリソグラフィ技術により配線の接続孔となる開口パターンを備えたレジスト膜１８を形成する。   Next, a low dielectric constant insulating film (Low-K film or SiOC film) 15 having the same physical properties is formed on the ELK film 14 by using the same formation method as that of the Low-k film 13, for example, about 100 nm. Next, a silicon oxide-based TEOS film 16 is formed to a thickness of, for example, about 100 nm using tetraethoxyoxosilane (TEOS) as a raw material by, for example, a low pressure CVD method. The TEOS film 16 is formed to prevent metal atoms in a barrier metal film formed in a later step from entering the Low-k film 15 and contaminating. Next, an organic antireflection film 17 is applied on the TEOS film 16, and a resist film 18 having an opening pattern serving as a connection hole for wiring is formed thereon by lithography.

次に図１（ｂ）に示すように、レジスト膜１８をマスクとし反射防止膜１７、ＴＥＯＳ膜１６、Ｌｏｗ−ｋ膜１５、ＥＬＫ膜１４、Ｌｏｗ−ｋ膜１３をエッチングストッパー膜１２が露出するまで順次異方性エッチングし、ほぼ垂直で凹凸のない一様な側壁面を有する接続孔１９ａを開口する。このエッチングは、例えばＩＣＰ（誘導結合プラズマ）方式のプラズマエッチング装置を用い、ＣＨＦ３流量：１０ｍｌ／ｍｉｎ（標準状態）、ＣＦ４流量：２０ｍｌ／ｍｉｎ（標準状態）、トータルガス圧力：１０Ｐａ、エッチングチャンバーの外部に設けられた上部コイル電極の印加電力：１０００Ｗ（１３．５６ＭＨｚ）、被エッチング基板を載置した下部電極の印加電力：２０００Ｗ（１３．５６ＭＨｚ）、下部電極温度：０度、エッチング時間：６０ｓｅｃの条件で行うことができる。   Next, as shown in FIG. 1B, the etching stopper film 12 exposes the antireflection film 17, TEOS film 16, Low-k film 15, ELK film 14, and Low-k film 13 using the resist film 18 as a mask. The contact holes 19a having a uniform side wall surface that is substantially vertical and has no unevenness are opened. This etching is performed using, for example, an ICP (inductively coupled plasma) type plasma etching apparatus, CHF3 flow rate: 10 ml / min (standard state), CF4 flow rate: 20 ml / min (standard state), total gas pressure: 10 Pa, Applied power of the upper coil electrode provided outside: 1000 W (13.56 MHz), applied power of the lower electrode on which the substrate to be etched is mounted: 2000 W (13.56 MHz), lower electrode temperature: 0 degree, etching time: 60 sec Can be performed under the following conditions.

次に図２（ａ）に示すように酸素プラズマアッシング処理によりレジスト膜１８と反射防止膜１７とを除去する。アッシングは、例えば平行平板電極を搭載したＲＩＥ方式プラズマアッシング装置を用い、Ｏ２流量：１００ｍｌ／ｍｉｎ（標準状態）、酸素ガス圧力：３０Ｐａ、被処理基板を載置した下部電極の印加電力：３００Ｗ（１３．５６ＭＨｚ）、アッシング時間：３０ｓｅｃの条件で行うことができる。このプラズマアッシング処理はレジスト膜１８および反射防止膜１７を除去すると同時に、接続孔１９ａの内部側壁面に露出するＬｏｗ−ｋ膜１３、１５とＥＬＫ膜１４の表面部にプラズマ変質層２０を形成するが、このプラズマ変質層２０はアッシングプラズマ衝撃によって形成された欠陥生成層であると推定される。Ｌｏｗ−ｋ膜１３、１５とＥＬＫ膜１４とでは上述のように膜質が異なるためにプラズマ衝撃による変質効果が異なる。すなわちＬｏｗ−ｋ膜１３および１５よりＥＬＫ膜１４の方が変質の程度が大きく、これにより図２（ａ）のようにＥＬＫ膜１４において側壁面からより深くプラズマ変質層が形成されると考えられる。   Next, as shown in FIG. 2A, the resist film 18 and the antireflection film 17 are removed by an oxygen plasma ashing process. For ashing, for example, an RIE type plasma ashing device equipped with parallel plate electrodes is used. O2 flow rate: 100 ml / min (standard state), oxygen gas pressure: 30 Pa, applied power of the lower electrode on which the substrate to be processed is placed: 300 W ( 13.56 MHz) and ashing time: 30 sec. In this plasma ashing process, the resist film 18 and the antireflection film 17 are removed, and at the same time, a plasma-modified layer 20 is formed on the surface portions of the Low-k films 13 and 15 and the ELK film 14 exposed on the inner side wall surface of the connection hole 19a. However, this plasma-modified layer 20 is presumed to be a defect generation layer formed by ashing plasma bombardment. As described above, the low-k films 13 and 15 and the ELK film 14 have different quality due to plasma bombardment. That is, it is considered that the degree of alteration of the ELK film 14 is larger than that of the Low-k films 13 and 15, and as a result, a plasma altered layer is formed deeper from the side wall surface in the ELK film 14 as shown in FIG. .

ここでＬｏｗ−ｋ膜とＥＬＫ膜との変質効果の違いについてさらに説明する。Ｌｏｗ−ｋ膜は上に述べたように、例えばトリメチルシランやテトラメチルシランを原料としたＣＶＤ法により成膜する。このようなＬｏｗ−ｋ膜は微視的に見ても概ね一様な原子密度分布を有する構造をしている。これに対してＥＬＫ膜は、例えばトリメチルシランやテトラメチルシランとポロジェンを混在させた材料を原料としてＣＶＤ法により成膜した後、紫外線照射によって形成される。紫外線照射を行うと成膜直後のＥＬＫ膜中のポロジェン物質に対応する環状分子構造部が除去され、そのあとに微小な空孔が形成されることになる。このようにしてＥＬＫ膜はＬｏｗ−ｋ膜と同じ酸化シリコン系あるいはＳｉＯＣ系の膜であるにもかかわらず膜中に多数の空孔（細孔）を有するものとなるが、空孔の誘電率は約１であるから、膜全体としての平均比誘電率はＬｏｗ−ｋ膜と比較して小さくなる。空孔のＳＡＸＳ（Ｓｍａｌｌ Ａｎｇｌｅ Ｘ−Ｒａｙ Ｓｃａｔｔｅｒｉｎｇ）法によって算出される寸法は１ｎｍ〜６ｎｍ程度である。ＥＬＫ膜はまた空孔の存在によりＬｏｗ−ｋ膜に比較して膜密度が低い膜ともいえる。   Here, the difference in alteration effect between the Low-k film and the ELK film will be further described. As described above, the low-k film is formed by a CVD method using, for example, trimethylsilane or tetramethylsilane as a raw material. Such a Low-k film has a substantially uniform atomic density distribution even when viewed microscopically. On the other hand, the ELK film is formed, for example, by ultraviolet irradiation after being formed by CVD using a material in which trimethylsilane or tetramethylsilane and porogen are mixed as a raw material. When the ultraviolet irradiation is performed, the cyclic molecular structure corresponding to the porogen substance in the ELK film immediately after the film formation is removed, and then a minute hole is formed. In this way, although the ELK film is the same silicon oxide or SiOC film as the low-k film, it has a large number of holes (pores) in the film. Is about 1, the average relative dielectric constant of the entire film is smaller than that of the low-k film. The dimension calculated by the SAXS (Small Angle X-Ray Scattering) method of the pores is about 1 nm to 6 nm. It can also be said that the ELK film has a lower film density than the low-k film due to the presence of vacancies.

ＥＬＫ膜中には極めて多数の空孔が存在するため、ＥＬＫ膜を酸素プラズマアッシングした場合その空孔内に酸素原子が多く入り込みトリメチルシランやテトラメチルシラン原料を起源とするＳｉ−ＣＨ３結合の切断およびポロジェン起源のＳｉ−Ｏ結合の切断による分子構造的なダメージ、変質を容易に引き起こす。Ｌｏｗ−ｋ膜にも確かに分子構造的なダメージ、変質が生じているが基本的に空孔が存在しないのでその程度は小さいといえる。   Since there are an extremely large number of vacancies in the ELK film, when oxygen plasma ashing is performed on the ELK film, many oxygen atoms enter the vacancies and break the Si-CH3 bond originating from trimethylsilane or tetramethylsilane material. In addition, molecular structural damage and alteration due to cleavage of porogen-derived Si—O bonds are easily caused. Although the molecular structure damage and alteration have certainly occurred in the Low-k film, it can be said that the degree is small because there are basically no vacancies.

ＥＬＫ膜とＬｏｗ−ｋ膜との膜質の差は以下のような実験からも示される。図６は、昇温脱離ガス分析法（ＴＤＳ法）によりＬｏｗ−ｋ膜とＥＬＫ膜の吸湿性を評価した結果を示すグラフである。縦軸は真空中で試料にランプ光を照射し、光吸収により昇温した際の試料から脱離するガスの質量分析から得た強度である。図６からわかるようにＥＬＫ膜の方がＬｏｗ−ｋ膜より２倍脱離ガス強度が高い、逆に言えばそれだけ水分吸収、吸湿性が高いことから、Ｌｏｗ−ｋ膜より２倍程度ダメージが入り易いといえる。このことは、図２（ａ）で説明すると、Ｌｏｗ−ｋ膜１３、１５よりＥＬＫ膜１４のほうが横方向により大きい領域にわたって変質層２０が生じることに対応する。   The difference in film quality between the ELK film and the Low-k film is also shown from the following experiment. FIG. 6 is a graph showing the results of evaluating the hygroscopicity of the Low-k film and the ELK film by the temperature programmed desorption gas analysis method (TDS method). The vertical axis represents the intensity obtained from mass analysis of the gas desorbed from the sample when the sample is irradiated with lamp light in a vacuum and heated by light absorption. As can be seen from FIG. 6, the ELK film is twice as strong as the desorbed gas than the low-k film, and conversely, it absorbs more moisture and absorbs moisture, so the damage is about twice that of the low-k film. It can be said that it is easy to enter. 2A, this corresponds to the fact that the altered layer 20 is generated in a region where the ELK film 14 is laterally larger than the low-k films 13 and 15.

次に図２（ｂ）に示すように例えばＨＦの純水希釈液を用いて薬液洗浄処理すると、Ｌｏｗ−ｋ膜１３、１５およびＥＬＫ膜１４のそれぞれにおいて、プラズマ変質層２０とそれ以外の部分とにエッチング速度の差があるのでプラズマ変質層２０を選択的に除去することができる。この薬液処理で接続孔１９ａの側壁面２１にはＬｏｗ−ｋ膜１３、１５、ＥＬＫ膜１４のプラズマ変質層２０の厚みに応じた凹凸ができる。次に図３（ａ）に示すように接続孔１９ａを含む全面にレジスト２２を塗布し、酸素を含むエッチングガスを用いたプラズマでエッチバックを行い、接続孔１９ａの外部に塗布されたレジスト２２を除去し、接続孔１９ａの内部にのみレジスト２２を埋め込む。さらにＴＥＯＳ膜１６上に有機系の反射防止膜２３を塗布し、次にリソグラフィ技術により配線溝となる開口パターンを備えたレジスト膜２４を形成する。   Next, as shown in FIG. 2B, when a chemical cleaning process is performed using, for example, a pure water dilution of HF, the plasma-modified layer 20 and other portions in each of the low-k films 13 and 15 and the ELK film 14 are obtained. Therefore, the plasma altered layer 20 can be selectively removed. By this chemical treatment, irregularities corresponding to the thicknesses of the plasma-affected layers 20 of the Low-k films 13 and 15 and the ELK film 14 are formed on the side wall surface 21 of the connection hole 19a. Next, as shown in FIG. 3A, a resist 22 is applied to the entire surface including the connection hole 19a, etched back with plasma using an etching gas containing oxygen, and the resist 22 applied outside the connection hole 19a. And the resist 22 is embedded only in the connection hole 19a. Further, an organic antireflection film 23 is applied on the TEOS film 16, and then a resist film 24 having an opening pattern serving as a wiring groove is formed by a lithography technique.

次に図３（ｂ）に示すように、レジストパターン２４をマスクとして反射防止膜２３、およびＴＥＯＳ膜１６を順次エッチングし、さらにレジスト２２を含めてＬｏｗ−ｋ膜１５をその膜厚より小さい所定の深さまでエッチングして配線溝２５ａを形成する。このときのエッチングは、例えばＩＣＰ方式のプラズマエッチング装置を用い、ＣＦ４流量：１００ｍｌ／ｍｉｎ（標準状態）、Ｎ２流量：５０ｍｌ／ｍｉｎ（標準状態）、トータルガス圧力：１０Ｐａ、エッチングチャンバーの外部に設けられた上部コイル電極の印加電力：５００Ｗ（１３．５６ＭＨｚ）、被エッチング基板を載置する下部電極の印加電力：１００Ｗ（１３．５６ＭＨｚ）、下部電極の温度：２０℃の条件で行うことができる。   Next, as shown in FIG. 3B, the antireflection film 23 and the TEOS film 16 are sequentially etched using the resist pattern 24 as a mask, and the Low-k film 15 including the resist 22 is made smaller than the film thickness. The wiring trench 25a is formed by etching to a depth of. Etching at this time uses, for example, an ICP type plasma etching apparatus, CF4 flow rate: 100 ml / min (standard state), N2 flow rate: 50 ml / min (standard state), total gas pressure: 10 Pa, provided outside the etching chamber. The applied power of the upper coil electrode is 500 W (13.56 MHz), the applied power of the lower electrode on which the substrate is to be etched is 100 W (13.56 MHz), and the temperature of the lower electrode is 20 ° C. .

次に図４（ａ）に示すように、接続孔１９ａに埋め込まれていたレジスト２２、レジスト膜２４、反射防止膜２３を酸素を含むガスによるプラズマアッシングとそれに続く純水で希釈したＨＦ薬液により除去、洗浄する。この工程後ＥＬＫ膜１４の側壁面の傾斜角度を水平面に対して４５°〜８０°とすることができる。この角度はＬｏｗ−ｋ膜１３、１５の側壁面に形成される角度より小さい。次に図４（ｂ）に示すように、配線溝２５ａの底面となっているＬｏｗ−ｋ膜１５を貫通し、さらにＥＬＫ膜１４をその膜厚より小さい深さまでエッチングを行い、ＥＬＫ膜１４の深さ方向の途中でエッチングを停止させて配線溝２５ｂとする。この際のエッチング停止はプラズマ放射光の光強度変化をモニターする公知のＥＰＤ（End Point Detector）を用い、Ｌｏｗ−ｋ膜１５のエッチング終点検出を行うことによって制御可能である。具体的には、エッチング処理中のプラズマ放射光のうち、Ｌｏｗ−ｋ膜１５が除去されてＥＬＫ膜１４が露出した際に光強度が変化する特定波長（例えばＣＯの波長４８３ｎｍ）の光を常時計測し、当該光の強度に変化が生じたことを検出することで精度良くエッチングを停止させることができる。   Next, as shown in FIG. 4A, the resist 22, the resist film 24, and the antireflection film 23 embedded in the connection hole 19a are subjected to plasma ashing with a gas containing oxygen, followed by HF chemical diluted with pure water. Remove and wash. After this step, the inclination angle of the side wall surface of the ELK film 14 can be set to 45 ° to 80 ° with respect to the horizontal plane. This angle is smaller than the angle formed on the side wall surfaces of the low-k films 13 and 15. Next, as shown in FIG. 4B, the ELK film 14 is etched to a depth smaller than the thickness of the ELK film 14 through the Low-k film 15 which is the bottom surface of the wiring trench 25a. Etching is stopped halfway in the depth direction to form a wiring trench 25b. The etching stop at this time can be controlled by detecting the etching end point of the low-k film 15 by using a known EPD (End Point Detector) that monitors the light intensity change of the plasma radiation light. Specifically, light of a specific wavelength (for example, a CO wavelength of 483 nm) whose light intensity changes when the Low-k film 15 is removed and the ELK film 14 is exposed is constantly emitted from the plasma radiation light during the etching process. Etching can be accurately stopped by measuring and detecting that the intensity of the light has changed.

このエッチングによって、銅表面の酸化を防ぐために、図１（ａ）〜図４（ａ）に示す工程で下層配線１１を被覆していたエッチングストッパー膜１２の接続孔１９ａ底面の残部がすべてエッチングされ、下層配線１１の表面が露出する。このときのエッチングは、例えばＩＣＰ方式のプラズマエッチング装置を用い、Ｃ４Ｆ８流量：１０ｍｌ／ｍｉｎ（標準状態）、ＣＦ４流量：１００ｍｌ／ｍｉｎ（標準状態）、トータルガス圧力：２０Ｐａ、エッチングチャンバーの外部に設けられた上部コイル電極の印加電力：５００Ｗ（１３．５６ＭＨｚ）、被エッチング基板を載置する下部電極の印加電力：３００Ｗ（１３．５６ＭＨｚ）、下部電極の温度：２０℃の条件で行うことができる。   By this etching, in order to prevent oxidation of the copper surface, the remainder of the bottom surface of the connection hole 19a of the etching stopper film 12 covering the lower layer wiring 11 in the steps shown in FIGS. 1 (a) to 4 (a) is etched. The surface of the lower layer wiring 11 is exposed. Etching at this time uses, for example, an ICP type plasma etching apparatus, C4F8 flow rate: 10 ml / min (standard state), CF4 flow rate: 100 ml / min (standard state), total gas pressure: 20 Pa, provided outside the etching chamber. The applied power of the upper coil electrode is 500 W (13.56 MHz), the applied power of the lower electrode on which the substrate is to be etched is 300 W (13.56 MHz), and the temperature of the lower electrode is 20 ° C. .

次に図５に示すように接続孔１９ｂおよび配線溝２５ｂの内部を含み、接続孔１９ｂの側壁において３ｎｍ程度、その底部において２０ｎｍ程度、配線溝２５ｂの側壁およびその底部において５ｎｍ程度の膜厚となるように窒化タンタルバリアメタル膜２６をスパッタリング法を用いて堆積する。次にＡｒガスのような希ガスまたは不活性ガスを用いてスパッタエッチングにより接続孔１９ｂ底部のバリア膜２６を１０ｎｍ程度残存するようにエッチングを行う。次に電解メッキ用のシード膜として薄い銅膜２７をスパッタリング法により堆積した後、電解メッキ法により銅膜２７上に銅膜２８を形成する。次に接続孔１９ｂおよび配線溝２５ｂの外部に形成されていた銅膜２８および薄い銅膜２７、バリアメタル膜２６、ＴＥＯＳ膜１６を例えばＣＭＰ法を用いて除去することにより、銅膜２７、２８およびバリアメタル膜２６からなる配線溝２５ｂに埋め込まれた上層配線、この上層配線と下層配線１１とを接続する接続孔１９ｂに埋め込まれたプラグを形成する。   Next, as shown in FIG. 5, including the inside of the connection hole 19b and the wiring groove 25b, a film thickness of about 3 nm at the side wall of the connection hole 19b, about 20 nm at the bottom, and about 5 nm at the side wall and the bottom of the wiring groove 25b. A tantalum nitride barrier metal film 26 is deposited using a sputtering method. Next, etching is performed by sputter etching using a rare gas such as Ar gas or an inert gas so that the barrier film 26 at the bottom of the connection hole 19b remains about 10 nm. Next, after a thin copper film 27 is deposited by sputtering as a seed film for electrolytic plating, a copper film 28 is formed on the copper film 27 by electrolytic plating. Next, the copper film 28, the thin copper film 27, the barrier metal film 26, and the TEOS film 16 that are formed outside the connection hole 19b and the wiring groove 25b are removed by using, for example, a CMP method, whereby the copper films 27 and 28 are removed. Then, an upper layer wiring buried in the wiring groove 25 b made of the barrier metal film 26 and a plug buried in the connection hole 19 b connecting the upper layer wiring and the lower layer wiring 11 are formed.

本発明によるデュアルダマシン法を用いた配線構造形成工程は、図２（ａ）の工程でＬｏｗ−ｋ膜１３とＥＬＫ膜１４に形成されたプラズマ変質層２０大きさの差を利用し、図２（ｂ）の工程に示すように接続孔１９ａ内におけるＬｏｗ−ｋ膜１３の側壁と比較してＥＬＫ膜１４の側壁に、より大きいテーパーをつけるものである。あるいはＥＬＫ膜１４に形成されるプラズマ変質層２０が酸素プラズマアッシング処理する前のＥＬＫ膜側壁面と平行に一様な厚さで生じる場合は、図５の接続孔１９ｂのコーナーを含む上部は階段状になる。このＥＬＫ膜１４の大きいテーパーまたは階段形状により接続孔１９ａの上部開口寸法を下部より大きく広げることができるので、バリアメタル膜２６、銅シード膜２７がオーバーハング形状に堆積されることを抑制し、各膜の膜厚を接続孔１９ｂの上部コーナーにおいてもその側壁においてもほぼ均一に形成することができる。従ってその後のメッキ法による銅膜２８などの導電膜埋め込み時の埋め込み不良、ボイド形成、プラグ導電性不良を防止することができる。   The wiring structure forming process using the dual damascene method according to the present invention utilizes the difference in the size of the plasma altered layer 20 formed in the Low-k film 13 and the ELK film 14 in the process of FIG. As shown in the step (b), the side wall of the ELK film 14 is tapered more than the side wall of the Low-k film 13 in the connection hole 19a. Alternatively, when the plasma-modified layer 20 formed on the ELK film 14 is formed in a uniform thickness parallel to the side wall surface of the ELK film before the oxygen plasma ashing process, the upper portion including the corner of the connection hole 19b in FIG. It becomes a shape. Since the upper opening size of the connection hole 19a can be made larger than the lower portion due to the large taper or step shape of the ELK film 14, it is possible to suppress the barrier metal film 26 and the copper seed film 27 from being deposited in an overhang shape, The thickness of each film can be formed substantially uniformly at the upper corner of the connection hole 19b and also at the side wall thereof. Therefore, it is possible to prevent a burying failure, void formation, or plug conductivity failure when the conductive film such as the copper film 28 is embedded by subsequent plating.

上記実施形態では、空孔が基本的に存在しないＬｏｗ−ｋ膜と多孔質のＥＬＫ膜との組み合わせ構造を用いたが、Ｌｏｗ−ｋ膜に代えて内部にＥＬＫ膜より小さい空孔密度を有する多孔質の絶縁膜としても上記実施形態と同様の効果がある。また本発明に係る方法ではＥＬＫ膜を用いたため、自動的に図５に示す膜１２〜１５の積層膜からなる層間絶縁膜が全体として低誘電率化されたことになるので上下配線層間の寄生容量を低減させ、半導体集積回路の高速化にも寄与する。   In the above embodiment, a combination structure of a low-k film and a porous ELK film that basically does not have pores is used, but instead of the low-k film, the pore density is smaller than that of the ELK film. The porous insulating film has the same effect as the above embodiment. Further, since the ELK film is used in the method according to the present invention, the interlayer insulating film composed of the laminated films 12 to 15 shown in FIG. This reduces the capacity and contributes to the speedup of the semiconductor integrated circuit.

以上説明したように、本発明によるデュアルダマシン法を用いた多層配線形成方法は、配線となる金属のような導電材料をボイドを生じることなく配線溝や接続孔に埋め込むことができるので、半導体集積回路装置のより微細なパターン寸法を有する多層配線形成に有用である。   As described above, the multi-layer wiring forming method using the dual damascene method according to the present invention can embed a conductive material such as a metal to be a wiring in a wiring groove or a connection hole without generating a void. This is useful for forming a multilayer wiring having a finer pattern size of a circuit device.

１０、３０ 層間絶縁膜
１１、３１ 下層配線
１２、３２ エッチングストッパー膜
１３、１５、３３ Ｌｏｗ−ｋ膜
１４ ＥＬＫ膜
１６、３４ ＴＥＯＳ膜
１７、２３、３５、３９ 反射防止膜
１８、２４、３６、４０ レジスト膜
１９ａ、１９ｂ、３７ａ、３７ｂ 接続孔
２０ プラズマ変質層
２１ 側壁面
２２、３８ レジスト
２５ａ、２５ｂ、４１ａ、４１ｂ 配線溝
２６、４２ バリアメタル膜
２７、２８、４３、４４ 銅膜 10, 30 Interlayer insulating film 11, 31 Lower layer wiring 12, 32 Etching stopper film 13, 15, 33 Low-k film 14 ELK film 16, 34 TEOS film 17, 23, 35, 39 Antireflection film 18, 24, 36, 40 Resist films 19a, 19b, 37a, 37b Connection hole 20 Plasma modified layer 21 Side wall surface 22, 38 Resist 25a, 25b, 41a, 41b Wiring groove 26, 42 Barrier metal film 27, 28, 43, 44 Copper film

Claims (15)

基板上に設けられた下層配線の上にエッチングストッパー膜を堆積する工程と、
前記エッチングストッパー膜の上に第１絶縁膜、第２絶縁膜および第３絶縁膜を順次堆積する工程と、
前記第３絶縁膜、前記第２絶縁膜および前記第１絶縁膜を順次選択的にエッチングし、前記第３絶縁膜および前記第２絶縁膜を貫通して前記第１絶縁膜まで延びる開口を形成する工程と、
前記開口の内部にガスのプラズマ処理を施す工程と、
前記プラズマ処理工程の後、前記開口の内部に薬液処理を施す工程と、
前記第３絶縁膜および前記第２絶縁膜の前記開口を含む領域を選択的にエッチングし、前記第２絶縁膜内で前記エッチングを停止して溝を形成する工程と、
前記溝および前記開口内部に導電膜を埋め込む工程とを備え、
少なくとも前記第２絶縁膜の膜密度は前記第１絶縁膜の膜密度より小さいことを特徴とする半導体装置の製造方法。 Depositing an etching stopper film on the lower wiring provided on the substrate;
Sequentially depositing a first insulating film, a second insulating film, and a third insulating film on the etching stopper film;
The third insulating film, the second insulating film, and the first insulating film are selectively etched sequentially to form an opening that extends through the third insulating film and the second insulating film to the first insulating film. And a process of
Applying a plasma treatment of gas inside the opening;
After the plasma treatment step, a step of applying a chemical treatment to the inside of the opening;
Selectively etching a region including the opening of the third insulating film and the second insulating film, and stopping the etching in the second insulating film to form a groove;
Filling the conductive film in the groove and the opening,
At least the film density of the second insulating film is smaller than the film density of the first insulating film. 前記第３絶縁膜および前記第２絶縁膜をエッチングして前記溝を形成する工程は、
前記第３絶縁膜の前記開口を含む領域を選択的にエッチングし、前記第３絶縁膜内で前記エッチングを停止して溝部を形成する工程と、
前記溝部の底面部においてさらに前記第３絶縁膜および前記第２絶縁膜を選択的にエッチングするとともに、前記開口の下の前記エッチングストッパー膜を選択的にエッチングして、前記下層配線の表面を露出させる工程と
を含むことを特徴とする半導体装置の製造方法。 Etching the third insulating film and the second insulating film to form the groove comprises the steps of:
Selectively etching a region including the opening of the third insulating film, stopping the etching in the third insulating film, and forming a groove;
The third insulating film and the second insulating film are further selectively etched at the bottom surface of the groove, and the etching stopper film below the opening is selectively etched to expose the surface of the lower layer wiring. A method for manufacturing a semiconductor device, comprising the steps of: 前記第２絶縁膜の比誘電率は前記第１絶縁膜の比誘電率より小さいことを特徴とする請求項１または２に記載の半導体装置に製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein a relative dielectric constant of the second insulating film is smaller than a relative dielectric constant of the first insulating film. 前記第２絶縁膜はその内部に微細な空孔を多数有し、前記第１絶縁膜は前記空孔を有していないことを特徴とする請求項１または２に記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film has a large number of fine holes therein, and the first insulating film does not have the holes. . 前記第１絶縁膜および前記第２絶縁膜はその内部に微細な空孔を多数有し、前記第２絶縁膜の空孔密度は前記第１絶縁膜の空孔密度より大きいことを特徴とする半導体装置の製造方法。   The first insulating film and the second insulating film have a large number of fine holes therein, and the hole density of the second insulating film is larger than the hole density of the first insulating film. A method for manufacturing a semiconductor device. 前記第１絶縁膜の比誘電率は２．８〜３．５であり、前記第２絶縁膜の比誘電率は２．８以下であることを特徴とする請求項１〜４のいずれかに記載の半導体装置の製造方法。   The relative dielectric constant of the first insulating film is 2.8 to 3.5, and the relative dielectric constant of the second insulating film is 2.8 or less. The manufacturing method of the semiconductor device of description. 前記プラズマ処理は、酸素を含むガスのプラズマ処理であることを特徴とする請求項１〜６のいずれかに記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the plasma treatment is a plasma treatment of a gas containing oxygen. 前記薬液処理はＨＦを含む薬液による処理であることを特徴とする請求項１〜７のいずれかに記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the chemical solution treatment is a treatment with a chemical solution containing HF. 基板上に設けられた下層配線と、
前記下層配線上に、下から順にそれぞれ積層された第１絶縁膜、第２絶縁膜および第３絶縁膜と、
前記第３絶縁膜および前記第２絶縁膜に形成され、前記第２絶縁膜中に底面を有する溝と、
前記溝の底面から前記第２絶縁膜および前記第１絶縁膜を貫通し、前記下層配線に達する開口と、
前記溝および前記開口内に埋め込まれた導電膜とを備え、
少なくとも前記第２絶縁膜の膜密度は前記第１絶縁膜の膜密度より小さく、前記開口の上部の寸法は下部の寸法より大きいことを特徴とする半導体装置。 Lower layer wiring provided on the substrate;
A first insulating film, a second insulating film, and a third insulating film, which are stacked in order from the bottom on the lower layer wiring;
A groove formed in the third insulating film and the second insulating film and having a bottom surface in the second insulating film;
An opening that penetrates the second insulating film and the first insulating film from the bottom surface of the groove and reaches the lower layer wiring;
A conductive film embedded in the groove and the opening,
The semiconductor device is characterized in that at least the film density of the second insulating film is smaller than the film density of the first insulating film, and the upper dimension of the opening is larger than the lower dimension. 前記第２絶縁膜の比誘電率は前記第１絶縁膜の比誘電率より小さいことを特徴とする請求項９に記載の半導体装置。   The semiconductor device according to claim 9, wherein a relative dielectric constant of the second insulating film is smaller than a relative dielectric constant of the first insulating film. 前記第２絶縁膜はその内部に微細な空孔を多数有し、前記第１絶縁膜は前記空孔を有していないことを特徴とする請求項９または１０に記載の半導体装置。   11. The semiconductor device according to claim 9, wherein the second insulating film has a large number of fine holes therein, and the first insulating film does not have the holes. 前記第１絶縁膜および前記第２絶縁膜はその内部に微細な空孔を多数有し、前記第２絶縁膜の空孔密度は前記第１絶縁膜の空孔密度より大きいことを特徴とする請求項９または１０に記載の半導体装置。   The first insulating film and the second insulating film have a large number of fine holes therein, and the hole density of the second insulating film is larger than the hole density of the first insulating film. The semiconductor device according to claim 9. 前記第１絶縁膜の比誘電率は２．８〜３．５であり、前記第２絶縁膜の比誘電率は２．８以下であることを特徴とする請求項１１に記載の半導体装置の製造方法。   The relative dielectric constant of the first insulating film is 2.8 to 3.5, and the relative dielectric constant of the second insulating film is 2.8 or less. Production method. 前記開口内部における前記第２絶縁膜の側壁面の、水平面に対する角度は、前記第１絶縁膜の側壁面の角度より小さいことを特徴とする請求項９〜１２のいずれかに記載の半導体装置。   The semiconductor device according to claim 9, wherein an angle of a side wall surface of the second insulating film inside the opening is smaller than an angle of a side wall surface of the first insulating film. 前記第２絶縁膜の側壁面の前記角度は４５°〜８０°であることを特徴とする請求項１４に記載の半導体装置。   The semiconductor device according to claim 14, wherein the angle of the side wall surface of the second insulating film is 45 ° to 80 °.
JP2009230215A 2009-10-02 2009-10-02 Semiconductor device manufacturing method and semiconductor device Withdrawn JP2011077468A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009230215A JP2011077468A (en) 2009-10-02 2009-10-02 Semiconductor device manufacturing method and semiconductor device
PCT/JP2010/001165 WO2011039898A1 (en) 2009-10-02 2010-02-23 Semiconductor device manufacturing method and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009230215A JP2011077468A (en) 2009-10-02 2009-10-02 Semiconductor device manufacturing method and semiconductor device

Publications (1)

Publication Number Publication Date
JP2011077468A true JP2011077468A (en) 2011-04-14

Family

ID=43825752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009230215A Withdrawn JP2011077468A (en) 2009-10-02 2009-10-02 Semiconductor device manufacturing method and semiconductor device

Country Status (2)

Country Link
JP (1) JP2011077468A (en)
WO (1) WO2011039898A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150228683A1 (en) * 2014-02-13 2015-08-13 Canon Kabushiki Kaisha Semiconductor device manufacturing method, and photoelectric conversion device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8784844B2 (en) 2009-09-30 2014-07-22 Lonza Ltd. Arabinogalactan for enhancing the adaptive immune response
KR20200016472A (en) * 2018-08-07 2020-02-17 삼성전자주식회사 Semiconductor device and method for fabricating the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2325083B (en) * 1997-05-09 1999-04-14 United Microelectronics Corp A dual damascene process
JP3445495B2 (en) * 1997-07-23 2003-09-08 株式会社東芝 Semiconductor device
JP3400770B2 (en) * 1999-11-16 2003-04-28 松下電器産業株式会社 Etching method, semiconductor device and manufacturing method thereof
JP4583678B2 (en) * 2001-09-26 2010-11-17 富士通株式会社 Semiconductor device manufacturing method and semiconductor device cleaning solution
JP2005019585A (en) * 2003-06-25 2005-01-20 Nec Electronics Corp Semiconductor device and its manufacturing method
JP2006060166A (en) * 2004-08-24 2006-03-02 Matsushita Electric Ind Co Ltd Electronic device and manufacturing method thereof
JP4716316B2 (en) * 2005-06-27 2011-07-06 次世代半導体材料技術研究組合 Manufacturing method of semiconductor device
JP2007165603A (en) * 2005-12-14 2007-06-28 Matsushita Electric Ind Co Ltd Method of manufacturing wiring structure
JP2008108892A (en) * 2006-10-25 2008-05-08 Denso Corp Method for forming interconnection of semiconductor device, and interconnection
JP4850891B2 (en) * 2008-12-19 2012-01-11 ルネサスエレクトロニクス株式会社 Wiring structure manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150228683A1 (en) * 2014-02-13 2015-08-13 Canon Kabushiki Kaisha Semiconductor device manufacturing method, and photoelectric conversion device
US9559136B2 (en) * 2014-02-13 2017-01-31 Canon Kabushiki Kaisha Semiconductor device manufacturing method, and photoelectric conversion device

Also Published As

Publication number Publication date
WO2011039898A1 (en) 2011-04-07

Similar Documents

Publication Publication Date Title
US7541276B2 (en) Methods for forming dual damascene wiring for semiconductor devices using protective via capping layer
US8564136B2 (en) Semiconductor device and method for fabricating the same
WO2007091574A1 (en) Multilayer wiring structure, and method for fabricating multilayer wiring
JP4567587B2 (en) Manufacturing method of semiconductor device
US7781301B2 (en) Method of fabricating semiconductor device
JP2009147096A (en) Semiconductor device and method of manufacturing same
JP5147751B2 (en) Manufacturing method of semiconductor device
JP2006216809A (en) Semiconductor device and its manufacturing method
WO2011039898A1 (en) Semiconductor device manufacturing method and semiconductor device
US7091612B2 (en) Dual damascene structure and method
JP4684866B2 (en) Manufacturing method of semiconductor device
US7482275B2 (en) Plasma treatment method and method of manufacturing semiconductor device
JP2006216964A (en) Method for manufacturing dual damascene wiring of semiconductor element using via capping protection film
JP2012134422A (en) Semiconductor device and manufacturing method of the same
JP5200436B2 (en) Manufacturing method of semiconductor device
JP2009004633A (en) Multilayer interconnection structure and method of manufacturing the same
CN108573912B (en) Semiconductor structure and forming method thereof
JPWO2007142172A1 (en) Multilayer wiring manufacturing method, multilayer wiring structure and multilayer wiring manufacturing apparatus
JP2007067324A (en) Method for manufacturing semiconductor device
JP4447433B2 (en) Semiconductor device manufacturing method and semiconductor device
JP4948278B2 (en) Manufacturing method of semiconductor device
JP2005203568A (en) Fabrication process of semiconductor device, and semiconductor device
JP2010129950A (en) Semiconductor device and method of manufacturing the same
KR100483838B1 (en) Dual damascene process of metal wire
JP2009117673A (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
A761 Written withdrawal of application

Effective date: 20111006

Free format text: JAPANESE INTERMEDIATE CODE: A761