JP2011063849A - Film deposition method and storage medium - Google Patents
Film deposition method and storage medium Download PDFInfo
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- JP2011063849A JP2011063849A JP2009215415A JP2009215415A JP2011063849A JP 2011063849 A JP2011063849 A JP 2011063849A JP 2009215415 A JP2009215415 A JP 2009215415A JP 2009215415 A JP2009215415 A JP 2009215415A JP 2011063849 A JP2011063849 A JP 2011063849A
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25D17/001—Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D21/00—Processes for servicing or operating cells for electrolytic coating
- C25D21/12—Process control or regulation
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/38—Electroplating: Baths therefor from solutions of copper
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/18—Electroplating using modulated, pulsed or reversing current
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/34—Pretreatment of metallic surfaces to be electroplated
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/04—Electroplating with moving electrodes
Abstract
Description
本発明は、Ｃｏシードの上に電解メッキによってＣｕ膜を成膜する成膜方法および記憶媒体に関する。 The present invention relates to a film forming method and a storage medium for forming a Cu film on a Co seed by electrolytic plating.
近時、半導体デバイスの高速化、配線パターンの微細化等に呼応して、Ａｌよりも導電性が高く、かつエレクトロマイグレーション耐性等も良好なＣｕが配線として注目されており、Ｃｕ配線層は電解メッキにより形成されている。従来から、電解メッキによるＣｕ配線のシードとしては、Ｃｕが用いられてきたが、配線パターンのさらなる微細化にともない、埋め込み性の向上が求められており、従来のＣｕから埋め込み性の良好なＣｏへの変更が検討されている。Ｃｏは抵抗が低く、Ｃｕとの密着性が高いという利点もある。 Recently, Cu, which has higher conductivity than Al and good electromigration resistance, is attracting attention as a wiring in response to the speeding up of semiconductor devices and the miniaturization of wiring patterns. It is formed by plating. Conventionally, Cu has been used as a seed for Cu wiring by electrolytic plating. However, with further miniaturization of the wiring pattern, improvement in embedding property has been demanded. Changes to are being considered. Co has the advantages of low resistance and high adhesion to Cu.
電解メッキによりＣｕ膜を形成する場合には、従来からメッキ液として硫酸銅を用いているが、Ｃｏは硫酸に可溶であるため、Ｃｏをメッキシードとして用いると、Ｃｏがメッキ液に溶出する。配線パターンの微細化にともない、メッキシードは５ｎｍ以下に薄膜化しており、このような薄いＣｏ膜をメッキシードとして用いた場合、メッキ処理の途中でＣｏ膜が消失してＣｕメッキが形成されない部分が生じたり、Ｃｕ膜の密着性が低下したりといった不都合が生じる。 In the case of forming a Cu film by electrolytic plating, copper sulfate has been conventionally used as a plating solution. However, since Co is soluble in sulfuric acid, when Co is used as a plating seed, Co is eluted into the plating solution. . Along with the miniaturization of the wiring pattern, the plating seed is thinned to 5 nm or less. When such a thin Co film is used as the plating seed, the Co film disappears during the plating process and the Cu plating is not formed. And the inconvenience that the adhesion of the Cu film decreases.
本発明はかかる事情に鑑みてなされたものであって、Ｃｏをメッキシードとして電解メッキによるＣｕ膜を成膜する場合に、Ｃｏの溶出を抑制してＣｏシード上に均質でかつ密着性の高いＣｕ膜を形成することができる成膜方法を提供することを目的とする。
また、そのような成膜方法を実行するためのプログラムを記憶した記憶媒体を提供することを目的とする。
The present invention has been made in view of such circumstances, and in the case of forming a Cu film by electrolytic plating using Co as a plating seed, the elution of Co is suppressed and homogeneous and highly adhesive on the Co seed. It aims at providing the film-forming method which can form Cu film | membrane.
It is another object of the present invention to provide a storage medium storing a program for executing such a film forming method.
上記課題を解決するため、本発明の第１の形態は、表面にシード層としてＣｏ膜が形成された基板を準備し、前記Ｃｏ膜の上に硫酸銅溶液を主体とするメッキ液を用いて、電解メッキにより前記基板のＣｏ膜上にＣｕ膜を成膜する成膜方法であって、前記基板表面をメッキ液に浸漬する前に、前記基板に対して、Ｃｏの表面電位がＣｏの酸化電位より低くなるような負の電圧を印加することを特徴とする成膜方法を提供する。 In order to solve the above problems, a first embodiment of the present invention provides a substrate having a Co film formed as a seed layer on the surface, and uses a plating solution mainly composed of a copper sulfate solution on the Co film. A film forming method of forming a Cu film on the Co film of the substrate by electrolytic plating, wherein the surface potential of Co is oxidized against Co before the substrate surface is immersed in a plating solution. There is provided a film forming method characterized by applying a negative voltage lower than a potential.
本発明の第２の形態は、基板上にシード層となるＣｏ膜をＣＶＤにより成膜する工程と、前記Ｃｏ膜の上に硫酸銅溶液を主体とするメッキ液を用いて、電解メッキにより前記基板のＣｏ膜上にＣｕ膜を成膜する工程とを有し、前記Ｃｕ膜を成膜する工程は、前記基板をメッキ液に浸漬する前に、前記基板に対して、Ｃｏの表面電位がＣｏの酸化電位より低くなるような負の電圧を印加することを特徴とする成膜方法を提供する。 According to a second aspect of the present invention, a Co film as a seed layer is formed on a substrate by CVD, and a plating solution mainly composed of a copper sulfate solution is formed on the Co film by electrolytic plating. Forming a Cu film on the Co film of the substrate, and the step of forming the Cu film has a surface potential of Co with respect to the substrate before the substrate is immersed in a plating solution. A film forming method characterized by applying a negative voltage lower than the oxidation potential of Co.
本発明の第３の観点は、コンピュータ上で動作し、成膜装置を制御するためのプログラムが記憶された記憶媒体であって、前記プログラムは、実行時に、上記第１の形態の成膜方法が行われるように、コンピュータに前記成膜装置を制御させることを特徴とする記憶媒体を提供する。 According to a third aspect of the present invention, there is provided a storage medium that operates on a computer and stores a program for controlling the film forming apparatus, and the program is executed at the time of execution. A storage medium is provided that causes a computer to control the film formation apparatus.
本発明によれば、基板をメッキ液に浸漬する前に、基板に対し、Ｃｏ膜の表面電位がＣｏの酸化電位より低くなるような負の電圧を印加するので、Ｃｏがメッキ液に溶出することが防止され、Ｃｕメッキが形成されない部分が生じることや、Ｃｕ膜の密着性の低下が生じることを防止することができ、均質で密着性の高いＣｕ膜を形成することができる。 According to the present invention, before the substrate is immersed in the plating solution, a negative voltage is applied to the substrate such that the surface potential of the Co film is lower than the oxidation potential of Co, so that Co is eluted into the plating solution. It is possible to prevent the occurrence of a portion where Cu plating is not formed and the deterioration of the adhesion of the Cu film, and a homogeneous and highly adhesive Cu film can be formed.
以下、添付図面を参照して、本発明の実施の形態について説明する。 Embodiments of the present invention will be described below with reference to the accompanying drawings.
＜本発明の成膜方法を実施するための成膜装置の一例の構成＞
図１は、本発明の成膜方法を実施する成膜装置の一例を示す略断面であり、電解メッキによりＣｕ膜を形成する含浸タイプの電解メッキ装置として構成される。
この成膜装置１００は、表面にシード層としてのＣｏ膜が形成された被処理基板である半導体ウエハ（以下単にウエハと記す）Ｗを支持する支持部材１を有している。支持部材１は回転機構（図示せず）により回転可能となっており、これによりウエハＷが面内回転される。ウエハＷの上面の被処理面にはエッジに沿って円筒状のエッジシール部材２がウエハＷに対して液密に設けられている。そして、ウエハＷの表面とエッジシール部材２とで形成される容器にメッキ液Ｌが貯留されるようになっており、下部チャンバーを構成している。また、ウエハＷの表面のエッジシール部材２の外側部分には電極接点４が設けられている。
<Configuration of an example of a film forming apparatus for carrying out the film forming method of the present invention>
FIG. 1 is a schematic cross-sectional view showing an example of a film forming apparatus that performs the film forming method of the present invention, and is configured as an impregnation type electrolytic plating apparatus that forms a Cu film by electrolytic plating.
The film forming apparatus 100 includes a support member 1 that supports a semiconductor wafer (hereinafter simply referred to as a wafer) W that is a substrate to be processed on which a Co film as a seed layer is formed. The support member 1 can be rotated by a rotation mechanism (not shown), whereby the wafer W is rotated in-plane. A cylindrical edge seal member 2 is provided on the surface to be processed on the upper surface of the wafer W in a liquid-tight manner with respect to the wafer W along the edge. The plating solution L is stored in a container formed by the surface of the wafer W and the edge seal member 2, and constitutes a lower chamber. An electrode contact 4 is provided on the outer portion of the edge seal member 2 on the surface of the wafer W.
支持部材１に支持されたウエハＷの上方には略円筒状をなすメッキヘッド１０が昇降機構１７により上下動可能に配置されている。メッキヘッド１０は、メッキ液Ｌが収容される上部チャンバー１１と、上部チャンバー１１内にウエハＷと対向するように設けられたアノード電極１２と、上部チャンバー１１の底部を構成するポーラスセラミックスからなる含浸部材１３とを有している。上部チャンバー１１の上部中央にはメッキ液供給口１４が設けられている。そして、メッキ液供給機構１６によりメッキ液供給口１４を介して上部チャンバー１１内にメッキ液Ｌが供給されるようになっている。アノード電極１２にはメッキ液Ｌが通過する多数のメッキ液通過孔１５が上下に貫通して設けられている。 Above the wafer W supported by the support member 1, a substantially cylindrical plating head 10 is disposed so as to be movable up and down by an elevating mechanism 17. The plating head 10 is impregnated with an upper chamber 11 in which a plating solution L is stored, an anode electrode 12 provided in the upper chamber 11 so as to face the wafer W, and a porous ceramic constituting the bottom of the upper chamber 11. Member 13. A plating solution supply port 14 is provided in the upper center of the upper chamber 11. The plating solution L is supplied into the upper chamber 11 by the plating solution supply mechanism 16 through the plating solution supply port 14. The anode electrode 12 is provided with a large number of plating solution passage holes 15 through which the plating solution L passes vertically.
カソード電極となるウエハＷとアノード電極１２との間には直流電源５が接続されている。ウエハＷへは電極接点４を介して直流電源５の負極が接続されており、アノード電極１２へは直流電源５の正極が接続されている。直流電源５は出力電圧が可変となっている。 A DC power supply 5 is connected between the wafer W serving as the cathode electrode and the anode electrode 12. The negative electrode of the DC power source 5 is connected to the wafer W through the electrode contact 4, and the positive electrode of the DC power source 5 is connected to the anode electrode 12. The DC power supply 5 has a variable output voltage.
メッキ処理を行うに際しては、メッキヘッド１０をウエハＷの表面に近接させ、メッキ液供給口１４からメッキ液Ｌを上部チャンバー１１内に供給する。メッキ液Ｌは含浸部材１３を経て下部チャンバーを構成するウエハＷの表面とエッジシール部材２とで形成される容器に貯留され、さらに上部チャンバー１１内に貯留される。その際のメッキ液Ｌの液面はアノード電極１２が浸漬される程度とされる。なお、供給されたメッキ液は、図示しない排液機構により排液される。 When performing the plating process, the plating head 10 is brought close to the surface of the wafer W, and the plating solution L is supplied into the upper chamber 11 from the plating solution supply port 14. The plating solution L is stored in a container formed by the surface of the wafer W constituting the lower chamber and the edge seal member 2 through the impregnation member 13 and further stored in the upper chamber 11. The liquid surface of the plating solution L at that time is set to such an extent that the anode electrode 12 is immersed. The supplied plating solution is drained by a draining mechanism (not shown).
成膜装置１００は制御部２０を有し、この制御部２０により各構成部、例えば直流電源５、昇降機構１７、メッキ液供給機構１６、ウエハ支持部材１の駆動機構等の制御を行うようになっている。この制御部２０は、マイクロプロセッサ（コンピュータ）を備えたプロセスコントローラ２１と、ユーザーインターフェース２２と、記憶部２３とを有している。プロセスコントローラ２１は成膜装置１００の各構成部に電気的に接続され、これらに制御信号を送るようになっている。ユーザーインターフェース２２は、プロセスコントローラ２１に接続されており、オペレータが成膜装置１００の各構成部を管理するためにコマンドの入力操作などを行うキーボードや、成膜装置１００の各構成部の稼働状況を可視化して表示するディスプレイ等からなっている。記憶部２３もプロセスコントローラ２１に接続されており、この記憶部２３には、成膜装置１００で実行される各種処理をプロセスコントローラ２１の制御にて実現するための制御プログラム、処理条件に応じて成膜装置１００の各構成部に所定の処理を実行させるための制御プログラムすなわち処理レシピ、各種データベース等が格納されている。処理レシピは記憶部２３の中の記憶媒体（図示せず）に記憶されている。記憶媒体は、ハードディスク等の固定的に設けられているものであってもよいし、ＣＤＲＯＭ、ＤＶＤ、フラッシュメモリ等の可搬性のものであってもよい。また、他の装置から、例えば専用回線を介してレシピを適宜伝送させるようにしてもよい。 The film forming apparatus 100 includes a control unit 20, and the control unit 20 controls each component, for example, the DC power supply 5, the lifting mechanism 17, the plating solution supply mechanism 16, the driving mechanism of the wafer support member 1, and the like. It has become. The control unit 20 includes a process controller 21 having a microprocessor (computer), a user interface 22, and a storage unit 23. The process controller 21 is electrically connected to each component of the film forming apparatus 100 and sends control signals thereto. The user interface 22 is connected to the process controller 21, and a keyboard on which an operator inputs a command to manage each component of the film forming apparatus 100, and an operation status of each component of the film forming apparatus 100. It consists of a display etc. that visualizes and displays. The storage unit 23 is also connected to the process controller 21, and the storage unit 23 corresponds to a control program and processing conditions for realizing various processes executed by the film forming apparatus 100 under the control of the process controller 21. A control program for causing each component of the film forming apparatus 100 to execute a predetermined process, that is, a process recipe, various databases, and the like are stored. The processing recipe is stored in a storage medium (not shown) in the storage unit 23. The storage medium may be a fixed medium such as a hard disk or a portable medium such as a CDROM, DVD, or flash memory. Moreover, you may make it transmit a recipe suitably from another apparatus via a dedicated line, for example.
そして、必要に応じて、ユーザーインターフェース２２からの指示等にて所定の処理レシピを記憶部２３から呼び出してプロセスコントローラ２１に実行させることで、プロセスコントローラ２１の制御下で、成膜装置１００での所望の処理が行われる。 Then, if necessary, a predetermined processing recipe is called from the storage unit 23 by an instruction from the user interface 22 and is executed by the process controller 21, so that the film forming apparatus 100 can control the process controller 21. Desired processing is performed.
＜本発明に係る成膜方法の実施形態＞
次に、以上のように構成された成膜装置を用いて行われる本発明に係る成膜方法の実施形態について説明する。
図２は本発明に係る成膜方法の実施形態を説明するためのフローチャートである。
<Embodiment of Film Formation Method According to the Present Invention>
Next, an embodiment of a film forming method according to the present invention performed using the film forming apparatus configured as described above will be described.
FIG. 2 is a flowchart for explaining an embodiment of the film forming method according to the present invention.
まず、表面にメッキシードとなるＣｏ膜が形成されたウエハＷを準備する（工程１）。Ｃｏ膜の厚さは、１．５〜５ｎｍの範囲であることが好ましい。次いで、このウエハＷを電解メッキによりＣｕ膜を成膜する成膜装置１００に搬入し（工程２）、支持部材１に支持させた状態とする。 First, a wafer W having a Co film to be a plating seed formed on the surface is prepared (Step 1). The thickness of the Co film is preferably in the range of 1.5 to 5 nm. Next, the wafer W is carried into a film forming apparatus 100 for forming a Cu film by electrolytic plating (step 2) and is made to be supported by the support member 1.
次に、メッキヘッド１０を下降させて処理状態とし、上部チャンバー１１内に硫酸銅を主体とするメッキ液Ｌを供給する（工程３）。そして、図３（ａ）の模式図に示すように、アノード電極１２がメッキ液Ｌに浸漬され、ウエハＷにはメッキ液が到達しない状態で、直流電源５からカソード電極となるウエハＷに、Ｃｏ膜３１の表面電位がＣｏの酸化電位（酸化還元電位ともいう）より低くなるような負の電圧を印加する（工程４）。 Next, the plating head 10 is lowered to a processing state, and a plating solution L mainly composed of copper sulfate is supplied into the upper chamber 11 (step 3). As shown in the schematic diagram of FIG. 3A, the anode electrode 12 is immersed in the plating solution L, and the plating solution does not reach the wafer W. From the DC power source 5 to the wafer W serving as the cathode electrode, A negative voltage is applied such that the surface potential of the Co film 31 is lower than the oxidation potential (also referred to as redox potential) of Co (step 4).
この状態で、さらにメッキ液Ｌを供給して、図３（ｂ）に示すように、ウエハＷの表面、すなわちＣｏ膜３１をメッキ液Ｌに浸漬された状態とする（工程５）。このとき、Ｃｏ膜３１の表面電位がＣｏの酸化電位よりも低いため、ウエハＷの表面に形成されたＣｏ膜に硫酸銅を主体とするメッキ液Ｌが接触しても、Ｃｏのメッキ液Ｌへの溶出が生じない。つまりＣｏが電気化学的に安定な状態となる。 In this state, the plating solution L is further supplied, and the surface of the wafer W, that is, the Co film 31 is immersed in the plating solution L as shown in FIG. 3B (step 5). At this time, since the surface potential of the Co film 31 is lower than the oxidation potential of Co, even if the plating solution L mainly composed of copper sulfate contacts the Co film formed on the surface of the wafer W, the Co plating solution L No elution occurs. That is, Co becomes electrochemically stable.
Ｃｏの酸化電位は−０．２８Ｖであるから、ウエハＷの表面がメッキ液Ｌに浸漬される前に、ウエハＷの表面がメッキ液Ｌに浸漬された時点で、ウエハＷ（Ｃｏ膜）とメッキ液との電位差が０．３Ｖ以上となるような電圧を印加することが好ましい。 Since the oxidation potential of Co is −0.28 V, when the surface of the wafer W is immersed in the plating solution L before the surface of the wafer W is immersed in the plating solution L, the wafer W (Co film) and It is preferable to apply a voltage such that the potential difference with the plating solution is 0.3 V or more.
このようにしてウエハＷ表面にメッキ液を浸漬した後、直流電源５からの電圧を実際のＣｕメッキの際の電圧に調節してＣｕメッキ処理を行う（工程６）。このときの電圧は好ましくは０．１〜３Ｖ程度とされる。これにより、ウエハＷ表面のＣｏ膜上にＣｕが析出し、Ｃｕ膜が形成される。 After immersing the plating solution on the surface of the wafer W in this way, the Cu plating process is performed by adjusting the voltage from the DC power source 5 to the voltage at the actual Cu plating (step 6). The voltage at this time is preferably about 0.1 to 3V. Thereby, Cu precipitates on the Co film on the surface of the wafer W, and a Cu film is formed.
メッキ処理が終了後、メッキヘッド１０を上昇させ、ウエハＷの表面状のメッキ液Ｌを排出し、ウエハＷを搬出する（工程７）。 After the plating process is finished, the plating head 10 is raised, the plating solution L on the surface of the wafer W is discharged, and the wafer W is unloaded (step 7).
ＣｏはＣｕよりもイオン化傾向が高く、硫酸に可溶なため、何らの操作なく硫酸銅を主体とするメッキ液にウエハＷ表面のＣｏ膜に硫酸銅を主体とするメッキ液を接触させると、ＣｏはＣｏ＋となってメッキ液Ｌ中に溶出する。特に、半導体デバイスの配線パターンが一層微細化していることにともない、メッキシード層の膜厚は５ｎｍ以下が求められているが、このように薄いＣｏ膜をメッキシード層として用いる場合には、Ｃｏ膜がメッキ液Ｌに浸漬された時点でＣｏの溶出にともないＣｏ膜が薄くなったり、消失したりして、Ｃｕメッキ膜が形成されない部分が生じることや、Ｃｕ膜の密着性の低下が生じる。 Since Co has a higher ionization tendency than Cu and is soluble in sulfuric acid, when a plating solution mainly composed of copper sulfate is brought into contact with the Co film on the surface of the wafer W without any operation, the plating solution mainly composed of copper sulfate is brought into contact with the plating solution. Co becomes Co + and is eluted in the plating solution L. In particular, as the wiring pattern of semiconductor devices is further miniaturized, the film thickness of the plating seed layer is required to be 5 nm or less. When such a thin Co film is used as the plating seed layer, Co When the film is immersed in the plating solution L, the Co film becomes thinner or disappears as the Co is eluted, resulting in a portion where the Cu plating film is not formed or a decrease in adhesion of the Cu film. .
これに対して、本実施形態では、ウエハＷの表面をメッキ液Ｌに浸漬する前に、カソード電極となるウエハＷに、Ｃｏ膜の表面電位がＣｏの酸化電位より低くなるような負の電圧を印加するので、Ｃｏがメッキ液に溶出することが防止され、Ｃｕメッキが形成されない部分が生じることや、Ｃｕ膜の密着性の低下が生じることを防止することができ、均質で密着性の高いＣｕ膜を形成することができる。 On the other hand, in the present embodiment, before the surface of the wafer W is immersed in the plating solution L, a negative voltage is applied to the wafer W serving as the cathode electrode so that the surface potential of the Co film is lower than the oxidation potential of Co. Therefore, it is possible to prevent the Co from eluting into the plating solution and prevent the formation of a portion where no Cu plating is formed or the decrease in the adhesion of the Cu film. A high Cu film can be formed.
Ｃｏ膜の厚さが５ｎｍより大きければこのような不都合が生じる可能性は小さいため、本実施形態の方法は、Ｃｏ膜の厚さが５ｎｍ以下の場合に有効である。一方、電解メッキによりＣｏ膜上にＣｕ膜を形成する場合には、最初、置換メッキによりＣｏ膜が１ｎｍ程度エッチングされるため、Ｃｏ膜の厚さはその分を考慮した厚さにすることが好ましい。したがって、Ｃｏ膜の膜厚は１．５〜５ｎｍの範囲であることが好ましい。 If the thickness of the Co film is larger than 5 nm, there is little possibility that such an inconvenience will occur. Therefore, the method of this embodiment is effective when the thickness of the Co film is 5 nm or less. On the other hand, when a Cu film is formed on a Co film by electrolytic plating, the Co film is first etched by about 1 nm by displacement plating. Therefore, the thickness of the Co film can be set in consideration of that amount. preferable. Therefore, the thickness of the Co film is preferably in the range of 1.5 to 5 nm.
Ｃｏ膜の形成方法は特に限定されず、スパッタリングのような物理蒸着（ＰＶＤ）でも化学蒸着（ＣＶＤ）でも構わない。ただし、配線パターンの微細化にともない、微細ホールにも厚さ５ｎｍ以下の薄いＣｏ膜を形成するためには、ステップカバレッジが良好なＣＶＤが好ましい。Ｃｏ膜を形成するためのウエハＷとしては、表面に下地となるＳｉＯｘＣｙ絶縁膜（ｘ、ｙは正の数）、または有機系絶縁物膜が形成されたものが用いられる。 The method for forming the Co film is not particularly limited, and physical vapor deposition (PVD) such as sputtering or chemical vapor deposition (CVD) may be used. However, in order to form a thin Co film having a thickness of 5 nm or less in a fine hole as the wiring pattern becomes finer, CVD with good step coverage is preferable. As the wafer W for forming the Co film, a wafer having a SiOxCy insulating film (x and y are positive numbers) or an organic insulating film as a base on the surface is used.
図４は、ＣＶＤによりＣｏ膜を成膜するＣＶＤ成膜装置の一例を示す概略図である。このＣＶＤ成膜装置２００は、チャンバー４１を有しており、その中の底部には被処理基板であるウエハＷを水平に支持するためのサセプタ４２が設けられている。サセプタ４２にはヒーター４３が埋め込まれており、ヒーター４３に通電することにより、サセプタ４２上のウエハＷを加熱するようになっている。 FIG. 4 is a schematic diagram showing an example of a CVD film forming apparatus for forming a Co film by CVD. This CVD film forming apparatus 200 has a chamber 41, and a susceptor 42 for horizontally supporting a wafer W as a substrate to be processed is provided at the bottom thereof. A heater 43 is embedded in the susceptor 42, and the wafer W on the susceptor 42 is heated by energizing the heater 43.
チャンバー４１の上部には、天壁から下方に突出するようにシャワーヘッド４５が設けられている。シャワーヘッド４５は、成膜のための処理ガスをチャンバー４１内に吐出するためのものであり、その上部中央には処理ガスが導入されるガス導入口４６が設けられている。シャワーヘッド４５の内部にはガス拡散空間４７が形成されており、シャワーヘッド４５の底板４８にはガス多数のガス吐出孔４９が設けられている。ガス導入口４６にはガス供給配管５１が接続されており、ガス供給配管５１には処理ガス供給機構５２が接続されている。そして、処理ガス供給機構５２からガス供給配管５１およびガス導入口４６を介してガス拡散空間４７に導入されたＣｏ膜成膜のための処理ガスがガス吐出孔４９からチャンバー４１内に吐出されるようになっている。 A shower head 45 is provided on the upper portion of the chamber 41 so as to protrude downward from the top wall. The shower head 45 is for discharging a processing gas for film formation into the chamber 41, and a gas introduction port 46 through which the processing gas is introduced is provided at the upper center. A gas diffusion space 47 is formed inside the shower head 45, and a large number of gas discharge holes 49 are provided in the bottom plate 48 of the shower head 45. A gas supply pipe 51 is connected to the gas inlet 46, and a processing gas supply mechanism 52 is connected to the gas supply pipe 51. Then, the processing gas for forming the Co film introduced into the gas diffusion space 47 from the processing gas supply mechanism 52 through the gas supply pipe 51 and the gas introduction port 46 is discharged into the chamber 41 from the gas discharge hole 49. It is like that.
チャンバー４１の底部には排気口５５が設けられており、この排気口５５に排気配管５６が接続されている。排気配管５６には圧力調整バルブおよび真空ポンプ（いずれも図示せず）が設けられている。チャンバー４１の側壁には、ウエハＷの搬入出を行うための搬入出口５７と、この搬入出口５７を開閉するゲートバルブ５８とが設けられている。 An exhaust port 55 is provided at the bottom of the chamber 41, and an exhaust pipe 56 is connected to the exhaust port 55. The exhaust pipe 56 is provided with a pressure adjusting valve and a vacuum pump (both not shown). On the side wall of the chamber 41, a loading / unloading port 57 for loading / unloading the wafer W and a gate valve 58 for opening / closing the loading / unloading port 57 are provided.
ＣＶＤ成膜装置２００は成膜装置１００における制御部２０と同様の制御部６０を有しており、制御部２０と全く同様にＣＶＤ成膜装置２００を制御するようになっている。 The CVD film forming apparatus 200 has a control unit 60 similar to the control unit 20 in the film forming apparatus 100, and controls the CVD film forming apparatus 200 just like the control unit 20.
このように構成されるＣＶＤ成膜装置においては、チャンバー４１内にウエハＷを搬入し、チャンバー４１内が所定の圧力になるまで真空排気し、処理ガス供給機構５２からガス供給配管５１およびシャワーヘッド４５を介してチャンバー４１内に処理ガスを導入し、所定温度に加熱されたウエハＷ上で成膜反応を生じさせ、ウエハ上にＣｏ膜を形成する。 In the CVD film forming apparatus configured as described above, the wafer W is loaded into the chamber 41, evacuated until the inside of the chamber 41 reaches a predetermined pressure, and the gas supply pipe 51 and the shower head are supplied from the processing gas supply mechanism 52. A processing gas is introduced into the chamber 41 through 45 to cause a film forming reaction on the wafer W heated to a predetermined temperature, thereby forming a Co film on the wafer.
このときの処理ガスとしては、実用的にＣｏ膜を成膜できれば特に限定されない。例えば、ビス（Ｎ−ターシャリブチル−Ｎ′−エチル−プロピオンアミジネート）コバルト（II）（Ｃｏ（ｔＢｕ−Ｅｔ−Ｅｔ−ａｍｄ）２）のようなコバルトアミジネートと還元剤とを用いることができる。還元剤としては、Ｈ２ガス、ＮＨ３ガス、カルボン酸ガスを用いることができる。また、コバルトカルボニル（Ｃｏ２（ＣＯ）８）を用い、これをウエハＷ上で熱分解してＣｏ膜を形成するようにしてもよい。成膜温度は前者で１００〜３００℃、後者で１２０〜３００℃が好ましい。 The processing gas at this time is not particularly limited as long as a Co film can be practically formed. For example, a cobalt amidinate such as bis (N-tertiarybutyl-N′-ethyl-propionamidinate) cobalt (II) (Co (tBu-Et-Et-amd) 2 ) and a reducing agent are used. be able to. As the reducing agent, H 2 gas, NH 3 gas, or carboxylic acid gas can be used. Alternatively, cobalt carbonyl (Co 2 (CO) 8 ) may be used and thermally decomposed on the wafer W to form a Co film. The film formation temperature is preferably 100 to 300 ° C. for the former and 120 to 300 ° C. for the latter.
このようにして、ウエハＷ上にＣＶＤでＣｏ膜を成膜してから、上述したように電解メッキによりＣｏ膜上にＣｕ膜を形成することにより、微細パターンであっても良好なステップカバレッジでＣｏ膜を５ｎｍ以下と薄く形成した後、Ｃｏ膜を消失させることなく、高い密着性でＣｕ膜を成膜することができる。 In this way, by forming a Co film on the wafer W by CVD and then forming a Cu film on the Co film by electrolytic plating as described above, even with a fine pattern, good step coverage is achieved. After forming the Co film as thin as 5 nm or less, the Cu film can be formed with high adhesion without losing the Co film.
＜本発明の成膜方法を実施するための成膜装置の他の例の構成＞
上記実施形態では、成膜装置１００として含浸タイプの電解メッキ装置を用いた例を示したが、ここでは、アノード電極および表面にＣｏ膜が形成されたウエハを単純にメッキ液に浸漬するタイプの電解メッキ装置として構成される成膜装置を示す。
<Configuration of Another Example of Film Forming Apparatus for Implementing Film Forming Method of the Present Invention>
In the above embodiment, an example in which an impregnation type electroplating apparatus is used as the film forming apparatus 100 has been described. However, here, a wafer in which a wafer having a Co film formed on the anode electrode and the surface is simply immersed in a plating solution. 1 shows a film forming apparatus configured as an electrolytic plating apparatus.
図５は、本発明の成膜方法を実施するための成膜装置の他の例を示す概略構成図である。この成膜装置１００′は、メッキ液Ｌを貯留するメッキ槽７１を有し、そのメッキ液Ｌ中にアノード電極７２が浸漬されている。そして、カソード電極としてのウエハＷがメッキ液Ｌに浸漬されるようになっている。ウエハＷは図示しない駆動機構により、図５に示すメッキ液Ｌに浸漬された状態とメッキ液Ｌ上に引き上げられた状態との間で移動可能となっている。アノード電極７２とウエハＷとの間には直流電源７３が接続されている。 FIG. 5 is a schematic configuration diagram showing another example of a film forming apparatus for carrying out the film forming method of the present invention. This film forming apparatus 100 ′ has a plating tank 71 for storing a plating solution L, and an anode electrode 72 is immersed in the plating solution L. A wafer W as a cathode electrode is immersed in the plating solution L. The wafer W can be moved between a state where it is immersed in the plating solution L shown in FIG. A DC power source 73 is connected between the anode electrode 72 and the wafer W.
このように構成される成膜装置１００′においては、図６に示すように、ウエハＷをメッキ液Ｌから引き上げた状態のときに、直流電源７３からカソード電極となるウエハＷに、Ｃｏ膜の表面電位がＣｏの酸化電位より低くなるような負の電圧を印加する。これにより、その後、ウエハＷを下降させてウエハＷをメッキ液Ｌに浸漬させても、Ｃｏ膜の表面電位がＣｏの酸化電位よりも低いため、Ｃｏがメッキ液Ｌへ溶出することが防止される。 In the film forming apparatus 100 ′ configured as described above, as shown in FIG. 6, when the wafer W is pulled up from the plating solution L, the Co film is applied from the DC power source 73 to the wafer W serving as the cathode electrode. A negative voltage is applied so that the surface potential is lower than the oxidation potential of Co. As a result, even if the wafer W is subsequently lowered and the wafer W is immersed in the plating solution L, the Co film is prevented from being eluted into the plating solution L because the surface potential of the Co film is lower than the oxidation potential of Co. The
この処理の後、直流電源７３からの電圧を実際のＣｕメッキの際の電圧に調節してＣｕメッキ処理を行い、Ｃｏ膜上にＣｕ膜を形成する。 After this process, the Cu plating process is performed by adjusting the voltage from the DC power source 73 to the voltage at the actual Cu plating, thereby forming a Cu film on the Co film.
＜実施例＞
次に、実施例について説明する。
基板上にメッキシードとなるＣｏ膜を１０ｎｍの厚さで形成したサンプルと、５ｎｍの厚さで形成したサンプルを作成し、まず、これらサンプルをメッキ液に浸漬させる前の電圧印加を行わずに電解メッキによりＣｕ膜を形成した。また、厚さ５ｎｍのＣｏ膜を形成したサンプルについて、メッキ液に浸漬させる前に−２０Ｖの電圧を印加し、その後電解メッキによりＣｕ膜を形成した。
<Example>
Next, examples will be described.
A sample in which a Co film as a plating seed is formed on a substrate with a thickness of 10 nm and a sample with a thickness of 5 nm are prepared. First, without applying a voltage before immersing these samples in a plating solution A Cu film was formed by electrolytic plating. Moreover, about the sample which formed Co film | membrane with a thickness of 5 nm, the voltage of -20V was applied before being immersed in plating solution, and Cu film | membrane was formed by electrolytic plating after that.
これらの経過時間毎のメッキ処理の状態の写真を図７に示す。この図に示すように、Ｃｏ膜の厚さが１０ｎｍのサンプルは、電解メッキ処理に先立って電圧印加しなくても、良好にＣｕ膜が形成されることが確認された。一方、Ｃｏ膜の厚さが５ｎｍのサンプルは、電解メッキ処理に先立って電圧印加しない場合にはＣｏが消失してＣｕ膜が形成されなかった。これに対し、Ｃｏ膜の厚さが５ｎｍのサンプルについて電気メッキ処理に先立って−２０Ｖの電圧を印加した場合には、良好にＣｕ膜が形成されることが確認された。 A photograph of the state of the plating process for each elapsed time is shown in FIG. As shown in this figure, it was confirmed that the sample with the Co film having a thickness of 10 nm formed a good Cu film without applying a voltage prior to the electrolytic plating process. On the other hand, in the sample having a Co film thickness of 5 nm, when no voltage was applied prior to the electrolytic plating process, Co disappeared and no Cu film was formed. On the other hand, when a voltage of −20 V was applied to the sample having a Co film thickness of 5 nm prior to the electroplating process, it was confirmed that the Cu film was satisfactorily formed.
＜本発明の他の適用＞
なお、本発明は、上記実施の形態に限定されることなく種々変形可能である。例えば、電解メッキ装置として構成される成膜装置については、上記実施形態に例示したものに限らず種々の形態の装置を適用することができる。
<Other applications of the present invention>
The present invention can be variously modified without being limited to the above embodiment. For example, the film forming apparatus configured as an electrolytic plating apparatus is not limited to the one exemplified in the above embodiment, and various types of apparatuses can be applied.
また、被処理基板として半導体ウエハを用いた場合を説明したが、これに限らず、フラットパネルディスプレイ（ＦＰＤ）基板等の他の基板であってもよい。 Moreover, although the case where the semiconductor wafer was used as a to-be-processed substrate was demonstrated, not only this but another board | substrates, such as a flat panel display (FPD) board | substrate, may be sufficient.
１；支持部材
２；エッジシール部材
５，７３；直流電源
１０；メッキヘッド
１１；上部チャンバー
１２，７２；アノード電極
１３；含浸部材
２０；制御部
２１；プロセスコントローラ
２３；記憶部（記憶媒体）
７１；メッキ槽
１００，１００′；成膜装置
Ｌ；メッキ液
Ｗ；半導体ウエハ
DESCRIPTION OF SYMBOLS 1; Support member 2; Edge seal member 5 and 73; DC power supply 10; Plating head 11; Upper chamber 12, 72; Anode electrode 13; Impregnation member 20;
71; plating tank 100, 100 '; film forming apparatus L; plating solution W; semiconductor wafer
Claims (8)
前記基板表面をメッキ液に浸漬する前に、前記基板に対して、Ｃｏの表面電位がＣｏの酸化電位より低くなるような負の電圧を印加することを特徴とする成膜方法。 A substrate having a Co film formed thereon as a seed layer is prepared, and a Cu film is formed on the Co film of the substrate by electrolytic plating using a plating solution mainly composed of a copper sulfate solution on the Co film. A film forming method for
A film forming method, wherein a negative voltage is applied to the substrate such that a surface potential of Co is lower than an oxidation potential of Co before the surface of the substrate is immersed in a plating solution.
前記Ｃｏ膜の上に硫酸銅溶液を主体とするメッキ液を用いて、
電解メッキにより前記基板のＣｏ膜上にＣｕ膜を成膜する工程とを有し、
前記Ｃｕ膜を成膜する工程は、前記基板をメッキ液に浸漬する前に、前記基板に対して、Ｃｏの表面電位がＣｏの酸化電位より低くなるような負の電圧を印加することを特徴とする成膜方法。 Forming a Co film to be a seed layer on a substrate by CVD;
Using a plating solution mainly composed of a copper sulfate solution on the Co film,
Forming a Cu film on the Co film of the substrate by electrolytic plating,
In the step of forming the Cu film, before immersing the substrate in a plating solution, a negative voltage is applied to the substrate such that the surface potential of Co is lower than the oxidation potential of Co. A film forming method.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009215415A JP2011063849A (en) | 2009-09-17 | 2009-09-17 | Film deposition method and storage medium |
| US13/054,331 US20110174630A1 (en) | 2009-09-17 | 2010-08-27 | Film formation method and storage medium |
| KR1020107026850A KR20110056455A (en) | 2009-09-17 | 2010-08-27 | Film formation method and storage medium |
| PCT/JP2010/064572 WO2011033916A1 (en) | 2009-09-17 | 2010-08-27 | Film-forming method and storage medium |
| TW099131353A TW201124564A (en) | 2009-09-17 | 2010-09-16 | Film-forming method and storage medium |
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| Application Number | Priority Date | Filing Date | Title |
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| JP2009215415A JP2011063849A (en) | 2009-09-17 | 2009-09-17 | Film deposition method and storage medium |
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| JP2011063849A true JP2011063849A (en) | 2011-03-31 |
| JP2011063849A5 JP2011063849A5 (en) | 2011-05-19 |
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| JP2009215415A Withdrawn JP2011063849A (en) | 2009-09-17 | 2009-09-17 | Film deposition method and storage medium |
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| Country | Link |
|---|---|
| US (1) | US20110174630A1 (en) |
| JP (1) | JP2011063849A (en) |
| KR (1) | KR20110056455A (en) |
| TW (1) | TW201124564A (en) |
| WO (1) | WO2011033916A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011063848A (en) * | 2009-09-17 | 2011-03-31 | Tokyo Electron Ltd | Film deposition method and storage medium |
| JP2014111831A (en) * | 2012-11-27 | 2014-06-19 | Lam Research Corporation | Method and apparatus for dynamic current distribution control during electroplating |
| US10017869B2 (en) | 2008-11-07 | 2018-07-10 | Novellus Systems, Inc. | Electroplating apparatus for tailored uniformity profile |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5659041B2 (en) * | 2011-02-24 | 2015-01-28 | 東京エレクトロン株式会社 | Film formation method and storage medium |
| JP6678490B2 (en) * | 2016-03-28 | 2020-04-08 | 株式会社荏原製作所 | Plating method |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3856986B2 (en) * | 1999-06-15 | 2006-12-13 | 大日本スクリーン製造株式会社 | Board plating equipment |
| JP3984767B2 (en) * | 1999-10-25 | 2007-10-03 | 株式会社日立製作所 | Plating equipment |
| US20050006245A1 (en) * | 2003-07-08 | 2005-01-13 | Applied Materials, Inc. | Multiple-step electrodeposition process for direct copper plating on barrier metals |
| US20040245107A1 (en) * | 2003-06-03 | 2004-12-09 | Guangli Che | Method for improving electroplating in sub-0.1um interconnects by adjusting immersion conditions |
| US7344972B2 (en) * | 2004-04-21 | 2008-03-18 | Intel Corporation | Photosensitive dielectric layer |
| JP2008007830A (en) * | 2006-06-30 | 2008-01-17 | Fujitsu Ltd | Plating method |
-
2009
- 2009-09-17 JP JP2009215415A patent/JP2011063849A/en not_active Withdrawn
-
2010
- 2010-08-27 US US13/054,331 patent/US20110174630A1/en not_active Abandoned
- 2010-08-27 WO PCT/JP2010/064572 patent/WO2011033916A1/en active Application Filing
- 2010-08-27 KR KR1020107026850A patent/KR20110056455A/en not_active Application Discontinuation
- 2010-09-16 TW TW099131353A patent/TW201124564A/en unknown
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10017869B2 (en) | 2008-11-07 | 2018-07-10 | Novellus Systems, Inc. | Electroplating apparatus for tailored uniformity profile |
| US10920335B2 (en) | 2008-11-07 | 2021-02-16 | Novellus Systems, Inc. | Electroplating apparatus for tailored uniformity profile |
| US11549192B2 (en) | 2008-11-07 | 2023-01-10 | Novellus Systems, Inc. | Electroplating apparatus for tailored uniformity profile |
| JP2011063848A (en) * | 2009-09-17 | 2011-03-31 | Tokyo Electron Ltd | Film deposition method and storage medium |
| JP2014111831A (en) * | 2012-11-27 | 2014-06-19 | Lam Research Corporation | Method and apparatus for dynamic current distribution control during electroplating |
| US9909228B2 (en) | 2012-11-27 | 2018-03-06 | Lam Research Corporation | Method and apparatus for dynamic current distribution control during electroplating |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20110056455A (en) | 2011-05-30 |
| WO2011033916A1 (en) | 2011-03-24 |
| US20110174630A1 (en) | 2011-07-21 |
| TW201124564A (en) | 2011-07-16 |
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