JP2011040051A - メモリリマップ情報を記憶する不揮発性メモリ - Google Patents
メモリリマップ情報を記憶する不揮発性メモリ Download PDFInfo
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- JP2011040051A JP2011040051A JP2010148353A JP2010148353A JP2011040051A JP 2011040051 A JP2011040051 A JP 2011040051A JP 2010148353 A JP2010148353 A JP 2010148353A JP 2010148353 A JP2010148353 A JP 2010148353A JP 2011040051 A JP2011040051 A JP 2011040051A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0409—Online test
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
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Abstract
【解決手段】メモリ装置455に関するリマップ情報を不揮発性離散的アドレス指定可能メモリ430に保持することで、リマップすべきメモリの特定エリアのより精細な制御を可能とし、メモリ装置455に対する読み出し/書き込みプロセスが開始されると、リマップ情報を参照して、読み出し/書き込みアドレスが対応するリマップアドレスを有するか否かを判定し、対応するリマップアドレスを有する場合は、リマップした読み出し/書き込みアドレスを使用してメモリ装置455からの読み出し/書き込みを行う。
【選択図】図4
Description
限定するものではない、また排他的なものではない実施形態を、添付図面につき説明するが、特に明示しない限り、図面において同一参照符号は同様の部分を示す。
Claims (20)
- メモリ装置に関するリマップ情報を表すデジタル信号を内容アドレス指定可能メモリ(CAM)に記憶するコントローラであって、前記CAMに記憶された前記リマップ情報が更新された場合、前記CAMに記憶されたリマップ情報の少なくとも一部を不揮発性離散的アドレス指定可能メモリ内に記憶するよう構成した、該コントローラを備えた、ことを特徴とするシステム。
- 請求項1記載のシステムにおいて、さらに、
メモリ装置から読み出したデータを表すデジタル信号を受信し、また前記データを表す前記読み出し信号に関連するビット誤り率および/またはビット誤り数を決定する誤り補正コーディング(ECC)デコーダを備え、
前記コントローラは、前記ビット誤り率および/または前記ビット誤り数がエラー閾値に一致するかまたは越えるかに、少なくとも部分的は基づいて、リマップ情報を記憶するよう構成した、システム。 - 請求項1記載のシステムにおいて、前記不揮発性離散的アドレス指定可能メモリは、相変化メモリ(PCM)を有する構成とした、システム。
- 請求項1記載のシステムにおいて、前記リマップ情報は、1つ以上のリマップアドレステーブルを有する、システム。
- 請求項1記載のシステムにおいて、前記不揮発性アドレス可能メモリは、前記メモリ装置に向けて指示される読み出し/書き込みプロセス実行中に、オン・ザ・フライで新しいリマップ情報を更新できる構成とした、システム。
- 請求項1記載のシステムにおいて、前記CAMおよび前記不揮発性離散的アドレス指定可能メモリは、互いにほぼ同期する構成とした、システム。
- 請求項1記載のシステムにおいて、前記不揮発性離散的アドレス指定可能メモリは、第2CAMを有する構成とした、システム。
- メモリ装置から読み出したデータを表すデジタル信号に関連付けしたビット誤り率および/またはビット誤り数を決定するステップと、および
前記メモリ装置に関するリマップ情報を表すデジタル信号を不揮発性離散的アドレス指定可能メモリに記憶する記憶ステップであって、前記リマップ情報は、前記ビット誤り率および/または前記ビット誤り数がエラー閾値に一致するまたは超えるかに、少なくとも部分的に基づくものとした、該記憶ステップと
を有する、方法。 - 請求項8記載の方法において、前記不揮発性離散的アドレス指定可能メモリは、相変化メモリ(PCM)を有する構成とした、方法。
- 請求項8記載の方法において、前記リマップ情報は、1つ以上のリマップアドレスを有する構成とした、方法。
- 請求項8記載の方法において、前記不揮発性離散的アドレス指定可能メモリは、前記メモリ装置に向けて指示される読み出し/書き込みプロセス実行中に、オン・ザ・フライで新しいリマップ情報を更新できる構成とした、方法。
- 請求項8記載の方法において、前記不揮発性離散的アドレス指定可能メモリは、連想メモリ装置(CAM)を有する構成とした、方法。
- 請求項10記載の方法において、前記メモリ装置は、メインメモリ部分およびスペアメモリ部分を有する構成とし、前記リマップアドレスは前記スペアメモリ部分のメモリ位置に対応するものとした、方法。
- 請求項8記載の方法において、前記記憶ステップは、さらに、前記リマップ情報を前記不揮発性離散的アドレス指定可能メモリの一部に書き込むステップを有し、前記不揮発性離散的アドレス指定可能メモリの一部は前記リマップ情報とほぼ同じサイズである、方法。
- メモリ装置に対して読み出し/書き込みを行い、また1つ以上のアプリケーションを実行するホストと、
前記メモリ装置から読み出したデータを表す信号を受信し、また前記データを表す前記読み出し信号に関連するビット誤り率および/またはビット誤り数を決定する、誤り訂正コーディング(ECC)デコーダと、および
前記ビット誤り率および/またはビット誤り数がエラー閾値と一致または超過するかに、少なくとも部分的に基づいて、前記メモリ装置をリマップしたリマップアドレスを表すデジタル信号を内容アドレス指定可能メモリ装置(CAM)に記憶するリマップコントローラであって、前記CAMは相変化メモリ(PCM)を有する構成とした、該リマップコントローラと
を備えた、ことを特徴とするシステム。 - 請求項15記載のシステムにおいて、前記CAMは、読み出しアドレスを表すデジタル信号を受信し、前記読み出しアドレスが前記CAM内に記憶された前記リマップアドレスに対応するか否かに、少なくとも部分的に応答する応答信号を表すデジタル信号を伝送するよう構成した、システム。
- 請求項16記載のシステムにおいて、さらに、
前記メモリ装置から読み出しを行うアドレスとして用いるため、読み出しアドレスまたはリマップアドレスのいずれかを選択する選択部であって、前記選択は、少なくとも部分的に、前記応答信号に基づくものとした、該選択部を備えた、システム。 - 請求項15記載のシステムにおいて、前記メモリ装置はメインメモリ部分およびスペアメモリ部分を有する構成とし、前記リマップアドレスは前記スペアメモリ部分のメモリ位置に対応するものとした、システム。
- 請求項18記載のシステムにおいて、前記メモリ装置は、さらに、前記ECCデコーダおよび相変化メモリ部分を有する構成とした、システム。
- 請求項15記載のシステムにおいて、前記ビット誤り率および/または前記ビット誤り数は、少なくとも部分的に、前記メモリの物理的劣化に応じて生ずるものである、システム。
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US12/494,994 | 2009-06-30 | ||
US12/494,994 US8412987B2 (en) | 2009-06-30 | 2009-06-30 | Non-volatile memory to store memory remap information |
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JP2011040051A true JP2011040051A (ja) | 2011-02-24 |
JP2011040051A5 JP2011040051A5 (ja) | 2013-08-01 |
JP5996838B2 JP5996838B2 (ja) | 2016-09-21 |
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US (1) | US8412987B2 (ja) |
JP (1) | JP5996838B2 (ja) |
KR (1) | KR101647845B1 (ja) |
CN (1) | CN101937374B (ja) |
DE (1) | DE102010030745B4 (ja) |
TW (1) | TWI484330B (ja) |
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KR102321501B1 (ko) | 2014-05-14 | 2021-11-05 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것을 포함하는 스토리지 장치의 동작 방법 |
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TWI484330B (zh) | 2015-05-11 |
DE102010030745B4 (de) | 2015-02-19 |
DE102010030745A1 (de) | 2011-01-05 |
KR101647845B1 (ko) | 2016-08-11 |
US8412987B2 (en) | 2013-04-02 |
TW201126329A (en) | 2011-08-01 |
CN101937374B (zh) | 2015-07-01 |
JP5996838B2 (ja) | 2016-09-21 |
CN101937374A (zh) | 2011-01-05 |
US20100332895A1 (en) | 2010-12-30 |
KR20110001882A (ko) | 2011-01-06 |
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