JP2011009800A

JP2011009800A - Operational amplifier

Info

Publication number: JP2011009800A
Application number: JP2009148075A
Authority: JP
Inventors: Toru Kawana; 徹川名
Original assignee: Individual
Current assignee: Individual
Priority date: 2009-05-26
Filing date: 2009-06-01
Publication date: 2011-01-13
Anticipated expiration: 2029-06-01
Also published as: JP4643728B2

Abstract

PROBLEM TO BE SOLVED: To provide a new operational amplifier circuit that stably operates in a wide band by being connected with a phase compensation circuit.SOLUTION: The operational amplifier circuit is configured by connecting Rc1 and Rc2 in series between a negative input terminal and an output terminal of an operational amplifier, connecting Cc1 between a node between the Rc1 and the Rc2 and a positive input terminal, and connecting a phase compensation capacitor Cc2 between the positive input terminal and a ground terminal. A capacitance value and a resistance value can be set within a range independent of an extreme increase in a chip area in a used process, respectively. Further, a capacitor and a resistor can be added after design and can be connected also to the outside of the chip.

Description

本発明はオペアンプに関し、位相補償回路を接続することで、広帯域で安定動作できるようにすることを目的とする。The present invention relates to an operational amplifier, and an object thereof is to enable a stable operation in a wide band by connecting a phase compensation circuit.

オペアンプのＤＣゲインやユニティゲイン周波数、位相余裕などの各指標はトレードオフの関係にある。半導体集積回路のチップ面積や消費電流を考慮したうえで、ゲインや周波数帯域を広げたい場合は、どうしても位相余裕が悪化し、安定動作の面で不安が出る。つまり最悪の場合、発振する危険が出る。Each index such as DC gain, unity gain frequency, and phase margin of the operational amplifier has a trade-off relationship. In consideration of the chip area and current consumption of the semiconductor integrated circuit, when it is desired to widen the gain and frequency band, the phase margin inevitably deteriorates, and there is anxiety in terms of stable operation. In other words, in the worst case, there is a risk of oscillation.

そこで位相補償を行い、位相余裕を改善する方法が取られる。一般的には２段オペアンプの場合は、１段目の出力と２段目の入力の間に、容量、容量と抵抗を接続する方法が取られる。Therefore, a method is adopted in which phase compensation is performed to improve the phase margin. In general, in the case of a two-stage operational amplifier, a method of connecting a capacitor, a capacitor and a resistor between the output of the first stage and the input of the second stage is taken.

また、出力端子とグラウンド間に、容量または容量と抵抗を接続する方法もある。There is also a method of connecting a capacitor or a capacitor and a resistor between the output terminal and the ground.

特許文献１や非特許文献１には、２段オペアンプの位相補償回路が開示されているが、１段オペアンプについてはもともと高安定なため、あまり位相補償回路が提案されていない。しかし広帯域での動作を考えた場合、１段オペアンプの性能を出し切って、位相補償したほうが望ましい場合もある。
特開２００９−５５５４７号公報谷口研二著ＣＭＯＳアナログ回路入門ＣＱ出版社ｐ１８６〜ｐ１８９ Patent Document 1 and Non-Patent Document 1 disclose a phase compensation circuit of a two-stage operational amplifier. However, since a single-stage operational amplifier is originally highly stable, few phase compensation circuits have been proposed. However, considering the operation in a wide band, it may be desirable to perform the phase compensation by taking out the performance of the one-stage operational amplifier.
JP 2009-55547 A Kenji Taniguchi Introduction to CMOS Analog Circuits CQ Publishing Company p186-p189

１段オペアンプの場合は、１段目の出力と、２段目の入力の間に位相補償をする方法は論理的に採用できない。また出力端子とグラウンド間に位相補償する方法もまだ一般的な設計方法として、確立されていない。In the case of a one-stage operational amplifier, the method of phase compensation between the output of the first stage and the input of the second stage cannot be logically adopted. A method for phase compensation between the output terminal and the ground has not yet been established as a general design method.

また多段オペアンプでも、一般的に、回路の外部に容量または容量と抵抗を電源ラインに接続して、ノイズ対策や位相補償を行っている。Also in a multi-stage operational amplifier, generally, a capacitor or a capacitor and a resistor are connected to a power supply line outside the circuit to take measures against noise and phase compensation.

そこで、負の入力端子と出力端子の間に、直列にＲｃ１とＲｃ２を、Ｒｃ１とＲｃ２の間のノードと正の入力端子の間にＣｃ１を、正の入力端子とグラウンド端子の間に位相補償容量Ｃｃ２をつなぐ位相補償回路を提案する。Therefore, Rc1 and Rc2 are connected in series between the negative input terminal and the output terminal, Cc1 is connected between the node between Rc1 and Rc2 and the positive input terminal, and phase compensation is performed between the positive input terminal and the ground terminal. A phase compensation circuit connecting the capacitor Cc2 is proposed.

オペアンプに新規な位相補償回路をつなげることで、今までにない広帯域のオペアンプを実現できる。By connecting a new phase compensation circuit to the operational amplifier, an unprecedented wideband operational amplifier can be realized.

また、オペアンプ外部に位相補償端子を設けることで、オペアンプの使用状況に応じて、位相補償することもできる。In addition, by providing a phase compensation terminal outside the operational amplifier, phase compensation can be performed according to the operational status of the operational amplifier.

本発明は特許請求の範囲により定義され、実施例に限定されるものではない。したがって、オペアンプの回路の外部であろうと内部であろうと、同様に位相補償でき、また既存の回路に事後的に位相補償を施すことも出来る。さらにあらゆる種類のオペアンプに適用可能である。The invention is defined by the claims and is not limited to the examples. Therefore, the phase compensation can be performed in the same manner whether the circuit is outside or inside the operational amplifier circuit, and the phase compensation can be applied to the existing circuit later. Furthermore, it can be applied to all kinds of operational amplifiers.

ＣＭＯＳプロセスでのシンメトリカルオペアンプを例に、この回路構成の効果を以下に示す。図１の回路で、電源電圧を１．８Ｖ、負荷容量を１０ｐＦとして解析したときの結果を示す。ＡＣ解析の結果、ＤＣゲイン４０．７ｄＢ、位相余裕５．５度、ＧＢＷ６４６ＭＨｚである。そのときの波形を図２に示す。したがってもうちょっと位相余裕が欲しいと考える。The effect of this circuit configuration will be described below by taking a symmetrical operational amplifier in a CMOS process as an example. The result when the power supply voltage is 1.8 V and the load capacitance is 10 pF in the circuit of FIG. 1 is shown. As a result of AC analysis, the DC gain is 40.7 dB, the phase margin is 5.5 degrees, and GBW 646 MHz. The waveform at that time is shown in FIG. Therefore, we want a little more phase margin.

そこで、図３のように、負の入力端子と出力端子の間に、直列にＲｃ１とＲｃ２を、Ｒｃ１とＲｃ２の間のノードと正の入力端子の間にＣｃ１を、正の入力端子とグラウンド端子の間に位相補償容量Ｃｃ２をつなぐ。これはＲｃ１、Ｒｃ２、Ｃｃ１、Ｃｃ２がローパスフィルタの受動素子としてはたらくことで、位相補償できるように構成している。Therefore, as shown in FIG. 3, Rc1 and Rc2 are connected in series between the negative input terminal and the output terminal, Cc1 is connected between the node between Rc1 and Rc2 and the positive input terminal, and the positive input terminal and the ground. A phase compensation capacitor Cc2 is connected between the terminals. This is configured so that phase compensation is possible by Rc1, Rc2, Cc1, and Cc2 acting as passive elements of the low-pass filter.

この回路のＡＣ解析の結果、ＤＣゲイン４０．０ｄＢ、位相余裕４５．３度、ＧＢＷ５００．９ＭＨｚである。そのときの波形を図４に示す。As a result of AC analysis of this circuit, the DC gain is 40.0 dB, the phase margin is 45.3 degrees, and GBW is 500.9 MHz. The waveform at that time is shown in FIG.

図１と同じ回路構成で、位相補償回路をオペアンプの外部に接続した回路を図５に示す。FIG. 5 shows a circuit in which the phase compensation circuit is connected to the outside of the operational amplifier with the same circuit configuration as FIG.

提案する回路でＤＣ解析を行なってみると、同相入力電圧範囲が０．２〜１．１５Ｖで、消費電流が５．４ｍＡとなる。そのときの波形を図６に示す。When DC analysis is performed with the proposed circuit, the common-mode input voltage range is 0.2 to 1.15 V, and the current consumption is 5.4 mA. The waveform at that time is shown in FIG.

パルスを与えて、ＴＲＡＮＳＩＥＮＴ解析を行なってみると、立ち上がりスルーレートは９１．６Ｖ／ｕＳ、立下りスルーレートは１００Ｖ／ｕＳとなり、きれいな波形を示している。そのときの波形を図７に示す。When a TRANSIENT analysis is performed by applying a pulse, the rising slew rate is 91.6 V / uS and the falling slew rate is 100 V / uS, indicating a clean waveform. The waveform at that time is shown in FIG.

Ｃｃ１とＣｃ２は同じ容量値で、製造プロセスや回路構成にもよるが、数ピコファラドでそれほどの半導体集積回路のチップ面積の増大や、寄生容量の増大にもつながらない。また、Ｒｃ１とＲｃ２の比で、回路の利得が変わってくるが、こちらも製造上実現可能な値となる。したがって効果的な回路構成だといえるCc1 and Cc2 have the same capacitance value, which depends on the manufacturing process and circuit configuration, but with a few picofarads, the increase in the chip area of the semiconductor integrated circuit and the increase in parasitic capacitance do not occur. Further, the gain of the circuit varies depending on the ratio of Rc1 and Rc2, but this is also a value that can be realized in manufacturing. Therefore, it can be said that it is an effective circuit configuration.

本発明の前提となる、位相補償の無い回路図。The circuit diagram without phase compensation which is a premise of the present invention. 図１の回路のＡＣ解析結果の波形。The waveform of the AC analysis result of the circuit of FIG. 本発明の第１の実施の形態にかかる回路図。1 is a circuit diagram according to a first embodiment of the present invention. 図３の回路のＡＣ解析結果の波形。The waveform of the AC analysis result of the circuit of FIG. 本発明の第２の実施の形態にかかる回路図。The circuit diagram concerning the 2nd Embodiment of this invention. 図１の回路のＤＣ解析結果の波形。The waveform of the DC analysis result of the circuit of FIG. 図１の回路のＴＲＡＮＳＩＥＮＴ解析結果の波形。The waveform of the TRANSIENT analysis result of the circuit of FIG.

Ｃｃ１・・・位相補償容量１
Ｃｃ２・・・位相補償容量２
Ｒｃ１・・・位相補償抵抗１
Ｒｃ２・・・位相補償抵抗２
Ｖｉｎｎ・・・負の入力端子
Ｖｉｎｐ・・・正の入力端子
Ｖｏｕｔ・・・出力端子
Ａ・・・位相補償端子
Ｂ・・・位相補償端子
Ｃ・・・位相補償端子Cc1 Phase compensation capacity 1
Cc2 Phase compensation capacity 2
Rc1 ... Phase compensation resistor 1
Rc2: Phase compensation resistor 2
Vinn ... Negative input terminal Vinp ... Positive input terminal Vout ... Output terminal A ... Phase compensation terminal B ... Phase compensation terminal C ... Phase compensation terminal

Claims

オペアンプの、負の入力端子と出力端子の間に、直列にＲｃ１とＲｃ２を、Ｒｃ１とＲｃ２の間のノードと正の入力端子の間にＣｃ１を、正の入力端子とグラウンド端子の間にＣｃ２を、つないだことを特徴とするオペアンプ。Rc1 and Rc2 in series between the negative input terminal and the output terminal of the operational amplifier, Cc1 between the node between Rc1 and Rc2 and the positive input terminal, and Cc2 between the positive input terminal and the ground terminal An operational amplifier characterized by connecting

オペアンプの、負の入力端子と出力端子の間に、直列にＲｃ１とＲｃ２を、Ｒｃ１とＲｃ２の間のノードと正の入力端子の間にＣｃ１を、正の入力端子とグラウンド端子の間にＣｃ２を、つなぐことを特徴とするオペアンプの位相補償方法。Rc1 and Rc2 in series between the negative input terminal and the output terminal of the operational amplifier, Cc1 between the node between Rc1 and Rc2 and the positive input terminal, and Cc2 between the positive input terminal and the ground terminal A phase compensation method for an operational amplifier characterized by connecting the two.

オペアンプの位相補償端子Ａ（負の入力端子と同じノード）、位相補償端子Ｂ（正の入力端子と同じノード）、位相補償端子Ｃ（出力端子と同じノード）を設け、ＡとＣの間に直列にＲｃ１とＲｃ２を、Ｒｃ２とＲｃ１の間のノードとＢの間にＣｃ１を、Ｂとグラウンドの間にＣｃ２をつないだことを特徴とする、外付けのオペアンプ位相補償回路。An operational amplifier phase compensation terminal A (same node as negative input terminal), phase compensation terminal B (same node as positive input terminal), and phase compensation terminal C (same node as output terminal) are provided. An external operational amplifier phase compensation circuit, wherein Rc1 and Rc2 are connected in series, Cc1 is connected between B and a node between Rc2 and Rc1, and Cc2 is connected between B and ground.