JP2011009740A - 半導体デバイスのための電力グリッド構造体及びその製造方法 - Google Patents
半導体デバイスのための電力グリッド構造体及びその製造方法 Download PDFInfo
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Abstract
【解決手段】 本発明の一実施形態は、誘電体層の内部に形成された第1の導電性材料のスタッドと、底部及び側壁を有する第2の導電性材料のビアであって、底部及び側壁は導電性ライナで覆われ、底部はスタッドの直接上に形成され、かつ、導電性ライナを通してビアと接触した状態にある、ビアと、ビアの側壁において導電性ライナを通してビアに接続する第3の導電性材料の1つ又は複数の導電性パスとを含むことができる半導体構造体を提供する。半導体構造体を製造する方法も提供される。
【選択図】 図12
Description
101、201:基板
102、202:半導体デバイス
111、211、214、232:層間誘電体層(ILD層)
112、212:導電性スタッド
121、213、221、241:導電性ライナ
122、222、301、302:導電性パス
131、231:誘電体キャッピング層
233、251、256:ビア孔
242:導電性ビア
291:レジスト層
292:ビア・パターン
300:電力グリッド
311:交差点
501:ビア孔の組
502:SEM図
Claims (18)
- 誘電体層の内部に形成された第1の導電性材料のスタッドと、
底部及び側壁を有する第2の導電性材料のビアであって、前記底部及び前記側壁は導電性ライナで覆われ、前記底部は、前記スタッドの直接上に形成され、かつ、前記導電性ライナを通して前記ビアと接触した状態にあるビアと、
前記ビアの前記側壁における前記導電性ライナを通して前記ビアに接続する第3の導電性材料の1つ又は複数の導電性パスと、
を備える半導体構造体。 - 前記ビアの前記第2の導電性材料の導電率は、前記底部及び前記側壁において前記ビアを覆う前記導電性ライナの導電率より大きい、請求項1に記載の半導体構造体。
- 互いに対向する2つの前記側壁によって測定された前記ビアの横方向寸法は、ブレック長さより短く、前記ブレック長さは、前記ビアの内部の金属原子のエレクトロマイグレーションと関連付けられ、かつ、前記ビアの前記第2の導電性材料の特性に少なくとも部分的に影響を受ける、請求項2に記載の半導体構造体。
- 前記第2の導電性材料は銅(Cu)であり、前記銅材料の前記ビアの内部の前記ブレック長さは、10マイクロメートルである、請求項3に記載の半導体構造体。
- 前記第1の導電性材料及び前記第2の導電性材料は、タングステン(W)、アルミニウム(Al)、銅(Cu)、及びそれらの合金からなる群から選択され、前記第3の導電性材料は、アルミニウム(Al)、銅(Cu)、銀(Ag)、金(Au)、及びそれらの合金からなる群から選択される、請求項3に記載の半導体構造体。
- 前記導電性ライナは、チタン(Ti)、タンタル(Ta)、ルテニウム(Ru)、タングステン(W)、窒化チタン(TiN)、窒化タンタル(TaN)、窒化ルテニウム(RuN)、及び窒化タングステン(WN)からなる群から選択される材料で作製され、前記導電性ライナは、導電性材料がそこを通って拡散するのを防ぐことができる、請求項1に記載の半導体構造体。
- 前記スタッドは、前記誘電体層の下にある基板内に形成された半導体デバイスのコンタクト位置の直接上に形成され、前記半導体デバイスは、電界効果トランジスタであり、前記コンタクト位置は前記電界効果トランジスタのゲート領域、ソース領域、又はドレイン領域である、電界効果トランジスタであるか、或いは、ヘテロ接合バイポーラ・トランジスタであり、前記コンタクト位置は前記ヘテロ接合バイポーラ・トランジスタのベース領域、エミッタ領域、又はコレクタ領域である、請求項1に記載の半導体構造体。
- 複数の半導体デバイスの上に形成された誘電体層と、
前記誘電体層の内部に形成され、かつ、前記複数の半導体デバイスの上に位置する複数の導電性スタッドと、
前記複数の導電性スタッドの1つの上に形成され、底部及び側壁が導電性ライナで覆われている少なくとも1つのビアと、
前記導電性ライナを通して前記ビアに接続する1つ又は複数の導電性パスと、
を備える電力グリッド。 - 前記複数の導電性スタッドは、第1の導電率を有する第1の導電性材料から形成され、前記ビアは、第2の導電率を有する第2の導電性材料から形成され、前記1つ又は複数の導電性パスは、第3の導電率を有する第3の導電性材料から形成され、前記第2の導電率は、前記ビアの前記底部及び前記側壁を覆う前記導電性ライナの導電率より大きい、請求項8に記載の電力グリッド。
- 互いに対向する2つの前記側壁によって測定された前記ビアの横方向寸法は、ブレック長さより短く、前記ブレック長さは、前記ビアの内部の金属原子のエレクトロマイグレーションと関連付けられ、かつ、前記ビアの前記第2の導電性材料の特性に少なくとも部分的に影響を受ける、請求項9に記載の電力グリッド。
- 第1の誘電体層の内部に導電性スタッドを形成するステップと、
前記第1の誘電体層の上にある第2の誘電体層の内部に1つ又は複数の導電性パスを形成するステップであって、前記1つ又は複数の導電性パスは、前記導電性スタッドの上面の上に残っている前記第2の誘電体層の領域に実質的に近接している、ステップと、
前記導電性スタッドの前記上面の上にビア孔を形成し、前記導電性スタッドの前記上面を露出させるステップであって、前記ビア孔は、前記1つ又は複数の導電性パスの側壁の少なくとも一部を露出させる、ステップと、
前記ビア孔の底部及び側壁において導電性ライナを堆積させるステップと、
前記ビア孔内に導電性材料を堆積してビアを形成するステップであって、前記ビアは前記導電性ライナを介して前記1つ又は複数の導電性パスと接触した状態にある、ステップと、
を含む方法。 - 前記導電性スタッドを形成するステップは、前記第1の誘電体層の下にある半導体基板内に生成された半導体デバイスのコンタクト位置の上に、これと接触した状態で前記導電性スタッドを形成するステップを含む、請求項11に記載の方法。
- 前記ビア孔内に前記導電性材料を堆積させるステップは、前記導電性ライナの導電率より小さい導電率を有する前記導電性材料を選択するステップと、前記ビア孔内に前記選択された導電性材料を堆積させるステップとを含む、請求項11に記載の方法。
- 前記1つ又は複数の導電性パス及び前記第2の誘電体層の上に第3の誘電体層を堆積させるステップをさらに含み、前記ビア孔を形成するステップは、前記第3の誘電体層及び前記第2の誘電体層内に前記ビア孔を形成するステップをさらに含む、請求項11に記載の方法。
- 前記ビア孔を形成するステップは、前記第3の誘電体層内に前記ビア孔の部分を形成するステップをさらに含み、前記第3の誘電体層内の前記ビア孔の前記部分は、前記導電性スタッドの前記上面の上に残っている前記第2の誘電体層の前記部分と少なくとも同じくらい大きく、かつ、これと実質的に重なり、前記導電性スタッドの前記上面の上に残っている前記第2の誘電体層の前記部分は、前記ビア孔を形成する際に実質的に除去される、請求項14に記載の方法。
- 前記導電性スタッドの前記上面の上の前記領域は、前記導電性材料で作製された前記ビアのブレック長さより短い横方向寸法を有する、請求項11に記載の方法。
- 前記ビアは銅(Cu)で作製され、10マイクロメートルのブレック長さを有する、請求項11に記載の方法。
- 前記導電性ライナは、チタン(Ti)、タンタル(Ta)、ルテニウム(Ru)、タングステン(W)、窒化チタン(TiN)、窒化タンタル(TaN)、窒化ルテニウム(RuN)、及び窒化タングステン(WN)からなる群から選択される材料で作製され、前記導電性ライナは、導電性材料がそこを通って拡散するのを防ぐことができる、請求項11に記載の方法。
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Also Published As
Publication number | Publication date |
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KR20100138752A (ko) | 2010-12-31 |
CN101930965A (zh) | 2010-12-29 |
CN101930965B (zh) | 2013-06-12 |
US8164190B2 (en) | 2012-04-24 |
JP5782232B2 (ja) | 2015-09-24 |
US20120100712A1 (en) | 2012-04-26 |
US8349723B2 (en) | 2013-01-08 |
US20100327445A1 (en) | 2010-12-30 |
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