JP2010511299A - 二重ライナ・キャッピング層の相互接続構造の半導体デバイス及びその製造方法 - Google Patents
二重ライナ・キャッピング層の相互接続構造の半導体デバイス及びその製造方法 Download PDFInfo
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
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- CNCZOAMEKQQFOA-HZQGBTCBSA-N 4-[(2s,3s,4r,5r,6r)-4,5-bis(3-carboxypropanoyloxy)-2-methyl-6-[[(2r,3r,4s,5r,6s)-3,4,5-tris(3-carboxypropanoyloxy)-6-[2-(3,4-dihydroxyphenyl)-5,7-dihydroxy-4-oxochromen-3-yl]oxyoxan-2-yl]methoxy]oxan-3-yl]oxy-4-oxobutanoic acid Chemical compound OC(=O)CCC(=O)O[C@@H]1[C@H](OC(=O)CCC(O)=O)[C@@H](OC(=O)CCC(O)=O)[C@H](C)O[C@H]1OC[C@@H]1[C@@H](OC(=O)CCC(O)=O)[C@H](OC(=O)CCC(O)=O)[C@@H](OC(=O)CCC(O)=O)[C@H](OC=2C(C3=C(O)C=C(O)C=C3OC=2C=2C=C(O)C(O)=CC=2)=O)O1 CNCZOAMEKQQFOA-HZQGBTCBSA-N 0.000 claims description 3
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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Abstract
【解決手段】 Cu/誘電体の界面におけるCu移動および原子ボイド形成を低減させるために、Cu相互接続の上に高い引っ張り応力のキャッピング層を設ける。引っ張り応力の高い誘電膜は、薄い誘電体材料を多層に堆積することによって形成する。これらの層は各々、厚さが約50オングストローム(5nm)未満である。各誘電体層にプラズマ処理を行った後に、これに続く各誘電体層を堆積することで、誘電体キャップが内部引っ張り応力を有するようにする。
【選択図】 図2
Description
Claims (17)
- 半導体デバイスであって、
少なくとも1つの導電性相互接続部が部分的に埋め込まれた誘電体層と、
前記少なくとも1つの導電性相互接続部に接触している引っ張りキャッピング層と、
を含む、半導体デバイス。 - 前記誘電体層に接触している圧縮キャッピング層を更に含む、請求項1に記載の半導体デバイス。
- 前記少なくとも1つの導電性相互接続部を部分的に囲む拡散バリア層を更に含む、請求項1に記載の半導体デバイス。
- 前記引っ張りキャッピング層が順次堆積した層から成る、請求項1に記載の半導体デバイス。
- 前記引っ張りキャッピング層が、二酸化シリコン(SiO2)、窒化シリコン(Si3N4)、およびSiCxNyHz等のシリコン化合物から成る群から選択された材料から成り、x、y、zは可変の比率である、請求項1に記載の半導体デバイス。
- 前記少なくとも1つの導電性相互接続部が、アルミニウム、銅、タングステン、銀、金、アルミニウム−銅、およびニッケルから成る群から選択された材料から成る、請求項1に記載の半導体デバイス。
- 前記拡散バリア層が、Ta、TaN、Ti、TiN、Ru、RuN、RuTa、RuTaN、W、およびWNから成る群から選択された材料から成る、請求項3に記載の半導体デバイス。
- 半導体デバイスを形成するための方法であって、
少なくとも1つの導電性相互接続部が部分的に埋め込まれた誘電体層を設けるステップと、
前記誘電体層および前記少なくとも1つの導電性相互接続部の上に引っ張りキャッピング層を堆積するステップと、
前記引っ張りキャッピング層にプラズマ処理を行うステップと、
前記誘電体層上にある前記引っ張りキャッピング層の部分を除去するステップと、
前記引っ張りキャッピング層および前記誘電体層の上に圧縮キャッピング層を堆積するステップと、
前記引っ張りキャッピング層から前記圧縮キャッピング層を除去するステップと、
を含む、方法。 - 半導体デバイスを形成するための方法であって、
少なくとも1つの導電性相互接続部が部分的に埋め込まれた誘電体層を設けるステップと、
前記誘電体層および前記少なくとも1つの導電性相互接続部の上に圧縮キャッピング層を堆積するステップと、
前記少なくとも1つの導電性相互接続部の上にある前記圧縮キャッピング層の部分を除去するステップと、
前記圧縮キャッピング層および前記少なくとも1つの導電性相互接続部の上に引っ張りキャッピング層を堆積するステップと、
前記圧縮キャッピング層から前記引っ張りキャッピング層を除去するステップと、
を含む、方法。 - 前記引っ張りキャッピング層が、圧力が7トール(933Pa)、温度が400℃、高周波電力が600ワット、低周波電力が0ワットの化学気相堆積によって堆積される、請求項8または9に記載の方法。
- 前記化学気相堆積が、SiH4が150sccm、N2が8,000sccm、NH3が2,500sccmのガス組成および流量を含む、請求項10に記載の方法。
- 前記引っ張りキャッピング層が、二酸化シリコン、窒化シリコン、ならびに、SiCxNyHzの形態のシリコン、炭素、窒素、および水素の化合物から成る群から選択された誘電体材料であり、x、y、zは可変の比率である、請求項8または9に記載の方法。
- 前記プラズマ処理が、圧力が5トール(667Pa)、温度が400℃、高周波電力が500ワット、低周波電力が0ワットで行われる、請求項8または9に記載の方法。
- 前記プラズマ処理が、40秒間でN2が8,000sccmのガス組成および流量を含む、請求項13に記載の方法。
- 前記引っ張りキャッピング層および前記プラズマ処理がインシチューで実施される、請求項8または9に記載の方法。
- 前記圧縮キャッピング層が、化学機械研磨によって前記引っ張りキャッピング層から除去される、請求項8または9に記載の方法。
- 前記引っ張りキャッピング層が、少なくとも2回の順次堆積およびプラズマ処理ステップによって前記誘電体層および前記少なくとも1つの導電性相互接続部の上に堆積された多層堆積キャッピング層である、請求項8または9に記載の方法。
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US11/564,314 US7576003B2 (en) | 2006-11-29 | 2006-11-29 | Dual liner capping layer interconnect structure and method |
US11/564,314 | 2006-11-29 | ||
PCT/EP2007/061481 WO2008064963A1 (en) | 2006-11-29 | 2007-10-25 | Dual liner capping layer interconnect structure |
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JP2016207945A (ja) * | 2015-04-27 | 2016-12-08 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
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US7625815B2 (en) * | 2006-10-31 | 2009-12-01 | International Business Machines Corporation | Reduced leakage interconnect structure |
US8178436B2 (en) * | 2006-12-21 | 2012-05-15 | Intel Corporation | Adhesion and electromigration performance at an interface between a dielectric and metal |
US7858532B2 (en) * | 2007-08-06 | 2010-12-28 | United Microelectronics Corp. | Dielectric layer structure and manufacturing method thereof |
US7687877B2 (en) * | 2008-05-06 | 2010-03-30 | International Business Machines Corporation | Interconnect structure with a mushroom-shaped oxide capping layer and method for fabricating same |
US8362596B2 (en) * | 2009-07-14 | 2013-01-29 | International Business Machines Corporation | Engineered interconnect dielectric caps having compressive stress and interconnect structures containing same |
US8299365B2 (en) * | 2010-01-07 | 2012-10-30 | International Business Machines Corporation | Self-aligned composite M-MOx/dielectric cap for Cu interconnect structures |
US9373584B2 (en) | 2011-11-04 | 2016-06-21 | Intel Corporation | Methods and apparatuses to form self-aligned caps |
US9431235B1 (en) | 2015-04-24 | 2016-08-30 | International Business Machines Corporation | Multilayer dielectric structures with graded composition for nano-scale semiconductor devices |
KR102592471B1 (ko) * | 2016-05-17 | 2023-10-20 | 에이에스엠 아이피 홀딩 비.브이. | 금속 배선 형성 방법 및 이를 이용한 반도체 장치의 제조 방법 |
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Citations (4)
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EP2092559A1 (en) | 2009-08-26 |
US20080122045A1 (en) | 2008-05-29 |
US20080290519A1 (en) | 2008-11-27 |
KR20090085066A (ko) | 2009-08-06 |
KR101126850B1 (ko) | 2012-03-23 |
WO2008064963A1 (en) | 2008-06-05 |
US7709960B2 (en) | 2010-05-04 |
US20080293257A1 (en) | 2008-11-27 |
US7772119B2 (en) | 2010-08-10 |
JP5325113B2 (ja) | 2013-10-23 |
US7576003B2 (en) | 2009-08-18 |
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