JP2010205887A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2010205887A
JP2010205887A JP2009049128A JP2009049128A JP2010205887A JP 2010205887 A JP2010205887 A JP 2010205887A JP 2009049128 A JP2009049128 A JP 2009049128A JP 2009049128 A JP2009049128 A JP 2009049128A JP 2010205887 A JP2010205887 A JP 2010205887A
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wiring board
semiconductor device
stiffener
resin
semiconductor chip
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JP5245917B2 (en
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Akane Kobayashi
茜 小林
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Toppan Inc
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Toppan Printing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device in a semiconductor device of the type having a thin wiring board with a semiconductor chip mounted thereon. <P>SOLUTION: The semiconductor device characterized in that the wiring board includes a stiffener and a region between the semiconductor chip and the stiffener on the wiring board is filled with a protective resin of an elastic modulus of at least 0.5 MPa and not more than 10 MPa. As the protective resin, a material selected from a silicone resin and an urethane resin is used. The thickness of the wiring board is at least 0.05 mm and not more than 0.6 mm. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、配線基板、半導体パッケージあるいは機能モジュール等の半導体装置に関する。   The present invention relates to a semiconductor device such as a wiring board, a semiconductor package, or a functional module.

近年、絶縁層に樹脂フィルムを用いた配線基板が多く用いられるようになった。絶縁フィルムを用いた配線基板は、基板全体の厚みを抑えることが出来る点で大変優れている。しかし、薄い基板は反りが生じやすく、また反りによって半導体チップの実装時に不具合が発生する恐れがある。   In recent years, many wiring boards using a resin film as an insulating layer have come to be used. A wiring board using an insulating film is very excellent in that the thickness of the entire board can be suppressed. However, a thin substrate is likely to warp, and the warpage may cause a problem when the semiconductor chip is mounted.

薄型の配線基板の補強として、スティフナを貼り付ける方法が知られている（特許文献１)。スティフナを貼り付けることにより、基板全体の反りを低下させることができる。このスティフナ付き配線基板には、半導体チップとスティフナの間に薄型の配線基板のみの部分が存在する。薄型の配線基板のみの部分は半導体チップ、スティフナ等の剛性の高い材料に保持されていないため、これらの部分と比較して強度が低い。温度サイクル等の負荷をかけた際に、応力が薄型の配線基板のみの部分に集中する恐れがある。   As a reinforcement of a thin wiring board, a method of attaching a stiffener is known (Patent Document 1). By attaching the stiffener, the warpage of the entire substrate can be reduced. In this wiring board with a stiffener, only a thin wiring board exists between the semiconductor chip and the stiffener. Since only the thin wiring board is not held by a highly rigid material such as a semiconductor chip or a stiffener, the strength is lower than these parts. When a load such as a temperature cycle is applied, the stress may concentrate on only the thin wiring board.

スティフナと薄型の配線基板の間の強度を高める方法として、補強樹脂を充填する方法（特許文献２）、第二のスティフナを配置する方法が報告されている(特許文献３)。補強樹脂および第二のスティフナを固定する樹脂にはエポキシ樹脂が用いられている。   As a method for increasing the strength between the stiffener and the thin wiring board, a method of filling a reinforcing resin (Patent Document 2) and a method of arranging a second stiffener have been reported (Patent Document 3). An epoxy resin is used as the resin for fixing the reinforcing resin and the second stiffener.

特開平１１−２８４０９７号公報JP-A-11-284097 特開２０００−１３３７４１号公報Japanese Patent Laid-Open No. 2000-133741 特開２００７−２２７５５０号公報JP 2007-227550 A

薄型の配線基板の半導体チップとスティフナの間を埋めるためには、エポキシ樹脂等の熱硬化樹脂は、弾性率が高く変形しにくいために適さない。弾性率が高い樹脂で補強すると、温度サイクル等による熱膨張などに耐え切れず、クラック等が発生する恐れがあるからである。そこで本発明では、弾性率が低く変形しやすい樹脂を用いて半導体チップとスティフナの間を埋め、柔軟性を有しながら配線基板を保護することが可能となる、信頼性の優れた半導体装置を提供することを目的とする。   In order to fill the gap between the semiconductor chip and the stiffener on the thin wiring board, a thermosetting resin such as an epoxy resin is not suitable because it has a high elastic modulus and is not easily deformed. This is because if the resin is reinforced with a resin having a high elastic modulus, it cannot withstand thermal expansion due to a temperature cycle or the like, and there is a possibility that cracks or the like may occur. Therefore, in the present invention, a highly reliable semiconductor device that can fill a gap between a semiconductor chip and a stiffener using a resin having low elasticity and easily deforms, and can protect a wiring board while having flexibility. The purpose is to provide.

上記の課題を解決するために、本発明は、半導体チップの搭載された導電パターンを有する配線基板において、該配線基板はスティフナを具備しており、かつ、前記配線基板の上の半導体チップとスティフナの間の領域に弾性率が０．５ＭＰａ以上１０ＭＰａ以下の保護樹脂を充填したことを特徴とする半導体装置である。   In order to solve the above problems, the present invention provides a wiring board having a conductive pattern on which a semiconductor chip is mounted, the wiring board including a stiffener, and the semiconductor chip and the stiffener on the wiring board. A semiconductor device characterized in that a protective resin having an elastic modulus of 0.5 MPa or more and 10 MPa or less is filled in a region between the layers.

また、本発明は、上記配線基板の厚さが０．０５ｍｍ以上０．６ｍｍ以下であることを特徴とする上記の半導体装置である。   The present invention is the above semiconductor device, wherein the wiring board has a thickness of 0.05 mm to 0.6 mm.

また、本発明は、上記保護樹脂が、シリコーン樹脂、ウレタン樹脂から選択された材料であることを特徴とする上記の半導体装置である。   The present invention is the above semiconductor device, wherein the protective resin is a material selected from a silicone resin and a urethane resin.

また、本発明は、上記保護樹脂の厚さが６０μｍ以上であることを特徴とする上記の半導体装置である。   The present invention is the above semiconductor device, wherein the protective resin has a thickness of 60 μm or more.

また、本発明は、上記半導体チップと上記配線基板が、フリップチップ接続されていることを特徴とする上記の半導体装置である。   The present invention is the above semiconductor device, wherein the semiconductor chip and the wiring board are flip-chip connected.

半導体チップとスティフナの間を弾性率の低い樹脂で満たすことによって、柔軟性を有しながら配線基板を保護することが可能となり、信頼性が高い配線基板、半導体パッケージ、あるいは機能モジュール等となる。   By filling the space between the semiconductor chip and the stiffener with a resin having a low elastic modulus, the wiring board can be protected while having flexibility, and a highly reliable wiring board, semiconductor package, or functional module is obtained.

本発明の一実施の形態における半導体装置を示す模式断面図である。1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment of the present invention. 本発明の半導体装置の製造方法の一例を説明する模式断面図である。It is a schematic cross section explaining an example of a method for manufacturing a semiconductor device of the present invention. 本発明の一実施の形態における半導体装置を示す模式断面図である。1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

本発明の半導体装置１０１は、図１（a）に示されるように、半導体チップ１０４が配線基板１０２に搭載され、基板の外周部にスティフナ１０６を貼り付け、配線基板１０２上の、半導体チップ１０４とスティフナ１０６の間の領域に保護樹脂１０８を充填したことを特徴とする半導体装置１０１である。   In the semiconductor device 101 of the present invention, as shown in FIG. 1A, a semiconductor chip 104 is mounted on a wiring board 102, a stiffener 106 is attached to the outer periphery of the board, and the semiconductor chip 104 on the wiring board 102 is placed. The semiconductor device 101 is characterized in that a protective resin 108 is filled in a region between the stiffener 106 and the stiffener 106.

本発明の半導体装置１０１では、配線基板１０２上の、半導体チップ１０４とスティフナ１０６の間の領域に保護樹脂１０８を充填することにより、温度サイクル等の負荷がかかった際の半導体装置構成材料の伸縮が緩和され、信頼性を向上させることができる。この効果は特に配線基板１０２が薄い場合に有効である。具体的には、配線基板１０２の厚さが０．０５ｍｍ以上０．６ｍｍ以下のときに特に有効である。０．０５ｍｍ以下であると、配線基板１０２が薄すぎるために保護樹脂１０８による効果が弱く、０．６ｍｍ以上であると、保護樹脂１０８を用いる必要がなくなる。配線基板１０２を薄くすることにより、高密度化、軽量化が期待できる。   In the semiconductor device 101 of the present invention, the region between the semiconductor chip 104 and the stiffener 106 on the wiring substrate 102 is filled with the protective resin 108 so that the semiconductor device constituent material expands and contracts when a load such as a temperature cycle is applied. Can be relaxed and reliability can be improved. This effect is particularly effective when the wiring board 102 is thin. Specifically, it is particularly effective when the thickness of the wiring board 102 is 0.05 mm or more and 0.6 mm or less. If it is 0.05 mm or less, the effect of the protective resin 108 is weak because the wiring substrate 102 is too thin, and if it is 0.6 mm or more, it is not necessary to use the protective resin 108. By reducing the thickness of the wiring board 102, high density and light weight can be expected.

配線基板１０２は、ポリイミド等の絶縁樹脂層と銅などの導体層からなる。絶縁樹脂層には、エポキシ系樹脂等を用いることも可能である。導電パターンを一層のみ有する片面配線基板、導電パターンを二層有する両面配線基板、多層の導電パターンを持つ多層配線基板のいずれも使用可能である。配線基板１０２は、図３のように第二の配線基板１１０とはんだボール１１１等を介して接続するための外部接続端子（パッド）を有している。   The wiring board 102 includes an insulating resin layer such as polyimide and a conductor layer such as copper. An epoxy resin or the like can also be used for the insulating resin layer. Any of a single-sided wiring board having only one conductive pattern, a double-sided wiring board having two conductive patterns, and a multilayer wiring board having multiple conductive patterns can be used. The wiring board 102 has external connection terminals (pads) for connecting to the second wiring board 110 via the solder balls 111 and the like as shown in FIG.

スティフナ１０６には銅、銅の合金、ステンレス、アルミニウム、４２アロイ等の金属あるいは、樹脂、セラミック等を用いることができる。スティフナ接着剤１０７にはエポキシ系樹脂の接着剤などの公知の接着剤を用いればよい。   The stiffener 106 can be made of metal such as copper, copper alloy, stainless steel, aluminum, 42 alloy, resin, ceramic, or the like. A known adhesive such as an epoxy resin adhesive may be used for the stiffener adhesive 107.

保護樹脂１０８には、弾性率が０．５ＭＰａ以上１０ＭＰａ以下の範囲の樹脂を用いることが好ましい。これにより、温度サイクル等における半導体装置構成材料の伸縮を緩和しながら、さらに配線基板１０２を保護することが可能となる。弾性率が０．５ＭＰａ以下だと、容易に変形できるために、保護樹脂１０８としての効力が十分でない。また、弾性率が１０ＭＰａ以上であると、温度サイクル等の負荷をかけた際、半導体装置構成材料の伸縮を緩和できない恐れがある。保護樹脂１０８として、具体的にはシリコーン樹脂を用いることができる。シリコーン樹脂は弾性率が低く、変形しやすいことを特徴とする。これにより、柔軟性を有しながら保護することが可能となる。   As the protective resin 108, it is preferable to use a resin having an elastic modulus in the range of 0.5 MPa to 10 MPa. As a result, it is possible to further protect the wiring substrate 102 while relaxing expansion and contraction of the semiconductor device constituent material in a temperature cycle or the like. If the elastic modulus is 0.5 MPa or less, it can be easily deformed, so that the effectiveness as the protective resin 108 is not sufficient. Further, when the elastic modulus is 10 MPa or more, there is a possibility that expansion and contraction of the semiconductor device constituent material cannot be relaxed when a load such as a temperature cycle is applied. Specifically, a silicone resin can be used as the protective resin 108. Silicone resin has a low elastic modulus and is easily deformed. Thereby, it becomes possible to protect while having flexibility.

保護樹脂１０８の厚さは６０μｍ以上であることが望ましい。６０μｍ以下であると、保護樹脂１０８としての効果を十分に発揮することができない。６０μｍ以上であれば、いずれの厚さでも可能であり、半導体チップ１０４の厚さに応じて厚さを変えることも可能である。半導体チップ１０４、スティフナ１０６の上も保護樹脂１０８で覆い、その上にリッド（蓋体）１０９を配置することもできる。また、シリコーン樹脂の他には、保護樹脂１０８としてウレタン樹脂等を用いることもできる。   The thickness of the protective resin 108 is desirably 60 μm or more. When the thickness is 60 μm or less, the effect as the protective resin 108 cannot be sufficiently exhibited. Any thickness is possible as long as it is 60 μm or more, and the thickness can be changed according to the thickness of the semiconductor chip 104. The semiconductor chip 104 and the stiffener 106 can also be covered with the protective resin 108, and a lid (lid body) 109 can be disposed thereon. In addition to the silicone resin, a urethane resin or the like can be used as the protective resin 108.

本発明に用いる半導体チップ１０４としては、トランジスタ、ダイオード、ＩＣチップ等、さらには、セラミックコンデンサ、セラミック抵抗等の受動部品も搭載可能である。半導体チップ１０４をフェイスダウンしてバンプ１０５で薄型の配線基板１０２に電気接続させるフリップチップ接続は、半導体装置１０１の薄型化、高密度化が図れるために特に効果的であるが、ワイヤボンディング等フェイスアップの半導体チップ１０４を用いることも可能である。   As the semiconductor chip 104 used in the present invention, a transistor, a diode, an IC chip, and the like, and further passive components such as a ceramic capacitor and a ceramic resistor can be mounted. Flip chip connection, in which the semiconductor chip 104 is face-downed and electrically connected to the thin wiring substrate 102 by the bump 105, is particularly effective because the semiconductor device 101 can be thinned and densified. It is also possible to use an up semiconductor chip 104.

アンダーフィル層１０３を形成する材料には、公知の絶縁樹脂を用いることが可能である。シリカ等のフィラーを含有したエポキシ樹脂を用いることが一般的である。アンダーフィル層１０３を形成することにより、フリップチップ接続のバンプ１０５による接続部を保護するとともに、半導体チップ１０４と配線基板１０２の熱膨張等による効力を緩和することができる。   As a material for forming the underfill layer 103, a known insulating resin can be used. It is common to use an epoxy resin containing a filler such as silica. By forming the underfill layer 103, it is possible to protect the connection portion by the flip chip connection bump 105 and to reduce the effect of the semiconductor chip 104 and the wiring substrate 102 due to thermal expansion or the like.

また、図１（ｂ）に示すように、半導体チップ１０４の上部にリッド１０９を配置しても良い。リッド（蓋体）１０９としては、金属、セラミックス、ガラス等公知の材料を用いることができる。また、保護樹脂１０８を半導体チップ１０４およびスティフナ１０６の上まで塗布し、その上にリッド１０９を取り付けることも可能である。リッド１０９を取り付けることにより、放熱特性を向上させることができる。さらに、剛性を高めることによる信頼性向上の効果も期待できる。また、熱伝導性の高いフィラー等が含まれた保護樹脂１０８を用いて半導体チップ１０４の上まで覆った後にリッド１０９を取り付けることにより、さらに高い放熱効果を発揮させることが可能となる。 Further, as shown in FIG. 1B, a lid 109 may be disposed on the semiconductor chip 104. As the lid (lid body) 109, a known material such as metal, ceramics, or glass can be used. It is also possible to apply the protective resin 108 over the semiconductor chip 104 and the stiffener 106 and attach the lid 109 thereon. By attaching the lid 109, the heat dissipation characteristics can be improved. Furthermore, the effect of the reliability improvement by raising rigidity can also be expected. Further, by attaching the lid 109 after covering the top of the semiconductor chip 104 with the protective resin 108 containing a filler or the like having a high thermal conductivity, it is possible to exhibit a higher heat dissipation effect.

次に、本発明の半導体装置１０１の製造方法について説明する。本発明の製造方法は、導電パターンが形成された配線基板１０２にスティフナ１０６を貼り付ける工程、半導体チップ１０４を実装する工程、保護樹脂１０８を充填する工程から構成されている。以下に詳細に説明する。   Next, a method for manufacturing the semiconductor device 101 of the present invention will be described. The manufacturing method of the present invention includes a step of attaching a stiffener 106 to a wiring substrate 102 on which a conductive pattern is formed, a step of mounting a semiconductor chip 104, and a step of filling a protective resin 108. This will be described in detail below.

まず、薄型の配線基板１０２にスティフナ１０６を貼り付ける。少なくとも半導体チップ１０４の搭載部を設けてある導電パターンに、接着剤を介してスティフナ１０６を貼り付ける（図２（ｂ））。スティフナ接着剤１０７には公知の材料を使用可能である。具体的には、エポキシ樹脂の接着剤を使用することができる。このとき、半導体チップ１０４を先に実装することも可能であるが、先にスティフナ１０６を貼り付けることによって薄型の配線基板１０２の反りを低下させることができ、半導体チップ１０４を実装しやすくできる。   First, the stiffener 106 is attached to the thin wiring board 102. A stiffener 106 is attached to the conductive pattern provided with at least the mounting portion of the semiconductor chip 104 via an adhesive (FIG. 2B). A known material can be used for the stiffener adhesive 107. Specifically, an epoxy resin adhesive can be used. At this time, the semiconductor chip 104 can be mounted first. However, by attaching the stiffener 106 first, the warp of the thin wiring board 102 can be reduced, and the semiconductor chip 104 can be easily mounted.

次に、スティフナ１０６付き配線基板１０２に半導体チップ１０４を実装する（図２（ｃ））。前述のように、実装方法としては半導体チップ１０４をバンプ１０５で配線基板１０２の配線に電気接続するフリップチップ接続、あるいは、ワイヤボンディング接続等の公知の接続方法を用いることができる。また、フリップチップ接続を行うとき必要に応じてアンダーフィル層１０３を形成する（図２（ｄ））。アンダーフィル層１０３を形成する材料についても、公知の絶縁樹脂を用いることが可能である。具体的には、シリカを充填したエポキシ樹脂を用いることができる。   Next, the semiconductor chip 104 is mounted on the wiring board 102 with the stiffener 106 (FIG. 2C). As described above, as a mounting method, a known connection method such as flip chip connection in which the semiconductor chip 104 is electrically connected to the wiring of the wiring substrate 102 by the bump 105 or wire bonding connection can be used. Further, an underfill layer 103 is formed as necessary when performing flip-chip connection (FIG. 2D). As a material for forming the underfill layer 103, a known insulating resin can be used. Specifically, an epoxy resin filled with silica can be used.

次に、図２（ｅ）に示すように、保護樹脂１０８を半導体チップ１０４とスティフナ１０６の間に充填する。また、図１（ｃ）で示したように、半導体チップ１０４上にリッド１０９を取り付けた構造としてもよい。   Next, as shown in FIG. 2E, the protective resin 108 is filled between the semiconductor chip 104 and the stiffener 106. Further, as shown in FIG. 1C, a structure in which a lid 109 is attached on the semiconductor chip 104 may be adopted.

本発明の半導体装置１０１の製造方法として、配線基板１０２に半導体チップ１０４を実装し、アンダーフィル層１０３を形成した後、スティフナ１０６を貼り付け、保護樹脂１０８を充填することも可能である（図２（ｂ'）、（ｃ'））。
以上の工程で、本発明の半導体装置１０１を製造することができる。 As a method for manufacturing the semiconductor device 101 of the present invention, it is possible to mount the semiconductor chip 104 on the wiring substrate 102 and form the underfill layer 103, and then attach the stiffener 106 and fill the protective resin 108 (FIG. 2 (b ′), (c ′)).
Through the above steps, the semiconductor device 101 of the present invention can be manufactured.

＜実施例１＞
本発明に係る半導体装置１０１の実施例１を図面に基づいて以下に説明する。まず図２（ａ）に示すような薄型の配線基板１０２を用意する。薄型の配線基板１０２は、Ｃｕを主体とした導電パターンを有し、絶縁樹脂層にはポリイミドを用いている。次に図２（ｂ）に示すように、エポキシ系樹脂のスティフナ接着剤１０７を用いて、配線基板１０２にスティフナ１０６を貼り付ける。 <Example 1>
A first embodiment of a semiconductor device 101 according to the present invention will be described below with reference to the drawings. First, a thin wiring board 102 as shown in FIG. The thin wiring board 102 has a conductive pattern mainly composed of Cu, and polyimide is used for the insulating resin layer. Next, as shown in FIG. 2B, a stiffener 106 is attached to the wiring board 102 using an epoxy resin stiffener adhesive 107.

次に、配線基板１０２の半導体チップ搭載部に半導体チップ１０４を固着し、半導体チップ１０４と配線基板１０２とを電気的に接続する。半導体チップ１０４は配線基板１０２にバンプ１０５で電気接続させフリップチップ接続した。その後、図２（ｄ）に示すように、半導体チップ１０４と配線基板１０２との間にアンダーフィル層１０３を形成する。   Next, the semiconductor chip 104 is fixed to the semiconductor chip mounting portion of the wiring board 102, and the semiconductor chip 104 and the wiring board 102 are electrically connected. The semiconductor chip 104 was electrically connected to the wiring substrate 102 with bumps 105 and flip-chip connected. Thereafter, as shown in FIG. 2D, an underfill layer 103 is formed between the semiconductor chip 104 and the wiring substrate 102.

次に、図２（ｅ）に示すように、半導体チップ１０４とスティフナ１０６の間を保護樹脂１０８にて充填した。保護樹脂１０８にはシリコーン樹脂を使用した。ここで充填した保護樹脂１０８の厚さは３００μｍであった。以上の工程にて、本発明の半導体装置１０１が製造される。   Next, as shown in FIG. 2E, the space between the semiconductor chip 104 and the stiffener 106 was filled with a protective resin 108. A silicone resin was used as the protective resin 108. The thickness of the protective resin 108 filled here was 300 μm. The semiconductor device 101 of the present invention is manufactured through the above steps.

本発明の半導体装置１０１の信頼性試験を実施するため、本発明の半導体装置１０１を、図３に示すように第二の配線基板１１０に実装する。半導体装置１０１の配線基板１０２の外部接続用端子（パッド）と、第二の配線基板１１０の半導体装置搭載部とをはんだボール１１１で電気的に接続した。   In order to perform the reliability test of the semiconductor device 101 of the present invention, the semiconductor device 101 of the present invention is mounted on the second wiring board 110 as shown in FIG. The external connection terminals (pads) of the wiring substrate 102 of the semiconductor device 101 and the semiconductor device mounting portion of the second wiring substrate 110 were electrically connected by solder balls 111.

＜比較例１＞
比較例１として、保護樹脂１０８を充填しない半導体装置を製造した。保護樹脂１０８を充填しない点以外は、同様の工程にて製造した後、半導体装置の配線基板１０２の外部接続用端子（パッド）と、第二の配線基板１１０の半導体装置搭載部とをはんだボール１１１で電気的に接続した。
＜比較例２＞
比較例２として、半導体チップ１０４とスティフナ１０６の間にエポキシ系樹脂を充填した半導体装置の配線基板１０２の外部接続用端子（パッド）と、第二の配線基板１１０の半導体装置搭載部とをはんだボール１１１で電気的に接続した。 <Comparative Example 1>
As Comparative Example 1, a semiconductor device not filled with the protective resin 108 was manufactured. After manufacturing in the same process except that the protective resin 108 is not filled, the external connection terminals (pads) of the wiring substrate 102 of the semiconductor device and the semiconductor device mounting portion of the second wiring substrate 110 are solder balls. 111 was electrically connected.
<Comparative example 2>
As Comparative Example 2, the external connection terminals (pads) of the wiring board 102 of the semiconductor device in which the epoxy resin is filled between the semiconductor chip 104 and the stiffener 106 and the semiconductor device mounting portion of the second wiring board 110 are soldered. The balls 111 were electrically connected.

［温度サイクル試験（ＴＣＴ）による信頼性評価］
実施例１の半導体装置１０１および比較例１及び２によって得られた半導体装置について、信頼性評価試験を行った。試験に用いた配線基板１０２の大きさは４５ｍｍ角であり、スティフナ１０６の開口部分の大きさは３０ｍｍ角である。また、使用した半導体チップ１０４の大きさは、２０ｍｍ角である。 [Reliability evaluation by temperature cycle test (TCT)]
A reliability evaluation test was performed on the semiconductor device 101 of Example 1 and the semiconductor devices obtained by Comparative Examples 1 and 2. The size of the wiring board 102 used for the test is 45 mm square, and the size of the opening of the stiffener 106 is 30 mm square. The size of the used semiconductor chip 104 is 20 mm square.

温度サイクル試験（ＴＣＴ）は、気相にて−４０℃の温度条件を３０分と１２５℃の温度条件に３０分さらすサイクルを３５００回繰り返した。各温度の切り替え時間については、装置の能力の許す限り速やかに行った。   In the temperature cycle test (TCT), a cycle in which the temperature condition of −40 ° C. was exposed to the temperature condition of 30 minutes and 125 ° C. for 30 minutes in the gas phase was repeated 3500 times. The switching time of each temperature was performed as quickly as the capacity of the apparatus allowed.

保護樹脂１０８を充填した実施例１の半導体装置１０１では、３５００サイクル後も、導体抵抗値上昇率は１０％以下であった。一方、保護樹脂１０８を充填しない比較例１の半導体装置では、断線等によりオープンとなり、導体抵抗値は計測不可能であった。断面観察により、半導体チップ１０４とスティフナ１０６の間の裏面にあるはんだボール１１１にクラックが入っていた。また、エポキシ樹脂を充填した比較例２の半導体装置においても、断線等によりオープンとなり、導体抵抗値は計測不可能であった。比較例１の断面観察により、半導体チップ１０４とスティフナ１０６の間の裏面にあるはんだボール１１１および半導体装置の最外周にあるはんだボール１１１にクラックが入っていた。エポキシ樹脂を充填した比較例２の半導体装置では、アンダーフィル層１０３と充填したエポキシ樹脂との境目にもクラックが観察された。   In the semiconductor device 101 of Example 1 filled with the protective resin 108, the increase rate of the conductor resistance value was 10% or less even after 3500 cycles. On the other hand, in the semiconductor device of Comparative Example 1 in which the protective resin 108 was not filled, the conductor resistance value could not be measured because it was opened due to disconnection or the like. As a result of cross-sectional observation, the solder ball 111 on the back surface between the semiconductor chip 104 and the stiffener 106 was cracked. Further, in the semiconductor device of Comparative Example 2 filled with epoxy resin, it was opened due to disconnection or the like, and the conductor resistance value could not be measured. According to the cross-sectional observation of Comparative Example 1, the solder ball 111 on the back surface between the semiconductor chip 104 and the stiffener 106 and the solder ball 111 on the outermost periphery of the semiconductor device were cracked. In the semiconductor device of Comparative Example 2 filled with the epoxy resin, cracks were also observed at the boundary between the underfill layer 103 and the filled epoxy resin.

本発明は、配線基板、半導体パッケージ、あるいは機能モジュール等の半導体装置１０１に使用できる。   The present invention can be used for a semiconductor device 101 such as a wiring board, a semiconductor package, or a functional module.

１０１・・・半導体装置
１０２・・・配線基板
１０３・・・アンダーフィル層
１０４・・・半導体チップ
１０５・・・バンプ
１０６・・・スティフナ
１０７・・・スティフナ接着剤
１０８・・・保護樹脂
１０９・・・リッド（蓋材）
１１０・・・第二の配線基板
１１１・・・はんだボール DESCRIPTION OF SYMBOLS 101 ... Semiconductor device 102 ... Wiring board 103 ... Underfill layer 104 ... Semiconductor chip 105 ... Bump 106 ... Stiffener 107 ... Stiffener adhesive 108 ... Protective resin 109- ..Lid (lid material)
110 ... second wiring board 111 ... solder ball

Claims (5)

半導体チップの搭載された導電パターンを有する配線基板において、該配線基板はスティフナを具備しており、かつ、前記配線基板の上の半導体チップとスティフナの間の領域に弾性率が０．５ＭＰａ以上１０ＭＰａ以下の保護樹脂を充填したことを特徴とする半導体装置。   In a wiring board having a conductive pattern on which a semiconductor chip is mounted, the wiring board includes a stiffener, and an elastic modulus is 0.5 MPa or more and 10 MPa in a region between the semiconductor chip and the stiffener on the wiring board. A semiconductor device filled with the following protective resin. 前記配線基板の厚さが０．０５ｍｍ以上０．６ｍｍ以下であることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a thickness of the wiring board is 0.05 mm or more and 0.6 mm or less. 前記保護樹脂が、シリコーン樹脂、ウレタン樹脂から選択された材料であることを特徴とする請求項１又は２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the protective resin is a material selected from a silicone resin and a urethane resin. 前記保護樹脂の厚さが６０μｍ以上であることを特徴とする請求項１から３の何れか一項記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the thickness of the protective resin is 60 [mu] m or more. 前記半導体チップと前記配線基板が、フリップチップ接続されていることを特徴とする請求項１から４の何れか一項記載の半導体装置。   5. The semiconductor device according to claim 1, wherein the semiconductor chip and the wiring board are flip-chip connected.
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