JP2010129576A - Lamination semiconductor substrate, and method of manufacturing lamination semiconductor substrate - Google Patents

Lamination semiconductor substrate, and method of manufacturing lamination semiconductor substrate Download PDF

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JP2010129576A
JP2010129576A JP2008299401A JP2008299401A JP2010129576A JP 2010129576 A JP2010129576 A JP 2010129576A JP 2008299401 A JP2008299401 A JP 2008299401A JP 2008299401 A JP2008299401 A JP 2008299401A JP 2010129576 A JP2010129576 A JP 2010129576A
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semiconductor substrate
marking
height
bump
semiconductor
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JP2010129576A5 (en
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Satoru Sanada
覚 真田
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Nikon Corp
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Nikon Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54413—Marks applied to semiconductor devices or parts comprising digital information, e.g. bar codes, data matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

<P>PROBLEM TO BE SOLVED: To prevent a lamination semiconductor substrate from having electrical connection failure by a peripheral edge part of a marking raised from a plate surface having the mark. <P>SOLUTION: The lamination semiconductor substrate formed by laminating a plurality of semiconductor substrates, includes: bumps 128, 158 which are arranged between junction surfaces of a pair of semiconductor substrates 120, 150 which face each other and electrically connecting the pair of semiconductor substrates 120, 150; and a bar code 124 for identification arranged on the junction surface, which faces the other in at least the one of the pair of semiconductor substrates 120, 150. A height H1 of the bump 128 from the junction surface with the bar code 124 arranged is higher than a height H2 of a peripheral edge part 125 of the bar code 124 from the junction surface with the bar code 124 arranged. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、複数の半導体基板を積層して接合した積層半導体基板、及び当該積層半導体基板の製造方法に関する。   The present invention relates to a stacked semiconductor substrate in which a plurality of semiconductor substrates are stacked and bonded, and a method for manufacturing the stacked semiconductor substrate.

半導体装置を面積を増やすことなく高性能化することを目的として、複数の半導体チップを積層して接合した積層半導体装置が知られている。この積層半導体装置では、互いに接合される一対の半導体基板は、互いの接合される側の面にそれぞれ配された一対のバンプが接合されることにより、電気的に接続される（例えば、特許文献１参照）。   2. Description of the Related Art A stacked semiconductor device in which a plurality of semiconductor chips are stacked and bonded for the purpose of improving the performance of the semiconductor device without increasing the area is known. In this stacked semiconductor device, a pair of semiconductor substrates bonded to each other are electrically connected by bonding a pair of bumps respectively arranged on the surfaces to be bonded to each other (for example, Patent Documents). 1).

ところで、積層半導体装置の製造工程では、ウエハにバーコード等の識別用の刻印を形成することが行われる。ここで、当該刻印をレーザ照射法により半導体基板に形成した場合、レーザアブレーション現象により基板表面が削られ、削られた表面材料が刻印の周縁部に堆積する。これにより、刻印の周縁部が基板表面から***する。
特開２００７−２７３７８２号公報 By the way, in the manufacturing process of the laminated semiconductor device, an identification mark such as a barcode is formed on the wafer. Here, when the marking is formed on the semiconductor substrate by the laser irradiation method, the substrate surface is scraped by the laser ablation phenomenon, and the scraped surface material is deposited on the peripheral portion of the stamp. As a result, the peripheral edge of the inscription is raised from the substrate surface.
JP 2007-273882 A

互いに接合される一対の半導体基板を重ね合わせたときに、刻印の周縁部と、当該刻印と対向する面とが干渉した場合には、当該一対の半導体基板の電気的な接続が妨げられる。   When a pair of semiconductor substrates bonded to each other are overlapped with each other, a peripheral portion of the marking and a surface opposed to the marking interfere with each other, and electrical connection between the pair of semiconductor substrates is hindered.

上記課題を解決するために、本発明の第１の態様においては、複数の半導体基板が積層された積層半導体基板において、一対の半導体基板の互いに対向した接合側の面の間に配され、前記一対の半導体基板を電気的に接続する端子部と、前記一対の半導体基板の少なくとも一方の半導体基板における接合側の面に設けられた識別用の刻印と、を備え、前記刻印が設けられた接合側の面からの前記端子部の高さが、前記刻印が設けられた接合側の面からの前記刻印の周縁部の高さより高い積層半導体基板が提供される。   In order to solve the above-described problem, in the first aspect of the present invention, in the laminated semiconductor substrate in which a plurality of semiconductor substrates are laminated, the semiconductor substrate is disposed between the surfaces of the pair of semiconductor substrates facing each other on the bonding side, A terminal portion for electrically connecting a pair of semiconductor substrates; and a marking for identification provided on a surface of a bonding side of at least one semiconductor substrate of the pair of semiconductor substrates. A stacked semiconductor substrate is provided in which the height of the terminal portion from the side surface is higher than the height of the peripheral portion of the marking from the surface on the bonding side where the marking is provided.

また、上記課題を解決するために、本発明の第２の態様においては、複数の半導体基板が積層された積層半導体基板の製造方法であって、互いに積層される一対の半導体基板の少なくとも一方の前記半導体基板の接合側の面に識別用の刻印を形成する刻印形成工程と、互いに積層される一対の半導体基板の互いの接合側の面の間に、前記一対の半導体基板を電気的に接続する端子部を形成する端子部形成工程と、を備え、前記刻印形成工程及び前記端子部形成工程の少なくとも一方の工程において、前記刻印が設けられる接合側の面からの前記端子部の高さを、前記刻印が設けられる接合側の面からの前記刻印の周縁部の高さより高くする積層半導体基板の製造方法が提供される。   In order to solve the above problems, in a second aspect of the present invention, there is provided a method for manufacturing a stacked semiconductor substrate in which a plurality of semiconductor substrates are stacked, and at least one of a pair of semiconductor substrates stacked together. The pair of semiconductor substrates are electrically connected between a marking forming step of forming a marking for identification on the bonding side surface of the semiconductor substrate and the bonding side surfaces of the pair of semiconductor substrates stacked on each other. A terminal portion forming step for forming a terminal portion, and in at least one of the stamp forming step and the terminal portion forming step, the height of the terminal portion from the surface on the joint side where the stamp is provided. A method of manufacturing a laminated semiconductor substrate is provided in which the height is higher than the height of the peripheral portion of the marking from the surface on the bonding side where the marking is provided.

なお、上記の発明の概要は、本発明の必要な特徴の全てを列挙したものではない。また、これらの特徴群のサブコンビネーションもまた、発明となりうる。   It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

以下、発明の実施の形態を通じて本発明を説明するが、以下の実施形態は特許請求の範囲にかかる発明を限定するものではない。また、実施形態の中で説明されている特徴の組み合わせの全てが発明の解決手段に必須であるとは限らない。   Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

図１には、基板貼り合わせ装置２００を断面図にて示している。基板貼り合わせ装置２００は、複数の半導体素子が形成された半導体基板１２０、１５０を加圧および加熱して貼り合わせることにより、三次元的な積層半導体基板を製造する。各半導体基板１２０、１５０は、図示の例では、それぞれ公知のウエハで構成されている。基板貼り合わせ装置２００は、枠体２１０の内側に配置された、押圧部２２０、加圧ステージ２３０、受圧ステージ２４０、圧力検知部２５０を備える。   FIG. 1 shows a cross-sectional view of the substrate bonding apparatus 200. The substrate bonding apparatus 200 manufactures a three-dimensional laminated semiconductor substrate by pressing and heating the semiconductor substrates 120, 150 on which a plurality of semiconductor elements are formed, and bonding them. Each of the semiconductor substrates 120 and 150 is composed of a known wafer in the illustrated example. The substrate bonding apparatus 200 includes a pressing unit 220, a pressure stage 230, a pressure receiving stage 240, and a pressure detection unit 250 that are disposed inside the frame body 210.

枠体２１０は、互いに平行で水平な天板２１２および底板２１６と、天板２１２および底板２１６を結合する複数の支柱２１４とを備える。天板２１２、支柱２１４および底板２１６は、半導体基板１２０、１５０への加圧の反力が作用した場合に変形が生じない程度の剛性を有する。   The frame body 210 includes a top plate 212 and a bottom plate 216 that are parallel and horizontal to each other, and a plurality of columns 214 that couple the top plate 212 and the bottom plate 216. The top plate 212, the support column 214, and the bottom plate 216 have such rigidity that no deformation occurs when a reaction force of pressure applied to the semiconductor substrates 120 and 150 is applied.

枠体２１０の内側において、底板２１６の上には、押圧部２２０が配置される。押圧部２２０は、底板２１６の上面に固定されたシリンダ２２２と、シリンダ２２２の内側に配置されたピストン２２４とを有する。ピストン２２４は、図示されていない流体回路、カム、輪列等により駆動されて、図中に矢印Ｚにより示す、底板２１６に対して直角な方向に昇降する。   On the inner side of the frame body 210, the pressing portion 220 is disposed on the bottom plate 216. The pressing unit 220 includes a cylinder 222 that is fixed to the upper surface of the bottom plate 216 and a piston 224 that is disposed inside the cylinder 222. The piston 224 is driven by a fluid circuit (not shown), a cam, a train wheel, and the like, and moves up and down in a direction perpendicular to the bottom plate 216 indicated by an arrow Z in the drawing.

ピストン２２４の上端には、加圧ステージ２３０が搭載される。加圧ステージ２３０は、ピストン２２４の上端に結合された水平な板状の支持部２３２と、支持部２３２に平行な板状の第１基板保持部２３４とを有する。   A pressure stage 230 is mounted on the upper end of the piston 224. The pressure stage 230 includes a horizontal plate-like support portion 232 coupled to the upper end of the piston 224 and a plate-like first substrate holding portion 234 parallel to the support portion 232.

第１基板保持部２３４は、複数のアクチュエータ２３５を介して、支持部２３２から支持される。アクチュエータ２３５は、図示された一対のアクチュエータ２３５の他に、紙面に対して前方および後方にも配置される。また、これらアクチュエータ２３５の各々は、相互に独立して動作させることができる。このような構造により、アクチュエータ２３５を適宜動作させることにより、第１基板保持部２３４の傾斜を任意に変えることができる。また、第１基板保持部２３４は、ヒータ２３６を有しており、当該ヒータ２３６により加熱される。   The first substrate holding part 234 is supported from the support part 232 via a plurality of actuators 235. In addition to the pair of actuators 235 shown in the figure, the actuator 235 is also arranged forward and backward with respect to the paper surface. Each of these actuators 235 can be operated independently of each other. With such a structure, the inclination of the first substrate holding part 234 can be arbitrarily changed by appropriately operating the actuator 235. The first substrate holding unit 234 includes a heater 236 and is heated by the heater 236.

また、半導体基板１２０は、ウエハホルダ３２０に静電吸着されており、第１基板保持部２３４は、真空吸着等により上面にウエハホルダ３２０を吸着する。これにより、半導体基板１２０は、ウエハホルダ３２０及び第１基板保持部２３４と共に揺動する一方、第１基板保持部２３４からの移動あるいは脱落を防止される。   The semiconductor substrate 120 is electrostatically attracted to the wafer holder 320, and the first substrate holder 234 attracts the wafer holder 320 to the upper surface by vacuum suction or the like. As a result, the semiconductor substrate 120 swings together with the wafer holder 320 and the first substrate holding part 234, while being prevented from moving or dropping from the first substrate holding part 234.

受圧ステージ２４０は、第２基板保持部２４２および複数の懸架部２４４を有する。懸架部２４４は、天板２１２の下面から垂下される。第２基板保持部２４２は、懸架部２４４の下端近傍において下方から支持され、加圧ステージ２３０に対向して配置される。また、半導体基板１５０は、ウエハホルダ３５０に静電吸着されており、第２基板保持部２４２は、真空吸着等により下面にウエハホルダ３５０を吸着する。さらに、懸架部２４４は、ヒータ２４６を有しており、当該ヒータ２４６により加熱される。   The pressure receiving stage 240 includes a second substrate holding part 242 and a plurality of suspension parts 244. The suspension portion 244 is suspended from the lower surface of the top plate 212. The second substrate holding unit 242 is supported from below in the vicinity of the lower end of the suspension unit 244 and is disposed to face the pressure stage 230. The semiconductor substrate 150 is electrostatically attracted to the wafer holder 350, and the second substrate holder 242 attracts the wafer holder 350 to the lower surface by vacuum suction or the like. Furthermore, the suspension part 244 has a heater 246 and is heated by the heater 246.

第２基板保持部２４２は、下方から懸架部２４４により支持される一方、上方への移動は規制されない。ただし、天板２１２および第２基板保持部２４２の間には、複数のロードセル２５２、２５４、２５６が挟まれる。複数のロードセル２５２、２５４、２５６は、圧力検知部２５０の一部を形成して、第２基板保持部２４２の上方移動を規制すると共に、第２基板保持部２４２に対して上方に印加された圧力を検出する。   The second substrate holding part 242 is supported by the suspension part 244 from below, but the upward movement is not restricted. However, a plurality of load cells 252, 254 and 256 are sandwiched between the top plate 212 and the second substrate holding part 242. The plurality of load cells 252, 254, 256 form a part of the pressure detection unit 250, regulate upward movement of the second substrate holding unit 242, and are applied upward to the second substrate holding unit 242. Detect pressure.

図示した状態では、押圧部２２０の支柱２１４はシリンダ２２２の中に引き込まれており、加圧ステージ２３０は降下している。従って、加圧ステージ２３０および受圧ステージ２４０の間には広い間隙がある。   In the illustrated state, the support column 214 of the pressing unit 220 is drawn into the cylinder 222, and the pressure stage 230 is lowered. Therefore, there is a wide gap between the pressure stage 230 and the pressure receiving stage 240.

接合の対象となる一対の半導体基板１２０、１５０のうち、一方の半導体基板１２０は、上記間隙に対して側方から挿入されて、加圧ステージ２３０の上に載せられる。他方の半導体基板１５０も同様に挿入され、半導体基板１５０に対向して受圧ステージ２４０に保持される。半導体基板１２０、１５０は、Ｚ方向に直交する平面内で相互に位置合わせされている。なお、基板貼り合わせ装置２００が半導体基板１２０、１５０を位置合わせしてもよく、あるいは、他の位置合わせ装置によって位置合わせされた半導体基板１２０、１５０が基板貼り合わせ装置２００に搬送されてもよい。   Of the pair of semiconductor substrates 120 and 150 to be bonded, one semiconductor substrate 120 is inserted into the gap from the side and placed on the pressure stage 230. The other semiconductor substrate 150 is similarly inserted and held on the pressure receiving stage 240 so as to face the semiconductor substrate 150. The semiconductor substrates 120 and 150 are aligned with each other in a plane orthogonal to the Z direction. The substrate bonding apparatus 200 may align the semiconductor substrates 120 and 150, or the semiconductor substrates 120 and 150 aligned by other alignment apparatuses may be transported to the substrate bonding apparatus 200. .

ここで、加圧ステージ２３０が受圧ステージ２４０に向かって上昇して、半導体基板１２０と半導体基板１５０とを押圧する。さらに、押圧中に、ヒータ２４６、２３６が加圧ステージ２３０および受圧ステージ２４０を加熱する。これにより、半導体基板１２０、１５０が接合される。   Here, the pressure stage 230 rises toward the pressure receiving stage 240 and presses the semiconductor substrate 120 and the semiconductor substrate 150. Further, the heaters 246 and 236 heat the pressure stage 230 and the pressure receiving stage 240 during pressing. Thereby, the semiconductor substrates 120 and 150 are joined.

図２には、基板貼り合わせ装置２００により貼り合わせられる半導体基板１２０、１５０を平面図にて示している。この図に示すように、半導体基板１２０、１５０には、後にダイシングされる多数の半導体チップ１２２、１５２が縦横に形成される。また、半導体基板１２０、１５０の半導体チップ１２２、１５２が形成された領域の外側には、識別用の刻印の一例としてバーコード１２４、１５４が、レーザ照射法により形成される。即ち、刻印形成工程が実施される。   In FIG. 2, the semiconductor substrates 120 and 150 bonded together by the substrate bonding apparatus 200 are shown in a plan view. As shown in this figure, a large number of semiconductor chips 122 and 152 to be diced later are formed vertically and horizontally on the semiconductor substrates 120 and 150. Further, barcodes 124 and 154 are formed by laser irradiation as an example of identification markings outside the region of the semiconductor substrates 120 and 150 where the semiconductor chips 122 and 152 are formed. That is, a stamp forming process is performed.

バーコード１２４、１５４は、半導体基板１２０、１５０に付与されたＩＤ番号をバーコード化したものであって、半導体基板１２０、１５０が基板貼り合わせ装置２００へ搬送される搬送経路等に配されたバーコードリーダにより読み取られる。そして、製造管理システムが、読み取られたバーコード１２４、１５４が表すＩＤ番号に対応付けて、半導体基板１２０、１５０等が積層されて形成される積層半導体基板を管理する。なお、バーコード１２４、１５４は、ダイシング工程において半導体チップ１２２、１５２から分離される。   The barcodes 124 and 154 are obtained by converting the ID numbers assigned to the semiconductor substrates 120 and 150 into barcodes, and are arranged on a conveyance path or the like where the semiconductor substrates 120 and 150 are conveyed to the substrate bonding apparatus 200. It is read by a bar code reader. Then, the manufacturing management system manages the stacked semiconductor substrates formed by stacking the semiconductor substrates 120 and 150 in association with the ID numbers indicated by the read barcodes 124 and 154. The bar codes 124 and 154 are separated from the semiconductor chips 122 and 152 in the dicing process.

図３には、基板貼り合わせ装置２００により貼り合わせられる半導体基板１２０、１５０を側断面図にて示している。この図に示すように、半導体基板１２０、１５０は、互いに基板積層方向に対向する接合される側の面（以下、接合面１２１、１５１という）を介して接合される。また、半導体基板１２０、１５０の半導体チップ１２２、１５２には、厚み方向に貫通するスルーホール１２３、１５３が形成されている。スルーホール１２３、１５３には、Ｃｕ等の導電性材料を埋め込んだ埋め込み電極１２６、１５６が形成されている。   In FIG. 3, the semiconductor substrates 120 and 150 to be bonded together by the substrate bonding apparatus 200 are shown in a side sectional view. As shown in this figure, the semiconductor substrates 120 and 150 are bonded via surfaces to be bonded (hereinafter referred to as bonding surfaces 121 and 151) facing each other in the substrate stacking direction. Further, through holes 123 and 153 penetrating in the thickness direction are formed in the semiconductor chips 122 and 152 of the semiconductor substrates 120 and 150. In the through holes 123 and 153, buried electrodes 126 and 156 in which a conductive material such as Cu is buried are formed.

また、半導体チップ１２２、１５２の接合面１２１、１５１におけるスルーホール１２３、１５３上には、半田又はＡｕ等の導電性材料を材料とする第１バンプとしてのバンプ１２８、第２バンプとしてのバンプ１５８が形成されている。バンプ１２８は、半導体チップ１２２におけるバンプ１２８が設けられた接合面１２１から半導体チップ１５２側へ突出しており、バンプ１５８は、半導体チップ１５２におけるバンプ１５８が設けられた接合面１５１から半導体チップ１２２側へ突出している。スルーホール１２３とスルーホール１５３とは、基板積層方向に見て重合するように配されている。このため、互いに位置合わせされた半導体基板１２０、１５０を、基板貼り合わせ装置２００により加圧加熱することにより、バンプ１２８とバンプ１５８とが熱圧着されて接合され、半導体チップ１２２と半導体チップ１５２とが機械的且つ電気的に接続される。   Also, bumps 128 as first bumps and bumps 158 as second bumps made of a conductive material such as solder or Au are provided on the through holes 123 and 153 in the bonding surfaces 121 and 151 of the semiconductor chips 122 and 152. Is formed. The bump 128 protrudes from the bonding surface 121 provided with the bump 128 in the semiconductor chip 122 to the semiconductor chip 152 side, and the bump 158 extends from the bonding surface 151 provided with the bump 158 in the semiconductor chip 152 to the semiconductor chip 122 side. It protrudes. The through hole 123 and the through hole 153 are arranged so as to overlap when viewed in the substrate stacking direction. For this reason, the semiconductor substrates 120 and 150 aligned with each other are pressurized and heated by the substrate bonding apparatus 200, whereby the bumps 128 and the bumps 158 are bonded by thermocompression bonding, and the semiconductor chip 122 and the semiconductor chip 152 are bonded. Are mechanically and electrically connected.

なお、本実施形態では、バンプ１２８、１５８は、半田を電気鍍金することにより形成した半田バンプとなっており、加圧加熱されることにより熱圧着されて接合される。しかしながら、バンプ１２８、１５８は、半田バンプ以外に、ニッケル、金等により形成されたバンプとしてもよい。この場合には、半導体チップ１２２と半導体チップ１５２との間に充填されるアンダーフィルでバンプ１２８とバンプ１５８との機械的接合強度を補強すればよい。   In the present embodiment, the bumps 128 and 158 are solder bumps formed by electroplating solder, and are bonded by thermocompression bonding by being heated under pressure. However, the bumps 128 and 158 may be bumps formed of nickel, gold or the like other than the solder bumps. In this case, the mechanical bonding strength between the bump 128 and the bump 158 may be reinforced by an underfill filled between the semiconductor chip 122 and the semiconductor chip 152.

図４には、互いに接合された一対の半導体基板１２０、１５０を側断面図にて示している。この図に示すように、半導体基板１２０、１５０の接合面１２１、１５１の外周部には、バーコード１２４、１５４が形成されている。ここで、バーコード１２４、１５４は、レーザ照射法により半導体基板１２０、１５０の接合面１２１、１５１に形成されるが、バーコード１２４、１５４を形成する工程において、レーザアブレーション現象で接合面１２１、１５１から削られた表面材料が、バーコード１２４、１５４を縁取る周縁部に堆積する。これにより、バーコード１２４を縁取る周縁部１２５が、接合面１２１から***する。また、同様に、バーコード１５４を縁取る周縁部が、接合面１５１から***する。   FIG. 4 is a side sectional view showing a pair of semiconductor substrates 120 and 150 bonded to each other. As shown in this figure, barcodes 124 and 154 are formed on the outer peripheral portions of the bonding surfaces 121 and 151 of the semiconductor substrates 120 and 150. Here, the barcodes 124 and 154 are formed on the bonding surfaces 121 and 151 of the semiconductor substrates 120 and 150 by a laser irradiation method. In the step of forming the barcodes 124 and 154, the bonding surfaces 121, The surface material shaved from 151 is deposited on the peripheral edge bordering the barcodes 124, 154. As a result, the peripheral edge 125 that borders the barcode 124 rises from the joint surface 121. Similarly, the peripheral edge that borders the barcode 154 rises from the joint surface 151.

また、バンプ１２８、１５８が接合されてなる端子部１３０が、一対の半導体基板１２０、１５０の接合面１２１、１５１の間に配される。ここで、バーコード１２４が形成された接合面１２１からの端子部１３０の高さＨ１、即ち、接合面１２１からのバンプ１２８の高さと接合面１５１からのバンプ１５８の高さとの合計Ｈ１が、接合面１２１からのバーコード１２４の周縁部１２５の高さＨ２より高くなっている。また、図示は省略するが、接合面１２１からの端子部１３０の高さＨ１が、接合面１５１からのバーコード１５４の周縁部の高さより高くなっている。このため、半導体基板１２０と半導体基板１５０とを重ね合わせたときに、接合面１５１とバーコード１２４の周縁部１２５、及び、接合面１２１とバーコード１５４の周縁部が干渉することを防止でき、バンプ１２８とバンプ１５８とを確実に当接させて熱圧着させることができる。従って、バンプ１２８とバンプ１５８との電気的な接続が、バーコード１２４の周縁部１２５、バーコード１５４の周縁部により妨げられることを防止できる。   Further, the terminal portion 130 formed by bonding the bumps 128 and 158 is disposed between the bonding surfaces 121 and 151 of the pair of semiconductor substrates 120 and 150. Here, the height H1 of the terminal portion 130 from the bonding surface 121 on which the barcode 124 is formed, that is, the total H1 of the height of the bump 128 from the bonding surface 121 and the height of the bump 158 from the bonding surface 151, The height H2 of the peripheral edge 125 of the barcode 124 from the joining surface 121 is higher. Although not shown, the height H <b> 1 of the terminal portion 130 from the joining surface 121 is higher than the height of the peripheral edge portion of the barcode 154 from the joining surface 151. For this reason, when the semiconductor substrate 120 and the semiconductor substrate 150 are overlapped, it is possible to prevent the bonding surface 151 and the peripheral portion 125 of the barcode 124 and the bonding surface 121 and the peripheral portion of the barcode 154 from interfering with each other. The bumps 128 and the bumps 158 can be reliably brought into contact with each other and thermocompression bonded. Accordingly, the electrical connection between the bump 128 and the bump 158 can be prevented from being hindered by the peripheral edge 125 of the barcode 124 and the peripheral edge of the barcode 154.

なお、バンプ１２８、１５８の高さは、種々の方法で調整できる。例えば、バンプ１２８、１５８を形成するバンプ形成工程において接合面１２１、１５１に付着させる半田の厚さを増減させたり、半導体基板１２０と半導体基板１５０とを接合する接合工程において半導体基板１２０と半導体基板１５０とを加圧するプレス圧力を増減させたりすることにより調整できる。   The height of the bumps 128 and 158 can be adjusted by various methods. For example, in the bump forming process for forming the bumps 128 and 158, the thickness of the solder attached to the bonding surfaces 121 and 151 is increased or decreased, or in the bonding process for bonding the semiconductor substrate 120 and the semiconductor substrate 150, the semiconductor substrate 120 and the semiconductor substrate. It can be adjusted by increasing or decreasing the press pressure for pressurizing 150.

また、バーコード１２４の周縁部１２５、バーコード１５４の周縁部１５５の高さは、表面形状測定装置等により測定できる。ここで、周縁部１２５、１５５の高さについては、全数検査を実施してもよいが、一定の割合での抜き取り検査を実施してもよい。   Further, the height of the peripheral edge portion 125 of the barcode 124 and the peripheral edge portion 155 of the barcode 154 can be measured by a surface shape measuring device or the like. Here, as for the heights of the peripheral edge portions 125 and 155, 100% inspection may be performed, but sampling inspection may be performed at a certain rate.

図５には、積層半導体装置１００を側断面図にて示している。この図に示すように、積層半導体装置１００では、上述の半導体チップ１２２、１５２の上にさらに複数の半導体チップ１６２が積層されている。また、最下層の半導体チップ１２２の下面には、外部接続基板としてのインターポーザ１７２が接合され、最上層の半導体チップ１６２の上面には、封止部としてのモールド部１８２が形成されている。また、各層の間にはアンダーフィル１８４が充填されている。   FIG. 5 is a sectional side view of the stacked semiconductor device 100. As shown in this figure, in the stacked semiconductor device 100, a plurality of semiconductor chips 162 are further stacked on the above-described semiconductor chips 122 and 152. An interposer 172 as an external connection substrate is bonded to the lower surface of the lowermost semiconductor chip 122, and a mold portion 182 as a sealing portion is formed on the upper surface of the uppermost semiconductor chip 162. In addition, an underfill 184 is filled between the layers.

インターポーザ１７２には複数のスルーホール１７３が、スルーホール１２３の位置に対応して形成されている。スルーホール１７３には、Ｃｕ等の導電性材料を埋め込んだ埋め込み電極１７６が形成されている。また、インターポーザ１７２の下面にはスルーホール１７３の位置に対応して、半田又はＡｕ等の導電性材料を材料とするボール状のバンプ１７８が形成されている。なお、上述のダイシング工程において、バーコード１２４、１５４が半導体チップ１２２、１５２から分離されることから、積層半導体装置１００は、バーコード１２４、１５４を具備しない。   A plurality of through holes 173 are formed in the interposer 172 corresponding to the positions of the through holes 123. An embedded electrode 176 in which a conductive material such as Cu is embedded is formed in the through hole 173. In addition, ball-shaped bumps 178 made of a conductive material such as solder or Au are formed on the lower surface of the interposer 172 corresponding to the positions of the through holes 173. In the dicing process described above, since the barcodes 124 and 154 are separated from the semiconductor chips 122 and 152, the stacked semiconductor device 100 does not include the barcodes 124 and 154.

図６には、半導体基板１２０、１５０の他の実施形態を側断面図にて示している。この図に示すように、バンプ１５８は、半導体基板１５０に埋設され、バンプ１２８との当接面は、接合面１５１と面一になっている。一方、バンプ１２８は、接合面１２１から接合面１５１側へ突出してバンプ１５８に当接している。   FIG. 6 is a side sectional view showing another embodiment of the semiconductor substrates 120 and 150. As shown in this figure, the bump 158 is embedded in the semiconductor substrate 150, and the contact surface with the bump 128 is flush with the bonding surface 151. On the other hand, the bump 128 protrudes from the bonding surface 121 toward the bonding surface 151 and contacts the bump 158.

ここで、接合面１２１からのバンプ１２８の高さＨ３は、接合面１２１からのバーコード１２４の周縁部１２５の高さＨ２より高くなっている。このため、半導体基板１２０と半導体基板１５０とを重ね合わせたときに、接合面１５１と周縁部１２５とが干渉することを防止でき、バンプ１２８とバンプ１５８とを確実に当接させることができる。従って、バンプ１２８とバンプ１５８との電気的な接続が、周縁部１２５により妨げられることを防止できる。   Here, the height H3 of the bump 128 from the bonding surface 121 is higher than the height H2 of the peripheral edge 125 of the barcode 124 from the bonding surface 121. For this reason, when the semiconductor substrate 120 and the semiconductor substrate 150 are overlapped, it is possible to prevent the bonding surface 151 and the peripheral edge portion 125 from interfering with each other, and the bump 128 and the bump 158 can be brought into contact with each other with certainty. Therefore, the electrical connection between the bump 128 and the bump 158 can be prevented from being obstructed by the peripheral edge portion 125.

図７には、半導体基板１２０、１５０の他の実施形態を側断面図にて示している。この図に示すように、バンプ１２８は、半導体基板１２０に埋設され、バンプ１５８との当接面は、接合面１２１と面一になっている。一方、バンプ１５８は、接合面１５１から接合面１２１側へ突出してバンプ１２８に当接している。   FIG. 7 is a side sectional view showing another embodiment of the semiconductor substrates 120 and 150. As shown in this figure, the bump 128 is embedded in the semiconductor substrate 120, and the contact surface with the bump 158 is flush with the bonding surface 121. On the other hand, the bump 158 protrudes from the bonding surface 151 toward the bonding surface 121 and contacts the bump 128.

ここで、接合面１５１からのバンプ１５８の高さＨ４は、接合面１２１からのバーコード１２４の周縁部１２５の高さＨ２より高くなっている。このため、半導体基板１２０と半導体基板１５０とを重ね合わせたときに、接合面１５１と周縁部１２５とが干渉することを防止でき、バンプ１２８とバンプ１５８とを確実に当接させることができる。従って、バンプ１２８とバンプ１５８との電気的な接続が、周縁部１２５により妨げられることを防止できる。   Here, the height H4 of the bump 158 from the bonding surface 151 is higher than the height H2 of the peripheral edge 125 of the barcode 124 from the bonding surface 121. For this reason, when the semiconductor substrate 120 and the semiconductor substrate 150 are overlapped, it is possible to prevent the bonding surface 151 and the peripheral edge portion 125 from interfering with each other, and the bump 128 and the bump 158 can be brought into contact with each other with certainty. Therefore, the electrical connection between the bump 128 and the bump 158 can be prevented from being obstructed by the peripheral edge portion 125.

図８には、半導体基板１２０、１５０の他の実施形態を側断面図にて示している。この図に示すように、バーコード１５４が、接合面１２１に形成されたバーコード１２４と基板積層方向に対向するように、接合面１５１に形成されている。   FIG. 8 is a side sectional view showing another embodiment of the semiconductor substrates 120 and 150. As shown in this figure, a barcode 154 is formed on the bonding surface 151 so as to face the barcode 124 formed on the bonding surface 121 in the substrate stacking direction.

ここで、バーコード１２４が形成された接合面１２１からの端子部１３０の高さＨ１が、接合面１２１からのバーコード１２４の周縁部１２５の高さＨ２と接合面１５１からのバーコード１５４の周縁部１５５の高さＨ２との合計より高くなっている。このため、半導体基板１２０と半導体基板１５０とを重ね合わせたときに、周縁部１２５と周縁部１５５とが干渉することを防止でき、バンプ１２８とバンプ１５８とを確実に当接させることができる。従って、バンプ１２８とバンプ１５８との電気的な接続が、周縁部１２５、１５５により妨げられることを防止できる。   Here, the height H1 of the terminal portion 130 from the joining surface 121 on which the barcode 124 is formed is equal to the height H2 of the peripheral edge 125 of the barcode 124 from the joining surface 121 and the barcode 154 from the joining surface 151. It is higher than the sum of the peripheral edge portion 155 and the height H2. For this reason, when the semiconductor substrate 120 and the semiconductor substrate 150 are overlapped, the peripheral edge 125 and the peripheral edge 155 can be prevented from interfering with each other, and the bump 128 and the bump 158 can be reliably brought into contact with each other. Therefore, the electrical connection between the bump 128 and the bump 158 can be prevented from being hindered by the peripheral edge portions 125 and 155.

以上、本発明を実施の形態を用いて説明したが、本発明の技術的範囲は上記実施の形態に記載の範囲には限定されない。上記実施の形態に、多様な変更または改良を加えることが可能であることが当業者に明らかである。その様な変更または改良を加えた形態も本発明の技術的範囲に含まれ得ることが、特許請求の範囲の記載から明らかである。   As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

基板貼り合わせ装置２００を側断面図にて示す。The board | substrate bonding apparatus 200 is shown with a sectional side view. 基板貼り合わせ装置２００により貼り合わせられる半導体基板１２０、１５０を平面図にて示す。The semiconductor substrates 120 and 150 bonded together by the substrate bonding apparatus 200 are shown in plan view. 基板貼り合わせ装置２００により貼り合わせられる半導体基板１２０、１５０を側断面図にて示す。The semiconductor substrates 120 and 150 bonded together by the substrate bonding apparatus 200 are shown in a side sectional view. 互いに接合された一対の半導体基板１２０、１５０を側断面図にて示す。A pair of semiconductor substrates 120 and 150 bonded to each other are shown in a side sectional view. 積層半導体装置１００を側断面図にて示す。A laminated semiconductor device 100 is shown in a side sectional view. 半導体基板１２０、１５０の他の実施形態を側断面図にて示す。Another embodiment of the semiconductor substrate 120, 150 is shown in a side sectional view. 半導体基板１２０、１５０の他の実施形態を側断面図にて示す。Another embodiment of the semiconductor substrate 120, 150 is shown in a side sectional view. 半導体基板１２０、１５０の他の実施形態を側断面図にて示す。Another embodiment of the semiconductor substrate 120, 150 is shown in a side sectional view.

符号の説明Explanation of symbols

１００ 積層半導体装置、１２０ 半導体基板、１２１ 接合面、１２２ 半導体チップ、１２３ スルーホール、１２４ バーコード、１２５ 周縁部、１２６ 埋め込み電極、１２８ バンプ、１３０ 端子部、１５０ 半導体基板、１５１ 接合面、１５２ 半導体チップ、１５３ スルーホール、１５４ バーコード、１５５ 周縁部、１５６ 埋め込み電極、１５８ バンプ、１６２ 半導体チップ、１７２ インターポーザ、１７３ スルーホール、１７６ 埋め込み電極、１７８ バンプ、１８２ モールド部、１８４ アンダーフィル、２００ 基板貼り合わせ装置、２１０ 枠体、２１２ 天板、２１４ 支柱、２１６ 底板、２２０ 押圧部、２２２ シリンダ、２２４ ピストン、２３０ 加圧ステージ、２３２ 支持部、２３４ 第１基板保持部、２３５ アクチュエータ、２３６ ヒータ、２４０ 受圧ステージ、２４２ 第２基板保持部、２４４ 懸架部、２４６ ヒータ、２５０ 圧力検知部、２５２ ロードセル、２５４ ロードセル、２５６ ロードセル、３２０ ウエハホルダ、３５０ ウエハホルダ 100 laminated semiconductor device, 120 semiconductor substrate, 121 bonding surface, 122 semiconductor chip, 123 through hole, 124 barcode, 125 peripheral portion, 126 embedded electrode, 128 bump, 130 terminal portion, 150 semiconductor substrate, 151 bonding surface, 152 semiconductor Chip, 153 through hole, 154 barcode, 155 peripheral edge, 156 buried electrode, 158 bump, 162 semiconductor chip, 172 interposer, 173 through hole, 176 buried electrode, 178 bump, 182 mold part, 184 underfill, 200 substrate pasting Alignment device, 210 frame, 212 top plate, 214 support, 216 bottom plate, 220 pressing part, 222 cylinder, 224 piston, 230 pressure stage, 232 support part, 234 first substrate holding Department, 235 actuator, 236 heater, 240 pressure stage, 242 second substrate holder, 244 the suspension unit, 246 a heater, 250 a pressure sensing unit, 252 load cell 254 load cell 256 load cell 320 wafer holder 350 holder

Claims (7)

複数の半導体基板が積層された積層半導体基板において、
一対の半導体基板の互いに対向した接合側の面の間に配され、前記一対の半導体基板を電気的に接続する端子部と、
前記一対の半導体基板の少なくとも一方の半導体基板における接合側の面に設けられた識別用の刻印と、
を備え、
前記刻印が設けられた接合側の面からの前記端子部の高さが、前記刻印が設けられた接合側の面からの前記刻印の周縁部の高さより高い積層半導体基板。 In a laminated semiconductor substrate in which a plurality of semiconductor substrates are laminated,
A terminal portion disposed between surfaces of the pair of semiconductor substrates facing each other and electrically connecting the pair of semiconductor substrates;
An inscription for identification provided on a surface on the bonding side of at least one semiconductor substrate of the pair of semiconductor substrates;
With
A stacked semiconductor substrate, wherein a height of the terminal portion from a bonding side surface provided with the marking is higher than a height of a peripheral portion of the marking from the bonding side surface provided with the marking. 前記端子部は、前記刻印が設けられた接合側の面に配されたバンプを備え、
前記刻印が設けられた接合側の面からの前記バンプの高さが、前記刻印が設けられた接合側の面からの前記刻印の周縁部の高さより高い請求項１に記載の積層半導体基板。 The terminal portion includes a bump disposed on a surface on the bonding side provided with the marking,
2. The stacked semiconductor substrate according to claim 1, wherein a height of the bump from a surface on the bonding side provided with the marking is higher than a height of a peripheral portion of the marking from the surface on the bonding side provided with the marking. 前記端子部は、前記刻印が設けられた接合側の面と対向する接合側の面に配されたバンプを備え、
前記バンプが配された接合側の面からの前記バンプの高さが、前記刻印が設けられた接合側の面からの前記刻印の周縁部の高さより高い請求項１に記載の積層半導体基板。 The terminal portion includes a bump disposed on a surface on the bonding side opposite to the surface on the bonding side provided with the marking,
2. The stacked semiconductor substrate according to claim 1, wherein a height of the bump from a bonding side surface on which the bump is disposed is higher than a height of a peripheral edge portion of the marking from a bonding side surface on which the marking is provided. 前記端子部は、前記一対の半導体基板の一方の前記半導体基板における接合側の面に配された第１バンプと、前記一対の半導体基板の他方の前記半導体基板における接合側の面に配された第２バンプとを備え、
前記第１バンプが設けられた接合側の面からの前記第１バンプの高さと、前記第２バンプが設けられた接合側の面からの前記第２バンプの高さとの合計が、前記刻印が設けられた接合側の面からの前記刻印の周縁部の高さより高い請求項１に記載の積層半導体基板。 The terminal portion is disposed on a bonding-side surface of the other semiconductor substrate of the pair of semiconductor substrates, and a first bump disposed on a bonding-side surface of the semiconductor substrate of the pair of semiconductor substrates. With a second bump,
The sum of the height of the first bump from the surface on the bonding side provided with the first bump and the height of the second bump from the surface on the bonding side provided with the second bump is the mark The laminated semiconductor substrate according to claim 1, wherein the height is higher than a height of a peripheral portion of the inscription from a provided joint-side surface. 前記刻印は、前記一対の半導体基板の双方の接合側の面に設けられ、
各刻印が設けられた接合側の面からの前記端子部の高さが、各刻印が設けられた接合側の面からの各刻印の周縁部の高さの合計より高い請求項１に記載の積層半導体基板。 The inscription is provided on the surfaces on the bonding side of the pair of semiconductor substrates,
The height of the said terminal part from the surface of the joining side provided with each marking is higher than the sum total of the height of the peripheral part of each marking from the surface of the joining side provided with each marking. Multilayer semiconductor substrate. 前記刻印は、レーザを半導体基板の接合側の面に照射することにより当該接合側の面に形成された請求項１から請求項５までの何れか１項に記載の積層半導体基板。   6. The stacked semiconductor substrate according to claim 1, wherein the inscription is formed on a surface on a bonding side of the semiconductor substrate by irradiating a surface on the bonding side of the semiconductor substrate. 7. 複数の半導体基板が積層された積層半導体基板の製造方法であって、
互いに積層される一対の半導体基板の少なくとも一方の前記半導体基板の接合側の面に識別用の刻印を形成する刻印形成工程と、
互いに積層される一対の半導体基板の互いの接合側の面の間に、前記一対の半導体基板を電気的に接続する端子部を形成する端子部形成工程と、
を備え、
前記刻印形成工程及び前記端子部形成工程の少なくとも一方の工程において、前記刻印が設けられる接合側の面からの前記端子部の高さを、前記刻印が設けられる接合側の面からの前記刻印の周縁部の高さより高くする積層半導体基板の製造方法。 A method of manufacturing a laminated semiconductor substrate in which a plurality of semiconductor substrates are laminated,
A marking forming step of forming a marking for identification on a surface of the semiconductor substrate bonded side of at least one of a pair of semiconductor substrates stacked on each other;
A terminal portion forming step for forming a terminal portion for electrically connecting the pair of semiconductor substrates between the surfaces of the pair of semiconductor substrates stacked on each other on the bonding side;
With
In at least one of the marking forming step and the terminal portion forming step, the height of the terminal portion from the bonding side surface where the marking is provided is set to the height of the marking from the bonding side surface where the marking is provided. A manufacturing method of a laminated semiconductor substrate which is higher than a height of a peripheral edge.
JP2008299401A 2008-11-25 2008-11-25 Lamination semiconductor substrate, and method of manufacturing lamination semiconductor substrate Pending JP2010129576A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9190275B2 (en) 2013-03-22 2015-11-17 Sony Corporation Bonding substrates with electrical connection through insulating film

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11261001A (en) * 1998-03-13 1999-09-24 Japan Science & Technology Corp Manufacture of three dimensional semiconductor integrated circuit device
JP2000252176A (en) * 1999-02-25 2000-09-14 Komatsu Ltd Semiconductor die
JP2001217387A (en) * 2000-02-03 2001-08-10 Rohm Co Ltd Semiconductor device and method of manufacturing the same
JP2007273782A (en) * 2006-03-31 2007-10-18 Oki Electric Ind Co Ltd Method of manufacturing semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11261001A (en) * 1998-03-13 1999-09-24 Japan Science & Technology Corp Manufacture of three dimensional semiconductor integrated circuit device
JP2000252176A (en) * 1999-02-25 2000-09-14 Komatsu Ltd Semiconductor die
JP2001217387A (en) * 2000-02-03 2001-08-10 Rohm Co Ltd Semiconductor device and method of manufacturing the same
JP2007273782A (en) * 2006-03-31 2007-10-18 Oki Electric Ind Co Ltd Method of manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9190275B2 (en) 2013-03-22 2015-11-17 Sony Corporation Bonding substrates with electrical connection through insulating film

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