JP2010073913A - Protection circuit - Google Patents

Protection circuit Download PDF

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JP2010073913A
JP2010073913A JP2008240265A JP2008240265A JP2010073913A JP 2010073913 A JP2010073913 A JP 2010073913A JP 2008240265 A JP2008240265 A JP 2008240265A JP 2008240265 A JP2008240265 A JP 2008240265A JP 2010073913 A JP2010073913 A JP 2010073913A
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protection circuit
power supply
potential power
diode
terminal
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Mitsunori Tokunaga
光紀 徳永
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New Japan Radio Co Ltd
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New Japan Radio Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a protection circuit for effectively protecting an internal circuit against surge voltage. <P>SOLUTION: The protection circuit includes: a diode 11 with an anode connected to an input terminal 1, and an NPN-type transistor 13 with a collector connected to a cathode of the diode 11, a base connected to a low potential power terminal 4 through a bias resistor 12, and an emitter connected to the low potential power terminal 4. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体装置（ＩＣ）の入力端子又は出力端子が外部からサージ電圧の印加を受けたときに内部回路の保護を行う保護回路に関するものである。   The present invention relates to a protection circuit that protects an internal circuit when an input terminal or an output terminal of a semiconductor device (IC) receives an external surge voltage.

従来の入力保護回路３０Ａの例を図３に示す。この入力保護回路３０Ａは、半導体装置の入力端子１と内部回路２との間の接続ノードＮ１とＶＣＣの高電位電源端子３との間にＰ型クランプダイオード３１が図示の極性で接続され、また、接続ノードＮ１とＶＥＥの低電位電源端子４との間にＮ型クランプダイオード３２が図示の極性で接続されて構成されている。   An example of a conventional input protection circuit 30A is shown in FIG. In this input protection circuit 30A, a P-type clamp diode 31 is connected with a polarity shown between a connection node N1 between the input terminal 1 and the internal circuit 2 of the semiconductor device and the high potential power supply terminal 3 of VCC. The N-type clamp diode 32 is connected between the connection node N1 and the low potential power supply terminal 4 of the VEE with the polarity shown in the figure.

これらのダイオード３１，３２は、そのダイオード３１，３２のクランプ電圧を１Ｖ程度とすると、入力端子１に正のサージ電圧が印加した場合、そのサージ電流をダイオード３１を経由して高電位電源端子３に流して、ノードＮ１を「ＶＣＣ＋１Ｖ」程度にクランプする。また、入力端子１に負のサージ電圧が印加した場合、そのサージ電流を低電位電源端子４からダイオード３２を経由して入力端子１に流して、ノードＮ１を「ＶＥＥ−１Ｖ」程度にクランプする。このように、ノードＮ１の電圧をクランプし、サージ電流が内部回路２へ流れ込むことを防止することによって内部回路２を保護し、静電耐量を向上させている。   These diodes 31 and 32 assume that the clamp voltage of the diodes 31 and 32 is about 1 V, and when a positive surge voltage is applied to the input terminal 1, the surge current is passed through the diode 31 to the high potential power supply terminal 3. The node N1 is clamped to about “VCC + 1V”. When a negative surge voltage is applied to the input terminal 1, the surge current flows from the low potential power supply terminal 4 to the input terminal 1 via the diode 32, and the node N 1 is clamped to about “VEE-1V”. . In this way, the voltage at the node N1 is clamped and the surge current is prevented from flowing into the internal circuit 2, thereby protecting the internal circuit 2 and improving the electrostatic resistance.

ところが、この入力保護回路３０Ａでは、入力端子１に正又は負のサージ電圧が印加された場合に、ダイオード３１又はダイオード３２を経由して高電位電源端子３又は低電位電源端子４に指数関数的な電流が流れるので、そのサージ電流が大きな場合、ダイオード３１，３２が破壊される恐れがあり、また電源回路および前段回路等に不具合をもたらす欠点がある。   However, in this input protection circuit 30A, when a positive or negative surge voltage is applied to the input terminal 1, it is exponentially applied to the high potential power supply terminal 3 or the low potential power supply terminal 4 via the diode 31 or the diode 32. Since a large current flows, if the surge current is large, the diodes 31 and 32 may be destroyed, and the power supply circuit and the pre-stage circuit have problems.

そこで、図４に示すような入力保護回路３０が提案されている（例えば、特許文献１〜３参照）。この入力保護回路３０は、図３の入力保護回路３０Ａのダイオード３１，３２の他に、入力端子１とノードＮ１との間に、ポリシリコンの電流制限抵抗３３（数ｋΩ〜１０ｋΩ程度）を直列接続したものである。   Thus, an input protection circuit 30 as shown in FIG. 4 has been proposed (see, for example, Patent Documents 1 to 3). In addition to the diodes 31 and 32 of the input protection circuit 30A of FIG. 3, the input protection circuit 30 includes a polysilicon current limiting resistor 33 (several kΩ to about 10 kΩ) in series between the input terminal 1 and the node N1. It is connected.

この入力保護回路３０では、入力端子１に正又は負のサージ電圧が印加した場合、指数関数的なサージ電流が電流制限抵抗３３によって大きく減衰されて、ダイオード３１，３２に流れるので、そのダイオード３１，３２の破壊や電源回路および前段回路等に不具合をもたらす問題を解消できる。
特開昭５３−０７６６７９号公報 特開昭５８−１２３７６３号公報 特開平０２−２１４１５１号公報 In this input protection circuit 30, when a positive or negative surge voltage is applied to the input terminal 1, an exponential surge current is greatly attenuated by the current limiting resistor 33 and flows to the diodes 31 and 32. , 32 and problems that cause problems in the power supply circuit and the previous circuit can be solved.
Japanese Patent Laid-Open No. 53-076679 JP 58-123763 A Japanese Patent Laid-Open No. 02-214151

ところが、図４の入力保護回路３０では、ＥＳＤ（Electro Static Discharge）等のようにある限度を超えたサージ電圧（数百Ｖ）が入力端子１に印加したときは、電流制限抵抗３３が破壊され易くなり、これを防止するためにはその電流制限抵抗３３のポリシリコンを大きくしなければならないという問題がある。また、その電流制限抵抗３３が破壊されない場合であっても、高電位電源端子３や低電位電源端子４に十分なサージ電流を流すことができず、内部回路２が悪影響を受ける恐れがある。   However, in the input protection circuit 30 of FIG. 4, when a surge voltage (several hundred volts) exceeding a certain limit such as ESD (Electro Static Discharge) is applied to the input terminal 1, the current limiting resistor 33 is destroyed. In order to prevent this, there is a problem that the polysilicon of the current limiting resistor 33 must be enlarged. Even if the current limiting resistor 33 is not destroyed, a sufficient surge current cannot be supplied to the high potential power supply terminal 3 or the low potential power supply terminal 4, and the internal circuit 2 may be adversely affected.

本発明の目的は、サージ電圧に対して内部回路が有効に保護される保護回路を提供することである。   An object of the present invention is to provide a protection circuit in which an internal circuit is effectively protected against a surge voltage.

上記課題を解決するために、請求項１にかかる発明の保護回路は、半導体装置の入力端子又は出力端子にアノードが接続される第１のダイオードと、該第１のダイオードのカソードにコレクタが接続され、ベースが第１のバイアス抵抗を介して前記半導体装置の低電位電源端子に接続され、エミッタが該低電位電源端子に接続される第１のＮＰＮ型のトランジスタと、からなることを特徴とする。
請求項２にかかる発明の保護回路は、半導体装置の低電位電源端子にアノードが接続される第２のダイオードと、該第２のダイオードのカソードにコレクタが接続され、ベースが第２のバイアス抵抗を介して前記半導体装置の入力端子又は出力端子に接続され、エミッタが前記入力端子又は出力端子に接続される第２のＮＰＮ型のトランジスタと、からなることを特徴とする。
請求項３にかかる発明の保護回路は、半導体装置の入力端子と低電位電源端子との間に接続された請求項１の保護回路を第１の保護回路とし、前記入力端子と前記低電位電源端子との間に接続された請求項２の保護回路を第２の保護回路とし、前記入力端子と前記半導体装置の内部回路の間に接続された電流制限抵抗と、アノードが前記内部回路にカソードが前記半導体装置の高電位電源端子に接続された第３のダイオードと、アノードが前記低電位電源端子にカソードが前記内部回路に接続された第４のダイオードとを有する回路を第３の保護回路とすることを特徴とする。 In order to solve the above-described problem, a protection circuit according to a first aspect of the present invention includes a first diode having an anode connected to an input terminal or an output terminal of a semiconductor device, and a collector connected to a cathode of the first diode. And a base connected to the low potential power supply terminal of the semiconductor device via a first bias resistor, and an emitter connected to the low potential power supply terminal. To do.
According to a second aspect of the present invention, there is provided a protection circuit comprising: a second diode having an anode connected to the low potential power supply terminal of the semiconductor device; a collector connected to the cathode of the second diode; And a second NPN transistor connected to an input terminal or an output terminal of the semiconductor device through an emitter and having an emitter connected to the input terminal or the output terminal.
According to a third aspect of the present invention, there is provided a protection circuit according to the first aspect, wherein the first protection circuit is connected between an input terminal of a semiconductor device and a low potential power supply terminal, and the input terminal and the low potential power supply are connected. A protection circuit according to claim 2 connected between the input terminal and the terminal is a second protection circuit, a current limiting resistor connected between the input terminal and the internal circuit of the semiconductor device, and an anode as a cathode to the internal circuit A third protection circuit includes a third diode connected to the high potential power supply terminal of the semiconductor device and a fourth diode having an anode connected to the low potential power supply terminal and a cathode connected to the internal circuit. It is characterized by.

請求項１にかかる発明の保護回路によれば、入力端子又は出力端子にＥＳＤ等のようにある限度を超えた正のサージ電圧が印加したとき、そのサージ電流が入力端子又は出力端子から低電位電源端子に流れることで回避され、入力端子又は出力端子に接続された内部回路が正のサージ電圧から保護される。
請求項２にかかる発明の保護回路によれば、入力端子又は出力端子にＥＳＤ等のようにある限度を超えた負のサージ電圧が印加したとき、そのサージ電流が低電位電源端子から入力端子又は出力端子に流れることで回避され、入力端子又は出力端子に接続された内部回路が負のサージ電圧から保護される。
請求項３にかかる発明の保護回路によれば、入力端子にＥＳＤ等よりも低い正又は負のサージ電圧が印加したときは、そのサージ電流が第３の保護回路で減衰されて正電位電源端子あるいは負電位電源端子に流れることで回避され、内部回路が保護される。入力端子にＥＳＤ等のようにある限度を超えた正又は負のサージ電圧が印加したときは、そのサージ電流が第１又は第２の保護回路を経由して流れることで回避され、内部回路が保護される。 According to the protection circuit of the first aspect of the present invention, when a positive surge voltage exceeding a certain limit such as ESD is applied to the input terminal or the output terminal, the surge current is low potential from the input terminal or the output terminal. It is avoided by flowing to the power supply terminal, and the internal circuit connected to the input terminal or the output terminal is protected from a positive surge voltage.
According to the protection circuit of the second aspect of the present invention, when a negative surge voltage exceeding a certain limit such as ESD is applied to the input terminal or the output terminal, the surge current is reduced from the low potential power supply terminal to the input terminal or the output terminal. This is avoided by flowing to the output terminal, and the internal circuit connected to the input terminal or the output terminal is protected from a negative surge voltage.
According to the protection circuit of the invention according to claim 3, when a positive or negative surge voltage lower than ESD or the like is applied to the input terminal, the surge current is attenuated by the third protection circuit, and the positive potential power supply terminal Alternatively, it is avoided by flowing to the negative potential power supply terminal, and the internal circuit is protected. When a positive or negative surge voltage exceeding a certain limit, such as ESD, is applied to the input terminal, the surge current is avoided by flowing through the first or second protection circuit, and the internal circuit is Protected.

図１に本発明の１つの実施例の入力保護回路を示す。１は入力端子、２は内部回路、３は高電位電源端子、４は低電位電源端子、１０は第１の保護回路、２０は第２の保護回路、３０は第３の保護回路である。これらはすべて半導体装置内に構成される。第１〜第３の保護回路１０〜３０によって入力保護回路が構成される。   FIG. 1 shows an input protection circuit according to one embodiment of the present invention. Reference numeral 1 denotes an input terminal, 2 denotes an internal circuit, 3 denotes a high potential power supply terminal, 4 denotes a low potential power supply terminal, 10 denotes a first protection circuit, 20 denotes a second protection circuit, and 30 denotes a third protection circuit. These are all configured in a semiconductor device. The first to third protection circuits 10 to 30 constitute an input protection circuit.

第１の保護回路１０は、入力端子１と低電位電源端子４との間に接続される。すなわち、アノードが入力端子１に接続されたＰ型クランプダイオード１１、そのダイオード１１のカソードにコレクタが接続され、エミッタが低電位電源端子４に接続され、ベースがポリシリコンのバイアス抵抗１２（数ｋΩ〜数十ｋΩ）を介して低電位電源端子４に接続されたＮＰＮ型のトランジスタ１３からなる。   The first protection circuit 10 is connected between the input terminal 1 and the low potential power supply terminal 4. That is, a P-type clamp diode 11 whose anode is connected to the input terminal 1, a collector is connected to the cathode of the diode 11, an emitter is connected to the low-potential power supply terminal 4, and a base is a bias resistor 12 (several kΩ) NPN transistor 13 connected to the low-potential power supply terminal 4 through .about.several tens of k.OMEGA.).

第２の保護回路２０も、入力端子１と低電位電源端子４との間に接続される。すなわちアノードが低電位電源端子４に接続されたＮ型クランプダイオード２１、そのダイオード２１のカソードにコレクタが接続され、エミッタが入力端子１に接続され、ベースがポリシリコンのバイアス抵抗２２（数ｋΩ〜数十ｋΩ）を介して入力端子１に接続されたＮＰＮ型のトランジスタ２３からなる。   The second protection circuit 20 is also connected between the input terminal 1 and the low potential power supply terminal 4. That is, an N-type clamp diode 21 whose anode is connected to the low-potential power supply terminal 4, a collector is connected to the cathode of the diode 21, an emitter is connected to the input terminal 1, and a base is a bias resistor 22 (several kΩ˜ It consists of an NPN transistor 23 connected to the input terminal 1 via several tens of kΩ).

第３の保護回路３０は、図４で説明したものと同じ構成であり、アノードがノードＮ１にカソードが高電位電源端子３に接続されたＰ型クランプダイオード３１、アノードが低電位電源端子４にカソードがノードＮ１に接続されたＮ型クランプダイオード３２、および入力端子１とノードＮ１との間に直列接続されたポリシリコンの電流制限抵抗３３からなる。   The third protection circuit 30 has the same configuration as that described with reference to FIG. 4. The anode is connected to the node N1 and the cathode is connected to the high potential power supply terminal 3. The anode is connected to the low potential power supply terminal 4. An N-type clamp diode 32 having a cathode connected to the node N1 and a polysilicon current limiting resistor 33 connected in series between the input terminal 1 and the node N1.

図２は半導体装置内に構成した第１および第２の保護回路１０，２０の断面図である。図２において、４１は低濃度Ｐ型の基板、４２〜４５は高濃度Ｎ型の埋込領域、４６〜４９は低濃度Ｎ型のエピタキシャル成長領域、５０〜５２は高濃度Ｐ型の拡散等による島、５３〜５８は高濃度Ｎ型の取出領域である。第１の保護回路１０のダイオード１１は島５０とエピタキシャル成長領域４６の境界に形成される。トランジスタ１３はエピタキシャル成長領域４７がコレクタ、島５１がベース、取出領域５５がエミッタとなる。また、第２の保護回路２０のダイオード２１は基板４１とエピタキシャル成長領域４９との境界に形成される。トランジスタ２３はエピタキシャル成長領域４８がコレクタ、島５２がベース、取出領域５６がエミッタとなる。   FIG. 2 is a cross-sectional view of the first and second protection circuits 10 and 20 configured in the semiconductor device. In FIG. 2, 41 is a low-concentration P-type substrate, 42 to 45 are high-concentration N-type buried regions, 46 to 49 are low-concentration N-type epitaxial growth regions, and 50 to 52 are high-concentration P-type diffusions. The islands 53 to 58 are high-concentration N-type extraction regions. The diode 11 of the first protection circuit 10 is formed at the boundary between the island 50 and the epitaxial growth region 46. In the transistor 13, the epitaxial growth region 47 is a collector, the island 51 is a base, and the extraction region 55 is an emitter. The diode 21 of the second protection circuit 20 is formed at the boundary between the substrate 41 and the epitaxial growth region 49. In the transistor 23, the epitaxial growth region 48 is a collector, the island 52 is a base, and the extraction region 56 is an emitter.

さて、入力端子１に、高電位電源端子３の電圧ＶＣＣより高い正のサージ電圧（数十Ｖ）、あるいは低電位電源端子４の電圧ＶＥＥより低い負のサージ電圧（−数十Ｖ）、が印加したときは、第３の保護回路３０が、サージ電流を電流制限抵抗３３によって抑制して、ダイオード３１又は３２を経由して高電位電源端子３又は低電位電源端子４に流すので、ダイオード３１，３２の保護および電源回路や前段回路の保護が効果的に行われる。また、内部回路２（ノードＮ１）には素子耐圧以下（ＶＣＣ＋１Ｖ、又はＶＥＥ−１Ｖ程度）の電圧しか印加されないため、内部回路２の保護も完全となる。   Now, a positive surge voltage (several tens of volts) higher than the voltage VCC of the high potential power supply terminal 3 or a negative surge voltage (−several tens of volts) lower than the voltage VEE of the low potential power supply terminal 4 is applied to the input terminal 1. When applied, the third protection circuit 30 suppresses the surge current by the current limiting resistor 33 and flows it to the high potential power supply terminal 3 or the low potential power supply terminal 4 via the diode 31 or 32, so that the diode 31 , 32 and the power supply circuit and the previous circuit are effectively protected. Further, since only a voltage equal to or lower than the element breakdown voltage (about VCC + 1V or VEE-1V) is applied to the internal circuit 2 (node N1), the protection of the internal circuit 2 is also complete.

次に、入力端子１に素子耐圧を超えるＥＳＤ等の限度を超えた正のサージ電圧（数百Ｖ）が印加されたときは、第１の保護回路１０において、入力端子１からダイオード１１とトランジスタ１３のコレタタ・ベース間寄生ダイオード１４（図２参照）を介して抵抗１２にアバランシェ電流が流れ低電位電源端子４に至るので、その抵抗１２の両端に電位差が発生する。この電圧によりトランジスタ１３のベース・エミッタ間に順方向バイアス電圧がかかり、スナップバック現象によって、そのトランジスタ１３が導通状態になり、入力端子１と低電位電源端子４間に電荷の回避経路（ダイオード１１とトランジス１３）が形成され、そこに十分なサージ電流が流れる。これによって、内部回路２側にかかる電圧を素子耐圧以下に降圧させることができ、静電耐量を十分に向上させることができる。スナップバック現象の発生する電圧は、抵抗１２の値によって設定できる。   Next, when a positive surge voltage (several hundred volts) exceeding the limit of ESD or the like exceeding the element withstand voltage is applied to the input terminal 1, the diode 11 and the transistor from the input terminal 1 in the first protection circuit 10 are applied. Since the avalanche current flows through the resistor 12 via the 13 collector-base parasitic diodes 14 (see FIG. 2) and reaches the low-potential power supply terminal 4, a potential difference is generated between both ends of the resistor 12. Due to this voltage, a forward bias voltage is applied between the base and emitter of the transistor 13, and the transistor 13 becomes conductive due to a snapback phenomenon, and a charge avoidance path (diode 11) between the input terminal 1 and the low potential power supply terminal 4. And a transistor 13) are formed, and a sufficient surge current flows there. As a result, the voltage applied to the internal circuit 2 can be lowered to the element withstand voltage or less, and the electrostatic withstand can be sufficiently improved. The voltage at which the snapback phenomenon occurs can be set by the value of the resistor 12.

また、入力端子１に素子耐圧を超えるＥＳＤ等の限度を超えた負のサージ電圧（数百Ｖ）が印加されたときは、第２の保護回路２０において、低電位電源端子４からダイオード２１とトランジスタ２３のコレタタ・ベース間寄生ダイオード２４（図２参照）を介して抵抗２２にアバランシェ電流が流れ入力端子１に至るので、その抵抗２２の両端に電位差が発生する。この電圧によりトランジスタ２３のベース・エミッタ間に順方向バイアス電圧がかかり、スナップバック現象によって、そのトランジスタ２３が導通状態になり、入力端子１と低電位電源端子４間に電荷の回避経路（ダイオード２１とトランジスタ２３）が形成され、そこに十分なサージ電流が流れる。これによって、内部回路２側にかかる電圧を素子耐圧以下に降圧させることができ、静電耐量を十分に向上させることができる。スナップバック現象の発生する電圧は、抵抗２２の値によって設定できる。   Further, when a negative surge voltage (several hundreds V) exceeding the limit of ESD or the like exceeding the element withstand voltage is applied to the input terminal 1, the second protection circuit 20 is connected to the diode 21 from the low potential power supply terminal 4. Since an avalanche current flows through the resistor 22 via the collector-base parasitic diode 24 (see FIG. 2) of the transistor 23 and reaches the input terminal 1, a potential difference is generated between both ends of the resistor 22. Due to this voltage, a forward bias voltage is applied between the base and emitter of the transistor 23, and the transistor 23 becomes conductive due to the snapback phenomenon, and a charge avoidance path (diode 21) between the input terminal 1 and the low potential power supply terminal 4. Transistor 23) is formed, and a sufficient surge current flows there. As a result, the voltage applied to the internal circuit 2 can be lowered to the element withstand voltage or less, and the electrostatic withstand can be sufficiently improved. The voltage at which the snapback phenomenon occurs can be set by the value of the resistor 22.

なお、第１の保護回路１０のダイオード１１および第２の保護回路２０のダイオード２１は必須である。例えば、ダイオード１１を削除すると、入力端子１に負のサージ電圧が印加したとき、トランジスタ１３のコレクタ４７と低電位電源端子４に接続される基板４１との間の寄生ダイオード１５（図２参照）を経由してサージ電流が流れ、低電位電源端子４側へのサージ電流が過大となり、電源回路の保護が不十分となる。   Note that the diode 11 of the first protection circuit 10 and the diode 21 of the second protection circuit 20 are essential. For example, when the diode 11 is eliminated, when a negative surge voltage is applied to the input terminal 1, the parasitic diode 15 between the collector 47 of the transistor 13 and the substrate 41 connected to the low potential power supply terminal 4 (see FIG. 2). A surge current flows through the low-potential power supply terminal 4 and the surge current to the low potential power supply terminal 4 becomes excessive, and the protection of the power supply circuit becomes insufficient.

また、ダイオード２１を削除すると、入力端子１に正のサージ電圧が印加したとき、抵抗２２とトランジスタ２３のベース・コレクタ間のダイオード２４（図２参照）をサージ電流が流れるので、そのサージ電流が抑制され、十分なサージ電流を流すことができなくなり、その分だけ内部回路２へのサージ電流が増えてその保護が不十分となる。   If the diode 21 is eliminated, when a positive surge voltage is applied to the input terminal 1, a surge current flows through the diode 24 (see FIG. 2) between the resistor 22 and the base and collector of the transistor 23. This prevents the surge current from flowing sufficiently, and the surge current to the internal circuit 2 increases by that amount, resulting in insufficient protection.

なお、以上では入力端子１の保護について説明したが、出力端子についても同様に保護回路１０，２０を接続することで、その保護を行うことができることは勿論である。ただし、出力端子を保護するとき、第３の保護回路３０の抵抗３３が通常動作に悪影響を及ぼす恐れがある場合は、その第３の保護回路３０を使用することは好ましくない。   Although the protection of the input terminal 1 has been described above, the output terminal can be protected by connecting the protection circuits 10 and 20 in the same manner. However, when protecting the output terminal, if the resistor 33 of the third protection circuit 30 may adversely affect normal operation, it is not preferable to use the third protection circuit 30.

本発明の１つの実施例の入力保護回路の回路図である。It is a circuit diagram of the input protection circuit of one Example of this invention. 半導体装置に構成した図１の入力保護回路の断面図である。It is sectional drawing of the input protection circuit of FIG. 1 comprised to the semiconductor device. 従来の入力保護回路の回路図である。It is a circuit diagram of the conventional input protection circuit. 従来の別の入力保護回路の回路図である。It is a circuit diagram of another conventional input protection circuit.

符号の説明Explanation of symbols

１：入力端子、２：内部回路、３：高電位電源端子、４：低電位電源端子
１０：第１の保護回路、１１：ダイオード、１２：バイアス抵抗、１３：トランジスタ、１４，１５：寄生ダイオード
２０：第２の保護回路、２１：ダイオード、２２：バイアス抵抗、２３：トランジスタ、２４：寄生ダイオード
３０：第３の保護回路、３１，３２：ダイオード、３３：電流制限抵抗 1: input terminal, 2: internal circuit, 3: high potential power supply terminal, 4: low potential power supply terminal, 10: first protection circuit, 11: diode, 12: bias resistor, 13: transistor, 14, 15: parasitic diode 20: second protection circuit, 21: diode, 22: bias resistor, 23: transistor, 24: parasitic diode 30: third protection circuit, 31, 32: diode, 33: current limiting resistor

Claims (3)

半導体装置の入力端子又は出力端子にアノードが接続される第１のダイオードと、該第１のダイオードのカソードにコレクタが接続され、ベースが第１のバイアス抵抗を介して前記半導体装置の低電位電源端子に接続され、エミッタが該低電位電源端子に接続される第１のＮＰＮ型のトランジスタと、からなることを特徴とする保護回路。   A first diode having an anode connected to an input terminal or an output terminal of the semiconductor device, a collector connected to a cathode of the first diode, and a base connected to the low potential power source of the semiconductor device via a first bias resistor And a first NPN-type transistor connected to the terminal and having an emitter connected to the low-potential power supply terminal. 半導体装置の低電位電源端子にアノードが接続される第２のダイオードと、該第２のダイオードのカソードにコレクタが接続され、ベースが第２のバイアス抵抗を介して前記半導体装置の入力端子又は出力端子に接続され、エミッタが前記入力端子又は出力端子に接続される第２のＮＰＮ型のトランジスタと、からなることを特徴とする保護回路。   A second diode having an anode connected to a low potential power supply terminal of the semiconductor device; a collector connected to a cathode of the second diode; and a base connected to an input terminal or an output of the semiconductor device via a second bias resistor. A protection circuit comprising: a second NPN transistor connected to a terminal and having an emitter connected to the input terminal or the output terminal. 半導体装置の入力端子と低電位電源端子との間に接続された請求項１の保護回路を第１の保護回路とし、
前記入力端子と前記低電位電源端子との間に接続された請求項２の保護回路を第２の保護回路とし、
前記入力端子と前記半導体装置の内部回路の間に接続された電流制限抵抗と、アノードが前記内部回路にカソードが前記半導体装置の高電位電源端子に接続された第３のダイオードと、アノードが前記低電位電源端子にカソードが前記内部回路に接続された第４のダイオードとを有する回路を第３の保護回路とすることを特徴とする保護回路。 The protection circuit of claim 1 connected between the input terminal of the semiconductor device and the low-potential power supply terminal is a first protection circuit,
The protection circuit according to claim 2 connected between the input terminal and the low potential power supply terminal as a second protection circuit,
A current limiting resistor connected between the input terminal and the internal circuit of the semiconductor device; a third diode whose anode is connected to the internal circuit; and a cathode is connected to the high potential power supply terminal of the semiconductor device; A circuit having a low-potential power supply terminal and a fourth diode having a cathode connected to the internal circuit is defined as a third protection circuit.
JP2008240265A 2008-09-19 2008-09-19 Protection circuit Withdrawn JP2010073913A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012001916A1 (en) * 2010-06-30 2012-01-05 Canon Kabushiki Kaisha Solid-state imaging device and imaging system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012001916A1 (en) * 2010-06-30 2012-01-05 Canon Kabushiki Kaisha Solid-state imaging device and imaging system
JP2012015277A (en) * 2010-06-30 2012-01-19 Canon Inc Solid-state imaging apparatus, and imaging system
US9252169B2 (en) 2010-06-30 2016-02-02 Canon Kabushiki Kaisha Solid-state imaging device and imaging system
US9899449B2 (en) 2010-06-30 2018-02-20 Canon Kabushiki Kaisha Solid-state imaging device and imaging system
US10304899B2 (en) 2010-06-30 2019-05-28 Canon Kabushiki Kaisha Solid-state imaging device and imaging system
US11102440B2 (en) 2010-06-30 2021-08-24 Canon Kabushiki Kaisha Solid-state imaging device and imaging system

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