JP2010062291A - Semiconductor substrate and its manufacturing method - Google Patents

Semiconductor substrate and its manufacturing method Download PDF

Info

Publication number
JP2010062291A
JP2010062291A JP2008225818A JP2008225818A JP2010062291A JP 2010062291 A JP2010062291 A JP 2010062291A JP 2008225818 A JP2008225818 A JP 2008225818A JP 2008225818 A JP2008225818 A JP 2008225818A JP 2010062291 A JP2010062291 A JP 2010062291A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
silicon
single crystal
substrate
nitrogen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008225818A
Other languages
Japanese (ja)
Inventor
Takehiro Hisatomi
健博 久富
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Corp
Original Assignee
Sumco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corp filed Critical Sumco Corp
Priority to JP2008225818A priority Critical patent/JP2010062291A/en
Priority to US12/548,762 priority patent/US20100052093A1/en
Publication of JP2010062291A publication Critical patent/JP2010062291A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor substrate used for manufacturing an SOI (silicon-on-insulator) substrate having the SOI structure having no relatively small sized defect on the surface, and to provide a method for manufacturing the semiconductor substrate. <P>SOLUTION: The semiconductor substrate 1 is used for manufacturing the SOI substrate having the SOI structure with a silicon oxide film and a silicon single crystal sequentially provided on the surface of the silicon substrate. A region 2 comprising the silicon single crystal layer having a thickness of not more than 10 μm and including no nitrogen is formed in the vicinity of the surface 1a, and a nitrogen concentration of a region 3 including nitrogen as a part excepting the region 2 is in the range of 1×10<SP>13</SP>to 5×10<SP>15</SP>atom/cm<SP>3</SP>. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体基板及びその製造方法に関し、更に詳しくは、シリコン酸化膜等の絶縁膜上に単結晶シリコン層を形成したＳＯＩ（Silicon On Insulator）構造を有する半導体基板及びその製造方法に関するものである。   The present invention relates to a semiconductor substrate and a manufacturing method thereof, and more particularly to a semiconductor substrate having an SOI (Silicon On Insulator) structure in which a single crystal silicon layer is formed on an insulating film such as a silicon oxide film and a manufacturing method thereof. is there.

近年、半導体回路の高集積化に伴い素子の微細化が促進され、その基板の元となるチョクラルスキー法（以下、「ＣＺ法」という）にて作製されたシリコン単結晶に対する品質要求が高まっており、さらに、低電力化に伴い表面直下にシリコン酸化膜等の絶縁膜を有するＳＯＩ基板（ＳＯＩウェーハ）が必要となってきた。
このＳＯＩ基板を作製する方法としては、シリコン基板に酸素のイオン注入を行うことにより、このシリコン基板の内部に埋め込み酸化膜を形成するＳＩＭＯＸ法（Separation by Ion Implanted Oxygen）が広く用いられている。
このＳＯＩ層に形成されたデバイスは、高放射線耐性、ラッチアップ耐性、ショートチャネル効果の抑制を有し、しかも低消費電力動作が可能となるため、ＳＯＩ基板が次世代高機能半導体基板として期待されている。 In recent years, miniaturization of elements has been promoted along with higher integration of semiconductor circuits, and quality requirements for a silicon single crystal produced by the Czochralski method (hereinafter referred to as “CZ method”) that is the base of the substrate have increased. Furthermore, with the reduction in power consumption, an SOI substrate (SOI wafer) having an insulating film such as a silicon oxide film immediately below the surface has become necessary.
As a method for manufacturing this SOI substrate, a SIMOX method (Separation by Ion Implanted Oxygen) in which a buried oxide film is formed inside the silicon substrate by ion implantation of oxygen into the silicon substrate is widely used.
The device formed in this SOI layer has high radiation resistance, latch-up resistance, suppression of short channel effect, and can operate with low power consumption. Therefore, an SOI substrate is expected as a next-generation high-performance semiconductor substrate. ing.

一般的に、チョクラルスキー法によって育成されたシリコン単結晶を加工して得られた鏡面研磨基板は、例えばＣＯＰ（Crystal Originated Particle）等の結晶育成時に導入される結晶欠陥がゲート酸化膜の耐圧劣化の要因となることが知られている。従って、デバイスメーカでは、結晶欠陥密度を低減させた基板、例えば、シリコン基板上に単結晶シリコンをエピタキシャル成長させた基板、あるいは低速引き上げ条件により育成された結晶欠陥を大幅に低減させた基板を使用することでゲート酸化膜の絶縁不良による歩留改善を実施している。   In general, a mirror-polished substrate obtained by processing a silicon single crystal grown by the Czochralski method has a crystal defect introduced during crystal growth, such as COP (Crystal Originated Particle), for example. It is known to cause deterioration. Therefore, a device manufacturer uses a substrate with a reduced crystal defect density, for example, a substrate obtained by epitaxially growing single crystal silicon on a silicon substrate, or a substrate with greatly reduced crystal defects grown under a slow pulling condition. As a result, the yield is improved by the insulation failure of the gate oxide film.

ＳＯＩ基板についても同様であり、ＳＩＭＯＸ法によるＳＯＩ基板においても、ＣＯＰもしくはボイド欠陥が基板表面もしくは表面近傍に存在することで、最終製品でのＳＯＩ層の表面上にピンホール欠陥などを誘発させデバイス特性を劣化させることになる。ＳＩＭＯＸ法では、イオン注入による照射欠陥を回復させ、さらに、打ち込まれた酸素を均質な欠陥のない埋め込み酸化膜とするために、高い温度（１３００℃以上）でのアニールが必要とされるが、基板表面に１０μｍ程度の大きさの四角錐あるいは円形状のくぼみが数十〜数百個／ｃｍ２発生する。 The same is true for SOI substrates. Even in SOI substrates based on the SIMOX method, COP or void defects exist on or near the surface of the substrate, thereby inducing pinhole defects on the surface of the SOI layer in the final product. The characteristics will be deteriorated. In the SIMOX method, annealing at a high temperature (1300 ° C. or higher) is required in order to recover irradiation defects caused by ion implantation and to make the implanted oxygen into a buried oxide film having no homogeneous defects. Several tens to several hundreds / cm 2 of quadrangular pyramids or circular depressions having a size of about 10 μm are generated on the substrate surface.

この高温アニール時に生じるくぼみ（ピット）はサーマルピットと呼ばれ、埋め込み酸化膜上のシリコン単結晶の膜厚を変化させるばかりでなく、しばしば埋め込み酸化膜自体をも破壊し、さらには貫通し、ＳＯＩ構造自体を破壊することとなる。このため、このサーマルピットが発生した箇所に形成されたデバイスは、デバイス本来の機能を発揮することができず、ＳＩＭＯＸウェーハを用いてデバイスを作製する際の大きな問題となっている。   The depression (pit) generated during the high-temperature annealing is called a thermal pit, which not only changes the film thickness of the silicon single crystal on the buried oxide film, but also often destroys the buried oxide film itself, and further penetrates it. The structure itself will be destroyed. For this reason, the device formed at the location where the thermal pits are generated cannot exhibit the original function of the device, which is a serious problem when a device is manufactured using a SIMOX wafer.

そこで、このＳＯＩ層の表面にピンホール欠陥などを誘発させないＳＩＭＯＸ基板の製造方法として、窒素を１×１０１４ａｔｏｍｓ／ｃｍ３〜１×１０１７ａｔｏｍｓ／ｃｍ３含むシリコン単結晶を用いた製造方法が提案されている（特許文献１参照）。
この製造方法では、ＳＩＭＯＸ法における高温アニール時に発生するサーマルピット等の欠陥の発生を、シリコン結晶中に微量の窒素を添加した半導体基板を適用することで抑制することができる。この抑制効果を発揮するために必要な窒素濃度は、高温アニール前においては１×１０１４〜１×１０１８ａｔｏｍｓ／ｃｍ３であり、高温アニール後においては１×１０１２〜１×１０１７ａｔｏｍｓ／ｃｍ３である。 Therefore, as a method for manufacturing a SIMOX substrate that does not induce pinhole defects or the like on the surface of this SOI layer, a method using a silicon single crystal containing 1 × 10 14 atoms / cm 3 to 1 × 10 17 atoms / cm 3 of nitrogen. Has been proposed (see Patent Document 1).
In this manufacturing method, the occurrence of defects such as thermal pits generated during high-temperature annealing in the SIMOX method can be suppressed by applying a semiconductor substrate in which a small amount of nitrogen is added to a silicon crystal. The nitrogen concentration necessary to exert this suppression effect is 1 × 10 14 to 1 × 10 18 atoms / cm 3 before high-temperature annealing, and 1 × 10 12 to 1 × 10 17 atoms after high-temperature annealing. / Cm 3 .

ところで、このシリコン単結晶中に微量の窒素が存在した場合、（１）デバイス作製時の熱処理により発生する熱応力を緩和する、（２）セコエッチング液等のエッチング液によるエッチピットの発生を抑制する、等の効果があることが知られているが、ＳＩＭＯＸ法で用いられる高温アニール時の欠陥発生への影響は知られていなかった。例えば、このＳＯＩ基板の製造方法では、窒素を含むシリコン基板に酸素イオンを注入し、その後１３５０℃で０．５％の酸素ガスを４時間、さらに酸素濃度７０％で更に４時間熱処理することにより、ＳＯＩ層の表面の０．３μｍ以上のサーマルピットの数が０個になっている。
特開平１０−６４８３７号公報 By the way, when a small amount of nitrogen is present in this silicon single crystal, (1) Relieve the thermal stress generated by heat treatment during device fabrication, (2) Suppress the generation of etch pits due to etchant such as Seco etchant However, the effect on the generation of defects during high-temperature annealing used in the SIMOX method has not been known. For example, in this method for manufacturing an SOI substrate, oxygen ions are implanted into a silicon substrate containing nitrogen, and then heat treatment is performed at 1350 ° C. with 0.5% oxygen gas for 4 hours and further with an oxygen concentration of 70% for 4 hours. The number of thermal pits of 0.3 μm or more on the surface of the SOI layer is zero.
Japanese Patent Laid-Open No. 10-64837

しかしながら、上述した特許文献１の製造方法においても、その基板の表面近傍に０．３μｍ未満のサイズの欠陥が高密度で存在しているという問題点があった（例えば、特開２００６−２６１６３２号公報等参照）。
すなわち、この現象は、微量酸素濃度のガス雰囲気では結晶欠陥が消滅しないことを示しており、したがって、この製造方法では、０．３μｍ未満のサイズの欠陥を消滅させることができないという問題点が依然として残存している。
また、半導体回路の高集積化に伴い素子の微細化が促進される昨今においては、この０．３μｍ未満のサイズの欠陥は、後のデバイス工程においては致命的な欠陥となる。 However, the above-described manufacturing method disclosed in Patent Document 1 also has a problem in that defects having a size of less than 0.3 μm are present at high density near the surface of the substrate (for example, Japanese Patent Laid-Open No. 2006-261632). (See publications).
That is, this phenomenon shows that crystal defects are not eliminated in a gas atmosphere with a trace oxygen concentration, and therefore, this manufacturing method still has a problem that defects having a size of less than 0.3 μm cannot be eliminated. Remains.
Further, in recent years when miniaturization of elements is promoted with higher integration of semiconductor circuits, the defect having a size of less than 0.3 μm becomes a fatal defect in a subsequent device process.

本発明は、上記の課題を解決するためになされたものであって、ＳＯＩ構造を有するＳＯＩ基板を製造する際に用いられる表面に比較的小さなサイズの欠陥が無い半導体基板、及び、この半導体基板の製造方法を提供することを目的とする。   The present invention has been made to solve the above-described problem, and a semiconductor substrate having no relatively small size defect on a surface used when manufacturing an SOI substrate having an SOI structure, and the semiconductor substrate It aims at providing the manufacturing method of.

本発明の請求項１に係る半導体基板は、シリコン基板の表面に、シリコン酸化膜、シリコン単結晶層を順次備えてなるＳＯＩ構造を有するＳＯＩ基板を製造する際に用いられる半導体基板であって、表面近傍に窒素を含有しない領域を有することを特徴とする。   A semiconductor substrate according to claim 1 of the present invention is a semiconductor substrate used when manufacturing an SOI substrate having an SOI structure in which a silicon oxide film and a silicon single crystal layer are sequentially provided on the surface of a silicon substrate, It has the area | region which does not contain nitrogen in the surface vicinity.

請求項２に係る半導体基板は、請求項１記載の半導体基板において、前記領域は、不活性ガスおよび／または還元性ガス雰囲気中、１０００〜１２８０℃の範囲内の温度にて熱処理してなる厚みが１０μｍ以下の窒素を含有しないシリコン単結晶層であることを特徴とする。   The semiconductor substrate according to claim 2 is the semiconductor substrate according to claim 1, wherein the region is heat-treated at a temperature in a range of 1000 to 1280 ° C. in an inert gas and / or reducing gas atmosphere. Is a silicon single crystal layer not containing nitrogen of 10 μm or less.

請求項３に係る半導体基板は、請求項１記載の半導体基板において、前記領域は、エピタキシャル法により形成してなる厚みが１０μｍ以下の窒素を含有しないシリコン単結晶層であることを特徴とする。   A semiconductor substrate according to a third aspect is the semiconductor substrate according to the first aspect, wherein the region is a silicon single crystal layer not formed of nitrogen having a thickness of 10 μm or less formed by an epitaxial method.

請求項４に係る半導体基板は、請求項１ないし３のいずれか１項記載の半導体基板において、
前記領域を除く部分の窒素濃度は、１×１０１３〜５×１０１５ａｔｏｍｓ／ｃｍ３の範囲内であることを特徴とする。 The semiconductor substrate according to claim 4 is the semiconductor substrate according to any one of claims 1 to 3,
Nitrogen concentration of the portion excluding the region is characterized in that it is in the range of 1 × 10 13 ~5 × 10 15 atoms / cm 3.

請求項６に係る半導体基板の製造方法は、単結晶シリコン基板に酸素イオンの注入を行い、前記単結晶シリコン基板内に埋め込み酸化膜を形成する半導体基板の製造方法において、表面近傍に窒素を含有しない領域を有する半導体基板を用いることを特徴とする。   A method of manufacturing a semiconductor substrate according to claim 6 is a method of manufacturing a semiconductor substrate in which oxygen ions are implanted into a single crystal silicon substrate, and a buried oxide film is formed in the single crystal silicon substrate. A semiconductor substrate having a region that is not used is used.

本発明の請求項１に係る半導体基板によれば、表面近傍に窒素を含有しない領域を有するので、その表面に窒素と酸素との結合に起因するピンホール欠陥等の電気的に活性な欠陥が生じるのを防止することができる。したがって、この半導体基板を用いてＳＯＩ基板を作製すれば、このＳＯＩ基板上に形成されるデバイスの特性を良好に保持することができ、デバイスの信頼性を高めることができる。   According to the semiconductor substrate of the first aspect of the present invention, since there is a region not containing nitrogen in the vicinity of the surface, there are electrically active defects such as pinhole defects due to the bond between nitrogen and oxygen on the surface. It can be prevented from occurring. Therefore, if an SOI substrate is manufactured using this semiconductor substrate, the characteristics of the device formed on the SOI substrate can be maintained well, and the reliability of the device can be improved.

請求項２に係る半導体基板によれば、前記領域を、不活性ガスおよび／または還元性ガス雰囲気中、１０００〜１２８０℃の範囲内の温度にて熱処理してなる厚みが１０μｍ以下の窒素を含有しないシリコン単結晶層としたので、その表面に微小な大きさのサーマルピット等の欠陥が発生するのを防止することができ、このシリコン単結晶層の面内均一性を高めることができる。   According to the semiconductor substrate of claim 2, the region contains nitrogen having a thickness of 10 μm or less obtained by heat-treating the region at a temperature in the range of 1000 to 1280 ° C. in an inert gas and / or reducing gas atmosphere. Since the silicon single crystal layer is not formed, it is possible to prevent the occurrence of defects such as micro pits on the surface of the silicon single crystal layer and to improve the in-plane uniformity of the silicon single crystal layer.

請求項３に係る半導体基板によれば、前記領域を、エピタキシャル法により形成してなる厚みが１０μｍ以下の窒素を含有しないシリコン単結晶層としたので、その表面に微小な大きさのサーマルピット等の欠陥が発生するのを防止することができ、このシリコン単結晶層の面内均一性を高めることができる。   According to the semiconductor substrate of the third aspect, since the region is a silicon single crystal layer that is formed by an epitaxial method and does not contain nitrogen having a thickness of 10 μm or less, a small size thermal pit or the like is formed on the surface thereof. Can be prevented, and the in-plane uniformity of the silicon single crystal layer can be improved.

請求項４に係る半導体基板によれば、前記領域を除く部分の窒素濃度を、１×１０１３〜５×１０１５ａｔｏｍｓ／ｃｍ３の範囲内としたので、窒素を含有しない領域の表面におけるＢＭＤ密度の面内均一性を高めることができ、この表面における酸素析出物の成長を促進させることができる。 According to the semiconductor substrate of the fourth aspect, since the nitrogen concentration in the portion excluding the region is in the range of 1 × 10 13 to 5 × 10 15 atoms / cm 3 , the BMD on the surface of the region not containing nitrogen The in-plane uniformity of density can be increased, and the growth of oxygen precipitates on this surface can be promoted.

請求項６に係る半導体基板の製造方法によれば、表面近傍に窒素を含有しない領域を有する半導体基板を用いるので、表面に窒素と酸素との結合に起因するピンホール欠陥等の電気的に活性な欠陥が生じる虞のない半導体基板を作製することができる。   According to the method for manufacturing a semiconductor substrate according to claim 6, since the semiconductor substrate having a region not containing nitrogen is used in the vicinity of the surface, the surface is electrically active such as pinhole defects caused by the bond between nitrogen and oxygen. It is possible to manufacture a semiconductor substrate that does not cause any defects.

本発明の半導体基板及びその製造方法を実施するための最良の形態について説明する。
なお、この形態は、発明の趣旨をより良く理解させるために具体的に説明するものであり、特に指定のない限り、本発明を限定するものではない。 The best mode for carrying out the semiconductor substrate and the manufacturing method thereof of the present invention will be described.
This embodiment is specifically described for better understanding of the gist of the invention, and does not limit the present invention unless otherwise specified.

図１は、本発明の一実施形態の半導体基板を示す断面図であり、図において、１は半導体基板であり、この半導体基板１の表面１ａの近傍に、窒素を含有しない領域２が形成されている。   FIG. 1 is a cross-sectional view showing a semiconductor substrate according to an embodiment of the present invention. In the figure, reference numeral 1 denotes a semiconductor substrate, and a region 2 not containing nitrogen is formed in the vicinity of a surface 1a of the semiconductor substrate 1. ing.

この半導体基板１は、例えば、ＣＺ法にて作製されたシリコン単結晶をウェーハ状に加工してなるシリコン基板であり、ホウ素（Ｂ）等のｐ型のドーパント、またはリン（Ｐ）等のｎ型のドーパントが添加されている。
このシリコン単結晶は、多結晶シリコンと、窒化ケイ素等の窒化物をＣＺ成長炉のるつぼに投入し溶融して多結晶シリコン溶融液とし、この多結晶シリコン溶融液にシリコン種結晶を接触させて引き上げることにより、作製することができる。 The semiconductor substrate 1 is, for example, a silicon substrate obtained by processing a silicon single crystal manufactured by the CZ method into a wafer shape, and a p-type dopant such as boron (B) or n such as phosphorus (P). A type of dopant is added.
In this silicon single crystal, polycrystalline silicon and nitride such as silicon nitride are put into a crucible of a CZ growth furnace and melted to obtain a polycrystalline silicon melt, and a silicon seed crystal is brought into contact with the polycrystalline silicon melt. It can be fabricated by pulling up.

この窒素を含有しない領域２は、次の（１）または（２）のシリコン単結晶層により構成されている。
（１）半導体基板１の表面１ａの近傍を、不活性ガスおよび／または還元性ガス雰囲気中、１０００〜１２８０℃の範囲内の温度、好ましくは１２００〜１２５０℃の範囲内の温度にて熱処理することにより得られた、窒素を含有しないシリコン単結晶層。
（２）半導体基板１の表面１ａにエピタキシャル法により形成することにより得られた、窒素を含有しないシリコン単結晶層。 The region 2 not containing nitrogen is constituted by the following silicon single crystal layer (1) or (2).
(1) The vicinity of the surface 1a of the semiconductor substrate 1 is heat-treated in an inert gas and / or reducing gas atmosphere at a temperature in the range of 1000 to 1280 ° C, preferably in the range of 1200 to 1250 ° C. A silicon single crystal layer containing no nitrogen, obtained by
(2) A silicon single crystal layer not containing nitrogen, obtained by forming the surface 1a of the semiconductor substrate 1 by an epitaxial method.

これらのシリコン単結晶層の厚みは、１０μｍ以下が好ましく、より好ましくは０．５μｍ以上かつ８μｍ以下、さらに好ましくは１μｍ以上かつ２．５μｍ以下である。
ここで、シリコン単結晶層の厚みを１０μｍ以下としたのは、この半導体基板１を用いてＳＯＩ構造を有するＳＯＩ基板を製造した際に、得られたＳＯＩ基板の表面における０．３μｍ未満の比較的小さなサイズの欠陥を低減させることができるからである。 The thickness of these silicon single crystal layers is preferably 10 μm or less, more preferably 0.5 μm or more and 8 μm or less, and further preferably 1 μm or more and 2.5 μm or less.
Here, the thickness of the silicon single crystal layer is set to 10 μm or less because when the SOI substrate having the SOI structure is manufactured using the semiconductor substrate 1, the comparison is less than 0.3 μm on the surface of the obtained SOI substrate. This is because defects of a small size can be reduced.

この半導体基板１のうち窒素を含有しない領域２を除く部分、すなわち窒素を含有する領域３の窒素濃度は１×１０１３〜５×１０１５ａｔｏｍｓ／ｃｍ３の範囲内、好ましくは５×１０１４〜１×１０１５ａｔｏｍｓ／ｃｍ３の範囲内である。
ここで、窒素濃度を１×１０１３〜５×１０１５ａｔｏｍｓ／ｃｍ３の範囲内で含有するのが望ましい理由は、窒素濃度が１×１０１３〜５×１０１５ａｔｏｍｓ／ｃｍ３の範囲内であると、ＢＭＤ密度が半導体基板１の表面１ａの全面に亘って均一となり、酸素析出物の成長を促進させるからである。また、窒素濃度が５×１０１５ａｔｏｍｓ／ｃｍ３を超えた場合、その溶解度からシリコン単結晶に含有させ得る限界に近い窒素濃度となり、シリコン単結晶の全長にわたって均一に濃度を維持するのが困難になる。
なお、窒素濃度は、初期のシリコン溶融液量およびシリコン溶融液に初期添加した窒素量およびインゴットに対するウェーハの採取位置を基に、窒素の偏析係数から計算した値である。 The nitrogen concentration of the semiconductor substrate 1 excluding the region 2 containing no nitrogen, that is, the region 3 containing nitrogen is in the range of 1 × 10 13 to 5 × 10 15 atoms / cm 3 , preferably 5 × 10 14. Within the range of ˜1 × 10 15 atoms / cm 3 .
Here, the reason why it is desirable to contain the nitrogen concentration within the range of 1 × 10 13 to 5 × 10 15 atoms / cm 3 is that the nitrogen concentration is within the range of 1 × 10 13 to 5 × 10 15 atoms / cm 3 . This is because the BMD density is uniform over the entire surface 1a of the semiconductor substrate 1 and promotes the growth of oxygen precipitates. Further, when the nitrogen concentration exceeds 5 × 10 15 atoms / cm 3 , the nitrogen concentration is close to the limit that can be contained in the silicon single crystal because of its solubility, and it is difficult to maintain the concentration uniformly over the entire length of the silicon single crystal. become.
The nitrogen concentration is a value calculated from the segregation coefficient of nitrogen based on the initial amount of silicon melt, the amount of nitrogen initially added to the silicon melt, and the wafer sampling position relative to the ingot.

次に、本実施形態の半導体基板１及びＳＯＩ基板の製造方法について、図２に基づき説明する。
まず、図２（ａ）に示すように、窒素濃度が１×１０１３〜５×１０１５ａｔｏｍｓ／ｃｍ３の範囲内のシリコン単結晶からなる半導体基板１１を用意する。
この半導体基板１１は、全体に均一に窒素が導入されていることが好ましい。 Next, a method for manufacturing the semiconductor substrate 1 and the SOI substrate of the present embodiment will be described with reference to FIG.
First, as shown in FIG. 2A, a semiconductor substrate 11 made of a silicon single crystal having a nitrogen concentration in the range of 1 × 10 13 to 5 × 10 15 atoms / cm 3 is prepared.
The semiconductor substrate 11 is preferably introduced with nitrogen uniformly throughout.

次いで、図２（ｂ）に示すように、この半導体基板１１を、不活性ガスおよび／または還元性ガス雰囲気中、１０００〜１２８０℃の範囲内の温度、好ましくは１２００〜１２５０℃の範囲内の温度にて、５分〜４時間、好ましくは６０分〜２時間、熱処理し、この半導体基板１１の表面１１ａ近傍を、厚みが１０μｍ以下の窒素を含有しないシリコン単結晶層１２とする。
ここで、不活性ガス雰囲気としては、Ａｒガス雰囲気が好適である。 Next, as shown in FIG. 2B, the semiconductor substrate 11 is placed in an inert gas and / or reducing gas atmosphere at a temperature in the range of 1000 to 1280 ° C., preferably in the range of 1200 to 1250 ° C. Heat treatment is performed at a temperature for 5 minutes to 4 hours, preferably 60 minutes to 2 hours, so that the vicinity of the surface 11a of the semiconductor substrate 11 is a silicon single crystal layer 12 having a thickness of 10 μm or less and containing no nitrogen.
Here, an Ar gas atmosphere is suitable as the inert gas atmosphere.

このシリコン単結晶層１２は、半導体基板１１の表面１１ａ上にエピタキシャル法によりシリコン単結晶層を堆積させることによっても作製することができる。
この半導体基板１１のうちシリコン単結晶層１２を除く部分、すなわち窒素を含有するシリコン単結晶１３の窒素濃度は、１×１０１３〜５×１０１５ａｔｏｍｓ／ｃｍ３の範囲内、好ましくは５×１０１４〜１×１０１５ａｔｏｍｓ／ｃｍ３の範囲内となっている。 The silicon single crystal layer 12 can also be produced by depositing a silicon single crystal layer on the surface 11a of the semiconductor substrate 11 by an epitaxial method.
The nitrogen concentration of the semiconductor substrate 11 excluding the silicon single crystal layer 12, that is, the silicon single crystal 13 containing nitrogen is in the range of 1 × 10 13 to 5 × 10 15 atoms / cm 3 , preferably 5 ×. It is in the range of 10 14 to 1 × 10 15 atoms / cm 3 .

ところで、従来例である特許文献１の発明では、シリコンウェーハに埋め込み酸化膜を形成するために高温アニールを施すと、この高温アニールにより空孔などの点欠陥が表面より発生して熱平衡濃度まで増加し、シリコンウェーハの結晶育成時や酸素イオン注入時にシリコンウェーハの表面及び表面近傍に発生していた欠陥を中心として凝集し、サーマルピットを形成する。
そこで、シリコン結晶中に窒素を添加すると、結晶に発生する点欠陥濃度や点欠陥の拡散によりサーマルピットの形成を抑制することができる。一方、窒素は酸素と結合し電気的に活性な欠陥を作る場合があるので、デバイスが形成される埋め込み酸化膜上のシリコン結晶層には窒素が存在しないことが望ましい。 By the way, in the invention of Patent Document 1 as a conventional example, when high-temperature annealing is performed to form a buried oxide film on a silicon wafer, point defects such as vacancies are generated from the surface by this high-temperature annealing and increase to the thermal equilibrium concentration. Then, when crystal growth of the silicon wafer or oxygen ion implantation is performed, the surface of the silicon wafer and the defects near the surface are aggregated to form thermal pits.
Therefore, when nitrogen is added to the silicon crystal, the formation of thermal pits can be suppressed by the concentration of point defects generated in the crystal and the diffusion of point defects. On the other hand, since nitrogen may combine with oxygen to create an electrically active defect, it is desirable that nitrogen does not exist in the silicon crystal layer on the buried oxide film where the device is formed.

そこで、本実施形態では、窒素濃度が１×１０１３〜５×１０１５ａｔｏｍｓ／ｃｍ３の範囲内のシリコン単結晶からなる半導体基板１１を用い、この半導体基板１１の表面１ａ近傍を、不活性ガスおよび／または還元性ガス雰囲気中、１０００〜１２８０℃の範囲内の温度にて、５分以上かつ４時間以下の時間、熱処理するか、あるいは、半導体基板１１の表面１１ａ上にエピタキシャル法によりシリコン単結晶層を堆積させることにより、厚みが１０μｍ以下の窒素を含有しないシリコン単結晶層１２を形成させる。
ここで、上記各々の手法による窒素が存在しない表面近傍のシリコン単結晶層１２は、デバイスが作成される埋め込み酸化膜を含む領域である。 Therefore, in this embodiment, the semiconductor substrate 11 made of a silicon single crystal having a nitrogen concentration in the range of 1 × 10 13 to 5 × 10 15 atoms / cm 3 is used, and the vicinity of the surface 1a of the semiconductor substrate 11 is inactive. Heat treatment is performed in a gas and / or reducing gas atmosphere at a temperature in the range of 1000 to 1280 ° C. for a period of 5 minutes to 4 hours, or silicon is formed on the surface 11a of the semiconductor substrate 11 by an epitaxial method. By depositing the single crystal layer, the silicon single crystal layer 12 having a thickness of 10 μm or less and containing no nitrogen is formed.
Here, the silicon single crystal layer 12 in the vicinity of the surface where nitrogen does not exist by each of the above methods is a region including a buried oxide film in which a device is formed.

以上により、表面１ａ近傍あるいは表面１ａ上に、厚みが１０μｍ以下のシリコン単結晶層からなる窒素を含有しない領域２が形成され、この窒素を含有しない領域２を除く部分、すなわち窒素を含有する領域３の窒素濃度が１×１０１３〜５×１０１５ａｔｏｍｓ／ｃｍ３の範囲内である半導体基板１を作製することができる。
この半導体基板１の表面は、０．３μｍ未満の微小な大きさのサーマルピット等の欠陥が極めて少なく、面内均一性が高いものとなっている。 As described above, the nitrogen-free region 2 made of a silicon single crystal layer having a thickness of 10 μm or less is formed in the vicinity of the surface 1a or on the surface 1a, and a portion excluding the nitrogen-free region 2, that is, a region containing nitrogen Thus, the semiconductor substrate 1 having a nitrogen concentration of 3 in the range of 1 × 10 13 to 5 × 10 15 atoms / cm 3 can be manufactured.
The surface of the semiconductor substrate 1 has very few defects such as thermal pits having a minute size of less than 0.3 μm and high in-plane uniformity.

また、半導体基板１１の表面１ａ近傍を、不活性ガスおよび／または還元性ガス雰囲気中、１０００〜１２８０℃の範囲内の温度にて、５分以上かつ４時間以下の時間、熱処理することにより、非酸化性ガス雰囲気下での熱処理による結晶欠陥、特にＧｒｏｗｎ−ｉｎ欠陥と称される空洞欠陥の内壁酸化膜を溶解させ、その後、内壁酸化膜が除去された空洞欠陥内に格子間シリコン原子の拡散による穴埋め効果により表面近傍のＧｒｏｗｎ−ｉｎ欠陥を縮小させて消滅させ、同時に１０μｍ以下の窒素を含有しないシリコン単結晶層１２を形成することができる。   Also, by subjecting the vicinity of the surface 1a of the semiconductor substrate 11 to a heat treatment in an inert gas and / or reducing gas atmosphere at a temperature in the range of 1000 to 1280 ° C. for a period of 5 minutes to 4 hours, Crystal defects caused by heat treatment in a non-oxidizing gas atmosphere, in particular, inner wall oxide films of cavity defects called “Grown-in defects” are dissolved. The grown-in defects near the surface can be reduced and eliminated by the hole filling effect by diffusion, and at the same time, the silicon single crystal layer 12 containing no more than 10 μm of nitrogen can be formed.

次いで、この半導体基板１を用いて、ＳＩＭＯＸ法によりＳＯＩ基板を作製する。
図２（ｃ）に示すように、この半導体基板１に、その表面１ａから酸素イオンを注入し、このシリコン基板１の表面１ａから所定の深さ、例えば１００ｎｍ〜１０００ｎｍ、好ましくは２００ｎｍ〜８００ｎｍの深さに高濃度酸素イオン注入層１４を形成する。 Next, using this semiconductor substrate 1, an SOI substrate is manufactured by the SIMOX method.
As shown in FIG. 2C, oxygen ions are implanted into the semiconductor substrate 1 from the surface 1a, and the semiconductor substrate 1 has a predetermined depth from the surface 1a of the silicon substrate 1, for example, 100 nm to 1000 nm, preferably 200 nm to 800 nm. A high concentration oxygen ion implanted layer 14 is formed to a depth.

次いで、アルゴン及び酸素の混合ガス雰囲気中、１３００〜１３８０℃の範囲内の温度にて、２４０〜１５００分間、熱処理する。この混合ガスとしては、例えば、０．５ｖ／ｖ％Ｏ２−９９．５ｖ／ｖ％Ａｒ、７０ｖ／ｖ％Ｏ２−３０ｖ／ｖ％Ａｒ等の混合ガスが好適である。
図３に、この熱処理のプロファイルの一例を示してある。
この熱処理のプロファイルでは、０．５ｖ／ｖ％Ｏ２−９９．５ｖ／ｖ％Ａｒの混合ガス雰囲気中にて、１３５０℃にて４時間熱処理し、次いで、ガス置換して７０ｖ／ｖ％Ｏ２−３０ｖ／ｖ％Ａｒの混合ガス雰囲気とし、この雰囲気中にて、１３５０℃にて４時間熱処理する。 Next, heat treatment is performed in a mixed gas atmosphere of argon and oxygen at a temperature in the range of 1300 to 1380 ° C. for 240 to 1500 minutes. As this mixed gas, for example, a mixed gas of 0.5 v / v% O 2 -99.5 v / v% Ar, 70 v / v% O 2 -30 v / v% Ar, or the like is suitable.
FIG. 3 shows an example of the heat treatment profile.
In this heat treatment profile, heat treatment was performed at 1350 ° C. for 4 hours in a mixed gas atmosphere of 0.5 v / v% O 2 to 99.5 v / v% Ar, and then gas replacement was performed to obtain 70 v / v% O. a mixed gas atmosphere of 2 -30v / v% Ar, C. in the atmosphere for the heat treatment for 4 hours at 1350 ° C..

これにより、高濃度酸素イオン注入層１４を含むシリコン基板１の表面が酸化され、図２（ｄ）に示すように、この高濃度酸素イオン注入層１４が埋め込み酸化膜１５となると共に、シリコン基板１の表面１ａ近傍である窒素を含有しない領域２内の上部にシリコン酸化膜１６が形成される。   As a result, the surface of the silicon substrate 1 including the high-concentration oxygen ion implantation layer 14 is oxidized, and as shown in FIG. 2D, the high-concentration oxygen ion implantation layer 14 becomes a buried oxide film 15 and the silicon substrate. A silicon oxide film 16 is formed on the upper portion in the region 2 not containing nitrogen, which is in the vicinity of the surface 1a of 1.

次いで、このシリコン酸化膜１６に、フッ化水素水溶液等のエッチング液を用いてエッチング処理を施し、このシリコン酸化膜１６を除去する。
次いで、シリコン酸化膜１６が除去された窒素を含有しない領域２をＳＣ−１洗浄して不純物等を取り除く。
以上により、図４に示すように、半導体基板１の表面１ａ近傍に、埋め込み酸化膜１５、窒素を含有しない領域２を用いてなるシリコン単結晶層１７を順次備えたＳＯＩ構造を有するＳＯＩ基板２１を製造することができる。
このＳＯＩ基板２１は、０．３μｍ未満のサイズの欠陥をも低減させることができる。
以上により、高温アニール時のピット発生が少なく、ＳＯＩ構造に欠陥の少ないＳＯＩ基板２１を作製することができる。 Next, the silicon oxide film 16 is etched using an etching solution such as an aqueous hydrogen fluoride solution, and the silicon oxide film 16 is removed.
Next, the nitrogen-free region 2 from which the silicon oxide film 16 has been removed is subjected to SC-1 cleaning to remove impurities and the like.
As described above, as shown in FIG. 4, an SOI substrate 21 having an SOI structure in which the buried oxide film 15 and the silicon single crystal layer 17 using the region 2 not containing nitrogen are sequentially provided in the vicinity of the surface 1a of the semiconductor substrate 1. Can be manufactured.
This SOI substrate 21 can also reduce defects having a size of less than 0.3 μm.
As described above, it is possible to manufacture the SOI substrate 21 in which the generation of pits during high-temperature annealing is small and the SOI structure has few defects.

以下、実施例により本発明を説明する。
（実施例１）
多結晶シリコンをＣＺ成長炉のるつぼに投入して加熱昇温し、この多結晶シリコンの融解中に窒素ガスを導入することにより、窒素を１×１０１４ａｔｏｍｓ／ｃｍ３含むシリコン単結晶を得た。このシリコン単結晶をウェーハ状に加工し、得られたシリコンウェーハ上に、エピタキシャル法によりシリコン単結晶層を堆積量が表面近傍２μｍとなるように堆積し、実施例１の３００ｍｍφのシリコン基板を作製した。 Hereinafter, the present invention will be described by way of examples.
Example 1
By introducing polycrystalline silicon into the crucible of the CZ growth furnace, heating and raising the temperature, and introducing nitrogen gas during melting of the polycrystalline silicon, a silicon single crystal containing 1 × 10 14 atoms / cm 3 of nitrogen is obtained. It was. This silicon single crystal is processed into a wafer shape, and a silicon single crystal layer is deposited on the obtained silicon wafer by an epitaxial method so that the deposition amount is 2 μm near the surface, thereby producing the 300 mmφ silicon substrate of Example 1. did.

次いで、ＳＩＭＯＸ法によりＳＯＩ基板を作製した。
まず、上記のシリコン基板に、注入エネルギー：１８０ＫｅＶ、ドーズ量：４．０×１０１７ｃｍ−２になるように酸素イオンを注入し、所定の深さに高濃度酸素イオン注入層を形成した。
次いで、このシリコン基板を、６００℃の０．５ｖ／ｖ％Ｏ２−９９．５ｖ／ｖ％Ａｒの混合ガス雰囲気中に投入し、次いで、１３５０℃まで昇温させて、１３５０℃にて４時間熱処理し、次いで、７０ｖ／ｖ％Ｏ２−３０ｖ／ｖ％Ａｒの混合ガス雰囲気中、１３５０℃にて４時間熱処理し、６００℃まで降温させた。 Next, an SOI substrate was produced by the SIMOX method.
First, oxygen ions were implanted into the silicon substrate so as to have an implantation energy of 180 KeV and a dose of 4.0 × 10 17 cm −2 , thereby forming a high concentration oxygen ion implanted layer at a predetermined depth.
Next, this silicon substrate was put into a mixed gas atmosphere of 0.5 v / v% O 2 to 99.5 v / v% Ar at 600 ° C., then heated to 1350 ° C., and 4 at 1350 ° C. Next, heat treatment was performed at 1350 ° C. for 4 hours in a mixed gas atmosphere of 70 v / v% O 2 -30 v / v% Ar, and the temperature was lowered to 600 ° C.

次いで、ＨＦ水溶液にて表面酸化膜を除去し、その後、ＳＣ−１洗浄を行い、実施例１のＳＯＩ基板を作製した。
このＳＯＩ基板の表面のシリコン単結晶層の厚みは約１６０ｎｍ、埋め込み酸化膜の厚みは１１０ｎｍであった。
このＳＯＩ基板の表面に発生したサーマルピットの数をパーティクルカウンターにより測定したところ、３００ｍｍφのシリコン基板全体で０．３μｍ以上のピットは０個であり、かつ０．０９μｍ以上のピットも３０個以下であった。
また光学顕微鏡によるシリコン基板の表面観察においても、サーマルピットの発生は観察されなかった。
このように、窒素導入によりサーマルピットの発生を完全に抑制し、かつ、表面の窒素濃度をデバイス作製に影響のない程度まで低減することができた。 Next, the surface oxide film was removed with an HF aqueous solution, and then SC-1 cleaning was performed, so that the SOI substrate of Example 1 was manufactured.
The thickness of the silicon single crystal layer on the surface of this SOI substrate was about 160 nm, and the thickness of the buried oxide film was 110 nm.
When the number of thermal pits generated on the surface of this SOI substrate was measured with a particle counter, the number of pits of 0.3 μm or more was 0 in the entire 300 mmφ silicon substrate, and the number of pits of 0.09 μm or more was 30 or less. there were.
In addition, the occurrence of thermal pits was not observed in the surface observation of the silicon substrate with an optical microscope.
In this way, the introduction of nitrogen completely suppressed the generation of thermal pits, and the surface nitrogen concentration could be reduced to a level that does not affect device fabrication.

（実施例２）
多結晶シリコンをＣＺ成長炉のるつぼに投入して加熱昇温し、この多結晶シリコンの融解中に窒素ガスを導入することにより、窒素を１×１０１４ａｔｏｍｓ／ｃｍ３含むシリコン単結晶を得た。このシリコン単結晶をウェーハ状に加工し、得られたシリコンウェーハ上に、１００ｖ／ｖ％Ａｒ雰囲気下にて、１２００℃で１時間の熱処理を行い、表面近傍１０μｍの深さにＧｒｏｗｎ−ｉｎ欠陥を縮小し消滅させた実施例２の３００ｍｍφのシリコン基板を作製した。 (Example 2)
By introducing polycrystalline silicon into the crucible of the CZ growth furnace, heating and raising the temperature, and introducing nitrogen gas during melting of the polycrystalline silicon, a silicon single crystal containing 1 × 10 14 atoms / cm 3 of nitrogen is obtained. It was. This silicon single crystal is processed into a wafer shape, and the resulting silicon wafer is heat-treated at 1200 ° C. for 1 hour in a 100 v / v% Ar atmosphere to grow-in defects to a depth of 10 μm near the surface. A 300 mmφ silicon substrate of Example 2 was produced in which is reduced and eliminated.

次いで、このシリコン基板を用いて、ＳＩＭＯＸ法により実施例１と同様にして実施例２のＳＯＩ基板を作製した。
このＳＯＩ基板の表面のシリコン単結晶層の厚みは約１６０ｎｍ、埋め込み酸化膜の厚みは１１０ｎｍであった。
このＳＯＩ基板の表面に発生したサーマルピットの数をパーティクルカウンターにより測定したところ、３００ｍｍφのシリコン基板全体で０．３μｍ以上のピットは０個であり、かつ０．０９μｍ以上のピットも３０個以下であった。
また光学顕微鏡によるシリコン基板の表面観察においても、サーマルピットの発生は観察されなかった。
このように、窒素導入によりサーマルピットの発生を完全に抑制し、かつ、表面の窒素濃度をデバイス作製に影響のない程度まで低減することができた。 Next, using this silicon substrate, an SOI substrate of Example 2 was produced in the same manner as in Example 1 by the SIMOX method.
The thickness of the silicon single crystal layer on the surface of this SOI substrate was about 160 nm, and the thickness of the buried oxide film was 110 nm.
When the number of thermal pits generated on the surface of this SOI substrate was measured with a particle counter, the number of pits of 0.3 μm or more was 0 in the entire 300 mmφ silicon substrate, and the number of pits of 0.09 μm or more was 30 or less. there were.
In addition, the occurrence of thermal pits was not observed in the surface observation of the silicon substrate with an optical microscope.
In this way, the introduction of nitrogen completely suppressed the generation of thermal pits, and the surface nitrogen concentration could be reduced to a level that does not affect device fabrication.

本発明の一実施形態の半導体基板を示す断面図である。It is sectional drawing which shows the semiconductor substrate of one Embodiment of this invention. 本発明の一実施形態の半導体基板及びＳＯＩ基板の製造方法を示す過程図である。It is process drawing which shows the manufacturing method of the semiconductor substrate and SOI substrate of one Embodiment of this invention. アルゴン及び酸素の混合ガス雰囲気中における熱処理のプロファイルの一例を示す図である。It is a figure which shows an example of the profile of the heat processing in the mixed gas atmosphere of argon and oxygen. 本発明の一実施形態の半導体基板を用いて作製されたＳＯＩ基板を示す断面図である。It is sectional drawing which shows the SOI substrate produced using the semiconductor substrate of one Embodiment of this invention.

符号の説明Explanation of symbols

１ 半導体基板
１ａ 表面
２ 窒素を含有しない領域
３ 窒素を含有する領域
１１ 半導体基板
１１ａ 表面
１２ 窒素を含有しないシリコン単結晶層
１３ 窒素を含有するシリコン単結晶
１４ 高濃度酸素イオン注入層
１５ 埋め込み酸化膜
１６ シリコン酸化膜
１７ シリコン単結晶層 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Surface 2 Nitrogen-free region 3 Nitrogen-containing region 11 Semiconductor substrate 11a Surface 12 Nitrogen-free silicon single crystal layer 13 Nitrogen-containing silicon single crystal 14 High-concentration oxygen ion implanted layer 15 Embedded oxide film 16 Silicon oxide film 17 Silicon single crystal layer

Claims (5)

シリコン基板の表面に、シリコン酸化膜、シリコン単結晶層を順次備えてなるＳＯＩ構造を有するＳＯＩ基板を製造する際に用いられる半導体基板であって、
表面近傍に窒素を含有しない領域を有することを特徴とする半導体基板。 A semiconductor substrate used when manufacturing an SOI substrate having an SOI structure in which a silicon oxide film and a silicon single crystal layer are sequentially provided on the surface of a silicon substrate,
A semiconductor substrate having a region not containing nitrogen in the vicinity of the surface. 前記領域は、不活性ガスおよび／または還元性ガス雰囲気中、１０００〜１２８０℃の範囲内の温度にて熱処理してなる厚みが１０μｍ以下の窒素を含有しないシリコン単結晶層であることを特徴とする請求項１記載の半導体基板。   The region is a silicon single crystal layer not containing nitrogen having a thickness of 10 μm or less, which is heat-treated at a temperature in the range of 1000 to 1280 ° C. in an inert gas and / or reducing gas atmosphere. The semiconductor substrate according to claim 1. 前記領域は、エピタキシャル法により形成してなる厚みが１０μｍ以下の窒素を含有しないシリコン単結晶層であることを特徴とする請求項１記載の半導体基板。   2. The semiconductor substrate according to claim 1, wherein the region is a silicon single crystal layer that is formed by an epitaxial method and has a thickness of 10 [mu] m or less and does not contain nitrogen. 前記領域を除く部分の窒素濃度は、１×１０１３〜５×１０１５ａｔｏｍｓ／ｃｍ３の範囲内であることを特徴とする請求項１ないし３のいずれか１項記載の半導体基板。 4. The semiconductor substrate according to claim 1, wherein a nitrogen concentration in a portion excluding the region is in a range of 1 × 10 13 to 5 × 10 15 atoms / cm 3 . 単結晶シリコン基板に酸素イオンの注入を行い、前記単結晶シリコン基板内に埋め込み酸化膜を形成する半導体基板の製造方法において、
表面近傍に窒素を含有しない領域を有する半導体基板を用いることを特徴とする半導体基板の製造方法。 In a method for manufacturing a semiconductor substrate, oxygen ions are implanted into a single crystal silicon substrate, and a buried oxide film is formed in the single crystal silicon substrate.
A method of manufacturing a semiconductor substrate, comprising using a semiconductor substrate having a region not containing nitrogen in the vicinity of the surface.
JP2008225818A 2008-09-03 2008-09-03 Semiconductor substrate and its manufacturing method Pending JP2010062291A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008225818A JP2010062291A (en) 2008-09-03 2008-09-03 Semiconductor substrate and its manufacturing method
US12/548,762 US20100052093A1 (en) 2008-09-03 2009-08-27 Semiconductor substrate and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008225818A JP2010062291A (en) 2008-09-03 2008-09-03 Semiconductor substrate and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2010062291A true JP2010062291A (en) 2010-03-18

Family

ID=41724054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008225818A Pending JP2010062291A (en) 2008-09-03 2008-09-03 Semiconductor substrate and its manufacturing method

Country Status (2)

Country Link
US (1) US20100052093A1 (en)
JP (1) JP2010062291A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101393611B1 (en) * 2009-06-02 2014-05-12 가부시키가이샤 사무코 Method and apparatus for manufacturing semiconductor substrate dedicated to semiconductor device, and method and apparatus for manufacturing semoconductor device
JP2011086828A (en) * 2009-10-16 2011-04-28 Sumco Corp Semiconductor device, and method of manufacturing the same
GB201202128D0 (en) * 2012-02-08 2012-03-21 Univ Leeds Novel material
US11545558B2 (en) * 2020-09-28 2023-01-03 Paragraf Limited Method of manufacturing a transistor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5219334B2 (en) * 2005-11-30 2013-06-26 株式会社Ｓｕｍｃｏ Semiconductor substrate manufacturing method and quality evaluation method
US7517706B2 (en) * 2006-07-21 2009-04-14 Sumco Corporation Method for evaluating quality of semiconductor substrate and method for manufacturing semiconductor substrate

Also Published As

Publication number Publication date
US20100052093A1 (en) 2010-03-04

Similar Documents

Publication Publication Date Title
US6492682B1 (en) Method of producing a bonded wafer and the bonded wafer
KR100573473B1 (en) Silicon wafer and method of fabricating the same
US6897084B2 (en) Control of oxygen precipitate formation in high resistivity CZ silicon
US8642449B2 (en) Silicon wafer
KR100758088B1 (en) Heat treatment method for silicon wafer
JP2006216826A (en) Manufacturing method of soi wafer
US20080044669A1 (en) Method for Manufacturing Simox Substrate and Simox Substrate Obtained by the Method
JPWO2004008521A1 (en) High resistance silicon wafer and manufacturing method thereof
KR20070100119A (en) Method for manufacturing simox wafer and simox wafer obtained by this method
JP5251137B2 (en) Single crystal silicon wafer and manufacturing method thereof
JP4419147B2 (en) Manufacturing method of bonded wafer
TWI628317B (en) Method for growing monocrystalline silicon by using czochralski method
JP2008263087A (en) Method of manufacturing soi substrate
JP2010062291A (en) Semiconductor substrate and its manufacturing method
EP1906450A1 (en) Process for producing simox substrate, and simox substrate produced by said process
TW201426877A (en) Production of high precipitate density wafers by activation of inactive oxygen precipitate nuclei
JP2009231429A (en) Method of manufacturing silicon wafer
JP5262021B2 (en) Silicon wafer and manufacturing method thereof
JP4706199B2 (en) SIMOX substrate manufacturing method
JP6303321B2 (en) Bonded wafer manufacturing method and bonded wafer
JP2011054655A (en) Silicon wafer for high-frequency device and manufacturing method thereof
JP2008270592A (en) Manufacturing method of soi substrate
JPH11288942A (en) Manufacture of semiconductor device
JP2010027731A (en) Method of manufacturing simox wafer, and simox wafer
US20230243062A1 (en) Silicon wafer and method for producing silicon wafer