JP2010056121A - Multilayer semiconductor device - Google Patents

Multilayer semiconductor device Download PDF

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JP2010056121A
JP2010056121A JP2008216463A JP2008216463A JP2010056121A JP 2010056121 A JP2010056121 A JP 2010056121A JP 2008216463 A JP2008216463 A JP 2008216463A JP 2008216463 A JP2008216463 A JP 2008216463A JP 2010056121 A JP2010056121 A JP 2010056121A
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Japan
Prior art keywords
semiconductor device
inter
stacked
row
wiring
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Japanese (ja)
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Masaru Sasaki
大 佐々木
Mitsuaki Katagiri
光昭 片桐
Hisafumi Tanie
尚史 谷江
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Hitachi Ltd
Micron Memory Japan Ltd
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Hitachi Ltd
Elpida Memory Inc
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Priority to JP2008216463A priority Critical patent/JP2010056121A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To lower stress generated in an inter-substrate connection terminal which connects adjacent wiring boards. <P>SOLUTION: The multilayer semiconductor device has a plurality of semiconductor devices 11 and 12 laminated with each other, and the respective semiconductor devices 11 and 12 include the wiring boards 2a and 2b and semiconductor chips 1a and 1b loaded on the wiring boards 2a and 2b. Also, the multilayer semiconductor device includes the inter-substrate connection terminal 7 for electrically connecting the wiring boards 2a and 2b of the adjacently laminated two semiconductor devices 11 and 12. The inter-substrate connection terminal 7 at least configures a first column 15 and a second column 16 disposed by a prescribed pitch along and in the vicinity of the ends of the wiring boards 2a and 2b. Then, the inter-substrate connection terminal 7 configuring the first column 15 and the inter-substrate connection terminal 7 configuring the second column 16 are shifted from each other and disposed in a direction along the first column 15. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、複数の半導体装置が積層されてなる積層型半導体装置に関する。   The present invention relates to a stacked semiconductor device in which a plurality of semiconductor devices are stacked.

近年、メモリの大容量化に対する需要がより高まっている。しかし、周辺回路の大規模化や複雑化、及び製造工程における微細化の困難性などの要因のため、半導体チップの面積を小さくすることは困難である。そのため、大容量化及び高集積化を図るため、複数の半導体チップが搭載された半導体装置の需要が高まっている。また、高密度化の要求もあることから、複数の半導体装置が積層されてなる積層型半導体装置の需要が高まっている。   In recent years, the demand for increasing the capacity of memories has increased. However, it is difficult to reduce the area of the semiconductor chip due to factors such as the increase in scale and complexity of the peripheral circuit and difficulty in miniaturization in the manufacturing process. Therefore, in order to increase the capacity and the integration, there is an increasing demand for a semiconductor device on which a plurality of semiconductor chips are mounted. In addition, since there is a demand for higher density, there is an increasing demand for stacked semiconductor devices in which a plurality of semiconductor devices are stacked.

積層型半導体装置の一形態として、ＦＢＧＡ（Fine Pitch Ball Grid Allay）構造の半導体装置（半導体パッケージ）が複数積層されてなるｓＦＢＧＡ（stacked FBGA）構造の積層型半導体装置が知られている（例えば、特許文献１参照。）。   As an example of a stacked semiconductor device, a stacked semiconductor device having an sFBGA (stacked FBGA) structure in which a plurality of semiconductor devices (semiconductor packages) having an FBGA (Fine Pitch Ball Grid Allay) structure are stacked is known (for example, (See Patent Document 1).

特許文献１には、ｓＦＢＧＡ構造の積層型半導体装置が開示されている。図９（ａ）は、特許文献１に記載の積層型半導体装置の模式的断面図であり、図９（ｂ）は、特許文献１に記載の積層型半導体装置が有する基板間接続端子の配置を示す模式図である。   Patent Document 1 discloses a stacked semiconductor device having an sFBGA structure. 9A is a schematic cross-sectional view of the stacked semiconductor device described in Patent Document 1, and FIG. 9B is an arrangement of inter-substrate connection terminals included in the stacked semiconductor device described in Patent Document 1. It is a schematic diagram which shows.

特許文献１に開示された積層型半導体装置１００は、第１の半導体装置１０１と、第１の半導体装置１０１の上方に配置される第２の半導体装置１０２と、を有している。第１の半導体装置１０１及び第２の半導体装置１０２は、それぞれ配線基板１０４ａ，１０４ｂと配線基板１０４ａ，１０４ｂに搭載された半導体チップ１０３ａ，１０３ｂとを有している。それぞれの半導体チップ１０３ａ，１０３ｂは、樹脂１０５によって封止されている。   A stacked semiconductor device 100 disclosed in Patent Document 1 includes a first semiconductor device 101 and a second semiconductor device 102 disposed above the first semiconductor device 101. The first semiconductor device 101 and the second semiconductor device 102 have wiring boards 104a and 104b and semiconductor chips 103a and 103b mounted on the wiring boards 104a and 104b, respectively. Each of the semiconductor chips 103 a and 103 b is sealed with a resin 105.

また、第１の半導体装置１０１の配線基板１０４ａと第２の半導体装置１０２の配線基板１０４ｂとは、基板間接続端子１０６によって電気的に接続されている。基板間接続端子１０６は、第１の半導体装置１０１に搭載された半導体チップ１０３ａを避けるように、半導体チップ１０３ａよりも外側に配置されている。   Further, the wiring substrate 104 a of the first semiconductor device 101 and the wiring substrate 104 b of the second semiconductor device 102 are electrically connected by an inter-substrate connection terminal 106. The inter-substrate connection terminal 106 is arranged outside the semiconductor chip 103 a so as to avoid the semiconductor chip 103 a mounted on the first semiconductor device 101.

更に、第１および第２の半導体装置１０１、１０２間の隙間には、補強用の樹脂１０５が充填されている。第１および第２の半導体装置１０１、１０２同士は、この樹脂１０５によっても互いに固定されている。   Further, a reinforcing resin 105 is filled in a gap between the first and second semiconductor devices 101 and 102. The first and second semiconductor devices 101 and 102 are also fixed to each other by this resin 105.

信号伝達速度の高速化と回路動作の安定化の要求によって、半導体チップに形成された電極パッドに接続される信号線及び電源／グランド（ＧＮＤ）線の数は増加している。そのため、基板間接続端子１０６ｂの数を増やすことが必要となる。   The number of signal lines and power / ground (GND) lines connected to electrode pads formed on a semiconductor chip is increasing due to demands for higher signal transmission speed and stabilization of circuit operation. Therefore, it is necessary to increase the number of inter-substrate connection terminals 106b.

特許文献１の図面には、略正方形状の配線基板の４辺に沿って配置された外側の基板間接続端子１０６ａと、当該外側の基板間接続端子１０６ａの内側に配置された内側の基板間接続端子１０６ｂが記載されている（図９（ｂ）参照。）。隣り合う２つの外側の基板間接続端子１０６ａと、隣り合う２つの内側の基板間接続端子１０６ｂとは、略正方形状に配置されている。
特開２００７−２８１１２９号公報 In the drawing of Patent Document 1, an outer inter-board connection terminal 106a arranged along four sides of a substantially square wiring board and an inner inter-board board arranged inside the outer inter-board connection terminal 106a are shown. A connection terminal 106b is described (see FIG. 9B). Two adjacent outer inter-substrate connection terminals 106a and two adjacent inner inter-substrate connection terminals 106b are arranged in a substantially square shape.
JP 2007-281129 A

特許文献１に記載の積層型半導体装置では、内側の基板間接続端子１０６ｂと半導体チップが搭載される領域（半導体チップ１０３ｂと樹脂１０５とが設けられている領域であり、以下「チップ搭載領域」と呼ぶことがある。）との間隔１０７が短くなる。   In the stacked semiconductor device described in Patent Document 1, an inner inter-substrate connection terminal 106b and a semiconductor chip mounting region (a region in which the semiconductor chip 103b and the resin 105 are provided are hereinafter referred to as “chip mounting region”. The distance 107 to the distance is shortened.

半導体チップ１０３ｂや樹脂１０５の線膨張係数は、配線基板１０４ｂの線膨張係数と異なる。そのため、使用時の温度変化によって、配線基板１０４ｂに応力が発生する。特に、配線基板１０４ｂのチップ搭載領域には大きな応力が生じる。   The linear expansion coefficient of the semiconductor chip 103b and the resin 105 is different from the linear expansion coefficient of the wiring board 104b. Therefore, stress is generated in the wiring board 104b due to a temperature change during use. In particular, a large stress is generated in the chip mounting region of the wiring substrate 104b.

したがって、チップ搭載領域の近くに配置された内側の基板間接続端子１０６ｂに大きな負荷が生じ、内側の基板間接続端子１０６ｂは断線し易くなる。つまり、基板間接続端子の接続の信頼性が低下するという課題がある。   Therefore, a large load is generated on the inner inter-substrate connection terminal 106b disposed near the chip mounting area, and the inner inter-substrate connection terminal 106b is easily disconnected. That is, there is a problem that the reliability of connection of the inter-substrate connection terminals is lowered.

また、特許文献１に記載の積層型半導体装置では、積層されて隣接している半導体装置１０１及び半導体装置１０２の隙間が補強用の樹脂１０５によって封止されている。そのため、第１及び第２の半導体装置１０１、１０２のうちの一方のみが不良品であった場合でも、両半導体装置１０１、１０２を共に廃棄する必要がある。結果として、廃棄すべき半導体装置の数が増え、製造コストが上昇するという課題がある。   In the stacked semiconductor device described in Patent Document 1, a gap between the stacked semiconductor devices 101 and 102 is sealed with a reinforcing resin 105. For this reason, even when only one of the first and second semiconductor devices 101 and 102 is defective, both the semiconductor devices 101 and 102 need to be discarded. As a result, there is a problem that the number of semiconductor devices to be discarded increases and the manufacturing cost increases.

本発明の目的は上記背景技術の課題の少なくとも一つを解決できる積層型半導体装置を提供することにある。その目的の一例は、隣接する配線基板間を接続する基板間接続端子に生じる応力が低下され、接続の信頼性が向上された積層型半導体装置を提供することである。   An object of the present invention is to provide a stacked semiconductor device that can solve at least one of the problems of the background art. An example of the object is to provide a stacked semiconductor device in which stress generated in an inter-substrate connection terminal that connects adjacent wiring substrates is reduced and connection reliability is improved.

上記課題の少なくとも１つを解決するため、本発明に係る積層型半導体装置は、配線基板と該配線基板に搭載された半導体チップとを有する互いに積層された複数の半導体装置と、隣り合って積層された２つの半導体装置の配線基板の間を電気的に接続する基板間接続端子と、を有している。基板間接続端子は、少なくとも、配線基板の端部近傍に該端部に沿って所定のピッチで配置された第１の列と第２の列とを構成している。そして、第１の列を構成する基板間接続端子と、第２の列を構成する基板間接続端子とが、第１の列に沿った方向に互いにずれて配置されていることを特徴とする。   In order to solve at least one of the above problems, a stacked semiconductor device according to the present invention includes a plurality of stacked semiconductor devices having a wiring board and a semiconductor chip mounted on the wiring board, and stacked adjacent to each other. And an inter-substrate connection terminal for electrically connecting the wiring substrates of the two semiconductor devices. The inter-substrate connection terminals constitute at least a first row and a second row arranged at a predetermined pitch along the end portion in the vicinity of the end portion of the wiring board. The inter-board connection terminals constituting the first row and the inter-board connection terminals constituting the second row are arranged so as to be shifted from each other in the direction along the first row. .

本発明によれば、隣接する配線基板間を接続する基板間接続端子に生じる応力を低下させ、接続の信頼性を向上させる。   According to the present invention, the stress generated in the inter-substrate connection terminal that connects the adjacent wiring substrates is reduced, and the connection reliability is improved.

以下、本発明の実施形態について図面を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

［第１の実施形態］
図１（ａ）は第１の実施形態に係る積層型半導体装置の模式的断面図である。本実施形態に係る積層型半導体装置は、第１の半導体装置１１と、第１の半導体装置１１に積層された第２の半導体装置１２を有している。 [First Embodiment]
FIG. 1A is a schematic cross-sectional view of the stacked semiconductor device according to the first embodiment. The stacked semiconductor device according to the present embodiment includes a first semiconductor device 11 and a second semiconductor device 12 stacked on the first semiconductor device 11.

第１の半導体装置１１は、配線基板２ａと半導体チップ１ａとを有している。半導体チップ１ａは、低弾性体であるエラストマ３ａを介して配線基板２ａに搭載されている。配線基板２ａとしては、例えばテープ基板を用いることができる。   The first semiconductor device 11 has a wiring substrate 2a and a semiconductor chip 1a. The semiconductor chip 1a is mounted on the wiring board 2a via an elastomer 3a which is a low elastic body. As the wiring substrate 2a, for example, a tape substrate can be used.

配線基板２ａには配線が形成されている。配線基板２ａの中央部には、半導体チップ１ａよりも小さい開口部が形成されている。配線基板２ａに形成された配線の一部は、開口部に向けて突出しており、内部導線４ａを形成している。エラストマ３ａには、配線基板２ａの開口部が形成された領域に対応して、開口部が形成されている。   Wiring is formed on the wiring board 2a. An opening smaller than the semiconductor chip 1a is formed at the center of the wiring board 2a. A part of the wiring formed on the wiring board 2a protrudes toward the opening and forms the internal conductor 4a. The elastomer 3a has an opening corresponding to a region where the opening of the wiring board 2a is formed.

半導体チップ１ａの一の面であって、当該一の面の中央部には電極パッド（不図示）が設けられている。半導体チップ１ａは、電極パッドが配線基板２ａの開口部に位置するように、一の面を配線基板２ａに向けて搭載されている。そして、内部導線４ａは当該電極パッドと接続されている。また、内部導線４ａと電極パッドとの接続部を覆うように、配線基板２ａの開口部は樹脂５ａによって封止されている。これにより、内部導線４ａの長期的な接続の信頼性が確保されている。樹脂５ａとしては、例えば、エポキシ系樹脂を用いることができる。   On one surface of the semiconductor chip 1a, an electrode pad (not shown) is provided at the center of the one surface. The semiconductor chip 1a is mounted with one surface facing the wiring board 2a so that the electrode pads are located in the openings of the wiring board 2a. The internal conductor 4a is connected to the electrode pad. Further, the opening of the wiring board 2a is sealed with a resin 5a so as to cover the connection portion between the internal conductor 4a and the electrode pad. Thereby, long-term connection reliability of the internal conductor 4a is ensured. For example, an epoxy resin can be used as the resin 5a.

第１の半導体装置１１の配線基板２ａには、外部端子６が設けられている。外部端子６は、第１の半導体チップ１ａが搭載された面とは反対側の面に設置されている。外部端子６としては、例えば半田ボールを用いることができる。   An external terminal 6 is provided on the wiring substrate 2 a of the first semiconductor device 11. The external terminal 6 is installed on the surface opposite to the surface on which the first semiconductor chip 1a is mounted. For example, a solder ball can be used as the external terminal 6.

第２の半導体装置１２は半導体チップ１ｂと配線基板２ｂとを有しており、第１の半導体装置１１とほぼ同様の構造となっている。半導体チップ１ｂは、エラストマ３ｂを介して配線基板２ｂに搭載されている。   The second semiconductor device 12 has a semiconductor chip 1b and a wiring substrate 2b, and has a structure substantially similar to that of the first semiconductor device 11. The semiconductor chip 1b is mounted on the wiring board 2b via the elastomer 3b.

第２の半導体装置１２の半導体チップ１ｂは、配線基板２ｂから突出した内部導線４ｂによって配線基板２ｂと接続されており、その接続部は樹脂５ｂによって封止されている。樹脂５ｂは、例えばエポキシ系樹脂から成る。   The semiconductor chip 1b of the second semiconductor device 12 is connected to the wiring board 2b by an internal conductor 4b protruding from the wiring board 2b, and the connecting portion is sealed with a resin 5b. The resin 5b is made of, for example, an epoxy resin.

積層型半導体装置は、第１の半導体装置１１の配線基板２ａと第２の半導体装置１２の配線基板２ｂとを電気的に接続する基板間接続端子７をさらに有している。基板間接続端子７によって、積層して隣接する配線基板２ａ，２ｂにそれぞれ設けられた配線同士が電気的に接続される。基板間接続端子７としては、半田ボールを用いることができる。   The stacked semiconductor device further includes an inter-substrate connection terminal 7 that electrically connects the wiring substrate 2 a of the first semiconductor device 11 and the wiring substrate 2 b of the second semiconductor device 12. By the inter-substrate connection terminal 7, the wirings provided on the adjacent wiring substrates 2 a and 2 b are electrically connected to each other. As the inter-substrate connection terminals 7, solder balls can be used.

図１（ｂ）は、基板間接続端子７の配置を示すための模式的平面図である。図１（ｂ）には、第１の半導体装置１１の配線基板２ａ及び半導体チップ１ａと、基板間接続端子７と、が示されている。   FIG. 1B is a schematic plan view for illustrating the arrangement of the inter-substrate connection terminals 7. FIG. 1B shows the wiring substrate 2 a and the semiconductor chip 1 a of the first semiconductor device 11 and the inter-substrate connection terminal 7.

本実施形態では、配線基板２ａ，２ｂの形状は略長方形であり、基板間接続端子７は配線基板２ｂの一端部と当該一端部と対向する他端部とに配置されている。基板間接続端子７は、配線基板２ａ，２ｂの端部近傍に当該端部に沿って所定のピッチ８で配置された第１の列１５と第２の列１６とを構成している。第２の列１６は第１の列１５と略平行であることが好ましい。   In the present embodiment, the shape of the wiring boards 2a and 2b is substantially rectangular, and the inter-substrate connection terminals 7 are arranged at one end of the wiring board 2b and the other end facing the one end. The inter-substrate connection terminals 7 constitute a first row 15 and a second row 16 arranged at a predetermined pitch 8 along the end portions in the vicinity of the end portions of the wiring boards 2a and 2b. The second row 16 is preferably substantially parallel to the first row 15.

基板間接続端子７同士の間隔は、製造工程において課せられる下限（以下、「ピッチの下限」と呼ぶ。）が存在する。したがって、第１の列１５と第２の列１６との間隔９には制限が課せられる。   There is a lower limit (hereinafter referred to as “pitch lower limit”) imposed on the interval between the inter-substrate connecting terminals 7 in the manufacturing process. Therefore, a limit is imposed on the distance 9 between the first column 15 and the second column 16.

第１の列１５を構成する基板間接続端子７と、第２の列１６を構成する基板間接続端子７とは、第１の列１５に沿った方向へ互いにずれて配置されている。また、第１の列１５を構成する一の基板間接続端子７の中心から、当該一の基板間接続端子７と最近接する第２の列１６の基板間接続端子７の中心までの中心間距離３３は、上記のピッチ８と同一の長さであることが好ましい。これにより、第１の列１５と第２の列１６との間隔９が上記のピッチ８よりも短くなるように、基板間接続端子７を配置することができる。   The inter-substrate connection terminals 7 constituting the first row 15 and the inter-substrate connection terminals 7 constituting the second row 16 are arranged so as to be shifted from each other in the direction along the first row 15. The center-to-center distance from the center of one inter-substrate connection terminal 7 constituting the first row 15 to the center of the inter-substrate connection terminal 7 in the second row 16 closest to the one inter-substrate connection terminal 7 33 is preferably the same length as the pitch 8 described above. Thereby, the inter-substrate connection terminals 7 can be arranged so that the distance 9 between the first row 15 and the second row 16 is shorter than the pitch 8 described above.

さらに、第１の列１５を構成する基板間接続端子７のうち隣接した２つの基板間接続端子７からの距離が等しくなる位置に、第２の列１６のうちの１つの基板間接続端子７が配置されていることが好ましい。これにより、第１の列１５と第２の列１６との間隔９を出来る限り短くすることができる（図１（ｂ）参照。）。   Furthermore, one inter-board connection terminal 7 in the second row 16 is located at a position where the distance from the adjacent two inter-board connection terminals 7 among the inter-board connection terminals 7 constituting the first row 15 becomes equal. Is preferably arranged. Thereby, the distance 9 between the first column 15 and the second column 16 can be made as short as possible (see FIG. 1B).

本実施形態の比較例として、特許文献１に記載された積層型半導体装置における基板間接続端子の配置について説明する（図９（ｂ）参照。）。図９（ｂ）に示された積層型半導体装置では、外側の基板間接続端子１０６ａと内側の基板間接続端子１０６ｂとの間隔１０９が、上述の「ピッチの下限」以上となる。そのため、配線基板のサイズが小さい場合、内側の基板間接続端子１０６ｂとチップ搭載領域との間隔１０７が短くなる。   As a comparative example of this embodiment, an arrangement of inter-substrate connection terminals in a stacked semiconductor device described in Patent Document 1 will be described (see FIG. 9B). In the stacked semiconductor device shown in FIG. 9B, the interval 109 between the outer inter-substrate connection terminal 106a and the inner inter-substrate connection terminal 106b is equal to or greater than the above-mentioned “lower limit of pitch”. Therefore, when the size of the wiring board is small, the distance 107 between the inner inter-substrate connection terminal 106b and the chip mounting area is shortened.

本実施形態では、上述したように、第１の列１５と第２の列１６との間隔９がピッチの下限よりも短くなる。つまり、図１（ｂ）に示す配置では、第１の列１５と第２の列１６との間隔９が、ピッチ８の（√３）／２倍（約０．８７倍）となる。従って、第１の列１５と第２の列１６との間隔９が、ピッチの下限よりも短くなる。   In the present embodiment, as described above, the interval 9 between the first row 15 and the second row 16 is shorter than the lower limit of the pitch. That is, in the arrangement shown in FIG. 1B, the interval 9 between the first row 15 and the second row 16 is (√3) / 2 times (about 0.87 times) the pitch 8. Therefore, the interval 9 between the first column 15 and the second column 16 is shorter than the lower limit of the pitch.

これにより、配線基板の面積を増大させること無く、半導体チップ１ｂの端部と基板間接続端子７との間隔１０が、特許文献１に記載の積層型半導体装置よりも、「（１−０．８７）×（ピッチ８）」の長さだけ広がる。   Accordingly, the distance 10 between the end of the semiconductor chip 1b and the inter-substrate connection terminal 7 is larger than that of the stacked semiconductor device described in Patent Document 1 without increasing the area of the wiring board. 87) × (pitch 8) ”.

本構成によれば、配線基板２ａ，２ｂの面積を増大させること無く、半導体チップ１ａと基板間接続端子７との間隔を長くすることができる。したがって、使用時の温度変化によって基板間接続端子７に生じる負荷（応力）が低減される。この結果、基板間接続端子７の断線が発生し難く、接続の信頼性が向上された積層型半導体装置を提供することができる。   According to this configuration, the distance between the semiconductor chip 1a and the inter-substrate connection terminal 7 can be increased without increasing the area of the wiring substrates 2a and 2b. Therefore, a load (stress) generated in the inter-substrate connection terminal 7 due to a temperature change during use is reduced. As a result, it is possible to provide a stacked semiconductor device in which disconnection of the inter-substrate connection terminal 7 hardly occurs and connection reliability is improved.

また、本実施形態の積層型半導体装置では、隣り合って積層された２つの半導体装置１１，１２の隙間を補強用の樹脂で封止する必要は無い。すなわち、隣り合って積層された２つの半導体装置１１，１２が、基板間接続端子７のみによって互いに固定されていて良い。   In the stacked semiconductor device of this embodiment, it is not necessary to seal the gap between the two semiconductor devices 11 and 12 stacked adjacent to each other with a reinforcing resin. That is, the two semiconductor devices 11 and 12 stacked adjacent to each other may be fixed to each other only by the inter-substrate connection terminal 7.

この場合でも、積層型半導体装置として必要な信頼性は確保される。これは半導体チップ１ａ，１ｂと、配線基板２ａ，２ｃとの接続部が、樹脂５ａ，５ｂによって封止されているためである。   Even in this case, the reliability required for the stacked semiconductor device is ensured. This is because the connecting portions between the semiconductor chips 1a and 1b and the wiring boards 2a and 2c are sealed with the resins 5a and 5b.

したがって、互いに積層された半導体装置１１，１２のうちの１つが動作不良であったとしても、動作不良となっている半導体装置のみを容易に取り替えることができる。結果として、特許文献１に記載の積層型半導体装置と比較して、製造コストが削減される。   Therefore, even if one of the semiconductor devices 11 and 12 stacked on each other has a malfunction, only the semiconductor device having the malfunction can be easily replaced. As a result, the manufacturing cost is reduced as compared with the stacked semiconductor device described in Patent Document 1.

ところで、第２の列１６を無くし、基板間接続端子を１列に配置することでも、半導体チップ１ａと基板間接続端子７との間隔を大きくすることは可能である。しかし、この場合、基板間接続端子７の数が減ってしまうとともに、配線基板２ａ、２ｂ同士の接続部が１列となるため、接続部における配線基板の曲げ剛性が大きく低下してしまうというデメリットがある。   By the way, the interval between the semiconductor chip 1a and the inter-substrate connection terminal 7 can be increased by eliminating the second row 16 and arranging the inter-substrate connection terminals in one row. However, in this case, the number of inter-substrate connection terminals 7 is reduced and the connection portions between the wiring substrates 2a and 2b are arranged in a row, so that the bending rigidity of the wiring substrate at the connection portion is greatly reduced. There is.

本実施形態の積層型半導体装置では、配線基板２ａ、２ｂの端部近傍に配置された基板間接続端子７が２列に構成されている。つまり、配線基板２ａ、２ｂ同士の接続部が配線基板２ａ，２ｂの両端側に２列存在するため、配線基板２ａ，２ｂの曲げ剛性の低下が防止される。このように、本実施形態に係る積層型半導体装置では、配線基板２ａ，２ｂ同士を接続する接続部における曲げ剛性の低下が防止されるとともに、半導体チップ１ａと基板間接続端子７との間隔を大きくすることができる。その結果、高い接続信頼性を持った積層型半導体装置を提供することができる。   In the stacked semiconductor device of this embodiment, the inter-substrate connection terminals 7 arranged in the vicinity of the ends of the wiring substrates 2a and 2b are configured in two rows. That is, since there are two rows of connecting portions between the wiring boards 2a and 2b on both ends of the wiring boards 2a and 2b, the bending rigidity of the wiring boards 2a and 2b is prevented from being lowered. As described above, in the stacked semiconductor device according to the present embodiment, a decrease in the bending rigidity in the connection portion connecting the wiring boards 2a and 2b is prevented, and the distance between the semiconductor chip 1a and the inter-substrate connection terminal 7 is increased. Can be bigger. As a result, a stacked semiconductor device with high connection reliability can be provided.

次に、本実施形態に係る積層型半導体装置の製造方法の一例について説明する。まず、第１の半導体装置の製造方法について、図２〜５を参照して説明する。   Next, an example of a manufacturing method of the stacked semiconductor device according to this embodiment will be described. First, a method for manufacturing the first semiconductor device will be described with reference to FIGS.

第１の半導体装置の製造方法として、始めに、配線基板２ａを準備し、配線基板２ａの一の面にエラストマ３ａを形成する（図２参照。）。ここで準備する配線基板２ａは、既述の開口部２０を有している。開口部２０は、後の工程で搭載される半導体チップ１ａの電極パッドの位置に対応して形成されている。   As a first method for manufacturing a semiconductor device, first, a wiring board 2a is prepared, and an elastomer 3a is formed on one surface of the wiring board 2a (see FIG. 2). The wiring board 2a prepared here has the opening 20 described above. The opening 20 is formed corresponding to the position of the electrode pad of the semiconductor chip 1a to be mounted in a later process.

配線基板２ａの配線の一部は、開口部２０の縁部上の２点間を結ぶように突出している。この突出した配線は、後の工程で半導体チップと結線される内部導線４ａとなる。エラストマ３ａは、半導体チップ１ａが搭載される側の面上に形成される。エラストマ３ａは、搭載する半導体チップ１ａより若干大きく、応力緩和材から構成されている。エラストマ３ａは、配線基板２ａの開口部２０と同じ部分に開口部を有している。   A part of the wiring of the wiring board 2 a protrudes so as to connect two points on the edge of the opening 20. The protruding wiring becomes an internal conductor 4a connected to the semiconductor chip in a later process. The elastomer 3a is formed on the surface on which the semiconductor chip 1a is mounted. The elastomer 3a is slightly larger than the semiconductor chip 1a to be mounted, and is made of a stress relaxation material. The elastomer 3a has an opening in the same portion as the opening 20 of the wiring board 2a.

次に、半導体チップ１ａが配線基板２ａに搭載される（図３参照。）。具体的には、半導体チップ１ａの電極パッドが形成された面を配線基板２ａのエラストマ３ａが形成された面側に向け、さらに半導体チップ１ａの電極パッドが配線基板２ａの開口部２０に位置するように、半導体チップ１ａを配置する。この状態で、エラストマ３ａを加熱することで、半導体チップ１ａが配線基板２ａに接合される。   Next, the semiconductor chip 1a is mounted on the wiring board 2a (see FIG. 3). Specifically, the surface of the semiconductor chip 1a on which the electrode pads are formed is directed toward the surface of the wiring board 2a on which the elastomer 3a is formed, and the electrode pads of the semiconductor chip 1a are located in the opening 20 of the wiring board 2a. Thus, the semiconductor chip 1a is arranged. In this state, by heating the elastomer 3a, the semiconductor chip 1a is bonded to the wiring board 2a.

次に、半導体チップ１ａの電極パッドと内部導線４ａとを接続する（図４参照。）。具体的には、配線基板２ａのエラストマ３ａが形成されていない側の面から、開口部２０を通じて内部導線４ａの一部を切断し、切断した内部導線４ａの端部を半導体チップ１ａの電極パッドとボンディング接合させる。   Next, the electrode pad of the semiconductor chip 1a and the internal conductor 4a are connected (see FIG. 4). Specifically, a part of the internal conductor 4a is cut through the opening 20 from the surface of the wiring board 2a where the elastomer 3a is not formed, and the end of the cut internal conductor 4a is used as an electrode pad of the semiconductor chip 1a. And bonding.

そして、開口部２０に樹脂５ａが形成され、さらに外部端子６が形成されることによって、第１の半導体装置１１が製造される（図５参照。）。具体的には、内部導線４ａを覆うように、配線基板２ａの開口部２０は樹脂５ａで封止される。そして、配線基板２ａに、半田ボールを用いて外部端子６を形成する。樹脂５ａとしては、例えばエポキシ系樹脂を用いることができる。また、半田ボールは、例えばＳｎ，Ａｇ，Ｃｕなどからなる。   Then, the resin 5a is formed in the opening 20, and the external terminal 6 is further formed, whereby the first semiconductor device 11 is manufactured (see FIG. 5). Specifically, the opening 20 of the wiring board 2a is sealed with the resin 5a so as to cover the internal conductor 4a. Then, external terminals 6 are formed on the wiring board 2a using solder balls. For example, an epoxy resin can be used as the resin 5a. The solder ball is made of, for example, Sn, Ag, Cu, or the like.

以上の工程により、第１の半導体装置１１を製造することができる。   Through the above steps, the first semiconductor device 11 can be manufactured.

第２の半導体装置１２の製造方法は、第１の半導体装置１１の製造方法とほぼ同様である。第２の半導体装置１２には、外部端子６の代わりに、基板間接続端子７を形成すれば良い（図６参照。）。   The method for manufacturing the second semiconductor device 12 is substantially the same as the method for manufacturing the first semiconductor device 11. In the second semiconductor device 12, an inter-substrate connection terminal 7 may be formed instead of the external terminal 6 (see FIG. 6).

基板間接続端子７としては、半田ボールを用いることが出来る。基板間接続端子７は配線基板２ｂの両端部近傍に配置される。基板間接続端子７の配置は、既に述べたとおりである。   A solder ball can be used as the inter-substrate connection terminal 7. The inter-substrate connection terminals 7 are arranged in the vicinity of both end portions of the wiring substrate 2b. The arrangement of the inter-substrate connection terminals 7 is as described above.

上記のように製造された第２の半導体装置１２を、第１の半導体装置１１に積層することで、図１（ａ），（ｂ）に示された積層型半導体装置を製造することが出来る。具体的には、第１の半導体装置１１上に第２の半導体装置を搭載し、基板間接続端子７をリフローする。これにより、第１の半導体装置１１の配線基板２ａと第２の半導体装置１２の配線基板２ｂとが、基板間接続端子７である半田ボールによって接続される。   By stacking the second semiconductor device 12 manufactured as described above on the first semiconductor device 11, the stacked semiconductor device shown in FIGS. 1A and 1B can be manufactured. . Specifically, the second semiconductor device is mounted on the first semiconductor device 11 and the inter-substrate connection terminal 7 is reflowed. As a result, the wiring board 2 a of the first semiconductor device 11 and the wiring board 2 b of the second semiconductor device 12 are connected by the solder balls that are the inter-substrate connection terminals 7.

なお、第１の半導体装置１１と第２の半導体装置１２との間に補強用の樹脂を充填する必要は無い。   It is not necessary to fill the reinforcing resin between the first semiconductor device 11 and the second semiconductor device 12.

このようにして、本実施形態の積層型半導体装置を製造することができる。上記の製造方法は一例であり、ここで述べた方法に限定されるものではない。例えば、各工程の順番は、可能な限り変更可能である。   In this way, the stacked semiconductor device of this embodiment can be manufactured. The above manufacturing method is an example, and is not limited to the method described here. For example, the order of each process can be changed as much as possible.

［第２の実施形態］
本発明に係る積層型半導体装置は、２層の半導体装置から構成される必要は無く、複数の半導体装置が互いに積層されて構成されていても良い。本実施形態では、一例として、４つの半導体装置が積層されてなる積層型半導体装置について説明する。 [Second Embodiment]
The stacked semiconductor device according to the present invention does not have to be composed of two layers of semiconductor devices, and a plurality of semiconductor devices may be stacked on each other. In the present embodiment, a stacked semiconductor device in which four semiconductor devices are stacked will be described as an example.

図７は、第２の実施形態に係る積層型半導体装置の模式的断面図である。本実施形態に係る積層型半導体装置は、第１，第２，第３，第４の半導体装置１１，１２，１３，１４を有している。それぞれの半導体装置の構成は、第１の実施形態で述べた半導体装置の構成と同様である。   FIG. 7 is a schematic cross-sectional view of the stacked semiconductor device according to the second embodiment. The stacked semiconductor device according to this embodiment includes first, second, third, and fourth semiconductor devices 11, 12, 13, and 14. The configuration of each semiconductor device is the same as the configuration of the semiconductor device described in the first embodiment.

第１の半導体装置１１には、例えば半田ボールからなる外部端子６が形成されている。そして、第１の半導体装置１１に第２の半導体装置１２が、第２の半導体装置１２に第３の半導体装置１３が、第３の半導体装置１３に第４の半導体装置１４が積層されている。   The first semiconductor device 11 is formed with external terminals 6 made of, for example, solder balls. The second semiconductor device 12 is stacked on the first semiconductor device 11, the third semiconductor device 13 is stacked on the second semiconductor device 12, and the fourth semiconductor device 14 is stacked on the third semiconductor device 13. .

積層型半導体装置は、隣り合って積層された２つの半導体装置の配線基板の間を電気的に接続する基板間接続端子７を有している。基板間接続端子７は、第１の実施形態で説明した配置と同様な配置となっている。   The stacked semiconductor device has an inter-substrate connection terminal 7 that electrically connects between wiring substrates of two semiconductor devices stacked adjacent to each other. The inter-substrate connection terminals 7 have the same arrangement as that described in the first embodiment.

第２の半導体装置１２の配線基板と第３の半導体装置１３の配線基板とを接続する基板間接続端子７は、第１の半導体装置１１の配線基板と第２の半導体装置１２の配線基板とを接続する基板間接続端子７と同一の配置である。また第３の半導体装置１３の配線基板と第４の半導体装置１４の配線基板とを接続する基板間接続端子７の配置も同様の配置である。   The inter-substrate connection terminal 7 that connects the wiring substrate of the second semiconductor device 12 and the wiring substrate of the third semiconductor device 13 is connected to the wiring substrate of the first semiconductor device 11 and the wiring substrate of the second semiconductor device 12. Is the same arrangement as the inter-substrate connection terminal 7 for connecting the two. The arrangement of the inter-substrate connection terminals 7 for connecting the wiring board of the third semiconductor device 13 and the wiring board of the fourth semiconductor device 14 is also the same arrangement.

本構成によると、使用時の熱によって各層の配線基板に反り変形が生じた場合でも、隣接する配線基板間の反りの差は低減される。そのため、基板間接続端子７に生じる負荷が低下し、接続の信頼性がより向上する。   According to this configuration, even when warpage deformation occurs in the wiring boards of each layer due to heat during use, the difference in warpage between adjacent wiring boards is reduced. Therefore, the load generated at the inter-substrate connection terminal 7 is reduced, and the connection reliability is further improved.

［第３の実施形態］
基板間接続端子及び外部端子は半田ボールに限定されず、種々のものを用いることができる。本実施形態における積層型半導体装置では、一例として、基板間接続端子として突起電極が用いられている。 [Third Embodiment]
The inter-substrate connection terminals and the external terminals are not limited to solder balls, and various types can be used. In the stacked semiconductor device according to the present embodiment, as an example, a protruding electrode is used as an inter-substrate connection terminal.

図８は、本実施形態の積層型半導体装置の模式的断面図である。本実施形態の積層型半導体装置は、第１の半導体装置１１と第２の半導体装置１２とを有しており、基板間接続端子７を除いて第１の実施形態と同様の構成である。   FIG. 8 is a schematic cross-sectional view of the stacked semiconductor device of this embodiment. The stacked semiconductor device according to this embodiment includes a first semiconductor device 11 and a second semiconductor device 12, and has the same configuration as that of the first embodiment except for the inter-substrate connection terminal 7.

本実施形態では、基板間接続端子７が、突起電極３１と接合材３２とから構成されている。突起電極３１としては、銅で形成されたＣｕポストを用いることができる。なお、突起電極３１の材料として、銅以外の一般的な金属も使用可能である。また、接合材３２は、例えば、半田や導電性樹脂からなる。   In the present embodiment, the inter-substrate connection terminal 7 is composed of the protruding electrode 31 and the bonding material 32. As the protruding electrode 31, a Cu post made of copper can be used. Note that a general metal other than copper can also be used as the material of the protruding electrode 31. The bonding material 32 is made of, for example, solder or conductive resin.

本実施形態においても、基板間接続端子７が第１の実施形態で述べた配置と同様に配置される。これにより、基板間接続端子７に生じる負荷が低減され、基板間接続端子７の断線防止効果を向上する。その結果、接続の信頼性が向上した積層型半導体装置を提供することができる。   Also in this embodiment, the inter-substrate connection terminals 7 are arranged in the same manner as the arrangement described in the first embodiment. Thereby, the load which arises in the connection terminal 7 between boards is reduced, and the disconnection prevention effect of the connection terminal 7 between boards is improved. As a result, a stacked semiconductor device with improved connection reliability can be provided.

以上、本発明の積層型半導体装置について詳細に説明したが、本発明は上記の実施形態に限定されるものではない。   Although the stacked semiconductor device of the present invention has been described in detail above, the present invention is not limited to the above-described embodiment.

例えば、基板間接続端子７は、配線基板２ａ，２ｂの端部に沿って３列以上形成されていても良い。この場合、隣り合う２列の基板間接続端子が、上記の実施形態で説明したように配置される。また、基板間接続端子７は、基板の周囲を取り囲むように配置されていても良い。   For example, the inter-substrate connection terminals 7 may be formed in three or more rows along the end portions of the wiring substrates 2a and 2b. In this case, adjacent two rows of inter-substrate connection terminals are arranged as described in the above embodiment. Further, the inter-substrate connection terminals 7 may be disposed so as to surround the periphery of the substrate.

使用する半導体チップ１ａとしては、種々のチップを用いることができる。その一例として、ＤＲＡＭのようなメモリチップを挙げることが出来る。また、積層された各層の半導体装置において、それぞれ異なる種類の半導体チップが用いられていても良い。   Various chips can be used as the semiconductor chip 1a to be used. One example is a memory chip such as a DRAM. Different types of semiconductor chips may be used in the stacked semiconductor devices of the respective layers.

以上、本発明の望ましい実施形態について提示し、詳細に説明したが、本発明は上記実施形態に限定されるものではなく、要旨を逸脱しない限り、さまざまな変更及び修正が可能であることを理解されたい。   Although the preferred embodiments of the present invention have been presented and described in detail above, the present invention is not limited to the above-described embodiments, and it is understood that various changes and modifications can be made without departing from the gist. I want to be.

（ａ）は第１の実施形態に係る積層型半導体装置の模式的断面図であり、（ｂ）は積層型半導体装置が有する基板間接続端子の配置を示すための模式的平面図である。FIG. 2A is a schematic cross-sectional view of the stacked semiconductor device according to the first embodiment, and FIG. 2B is a schematic plan view for illustrating the arrangement of inter-substrate connection terminals included in the stacked semiconductor device. 第１の実施形態に係る積層型半導体装置の一製造工程を示す模式的断面図。FIG. 3 is a schematic cross-sectional view showing one manufacturing process of the stacked semiconductor device according to the first embodiment. 第１の実施形態に係る積層型半導体装置の一製造工程を示す模式的断面図。FIG. 3 is a schematic cross-sectional view showing one manufacturing process of the stacked semiconductor device according to the first embodiment. 第１の実施形態に係る積層型半導体装置の一製造工程を示す模式的断面図。FIG. 3 is a schematic cross-sectional view showing one manufacturing process of the stacked semiconductor device according to the first embodiment. 第１の実施形態に係る積層型半導体装置の一製造工程を示す模式的断面図。FIG. 3 is a schematic cross-sectional view showing one manufacturing process of the stacked semiconductor device according to the first embodiment. 第１の実施形態に係る積層型半導体装置の一製造工程を示す模式的断面図。FIG. 3 is a schematic cross-sectional view showing one manufacturing process of the stacked semiconductor device according to the first embodiment. 第２の実施形態に係る積層型半導体装置の模式的断面図。FIG. 6 is a schematic cross-sectional view of a stacked semiconductor device according to a second embodiment. 第３の実施形態に係る積層型半導体装置の模式的断面図。FIG. 9 is a schematic cross-sectional view of a stacked semiconductor device according to a third embodiment. （ａ）は特許文献１に記載された積層型半導体装置の模式的断面図であり、（ｂ）は当該積層型半導体装置が有する基板間接続端子の配置を示すための模式的平面図である。(A) is a typical sectional view of a lamination type semiconductor device indicated in patent documents 1, and (b) is a typical plan view for showing arrangement of inter-substrate connection terminal which the lamination type semiconductor device has. .

符号の説明Explanation of symbols

１ａ、１ｂ 半導体チップ
２ａ、２ｂ 配線基板
３ａ、３ｂ エラストマ
４ａ、４ｂ 内部導線
５ａ、５ｂ 樹脂
６ 外部端子
７ 基板間接続端子
８ ピッチ
９ 間隔
１０ 間隔
１１ 第１の半導体装置
１２ 第２の半導体装置
１３ 第１の半導体装置
１４ 第２の半導体装置
１５ 第１の列
１６ 第２の列
２０ 開口部
３１ 突起電極
３２ 接合材
３３ 中心間距離
１００ 積層型半導体装置
１０１ 第１の半導体装置
１０２ 第２の半導体装置
１０３ａ，１０３ｂ 半導体チップ
１０４ａ，１０４ｂ 配線基板
１０５ 樹脂
１０６ 基板間接続端子
１０６ａ 外側の基板間接続端子
１０６ｂ 内側の基板間接続端子
１０７ 間隔
１０９ 間隔 1a, 1b Semiconductor chip 2a, 2b Wiring substrate 3a, 3b Elastomer 4a, 4b Internal conductor 5a, 5b Resin 6 External terminal 7 Inter-substrate connection terminal 8 Pitch 9 Interval 10 Interval 11 First semiconductor device 12 Second semiconductor device 13 1st semiconductor device 14 2nd semiconductor device 15 1st row | line | column 16 2nd row | line | column 20 Opening part 31 Projection electrode 32 Joining material 33 Center distance 100 Laminated | stacked semiconductor device 101 1st semiconductor device 102 2nd semiconductor Device 103a, 103b Semiconductor chip 104a, 104b Wiring board 105 Resin 106 Inter-board connection terminal 106a Outer inter-board connection terminal 106b Inner inter-board connection terminal 107 Spacing 109 Spacing

Claims (12)

配線基板と該配線基板に搭載された半導体チップとを有する互いに積層された複数の半導体装置と、隣り合って積層された２つの前記半導体装置の前記配線基板の間を電気的に接続する基板間接続端子と、を有する積層型半導体装置において、
前記基板間接続端子は、少なくとも、前記配線基板の端部近傍に該端部に沿って所定のピッチで配置された第１の列と第２の列とを構成しており、
前記第１の列を構成する前記基板間接続端子と、前記第２の列を構成する前記基板間接続端子とが、前記第１の列に沿った方向に互いにずれて配置されていることを特徴とする、積層型半導体装置。 Between a plurality of mutually stacked semiconductor devices having a wiring substrate and a semiconductor chip mounted on the wiring substrate, and between the substrates electrically connecting between the wiring substrates of two adjacent semiconductor devices stacked In a stacked semiconductor device having a connection terminal,
The inter-substrate connection terminals constitute at least a first row and a second row arranged at a predetermined pitch along the end portion in the vicinity of the end portion of the wiring board,
The inter-board connection terminals constituting the first row and the inter-board connection terminals constituting the second row are arranged so as to be shifted from each other in the direction along the first row. A feature of a stacked semiconductor device. 前記第１の列と前記第２の列との間隔が前記ピッチよりも短いことを特徴とする、請求項１に記載の積層型半導体装置。   2. The stacked semiconductor device according to claim 1, wherein an interval between the first row and the second row is shorter than the pitch. 前記第１の列を構成する前記基板間接続端子のうち隣接した２つの前記基板間接続端子からの距離が等しい位置に、前記第２の列を構成する前記基板間接続端子が配置されていることを特徴とする、請求項１または２に記載の積層型半導体装置。   The inter-substrate connection terminals constituting the second row are arranged at positions where the distances between two adjacent inter-substrate connection terminals among the inter-substrate connection terminals constituting the first row are equal. The stacked semiconductor device according to claim 1, wherein the stacked semiconductor device is a semiconductor device. 前記第１の列を構成する一の基板間接続端子の中心から、前記第２の列を構成する前記基板間接続端子のうち前記一の基板間接続端子と最近接する前記基板間接続端子の中心までの距離が、前記ピッチと同一の長さであることを特徴とする、請求項１から３のいずれか１項に記載の積層型半導体装置。   The center of the inter-board connection terminal closest to the inter-board connection terminal among the inter-board connection terminals constituting the second row from the center of the inter-board connection terminal constituting the first row. 4. The stacked semiconductor device according to claim 1, wherein a distance up to is the same length as the pitch. 5. 前記基板間接続端子が半田ボールであることを特徴とする、請求項１から４のいずれか１項に記載の積層型半導体装置。   The stacked semiconductor device according to claim 1, wherein the inter-substrate connection terminal is a solder ball. 前記配線基板は前記半導体チップよりも小さな開口部を有し、
前記半導体チップの一の面には電極パッドが設けられており、
前記電極パッドが前記開口部に位置するように、前記一の面を前記配線基板に向けて前記半導体チップが搭載されていることを特徴とする、請求項１から５のいずれか１項に記載の積層型半導体装置。 The wiring board has an opening smaller than the semiconductor chip,
An electrode pad is provided on one surface of the semiconductor chip,
6. The semiconductor chip according to claim 1, wherein the semiconductor chip is mounted with the one surface facing the wiring substrate so that the electrode pad is positioned in the opening. 7. Multilayer semiconductor device. 前記開口部が前記配線基板の中央部に形成されており、
前記電極パッドが前記半導体チップの中央部に形成されていることを特徴とする、請求項６に記載の積層型半導体装置。 The opening is formed in the center of the wiring board;
The stacked semiconductor device according to claim 6, wherein the electrode pad is formed in a central portion of the semiconductor chip. 前記半導体チップは、エラストマを介して前記配線基板に搭載されており、
該エラストマは、前記配線基板の前記開口部が形成された領域に開口部が形成されていることを特徴とする、請求項６または７に記載の積層型半導体装置。 The semiconductor chip is mounted on the wiring board via an elastomer,
8. The stacked semiconductor device according to claim 6, wherein the elastomer has an opening formed in a region of the wiring board where the opening is formed. 9. 前記配線基板に形成された配線の一部が前記開口部へ突出した内部導線を成しており、
該内部導線が前記電極パッドと接続されていることを特徴とする、請求項６から８のいずれか１項に記載の積層型半導体装置。 A part of the wiring formed on the wiring board constitutes an internal conductor protruding to the opening,
9. The stacked semiconductor device according to claim 6, wherein the internal conductor is connected to the electrode pad. 前記内部導線と前記電極パッドとの接続部を覆うように、前記開口部が樹脂で封止されていることを特徴とする、請求項９に記載の積層型半導体装置。   The stacked semiconductor device according to claim 9, wherein the opening is sealed with a resin so as to cover a connection portion between the internal conductor and the electrode pad. 隣り合って積層された２つの前記半導体装置は、前記基板間接続端子のみによって互いに固定されていることを特徴とする、請求項１から１０のいずれか１項に記載の積層型半導体装置。   11. The stacked semiconductor device according to claim 1, wherein the two semiconductor devices stacked adjacent to each other are fixed to each other only by the inter-substrate connection terminals. 11. 前記半導体チップがメモリチップであることを特徴とする、請求項１から１１のいずれか１項に記載の積層型半導体装置。   The stacked semiconductor device according to claim 1, wherein the semiconductor chip is a memory chip.
JP2008216463A 2008-08-26 2008-08-26 Multilayer semiconductor device Pending JP2010056121A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109560182A (en) * 2017-09-25 2019-04-02 日亚化学工业株式会社 Light-emitting component and light emitting device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109560182A (en) * 2017-09-25 2019-04-02 日亚化学工业株式会社 Light-emitting component and light emitting device
CN109560182B (en) * 2017-09-25 2023-09-15 日亚化学工业株式会社 Light-emitting element and light-emitting device

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