JP2010010325A - Printed circuit board, and method of forming solder resist of printed circuit board - Google Patents

Printed circuit board, and method of forming solder resist of printed circuit board Download PDF

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JP2010010325A
JP2010010325A JP2008166877A JP2008166877A JP2010010325A JP 2010010325 A JP2010010325 A JP 2010010325A JP 2008166877 A JP2008166877 A JP 2008166877A JP 2008166877 A JP2008166877 A JP 2008166877A JP 2010010325 A JP2010010325 A JP 2010010325A
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solder resist
pads
printed wiring
wiring board
circuit board
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JP5399012B2 (en
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Takashi Shiiba
尊 椎葉
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Elna Co Ltd
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Elna Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a printed circuit board which is free of absence of solder resist stacked more than twice when pitch intervals between pads are extremely narrow, and to provide a method of forming the solder resist. <P>SOLUTION: For three-layered coating, an uneven part is formed on a surface of first solder resist which is previously applied to a gap part between two pads, the surface of the first solder resist where the uneven part is formed is coated with second solder resist, an uneven part is formed on a surface of the second solder resist, and the surface of the second solder resist where the uneven part is formed is coated with third solder resist. An uneven part on a surface of solder resist may comprise only longitudinal grooves, only lateral grooves, a combination of longitudinal grooves and lateral grooves, dotted recessed parts, ant grooves, etc. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は、プリント配線基板及びプリント配線基板におけるソルダーレジストの形成方法に関するもので、さらに詳しくは、ソルダーレジストは、プリント配線基板の半田付けをする部分を除いて全面に塗布し、半田の付着防止、導体管理の絶縁性の維持、導体の保護、電気特性の改善、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）などのパッケージのモールドの下地などを目的として行われるが、特に、パターン間の狭い隙間に何層かを塗布したときのソルダーレジストの密着性の向上を図ったプリント配線基板及びプリント配線基板におけるソルダーレジストの形成方法に関するものである。   The present invention relates to a printed wiring board and a method for forming a solder resist on the printed wiring board. More specifically, the solder resist is applied to the entire surface except a portion to be soldered on the printed wiring board to prevent adhesion of solder. It is performed for the purpose of maintaining insulation of conductor management, protecting conductors, improving electrical characteristics, and the base of molds for packages such as BGA (Ball Grid Array). It is related with the formation method of the soldering resist in the printed wiring board which aimed at the improvement of the adhesiveness of the soldering resist when apply | coating, and a printed wiring board.

多層プリント配線板のプロセスは、一般に図３に示す工程で行われる。
内層銅張積層板を出発物質とし、「内層パターン作成」、「積層」（この工程で多層銅箔プリプレクも積層編成される）、「穴加工」（両面プリント配線板の場合、この工程で両面銅張積層板の穴加工を行う）、「無電解銅メッキ」、「パネル銅メッキ」、「外層パターン作成」、「ソルダーレジストマーキング形成」、「フラックス塗布などの後処理」、「外形加工・洗浄」の各工程を経て「多層プリント配線板完成」となる。
パターンやマーキング作成は、感光フィルムを出発物質とし、「レーザ描写」、「作業マスク完成」、「マスク検査」により行われる。 The process of a multilayer printed wiring board is generally performed in the steps shown in FIG.
Starting with an inner layer copper clad laminate, “inner layer pattern creation”, “lamination” (multilayer copper foil prepreg is also layered and knitted in this process), “hole processing” (both sides in this process for double-sided printed wiring boards) Copper-clad laminate holes), “electroless copper plating”, “panel copper plating”, “outer layer pattern creation”, “solder resist marking formation”, “post-treatment such as flux coating”, “outline processing / Through each process of “cleaning”, “multi-layer printed wiring board completed”.
Patterns and markings are made by “laser drawing”, “work mask completion”, and “mask inspection” using a photosensitive film as a starting material.

図３に示す「ソルダーレジストマーキング作成」工程において、ソルダーレジストは、プリント配線基板のパターンの半田付けをする部分を除き全面に塗布される。半田付けをする部分としては、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）・ＢＧＡ・チップ部品などのパッドと、必要に応じて外部接続端子を露出させている。
このソルダーレジスト塗布工程において、図４に示すようにプリント配線基板１０の１回目のソルダーレジスト１２の上にさらに２回目のソルダーレジスト１３を塗布することが知られている（特許文献１）。
これは、次の工程により、プリント配線基板１０が製造される。
（１）プリント配線基板１０の銅箔に銅メッキを施す工程。
（２）不要な銅メッキと銅箔をエッチングしてパッド１１を形成する工程。
（３）１回目のソルダーレジスト１２を塗布する工程。
（４）１回目と同じ位置に重ねて２回目のソルダーレジスト１３を塗布する工程。 In the “solder resist marking creation” step shown in FIG. 3, the solder resist is applied to the entire surface except for the portion where the pattern of the printed wiring board is to be soldered. As parts to be soldered, pads such as QFP (Quad Flat Package), BGA, chip parts, and external connection terminals are exposed as necessary.
In this solder resist coating process, it is known that a second solder resist 13 is further coated on the first solder resist 12 of the printed wiring board 10 as shown in FIG. 4 (Patent Document 1).
In this process, the printed wiring board 10 is manufactured by the following process.
(1) A step of performing copper plating on the copper foil of the printed wiring board 10.
(2) A step of forming the pad 11 by etching unnecessary copper plating and copper foil.
(3) A step of applying the first solder resist 12.
(4) A step of applying the second solder resist 13 in the same position as the first time.

また、図５に示すように、封止樹脂１８が外部接続端子１５に流れ込んで接触不良を起こすのを防止するために１回目のソルダーレジスト１２に溝１９や段差部２０を形成する方法が知られている（特許文献２）。
この方法は、プリント配線基板１０の裏面に接着剤層２２によって電子部品２１を搭載し、プリント配線基板１０のスリット１６を通して表面のデバイス側接続端子２３にボンディングワイヤ１７で接続し、電子部品２１との接続部分が封止樹脂１８のモールドにより封止されるようにした方法において、モールドされる領域のソルダーレジスト１２に溝１９及び／又は段差部２０を形成して封止樹脂１８が外部接続端子１５側へ流れ込まないようにしたものである。
特開平８−１１１５７８号公報。 特開２００２−１５１８３３号公報。 Further, as shown in FIG. 5, there is known a method of forming a groove 19 or a stepped portion 20 in the first solder resist 12 in order to prevent the sealing resin 18 from flowing into the external connection terminal 15 to cause a contact failure. (Patent Document 2).
In this method, the electronic component 21 is mounted on the back surface of the printed wiring board 10 by the adhesive layer 22, and is connected to the device-side connection terminal 23 on the surface through the slit 16 of the printed wiring board 10 with the bonding wire 17. In this method, the groove 19 and / or the step 20 is formed in the solder resist 12 in the region to be molded, so that the sealing resin 18 is connected to the external connection terminal. This is designed not to flow into the 15 side.
JP-A-8-111578. Japanese Patent Laid-Open No. 2002-151833.

特許文献１記載の発明は、パッド１１とソルダーレジスト１２の厚さが略同じ約５０μｍであるのに対し、当時のパッド１１間の隙間が約３００μｍと比較的大きいので、１回目のソルダーレジスト１２を塗布し、この１回目と同じ位置に重ねて２回目のソルダーレジスト１３を塗布しても１回目のソルダーレジスト１２と２回目のソルダーレジスト１３の密着性はあまり問題にされなかった。
ところが、最近のプリント配線板では、実装の高密度化に伴い、パッド１１の大きさ、パッド１１のピッチ間隔が年々小さくなってきている。具体的には、パッド１１とソルダーレジスト１２の厚さが略同じ約５０μｍであるのに対し、２つのパッド１１のピッチ間隔が１５０μｍのように極めて狭くなってきている。
半面、ソルダーレジストによる、半田耐熱性、電気絶縁性、耐候性、耐メッキ性、その他の電気的、機械的特性を保持するためには、所定以上の厚さを必要とし、ソルダーレジストの２回重ね、３回重ね、さらにそれ以上重ねて塗布することが行われるようになってきた。そのため、２回以上重ねたソルダーレジスト部分の欠落が発生するという問題があった。
例えば、パッド１１のピッチ間隔が１５０μｍとすると、ソルダーレジストの厚さは、２回重ねで１００μｍとなり、３回重ねで１５０μｍとなる。このように、幅に対する厚さの比が次第に大きくなり、パッド１１の間のソルダーレジストに欠落の恐れがあった。 In the invention described in Patent Document 1, the thickness of the pad 11 and the solder resist 12 is approximately the same of about 50 μm, whereas the gap between the pads 11 at that time is relatively large at about 300 μm. Even when the second solder resist 13 was applied in the same position as the first time, the adhesion between the first solder resist 12 and the second solder resist 13 was not a problem.
However, in recent printed wiring boards, the size of the pads 11 and the pitch interval between the pads 11 are decreasing year by year as the mounting density is increased. Specifically, the pad 11 and the solder resist 12 have substantially the same thickness of about 50 μm, whereas the pitch interval between the two pads 11 has become extremely narrow, such as 150 μm.
On the other hand, in order to maintain solder heat resistance, electrical insulation, weather resistance, plating resistance, and other electrical and mechanical properties by solder resist, a thickness greater than a predetermined thickness is required. It has come to be performed by applying three times, three times, and further. For this reason, there is a problem in that a portion of the solder resist portion that has been stacked two or more times is lost.
For example, when the pitch interval of the pads 11 is 150 μm, the thickness of the solder resist is 100 μm when it is overlapped twice and 150 μm when it is overlapped three times. Thus, the ratio of the thickness to the width gradually increased, and the solder resist between the pads 11 might be missing.

特許文献２記載の発明は、１回目のソルダーレジスト１２に溝１９や段差部２０を形成して封止樹脂１８が外部接続端子１５側へ流れ込むのを防止するものであり、ソルダーレジストを複数回重ねて塗布するものとは異質な発明である。
本発明は、プリント配線板における実装の高密度化に伴い、ソルダーレジストの解像度、パッド間に形成しうるパターンの位置合わせ精度、幅の狭いレジストで強度の高いものが必要となってきたことに鑑み、パッド間のピッチ間隔が極めて狭くなってきている場合において、２回以上重ねたソルダーレジスト部分の欠落のないプリント配線基板及びソルダーレジストの形成方法を提供することを目的とするものである。 In the invention described in Patent Document 2, the groove 19 and the stepped portion 20 are formed in the first solder resist 12 to prevent the sealing resin 18 from flowing into the external connection terminal 15 side. It is an invention different from what is applied in layers.
The present invention has become necessary to increase the resolution of the solder resist, the alignment accuracy of the pattern that can be formed between the pads, the resist having a narrow width and high strength as the mounting density of the printed wiring board is increased. In view of the above, it is an object of the present invention to provide a printed wiring board and a method for forming a solder resist without missing a solder resist portion that has been stacked twice or more when the pitch interval between pads has become extremely narrow.

本発明は、２層塗の場合、予め塗布されたソルダーレジストであって、２つのパッド間の隙間部分に塗布されたソルダーレジストの表面に凹凸部を形成し、 この凹凸部を形成したソルダーレジストの表面に重ねてソルダーレジストを塗布してなることを特徴とする。   In the case of two-layer coating, the present invention is a solder resist that has been applied in advance, and has an uneven portion formed on the surface of the solder resist applied to a gap portion between two pads. It is characterized in that it is formed by applying a solder resist on the surface.

また、３層塗の場合、予め塗布された１回目のソルダーレジストであって、２つのパッド間の隙間部分に塗布された１回目のソルダーレジストの表面に凹凸部を形成し、この凹凸部を形成した１回目のソルダーレジストの表面に２回目のソルダーレジストを塗布し、この２回目のソルダーレジストの表面に凹凸部を形成し、この凹凸部を形成した２回目のソルダーレジストの表面に３回目のソルダーレジストを塗布してなることを特徴とする。   Also, in the case of three-layer coating, a first-time solder resist applied in advance, an uneven portion is formed on the surface of the first solder resist applied to a gap portion between two pads, and this uneven portion is A second solder resist is applied to the surface of the first solder resist formed, an uneven portion is formed on the surface of the second solder resist, and a third time is applied to the surface of the second solder resist formed with the uneven portion. It is characterized by being coated with a solder resist.

ソルダーレジストの表面の凹凸部は、縦溝のみ、横溝のみ、縦溝と横溝の組み合わせ、点在する凹部、蟻溝などからなるものとすることができる。 The uneven portion on the surface of the solder resist can be composed of only vertical grooves, only horizontal grooves, a combination of vertical grooves and horizontal grooves, interspersed concave portions, dovetail grooves, and the like.

本発明は、上述のように構成することにより、以下の効果を有する。
（１）下層のソルダーレジスト表面の凹凸部に上層のソルダーレジストが入りこみ、両者の密着性が向上する。
（２）上層のソルダーレジストが下層のソルダーレジスト表面から欠落するのを防止するので、品質が向上する。
（３）下層のソルダーレジスト表面に凹凸部を形成してその上に重ねてソルダーレジストを塗布するだけなので、作業性にも優れている。 The present invention has the following effects by being configured as described above.
(1) The upper solder resist penetrates into the concavo-convex portion of the lower solder resist surface, and the adhesion between them is improved.
(2) Since the upper solder resist is prevented from being missing from the lower solder resist surface, the quality is improved.
(3) Since the uneven part is formed on the surface of the lower layer solder resist and only the solder resist is applied thereon, it is excellent in workability.

本発明は、パッドその他の半田付けをする部分を除いてソルダーレジストを塗布したプリント配線基板であって、２つのパッド間の隙間部分に多層のソルダーレジストを塗布するものに適用される。
予め塗布されたソルダーレジストであって、２つのパッド間の隙間部分に塗布されたソルダーレジストの表面に凹凸部を形成し、この凹凸部を形成したソルダーレジストの表面に重ねてソルダーレジストを塗布してなるものである。
具体的には、予め塗布された１回目のソルダーレジストであって、２つのパッド間の隙間部分に塗布された１回目のソルダーレジストの表面に凹凸部を形成し、この凹凸部を形成した１回目のソルダーレジストの表面に２回目のソルダーレジストを塗布し、この２回目のソルダーレジストの表面に凹凸部を形成し、この凹凸部を形成した２回目のソルダーレジストの表面に３回目のソルダーレジストを塗布してなるものである。
凹凸部は、縦溝のみ、横溝のみ、縦溝と横溝の組み合わせ、点在する凹部、蟻溝などからなるものとすることができる。 The present invention is applied to a printed wiring board to which a solder resist is applied except for pads and other parts to be soldered, in which a multilayer solder resist is applied to a gap portion between two pads.
A solder resist that has been applied in advance, forming an uneven portion on the surface of the solder resist applied to the gap between the two pads, and applying the solder resist on the surface of the solder resist that has been formed with the uneven portion. It will be.
Specifically, it is a first solder resist applied in advance, and an uneven portion is formed on the surface of the first solder resist applied to a gap portion between two pads. The second solder resist is applied to the surface of the second solder resist, an uneven portion is formed on the surface of the second solder resist, and the third solder resist is formed on the surface of the second solder resist formed with the uneven portion. Is applied.
The concavo-convex portion can be composed of only a vertical groove, only a horizontal groove, a combination of a vertical groove and a horizontal groove, dotted concave portions, dovetail grooves, and the like.

本発明によるプリント配線基板におけるソルダーレジスト塗布工程を図１に基づき説明する。
１．第１回目のソルダーレジスト塗布工程（図１の（ａ−１）（ａ−２））
プリント配線基板１０のパッド１１を残して１回目のソルダーレジスト１２を塗布する。ソルダーレジストには、ドライフィルムと液状のものがあるが、本発明では、液状のものが使用される。液状レジストには、熱硬化型、紫外線硬化型と感光性型があり、熱硬化型、紫外線硬化型は、スクリーン印刷法でパターンを形成する。感光性型は、パネル全面にスクリーン印刷法、カーテンコート法、スプレーコート法などでコーティングされる。
このようにして、パッド１１の部分を露出した状態に塗布される。外部接続端子１５は、必要に応じて一部が露出される。
１回目のソルダーレジスト１２は、厚さがパッド１１と略同じ約５０μｍ、幅が約１５０μｍに塗布される。 The solder resist coating process in the printed wiring board according to the present invention will be described with reference to FIG.
1. First solder resist coating step ((a-1) (a-2) in FIG. 1)
The first solder resist 12 is applied leaving the pads 11 of the printed wiring board 10. The solder resist includes a dry film and a liquid one. In the present invention, a liquid one is used. The liquid resist includes a thermosetting type, an ultraviolet curable type, and a photosensitive type. The thermosetting type and the ultraviolet curable type form a pattern by a screen printing method. The photosensitive mold is coated on the entire panel by screen printing, curtain coating, spray coating, or the like.
In this way, the pad 11 is applied in an exposed state. A part of the external connection terminal 15 is exposed as necessary.
The first solder resist 12 is applied to a thickness of about 50 μm, which is substantially the same as the pad 11, and a width of about 150 μm.

２．１回目のソルダーレジスト１２に凹凸部２４を形成する工程（図１の（ｂ−１）（ｂ−２））
２つのパッド１１によって形成された隙間部分の１回目のソルダーレジスト１２に凹凸部２４を形成する。この凹凸部２４は、１本の縦溝２５と複数本の横溝２６が交差するように形成した例を示している。
この凹凸部２４を形成する具体的方法は、例えば、フォトマスクを介して露光、現像してパターニングする方法、レーザ加工による方法などが挙げられる。縦溝２５と横溝２６の深さは、２０μｍ程度とし、幅は、２５μｍ程度とする。 2.1 Step of forming concave and convex portion 24 on solder resist 12 ((b-1) (b-2) in FIG. 1)
An uneven portion 24 is formed in the first solder resist 12 in the gap formed by the two pads 11. This uneven portion 24 shows an example in which one vertical groove 25 and a plurality of horizontal grooves 26 are formed to intersect each other.
Specific methods for forming the uneven portion 24 include, for example, a method of patterning by exposure and development through a photomask, a method by laser processing, and the like. The depth of the vertical groove 25 and the horizontal groove 26 is about 20 μm, and the width is about 25 μm.

３．第２回目のソルダーレジスト塗布工程（図１の（ｃ−１）（ｃ−２））
凹凸部２４を形成した１回目のソルダーレジスト１２の上に第２回目の２回目のソルダーレジスト１３を塗布する。
２回目のソルダーレジスト１２は、厚さが２０〜５０μｍ、幅が１００〜１５０μｍ、長さが約１３００μｍに塗布される。縦溝２５と横溝２６の深さは、１０〜２０μｍ程度とし、幅は、２５μｍ程度とする。 3. Second solder resist coating step ((c-1) (c-2) in FIG. 1)
A second solder resist 13 is applied for the second time on the solder resist 12 for the first time on which the uneven portions 24 are formed.
The second solder resist 12 is applied to a thickness of 20 to 50 μm, a width of 100 to 150 μm, and a length of about 1300 μm. The depth of the vertical groove 25 and the horizontal groove 26 is about 10 to 20 μm, and the width is about 25 μm.

４．２回目のソルダーレジスト１３に凹凸部２４を形成する工程（図１の（ｄ−１）（ｄ−２））
２回目のソルダーレジスト１３に凹凸部２４を形成する。この凹凸部２４は、前記同様１本の縦溝２５と複数本の横溝２６が交差するように形成した例を示している。 4. Step of forming the uneven portion 24 in the second solder resist 13 ((d-1) (d-2) in FIG. 1)
The uneven portion 24 is formed in the solder resist 13 for the second time. The uneven portion 24 is an example in which one vertical groove 25 and a plurality of horizontal grooves 26 are formed so as to intersect each other as described above.

５．第３回目のソルダーレジスト塗布工程（図１の（ｅ−１）（ｅ−２））
凹凸部２４を形成した２回目のソルダーレジスト１３の上に第３回目の３回目のソルダーレジスト２８を塗布する。
ソルダーレジスト１２の厚さが目的の高さに達しない場合には、達するまで凹凸部２４を形成する工程とソルダーレジスト塗布する工程を繰り返す。 5). Third solder resist coating step ((e-1) (e-2) in FIG. 1)
A third solder resist 28 is applied on the second solder resist 13 on which the concavo-convex portion 24 is formed.
When the thickness of the solder resist 12 does not reach the target height, the process of forming the uneven portion 24 and the process of applying the solder resist are repeated until the solder resist 12 reaches the target height.

以上のように、１回目のソルダーレジスト１２に凹凸部２４を形成して２回目のソルダーレジスト１３を塗布し、さらに２回目のソルダーレジスト１３に凹凸部２４を形成して３回目のソルダーレジスト２８を塗布したので、１回目のソルダーレジスト接着剤層１２、２回目のソルダーレジスト１３、３回目のソルダーレジスト２８の間がしっかりと保持されて欠落することがなくなる。   As described above, the uneven portion 24 is formed on the first solder resist 12 and the second solder resist 13 is applied, and the uneven portion 24 is formed on the second solder resist 13 to form the third solder resist 28. Is applied between the first solder resist adhesive layer 12, the second solder resist 13, and the third solder resist 28, so that there is no loss.

前記実施例では、凹凸部２４の形状を１本の縦溝２５と複数本の横溝２６を交差させたものとした。しかし、これに限られるものではなく、図２に示すような種種の形態とすることができる。
図２（ａ−１）（ａ−２）は、凹凸部２４が２本またはそれ以上の縦溝２５からなる例を示している。形状が単純なので製作が容易である。
図２（ｂ−１）（ｂ−２）は、凹凸部２４が複数個の４角形の凹部２７を点線状に形成した例を示している。
図２（ｃ−１）（ｃ−２）は、凹凸部２４が１本の縦溝２５であって、内側が幅広い、いわゆる蟻溝からなる例を示している。内側が幅広いので、上下の層が互いにしっかりと保持される。
図２（ｄ−１）（ｄ−２）は、凹凸部２４が複数個の円形の凹部２７を連続的に連通して縦溝２５とした例を示している。縦溝２５の側壁に凹凸が形成されるので、しっかりと保持される。 In the above-described embodiment, the shape of the concavo-convex portion 24 is such that one vertical groove 25 and a plurality of horizontal grooves 26 intersect each other. However, the present invention is not limited to this, and various forms as shown in FIG.
FIGS. 2A-1 and 2A-2 show an example in which the uneven portion 24 includes two or more vertical grooves 25. FIG. Easy to manufacture because of its simple shape.
FIGS. 2B-1 and 2B-2 show an example in which the concave and convex portion 24 has a plurality of quadrangular concave portions 27 formed in dotted lines.
2 (c-1) and 2 (c-2) show an example in which the concave and convex portion 24 is a single vertical groove 25 and the inner side is wide, so-called dovetails. Since the inside is wide, the upper and lower layers are held firmly together.
FIGS. 2D-1 and 2D-2 show an example in which the concavo-convex portion 24 is formed as a longitudinal groove 25 by continuously communicating a plurality of circular concave portions 27. Since unevenness is formed on the side wall of the vertical groove 25, it is firmly held.

本発明は、凹凸部２４を以上の例に限るものではなく、塗布したソルダーレジストの表面に凹凸をつけて上下の層が互いに密着し、欠落することを防止するという本発明の目的を達成できる形態であればよい。   The present invention is not limited to the concavo-convex portion 24 as described above, and can achieve the object of the present invention to prevent the upper and lower layers from sticking to each other and missing from the surface of the applied solder resist. Any form is acceptable.

本発明によるソルダーレジストの形成方法の各工程を示すもので、（ａ−１）は、第１工程の平面図、（ａ−２）は、Ａ−Ａ線断面図、（ｂ−１）は、第２工程の平面図、（ｂ−２）は、Ｂ−Ｂ線断面図、（ｃ−１）は、第３工程の平面図、（ｃ−２）は、Ｃ−Ｃ線断面図、（ｄ−１）は、第４工程の平面図、（ｄ−２）は、Ｄ−Ｄ線断面図、（ｅ−１）は、第５工程の平面図、（ｅ−２）は、Ｅ−Ｅ線断面図である。Each step of the method for forming a solder resist according to the present invention is shown, wherein (a-1) is a plan view of the first step, (a-2) is a cross-sectional view along the line AA, and (b-1) is , A plan view of the second step, (b-2) is a sectional view taken along the line BB, (c-1) is a plan view of the third step, (c-2) is a sectional view taken along the line CC, (D-1) is a plan view of the fourth step, (d-2) is a sectional view taken along the line DD, (e-1) is a plan view of the fifth step, and (e-2) is E FIG. 本発明によるソルダーレジストの形成方法の凹凸部２４の他の例を示すもので、（ａ−１）は、実施例２の平面図、（ａ−２）は、Ｆ−Ｆ線断面図、（ｂ−１）は、実施例３の平面図、（ｂ−２）は、Ｇ−Ｇ線断面図、（ｃ−１）は、実施例４の平面図、（ｃ−２）は、Ｈ−Ｈ線断面図、（ｄ−１）は、実施例５の平面図、（ｄ−２）は、Ｉ−Ｉ線断面図である。The other example of the uneven | corrugated | grooved part 24 of the formation method of the soldering resist by this invention is shown, (a-1) is a top view of Example 2, (a-2) is FF sectional view taken on the line, ( b-1) is a plan view of Example 3, (b-2) is a sectional view taken along line GG, (c-1) is a plan view of Example 4, and (c-2) is H- H line sectional view, (d-1) is a plan view of Example 5, (d-2) is a II line sectional view. 一般的な多層プリント配線板の工程を示すフローチャートである。It is a flowchart which shows the process of a general multilayer printed wiring board. 従来の多層プリント配線板の第１例を示す断面図である。It is sectional drawing which shows the 1st example of the conventional multilayer printed wiring board. 従来の多層プリント配線板の第２例を示す断面図である。It is sectional drawing which shows the 2nd example of the conventional multilayer printed wiring board.

符号の説明Explanation of symbols

１０…プリント配線基板、１１…パッド、１２…１回目のソルダーレジスト、１３…２回目のソルダーレジスト、１４…フラックス、１５…外部接続端子、１６…スリット、１７…ボンディングワイヤ、１８…封止樹脂、１９…溝、２０…段差部、２１…電子部品、２２…接着剤層、２３…デバイス側接続端子、２４…凹凸部、２５…縦溝、２６…横溝、２７…凹部、２８…３回目のソルダーレジスト。   DESCRIPTION OF SYMBOLS 10 ... Printed wiring board, 11 ... Pad, 12 ... First solder resist, 13 ... Second solder resist, 14 ... Flux, 15 ... External connection terminal, 16 ... Slit, 17 ... Bonding wire, 18 ... Sealing resin , 19, groove, 20, stepped portion, 21, electronic component, 22, adhesive layer, 23, device side connection terminal, 24, uneven portion, 25, vertical groove, 26, horizontal groove, 27, concave portion, 28, third time. Solder resist.

Claims (7)

パッドその他の半田付けをする部分を除いてソルダーレジストを塗布したプリント配線基板において、
予め塗布されたソルダーレジストの表面に凹凸部を形成し、この凹凸部を形成したソルダーレジストの表面に重ねてソルダーレジストを塗布してなることを特徴とするプリント配線基板。 In the printed circuit board where the solder resist is applied except the pad and other parts to be soldered,
A printed wiring board, wherein a concavo-convex portion is formed on a surface of a solder resist applied in advance, and the solder resist is applied on the surface of the solder resist on which the concavo-convex portion is formed. 予め塗布されたソルダーレジストであって、２つのパッド間の隙間部分に塗布されたソルダーレジストの表面に凹凸部を形成し、この凹凸部を形成したソルダーレジストの表面に重ねてソルダーレジストを塗布してなることを特徴とする請求項１記載のプリント配線基板。   A solder resist that has been applied in advance, forming an uneven portion on the surface of the solder resist applied to the gap between the two pads, and applying the solder resist on the surface of the solder resist that has been formed with the uneven portion. The printed wiring board according to claim 1, wherein 予め塗布された１回目のソルダーレジストであって、２つのパッド間の隙間部分に塗布された１回目のソルダーレジストの表面に凹凸部を形成し、この凹凸部を形成した１回目のソルダーレジストの表面に２回目のソルダーレジストを塗布してなることを特徴とする請求項１記載のプリント配線基板。   A first-time solder resist that is pre-applied and has an uneven portion formed on the surface of the first solder resist applied to a gap portion between two pads, and the first solder resist formed with the uneven portion. The printed wiring board according to claim 1, wherein a second solder resist is applied to the surface. 凹凸部は、縦溝及び／又は横溝からなることを特徴とする請求項１、２又は３記載のプリント配線基板。 The printed wiring board according to claim 1, wherein the concavo-convex portion comprises a vertical groove and / or a horizontal groove. プリント配線基板のパッドその他の半田付けをする部分を除いてソルダーレジストを塗布する方法において、
予め塗布されたソルダーレジストの表面に凹凸部を形成する工程と、
この凹凸部を形成した下層のソルダーレジストの表面に重ねてソルダーレジストを塗布する工程と
からなることを特徴とするプリント配線基板におけるソルダーレジストの形成方法。 In the method of applying the solder resist except for the parts to be soldered, such as pads on the printed circuit board,
Forming a concavo-convex portion on the surface of a solder resist applied in advance;
A method of forming a solder resist on a printed wiring board, comprising: applying a solder resist on the surface of a lower layer solder resist on which the uneven portion is formed. プリント配線基板のパッドその他の半田付けをする部分を除いてソルダーレジストを塗布する方法において、
隣接する前記パッド間の隙間部分に塗布されたソルダーレジストの表面に凹凸部を形成する工程と、
この凹凸部を形成したソルダーレジストの表面に重ねてソルダーレジストを塗布する工程と
からなることを特徴とするプリント配線基板におけるソルダーレジストの形成方法。 In the method of applying the solder resist except for the parts to be soldered, such as pads on the printed circuit board,
Forming a concavo-convex portion on the surface of a solder resist applied to a gap portion between adjacent pads;
A method of forming a solder resist on a printed wiring board, comprising: applying a solder resist on the surface of the solder resist on which the uneven portions are formed. プリント配線基板のパッドその他の半田付けをする部分を除いてソルダーレジストを塗布する方法において、
隣接する前記パッド間の隙間部分に塗布されたソルダーレジストの表面に凹凸部を形成する工程と、
この凹凸部を形成した下層のソルダーレジストの表面に重ねてソルダーレジストを塗布する工程と、
この凹凸部の形成と塗布とを繰り返してソルダーレジストを少なくとも３層としたことを特徴とするプリント配線基板におけるソルダーレジストの形成方法。 In the method of applying the solder resist except for the parts to be soldered, such as pads on the printed circuit board,
Forming a concavo-convex portion on the surface of a solder resist applied to a gap portion between adjacent pads;
A step of applying a solder resist on the surface of the solder resist of the lower layer on which the uneven portion is formed;
A method for forming a solder resist on a printed wiring board, wherein the formation and application of the concavo-convex portion is repeated to form at least three layers of solder resist.
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JP2015226050A (en) * 2014-05-27 2015-12-14 サムソン エレクトロ−メカニックス カンパニーリミテッド． Method for manufacturing printed circuit board

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JPH038390A (en) * 1989-06-06 1991-01-16 Ibiden Co Ltd Manufacture of substrate for mounting electronic component
JPH0575240A (en) * 1991-09-12 1993-03-26 Matsushita Electric Ind Co Ltd Manufacture of printed wiring board
JPH08291231A (en) * 1996-05-01 1996-11-05 Ibiden Co Ltd Photosensitive resin insulation material
JPH10163608A (en) * 1996-11-29 1998-06-19 Nec Corp Printed wiring board and its manufacture

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
JPH038390A (en) * 1989-06-06 1991-01-16 Ibiden Co Ltd Manufacture of substrate for mounting electronic component
JPH0575240A (en) * 1991-09-12 1993-03-26 Matsushita Electric Ind Co Ltd Manufacture of printed wiring board
JPH08291231A (en) * 1996-05-01 1996-11-05 Ibiden Co Ltd Photosensitive resin insulation material
JPH10163608A (en) * 1996-11-29 1998-06-19 Nec Corp Printed wiring board and its manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015226050A (en) * 2014-05-27 2015-12-14 サムソン エレクトロ−メカニックス カンパニーリミテッド． Method for manufacturing printed circuit board

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