JP2009503860A - 不連続蓄積素子を含む電子デバイスを形成するための方法 - Google Patents
不連続蓄積素子を含む電子デバイスを形成するための方法 Download PDFInfo
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Abstract
【選択図】図14
Description
52、53 ドープ領域
62 誘電体層
92、93 ゲート電極
112 ゲート誘電体部分
114、115 ゲート間誘電体部分
142、143、144、145 導電線
146 側壁スペーサ
Claims (20)
- 電子デバイスを形成するための方法であって、
壁部及び底部を含み且つ基板の主要面から延びる第1のトレンチを前記基板内に形成する段階と、
前記基板の主要面を覆い且つ前記第1のトレンチ内に不連続蓄積素子を形成する段階と、
前記不連続蓄積素子を形成した後で、前記第1のトレンチの壁部との間に前記不連続蓄積素子のうちの第1の不連続蓄積素子が位置するように前記第1のトレンチ内に第1のゲート電極を形成する段階と、
前記不連続蓄積素子の第1の部分が前記第1のトレンチ内に留まるように、前記基板の主要面の上に重なる前記不連続蓄積素子を除去する段階と、
前記不連続蓄積素子を除去した後に、前記第1のゲート電極及び前記基板の主要面の上に重なる第2のゲート電極を形成する段階と、
を含む方法。 - 前記第1のゲート電極を形成する段階が、前記第1のゲート電極の上面が前記基板の主要面の下に位置するように該第1のゲート電極を形成する段階を含み、
前記第2のゲート電極を形成する段階が、前記第2のゲート電極の一部分が前記第1のトレンチ内に延びるように該第2のゲート電極を形成する段階を含む、
ことを特徴とする請求項1に記載の方法。 - 第2のトレンチ内に第3のゲート電極を形成する段階を更に含み、
前記第1のトレンチを形成する段階が、該第1のトレンチから間隔を置いて配置された前記第2のトレンチを形成する段階を更に含み、該第2のトレンチは壁部及び底部を含み且つ前記基板の主要面から延びており、
前記不連続蓄積素子を形成する段階が、前記第2のトレンチ内で前記不連続蓄積素子を形成する段階を更に含み、
前記第3のゲート電極を形成する段階は、前記不連続蓄積素子のうちの第2の不連続蓄積素子が前記第3のゲート電極と前記第2のトレンチの壁部との間に位置するように該第3のゲート電極を形成する段階を含み、
前記不連続蓄積素子を除去する段階は、前記基板の主要面の上に重なる前記不連続蓄積素子を除去する段階を含み、該不連続蓄積素子の第2の部分は前記第2のトレンチ内に留まる、
ことを特徴とする請求項1に記載の方法。 - 前記第1及び第2のトレンチのそれぞれの前記底部に沿って第1のドープ領域及び第2のドープ領域を形成する段階を更に含む、
請求項3に記載の方法。 - 前記第1及び第2のトレンチ間の前記基板の主要面に沿って位置する第3のドープ領域を形成する段階を更に含む、
請求項4に記載の方法。 - 前記第2のゲート電極を形成する段階の前に、前記第3のドープ領域を形成する段階を実施する、
ことを特徴とする請求項5に記載の方法。 - 前記第2のゲート電極を形成した後に前記第3のドープ領域を形成する段階を実施する、
ことを特徴とする請求項5に記載の方法。 - 前記不連続蓄積素子を除去する段階は、
前記第1の不連続蓄積素子は第1の電荷蓄積領域の一部であり、前記第1のドープ領域よりも前記第1のゲート電極の上面により近接して位置しており、
前記第2の不連続蓄積素子は第2の電荷蓄積領域の一部であり、前記第2のドープ領域よりも前記第3のゲート電極の上面により近接して位置しており、該第2の電荷蓄積領域は前記第1の電荷蓄積領域から間隔を置いて配置される、
ように前記不連続蓄積素子を除去する段階を含む、
ことを特徴とする請求項3に記載の方法。 - 前記第2のゲート電極を形成する段階は、
前記第2のゲート電極が前記第1及び第3のゲート電極の上に重なり、
平面図において、前記第1及び第2のトレンチの長さが前記第2のゲート電極の長さに対して実質的に直角である、
ように前記第2のゲート電極を形成する段階を含む、
ことを特徴とする請求項3に記載の方法。 - 第4のゲート電極を形成する段階を更に含み、
前記第2のゲート電極を形成する段階は、該第2のゲート電極が前記第1のゲート電極の上に重なるように該第2のゲート電極を形成する段階を含み、
前記第4のゲート電極を形成する段階は、該第4のゲート電極が前記第3のゲート電極の上に重なるように該第4のゲート電極を形成する段階を含み、
平面図において、
前記第1のトレンチの長さは前記第2のゲート電極の長さに対して実質的に平行であり、
前記第2のトレンチの長さが前記第4のゲート電極の長さに対して実質的に平行である、
ことを特徴とする請求項3に記載の方法。 - 前記第1のトレンチの壁部及び底部に沿って位置する第1の誘電体層を形成する段階と、
前記不連続蓄積素子を形成した後に第2の誘電体層を形成する段階と、
前記第1のゲート電極を形成した後に第3の誘電体層を形成する段階と、
を更に含む、
請求項1に記載の方法。 - 前記第3の誘電体層を形成する段階及び前記基板の主要面の上に重なる前記不連続蓄積素子を除去する段階は、
前記第1のゲート電極の露出部分と、
前記第1のゲート電極と前記基板の主要面との間の高さ位置に位置する前記不連続蓄積素子と、
を酸化する段階を含む、
ことを特徴とする請求項11に記載の方法。 - 前記第1のゲート電極を形成する段階は、
前記不連続蓄積素子を形成した後に導電層を形成する段階と、
前記導電層を研磨して前記基板の主要面の上に重なる前記導電層の除去部分にする段階と、
前記第1のトレンチ内の前記導電層を陥凹部に配置して、前記第1のゲート電極の上面が前記主要面の下に位置するように該第1のゲート電極を形成する段階と、
を含む、
ことを特徴とする請求項1に記載の方法。 - 前記第1のゲート電極を形成する段階は、
前記不連続蓄積素子を形成した後に導電層を形成する段階と、
前記導電層を異方性エッチングして、断面図において側壁スペーサ形状を有する前記第1のゲート電極を形成する段階と、
を含む、
ことを特徴とする請求項1に記載の方法。 - 前記不連続蓄積素子を形成する段階は、シリコンナノ結晶を形成する段階、又は金属ナノクラスターを形成する段階を含む、
ことを特徴とする請求項1に記載の方法。 - 電子デバイスを形成するための方法であって、
互いに間隔を置いて配置され、各々が壁部及び底部を含み且つ基板の主要面から延びる第1のトレンチ及び第2のトレンチを前記基板内で形成する段階と、
前記基板の主要面を覆い且つ前記第1及び第2のトレンチ内に不連続蓄積素子を形成する段階と、
前記不連続蓄積素子を形成した後に第1の導電層を形成する段階と、
前記基板の主要面の上に重なる前記第1の導電層の一部分を除去して、前記第1のトレンチ内に第1のゲート電極を形成し前記第2のトレンチ内に第2のゲート電極を形成する段階と、
を含み、
前記不連続蓄積素子の第1の部分が前記第1のゲート電極と前記第1のトレンチの壁部との間に位置し、
前記不連続蓄積素子の第2の部分が前記第2のゲート電極と前記第2のトレンチの壁部との間に位置しており、
前記方法が更に、
前記基板の主要面の上に重なる前記不連続蓄積素子を除去する段階と、
前記基板の主要面の上に重なる前記不連続蓄積素子を除去した後に第2の導電層を形成する段階と、
前記第2の導電層をパターン化して、前記基板の主要面並びに前記第1のゲート電極又は前記第2のゲート電極のうちの少なくとも1つの上に重なる第3のゲート電極を形成する段階と、
を含む方法。 - 前記第1及び第2のトレンチのそれぞれの底部に沿って第1のドープ領域及び第2のドープ領域を形成する段階を更に含む、
請求項16に記載の方法。 - 前記第1及び第2のトレンチ間の前記基板の主要面に沿って位置する第3のドープ領域を形成する段階を更に含む、
請求項17に記載の方法。 - 前記第1の導電層の一部分を除去する段階は、前記第1及び第2のトレンチ内で前記第1の導電層を陥凹部に配置させ、前記第1及び第2のゲート電極の上面が前記主要面の下に位置するように該第1及び第2のゲート電極を形成する段階を含む、
ことを特徴とする請求項16に記載の方法。 - 電子デバイスを形成するための方法であって、
互いに間隔を置いて配置され、各々が壁部及び底部を含み且つ基板の主要面から延びる第1のトレンチ及び第2のトレンチを前記基板内で形成する段階と、
前記基板内で前記第1のトレンチの底部に沿って位置する第1のドープ領域と、前記基板内で前記第2のトレンチの底部に沿って位置する第2のドープ領域とを形成する段階と、
前記第1及び第2のトレンチの壁部及び底部に沿って位置する第1の誘電体層を形成する段階と、
前記第1の誘電体層を形成した後に不連続蓄積素子を形成する段階と、
前記不連続蓄積素子を形成した後に第2の誘電体層を形成する段階と、
前記第2の誘電体層を形成した後に第1の導電層を形成する段階と、
前記第1の導電層をパターン化して、前記基板の主要面の下に位置する上面を有し且つ前記第1のトレンチの壁部との間に前記不連続蓄積素子の第1の部分が位置するように前記第1のトレンチ内に第1のゲート電極を形成し、前記基板の主要面の下に位置する上面を有し且つ前記第2のトレンチの壁部との間に前記不連続蓄積素子の第2の部分が位置するように前記第2のトレンチ内に第2のゲート電極を形成する段階と、
前記不連続蓄積素子の第3の部分を除去して、前記不連続蓄積素子の第1の部分と前記不連続蓄積素子の第2の部分とを含む前記不連続蓄積素子の残りの部分を残し、前記不連続蓄積素子の第1の部分が前記第1のトレンチ内に位置し、前記不連続蓄積素子の第2の部分が前記第2のトレンチ内に位置し、前記不連続蓄積素子の前記第1及び第2の部分が前記基板の主要面から間隔を置いて配置され、前記第1及び第2のトレンチ間の基板の主要面の上には、前記不連続蓄積素子が実質的に重ならないようにする段階と、
前記第1のトレンチ内の第1のゲート電極に重なる第1の部分と、前記第2のトレンチ内の第2のゲート電極に重なる第2の部分とを有する第3の誘電体層を形成する段階と、
前記第3の誘電体層を形成した後に第2の導電層を形成する段階と、
前記第2の導電層をパターン化して、前記第3の誘電体層の上に重なり且つ前記第1のトレンチ及び前記第2のトレンチ内に少なくとも部分的に位置する第3のゲート電極を形成する段階と、
を含む方法。
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