JP2009302180A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2009302180A
JP2009302180A JP2008152798A JP2008152798A JP2009302180A JP 2009302180 A JP2009302180 A JP 2009302180A JP 2008152798 A JP2008152798 A JP 2008152798A JP 2008152798 A JP2008152798 A JP 2008152798A JP 2009302180 A JP2009302180 A JP 2009302180A
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Prior art keywords
signal line
bonding
wires
bonding wires
signal
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Japanese (ja)
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Kunio Ota
邦夫 太田
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Toshiba Corp
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Toshiba Corp
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Priority to JP2008152798A priority Critical patent/JP2009302180A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing the degradation of wiring density without increasing the intervals of bonding wires, and reducing crosstalk noises caused between bonding wires. <P>SOLUTION: The semiconductor device is constituted by alternately arraying normal bonding wires having ball bonding portions 21B, 23B, and 25B connecting a first end of a signal line bonding wire to an integrated circuit chip and wedge bonding portions 21C, 23C, and 25C connecting a second end of the signal line bonding wire to signal wiring, and reverse bonding wires having ball bonding portions 22B, 24B, and 26B connecting the first end of the signal line bonding wire to the signal wiring and wedge bonding portions 22C, 24C, and 26C connecting the second end of the signal line bonding wire to the integrated circuit chip. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体装置に関し、特にＩＣ（集積回路）チップとＩＣパッケージのインターポーザ基板の信号線トレースを電気的に接続する複数のボンディングワイヤを有する半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a plurality of bonding wires for electrically connecting an IC (integrated circuit) chip and a signal line trace of an interposer substrate of an IC package.

図７と図８は、従来のボンディングワイヤを有するＩＣパッケージの概略図を示している。図７は、ＩＣパッケージのボンディングワイヤの状態を示す断面図であり、図８は、ＩＣパッケージのボンディングワイヤの状態を示す平面図である。図７と図８では、それぞれ一部Ｂを代表して拡大して示している。   7 and 8 show schematic views of an IC package having a conventional bonding wire. FIG. 7 is a cross-sectional view showing the state of bonding wires of the IC package, and FIG. 8 is a plan view showing the state of bonding wires of the IC package. In FIGS. 7 and 8, a part B is shown on an enlarged scale.

ＩＣチップ１０１がパッケージのインターポーザ基板１００の中央にマウントされている。プレーン状のＧＮＤ（グランド）パッド１０２が、ＩＣチップ１０１の下部とその周辺に配置されている。プレーン状の各種の電源パッド１０３がＧＮＤパッド１０２の外周囲に配置され、さらに電源パッド１０３の外周囲には信号線トレース１０７が配置されている。   The IC chip 101 is mounted at the center of the interposer substrate 100 of the package. A plain GND (ground) pad 102 is disposed on the lower part of the IC chip 101 and on the periphery thereof. Various plain power supply pads 103 are arranged around the outer periphery of the GND pad 102, and a signal line trace 107 is arranged around the outer periphery of the power supply pad 103.

図７の一部Ｂと図８の一部Ｂに示すように、信号線ボンディングワイヤ１０６は、ＩＣチップ１０１の端子と信号線トレース１０７を接続し、電源ボンディングワイヤ１１１は、ＩＣチップ１０１の端子と電源パッド１０３をそれぞれ接続している。ＧＮＤボンディングワイヤ１１２は、ＩＣチップ１０１のＧＮＤ端子とＧＮＤパッド１０２と接続している。   As shown in part B of FIG. 7 and part B of FIG. 8, the signal line bonding wire 106 connects the terminal of the IC chip 101 and the signal line trace 107, and the power supply bonding wire 111 is the terminal of the IC chip 101. And the power supply pad 103 are connected to each other. The GND bonding wire 112 is connected to the GND terminal of the IC chip 101 and the GND pad 102.

このような構造を有するＩＣパッケージでは、信号線ボンディングワイヤ１０６は電流の往路であり、ＧＮＤボンディングワイヤ１１２あるいは電源ボンディングワイヤ１１１は電流の帰路すなわちリターンパスである。信号線ボンディングワイヤ１０６とＧＮＤボンディングワイヤ１１２あるいは電源ボンディングワイヤ１１１が、相互に離れて配置されているが、相互に並走して配列されている距離は小さく、隣接の信号線ボンディングワイヤ１０６間の間隔は比較的狭い。   In the IC package having such a structure, the signal line bonding wire 106 is a current outgoing path, and the GND bonding wire 112 or the power source bonding wire 111 is a current return path, that is, a return path. The signal line bonding wire 106 and the GND bonding wire 112 or the power supply bonding wire 111 are arranged apart from each other, but the distance in which the signal line bonding wire 106 and the power supply bonding wire 111 are arranged in parallel with each other is small. The interval is relatively narrow.

高周波回路においては、電流の往路と電流の帰路の間に、電磁界が閉じこめられて信号伝送されるために、上述したように電流の往路と電流の帰路が離れていると電磁界の広がりが大きくなり、隣接する信号線に発生するクロストークノイズ、いわゆる電磁干渉現象が大きくなる。   In a high-frequency circuit, since the electromagnetic field is confined between the current forward path and the current return path, signal transmission is performed. Therefore, if the current forward path and the current return path are separated as described above, the electromagnetic field spreads. The crosstalk noise generated in adjacent signal lines, that is, so-called electromagnetic interference phenomenon increases.

また、隣接する信号線ボンディングワイヤ１０６同士は比較的並走距離が長いが、隣接する信号線ボンディングワイヤ同士の並走距離が長いほど、クロストークノイズが大きくなる。   Further, the adjacent signal line bonding wires 106 have a relatively long parallel running distance, but the crosstalk noise increases as the parallel running distance between the adjacent signal line bonding wires 106 increases.

このような半導体装置の関連技術は、特許文献１に開示されている。特許文献１では、複数の半導体チップが基台の上に積層されており、各半導体装置（半導体チップ）の配線パターンがお互いに平行にならないように複数の半導体チップを積層することで、各半導体装置のパターン配線間に生じる誘導結合を小さくしている。
特開２００６−７３６２５号公報 A related technology of such a semiconductor device is disclosed in Patent Document 1. In Patent Document 1, a plurality of semiconductor chips are stacked on a base, and a plurality of semiconductor chips are stacked so that wiring patterns of each semiconductor device (semiconductor chip) are not parallel to each other. Inductive coupling generated between the pattern wirings of the device is reduced.
JP 2006-73625 A

ところで、信号線ボンディングワイヤにおけるクロストークノイズが大きい場合の対策として、例えば信号線ボンディングワイヤの間隔を離すことが挙げられる。しかし、この場合には、配線密度が低下するので、ＩＣパッケージのサイズが大きくなり半導体装置の大型化が避けられない。   By the way, as a countermeasure when the crosstalk noise in the signal line bonding wire is large, for example, the interval between the signal line bonding wires is increased. However, in this case, since the wiring density is lowered, the size of the IC package is increased, and the enlargement of the semiconductor device is inevitable.

また、特許文献１に開示されている技術は、複数の半導体装置（半導体チップ）が積層されることで、各半導体装置のパターン配線間に生じる誘導結合が小さくしているだけであり、単一の半導体装置内において隣接する信号線ボンディングワイヤが平行であることにより生じるクロストークを解消するものではない。   In addition, the technique disclosed in Patent Document 1 merely reduces inductive coupling generated between the pattern wirings of each semiconductor device by stacking a plurality of semiconductor devices (semiconductor chips). This does not eliminate crosstalk that occurs when adjacent signal line bonding wires are parallel in the semiconductor device.

そこで、本発明は上記課題を解決するためになされたものであり、本発明の目的は、ボンディングワイヤの間隔を離すことなく配線密度の低下を防ぎ、ボンディングワイヤのボンディング順序を変更するだけでボンディングワイヤ間に生じるクロストークノイズを減少することができる半導体装置を提供することである。   Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to prevent a decrease in wiring density without leaving the bonding wires apart and to perform bonding only by changing the bonding order of the bonding wires. It is an object of the present invention to provide a semiconductor device capable of reducing crosstalk noise generated between wires.

本発明の半導体装置は、集積回路チップと、複数の信号配線を有する基板と、前記集積回路チップと前記信号配線とを電気的に接続する複数本のボンディングワイヤと、を備え、前記ボンディングワイヤは、第１端部を前記集積回路チップに接続するボールボンディング部と、第２端部を前記信号配線に接続するウェッジボンディング部とを有する正ボンディングワイヤと、第１端部を前記信号配線に接続するボールボンディング部と、第２端部を前記集積回路チップに接続するウェッジボンディング部とを有する逆ボンディングワイヤと、を有し、前記正ボンディングワイヤと前記逆ボンディングワイヤとを交互に隣接して並置したことを特徴とする。   A semiconductor device of the present invention includes an integrated circuit chip, a substrate having a plurality of signal wirings, and a plurality of bonding wires that electrically connect the integrated circuit chip and the signal wirings. A positive bonding wire having a ball bonding portion connecting the first end to the integrated circuit chip and a wedge bonding portion connecting the second end to the signal wiring; and connecting the first end to the signal wiring. And a reverse bonding wire having a wedge bonding portion connecting a second end portion to the integrated circuit chip, and the normal bonding wire and the reverse bonding wire are alternately arranged adjacent to each other. It is characterized by that.

本発明によれば、ボンディングワイヤの間隔を離すことなく配線密度の低下を防ぎ、ボンディングワイヤのボンディング順序を変更するだけでボンディングワイヤ間に生じるクロストークノイズを減少することができる半導体装置を提供することができる。   According to the present invention, there is provided a semiconductor device capable of preventing a decrease in wiring density without separating bonding wires and reducing crosstalk noise generated between bonding wires only by changing the bonding order of the bonding wires. be able to.

以下、本発明の実施の形態について図面を参照して詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

（第１実施形態）
図１は、本発明の半導体装置の好ましい第１実施形態を示している。図１は、半導体装置の一部を拡大して示している。図１（Ａ）は、半導体装置の一部を示す平面図であり、図１（Ｂ）は、図１（Ａ）の半導体装置の一部を示す断面図である。 (First embodiment)
FIG. 1 shows a first preferred embodiment of the semiconductor device of the present invention. FIG. 1 shows an enlarged part of a semiconductor device. FIG. 1A is a plan view illustrating a part of the semiconductor device, and FIG. 1B is a cross-sectional view illustrating a part of the semiconductor device in FIG.

図１（Ａ）と図１（Ｂ）に示すように、ＩＣチップ（集積回路チップ）１が、ＩＣパッケージ３０のパッケージのインターポーザ基板９５の中央にマウントされている。インターポーザ基板９５は、グランドパターン部としてのプレーン状のＧＮＤパッド２と、電源導体部としてのプレーン状の電源パッド３と、複数本の信号線トレース７を有している。信号線トレース７は信号配線の一例である。   As shown in FIGS. 1A and 1B, an IC chip (integrated circuit chip) 1 is mounted at the center of an interposer substrate 95 of the package of the IC package 30. The interposer substrate 95 has a plain GND pad 2 as a ground pattern portion, a plain power pad 3 as a power conductor portion, and a plurality of signal line traces 7. The signal line trace 7 is an example of signal wiring.

ＧＮＤパッド２は、ＩＣチップ１の下部とその周辺に配置され、ＩＣチップ１を保持している。電源パッド３はＧＮＤパッド２の外周囲に配置され、さらに複数本の信号線トレース７は電源パッド３の外周囲に配置されている。図１（Ａ）では、一例として６本の複数本の信号線トレース７は互いに間隔をおいて平行に配列されている。図１（Ｂ）に示すように、信号線トレース７とＧＮＤプレーン１３は、インターポーザ基板９５の誘電体１４に配置されている。   The GND pad 2 is disposed below and around the IC chip 1 and holds the IC chip 1. The power supply pad 3 is disposed on the outer periphery of the GND pad 2, and a plurality of signal line traces 7 are disposed on the outer periphery of the power supply pad 3. In FIG. 1A, as an example, six signal line traces 7 are arranged in parallel at intervals. As shown in FIG. 1B, the signal line trace 7 and the GND plane 13 are disposed on the dielectric 14 of the interposer substrate 95.

図１（Ａ）と図１（Ｂ）に示すように、複数本の電源ワイヤ１１は、ＩＣチップ１の端子と電源パッド３を接続している。複数本のＧＮＤワイヤ１２は、ＩＣチップ１のＧＮＤ端子とＧＮＤパッド２を接続している。電源ワイヤ１１は電源ボンディングワイヤともいい、ＧＮＤワイヤ１２はＧＮＤボンディングワイヤともいう。   As shown in FIGS. 1A and 1B, the plurality of power wires 11 connect the terminals of the IC chip 1 and the power pads 3. The plurality of GND wires 12 connect the GND terminal of the IC chip 1 and the GND pad 2. The power supply wire 11 is also called a power supply bonding wire, and the GND wire 12 is also called a GND bonding wire.

図１（Ａ）に示すように、信号線ボンディングワイヤ２１，２２，２３，２４，２５，２６は、それぞれＩＣチップ１の端子と各信号線トレース７を接続している。信号線ボンディングワイヤ２１，２２，２３，２４，２５，２６は、間隔をおいて配列されている。図１（Ａ）と図１（Ｂ）に示す第１実施形態の信号線トレース７の配線形式は、１つの信号情報を各信号線トレース７により伝えるシングルエンド配線の例である。各信号線トレース７は、それぞれ信号線ボンディングワイヤ２１，２２，２３，２４，２５，２６を介してＩＣチップ１の端子に接続されている。   As shown in FIG. 1A, the signal line bonding wires 21, 22, 23, 24, 25, and 26 connect the terminals of the IC chip 1 and the signal line traces 7 respectively. The signal line bonding wires 21, 22, 23, 24, 25, and 26 are arranged at intervals. The wiring form of the signal line trace 7 of the first embodiment shown in FIGS. 1A and 1B is an example of single-ended wiring that transmits one signal information by each signal line trace 7. Each signal line trace 7 is connected to a terminal of the IC chip 1 through signal line bonding wires 21, 22, 23, 24, 25, and 26, respectively.

図２は、図１に示す第１実施形態を拡大して示す斜視図である。   FIG. 2 is an enlarged perspective view showing the first embodiment shown in FIG.

図１（Ａ）と図１（Ｂ）と図２では、信号線ボンディングワイヤ２１，２２，２３，２４，２５，２６の内の３本の信号線ボンディングワイヤ２１，２３，２５のワイヤのループ形状と、３本の信号線ボンディングワイヤ２２，２４，２６のワイヤループ形状が異なっているので、区別して見易くするために、３本の信号線ボンディングワイヤ２１，２３，２５は実線で示し、３本の信号線ボンディングワイヤ２２，２４，２６は破線で示している。
図１と図２の実線で示す３本の信号線ボンディングワイヤ２１，２３，２５は、正ボンディング接続部で接続されており、図１と図２の破線で示す３本の信号線ボンディングワイヤ２２，２４，２６は、逆ボンディング接続部で接続されている。 In FIG. 1A, FIG. 1B, and FIG. 2, a loop of three signal line bonding wires 21, 23, 25 of the signal line bonding wires 21, 22, 23, 24, 25, 26. Since the shape and the wire loop shape of the three signal line bonding wires 22, 24, 26 are different, the three signal line bonding wires 21, 23, 25 are shown by solid lines for easy distinction and viewing. The signal wire bonding wires 22, 24, and 26 are indicated by broken lines.
The three signal line bonding wires 21, 23, 25 shown by solid lines in FIG. 1 and FIG. 2 are connected at the positive bonding connection portion, and the three signal line bonding wires 22 shown by broken lines in FIG. 1 and FIG. , 24 and 26 are connected by a reverse bonding connection portion.

ここで、正ボンディングワイヤとは、信号線ボンディングワイヤ２１，２３，２５のＩＣチップ１の端子側の第１端部２１Ｂ，２３Ｂ，２５Ｂを、ＩＣチップ１の端子に対してファーストボンディング接続（第１ボンディング接続、先のボンディング接続とも言う。）して、そして信号線ボンディングワイヤ２１，２３，２５の信号線トレース７側の第２端部２１Ｃ，２３Ｃ，２５Ｃを、信号線トレース７に対してセカンドボンディング接続（第２ボンディング接続、後のボンディング接続とも言う。）をする部分である。   Here, the positive bonding wire means that the first end portions 21B, 23B, 25B on the terminal side of the IC chip 1 of the signal line bonding wires 21, 23, 25 are first bonded to the terminals of the IC chip 1 (first bonding). 1 bonding connection, also referred to as the previous bonding connection), and the second end portions 21C, 23C, 25C of the signal line bonding wires 21, 23, 25 on the signal line trace 7 side are connected to the signal line trace 7. This is a portion for making a second bonding connection (also referred to as a second bonding connection or a subsequent bonding connection).

また、逆ボンディングワイヤとは、信号線ボンディングワイヤ２２，２４，２６の信号線トレース７側の第１端部２２Ｂ，２４Ｂ，２６Ｂを、信号線トレース７に対してファーストボンディング接続（第１ボンディング接続、先のボンディング接続とも言う。）をすることであり、そして信号線ボンディングワイヤ２２，２４，２６のＩＣチップ１の端子側の第２端部２２Ｃ，２４Ｃ，２６Ｃを、ＩＣチップ１の端子に対してセカンドボンディング接続（第２ボンディング接続、後のボンディング接続とも言う。）をする部分である。   The reverse bonding wire is a first bonding connection (first bonding connection) of the first end portions 22B, 24B, and 26B of the signal line bonding wires 22, 24, and 26 on the signal line trace 7 side to the signal line trace 7. The second end portions 22C, 24C, 26C on the terminal side of the IC chip 1 of the signal line bonding wires 22, 24, 26 are used as terminals of the IC chip 1. The second bonding connection (also referred to as a second bonding connection or a subsequent bonding connection) is performed.

図２と図１に例示するように、信号線ボンディングワイヤ２１，２３，２５の第１端部２１Ｂ，２３Ｂ，２５Ｂと、信号線ボンディングワイヤ２２，２４，２６の第１端部２２Ｂ，２４Ｂ，２６Ｂは、それぞれボールボンディング部８０で接続されている。   As illustrated in FIGS. 2 and 1, the first ends 21B, 23B, 25B of the signal line bonding wires 21, 23, 25 and the first ends 22B, 24B of the signal line bonding wires 22, 24, 26, 26B is connected by the ball bonding part 80, respectively.

また、図１と図２に例示するように、信号線ボンディングワイヤ２１，２３，２５の第１端部２１Ｃ，２３Ｃ，２５Ｃと、信号線ボンディングワイヤ２２，２４，２６の第１端部２２Ｃ，２４Ｃ，２６Ｃは、ウェッジボンディング部９０で接続されている。   1 and 2, the first end portions 21C, 23C, 25C of the signal line bonding wires 21, 23, 25 and the first end portions 22C of the signal line bonding wires 22, 24, 26, 24C and 26C are connected by a wedge bonding unit 90.

従って、図１と図２に示すように、信号線ボンディングワイヤ２１，２２，２３，２４，２５，２６は、隣接するワイヤのボンディング方向を交互に逆にしている。すわなち、隣接する信号線ボンディングワイヤ２１，２２，２３，２４，２５，２６は、正ボンディングワイヤと逆ボンディングワイヤが交互になるように配列されている。   Therefore, as shown in FIGS. 1 and 2, the signal line bonding wires 21, 22, 23, 24, 25, and 26 alternately reverse the bonding directions of adjacent wires. That is, the adjacent signal line bonding wires 21, 22, 23, 24, 25, and 26 are arranged so that the normal bonding wires and the reverse bonding wires are alternately arranged.

これにより、隣接する信号線ボンディングワイヤ２１，２２，２３，２４，２５，２６は、交互に正ボンディングワイヤと逆ボンディングワイヤにしているので、ワイヤの軌跡が異なり平行ではない。このため、隣接する信号線ボンディングワイヤ２１，２２，２３，２４，２５，２６の信号線同士の誘導性結合が弱く相互インダクタンスが小さくなり、隣接する信号線ボンディングワイヤ２１，２２，２３，２４，２５，２６間のクロストークを低減することができる。信号線ボンディングワイヤの間隔を離すことなく配線密度の低下を防ぎ、信号線ボンディングワイヤのボンディング順序を変更するだけで信号線ボンディングワイヤ間に生じるクロストークノイズを減少することができる。   As a result, the adjacent signal line bonding wires 21, 22, 23, 24, 25, and 26 are alternately made into a normal bonding wire and a reverse bonding wire, so that the wire trajectories are different and are not parallel. Therefore, the inductive coupling between the signal lines of the adjacent signal line bonding wires 21, 22, 23, 24, 25, and 26 is weak and the mutual inductance is reduced, and the adjacent signal line bonding wires 21, 22, 23, 24, Crosstalk between 25 and 26 can be reduced. It is possible to prevent a decrease in wiring density without separating the signal line bonding wires, and to reduce crosstalk noise generated between the signal line bonding wires only by changing the bonding order of the signal line bonding wires.

なお、このような構造を有するＩＣパッケージ３０では、信号線ボンディングワイヤ２１，２２，２３，２４，２５，２６は電流の往路であり、複数本のＧＮＤワイヤ１２あるいは複数本の電源ワイヤ１１は電流の帰路すなわちリターンパスである。複数本のＧＮＤワイヤ１２あるいは複数本の電源ワイヤ１１は、誘導性結合を強くするために全て正ボンディングである。   In the IC package 30 having such a structure, the signal line bonding wires 21, 22, 23, 24, 25, and 26 are forward current paths, and the plurality of GND wires 12 or the plurality of power supply wires 11 are current paths. This is the return path, that is, the return path. The plurality of GND wires 12 or the plurality of power supply wires 11 are all positively bonded to strengthen inductive coupling.

（第２の実施の形態）
図３は、本発明の半導体装置の好ましい第２実施形態を示している。図３は、半導体装置の一部を拡大して示している。図３（Ａ）は、半導体装置の一部を示す平面図であり、図３（Ｂ）は、図３（Ａ）の半導体装置の一部を示す断面図である。尚、本発明の半導体装置の第２実施形態では、図１に示す本発明の半導体装置の第１実施形態と同様の箇所には同じ符号を付ける。 (Second Embodiment)
FIG. 3 shows a second preferred embodiment of the semiconductor device of the present invention. FIG. 3 shows an enlarged part of the semiconductor device. FIG. 3A is a plan view illustrating a part of the semiconductor device, and FIG. 3B is a cross-sectional view illustrating a part of the semiconductor device in FIG. In the second embodiment of the semiconductor device of the present invention, the same reference numerals are given to the same portions as those of the first embodiment of the semiconductor device of the present invention shown in FIG.

図３（Ａ）と図３（Ｂ）に示すように、ＩＣチップ（集積回路チップ）１が、ＩＣパッケージ３０Ｂのパッケージのインターポーザ基板９５Ｂの中央にマウントされている。インターポーザ基板９５Ｂは、グランドパターン部としてのプレーン状のＧＮＤパッド２と、電源導体部としてのプレーン状の電源パッド３と、複数本の信号線トレース７を有している。   As shown in FIGS. 3A and 3B, the IC chip (integrated circuit chip) 1 is mounted at the center of the interposer substrate 95B of the package of the IC package 30B. The interposer substrate 95 </ b> B has a plain GND pad 2 as a ground pattern portion, a plain power pad 3 as a power conductor portion, and a plurality of signal line traces 7.

図３（Ａ）と図３（Ｂ）に示すように、複数本の電源ワイヤ１１は、ＩＣチップ１の端子と電源パッド３を接続している。複数本のＧＮＤワイヤ１２は、ＩＣチップ１のＧＮＤ端子とＧＮＤパッド２を接続している。電源ワイヤ１１は電源ボンディングワイヤともいい、ＧＮＤワイヤ１２はＧＮＤボンディングワイヤともいう。   As shown in FIGS. 3A and 3B, the plurality of power wires 11 connect the terminals of the IC chip 1 to the power pads 3. The plurality of GND wires 12 connect the GND terminal of the IC chip 1 and the GND pad 2. The power supply wire 11 is also called a power supply bonding wire, and the GND wire 12 is also called a GND bonding wire.

図３（Ａ）に示すように、信号線ボンディングワイヤ３１，３２，３３，３４，３５，３６は、それぞれＩＣチップ１の端子と各信号線トレース７を接続している。信号線ボンディングワイヤ３１，３２，３３，３４，３５，３６は、間隔をおいて配列されている。 図３（Ａ）と図３（Ｂ）に示す第２実施形態の配線形式は、１つの信号情報を各差動ペア７Ｐ、７Ｒ、７Ｓの２本の信号線トレース７により伝える差動配線の例であり、３つの信号線トレース７の差動ペア７Ｐ、７Ｒ、７Ｓを有している。各信号線トレース７は、対応する信号線ボンディングワイヤ３１，３２，３３，３４，３５，３６を介してＩＣチップ１の端子に接続されている。   As shown in FIG. 3A, the signal line bonding wires 31, 32, 33, 34, 35, and 36 connect the terminals of the IC chip 1 and the signal line traces 7, respectively. The signal line bonding wires 31, 32, 33, 34, 35, and 36 are arranged at intervals. The wiring form of the second embodiment shown in FIG. 3A and FIG. 3B is a differential wiring that transmits one signal information by two signal line traces 7 of each differential pair 7P, 7R, 7S. It is an example and has a differential pair 7P, 7R, 7S of three signal line traces 7. Each signal line trace 7 is connected to a terminal of the IC chip 1 via a corresponding signal line bonding wire 31, 32, 33, 34, 35, 36.

図３（Ａ）と図３（Ｂ）に示すように、信号線ボンディングワイヤ３１，３２，３３，３４，３５，３６の内の４本の信号線ボンディングワイヤ３１，３２，３５，３６のワイヤのループ形状と、２本の信号線ボンディングワイヤ３３，３４のワイヤループ形状が異なっているので、区別して見易くするために、４本の信号線ボンディングワイヤ３１，３２，３５，３６は実線で示し、２本の信号線ボンディングワイヤ３３，３４は破線で示している。   As shown in FIGS. 3A and 3B, four of the signal line bonding wires 31, 32, 33, 34, 35, and 36 are the wires of the four signal line bonding wires 31, 32, 35, and 36. Since the loop shape of the two and the wire loop shapes of the two signal line bonding wires 33 and 34 are different, the four signal line bonding wires 31, 32, 35 and 36 are indicated by solid lines for the sake of distinction and easy understanding. The two signal line bonding wires 33 and 34 are indicated by broken lines.

ＧＮＤパッド２は、ＩＣチップ１の下部とその周辺に配置され、ＩＣチップ１を保持している。電源パッド３はＧＮＤパッド２の外周囲に配置され、さらに複数本の信号線トレース７は電源パッド３の外周囲に配置されている。隣接する２本の信号線トレース７は、互いに間隔をおいて平行に配列されている。ただし、２本の信号線トレース７の差動ペア７Ｐは、隣の２本の信号線トレース７の差動ペア７Ｒ、７Ｓとは、さらに間隔をおいて形成されている。図３（Ｂ）に示すように、信号線トレース７とＧＮＤプレーン１３とは、インターポーザ基板９５Ｂの誘電体１４に配置されている。   The GND pad 2 is disposed below and around the IC chip 1 and holds the IC chip 1. The power supply pad 3 is disposed on the outer periphery of the GND pad 2, and a plurality of signal line traces 7 are disposed on the outer periphery of the power supply pad 3. Two adjacent signal line traces 7 are arranged in parallel with an interval between each other. However, the differential pair 7P of the two signal line traces 7 is formed further apart from the differential pair 7R, 7S of the two adjacent signal line traces 7. As shown in FIG. 3B, the signal line trace 7 and the GND plane 13 are disposed on the dielectric 14 of the interposer substrate 95B.

図３において実線で示す信号線ボンディングワイヤ３１，３２，３５，３６は、正ボンディングワイヤであり、図３において破線で示す信号線ボンディングワイヤ３３，３４は、逆ボンディングワイヤである。   The signal line bonding wires 31, 32, 35, and 36 indicated by solid lines in FIG. 3 are normal bonding wires, and the signal line bonding wires 33 and 34 indicated by broken lines in FIG. 3 are reverse bonding wires.

ここで、正ボンディングワイヤとは、信号線ボンディングワイヤ３１，３２，３５，３６のＩＣチップ１の端子側の第１端部３１Ｂ，３２Ｂ，３５Ｂ，３６Ｂを、ＩＣチップ１の端子に対してファーストボンディング接続（第１ボンディング接続部、先のボンディング接続部とも言う。）して、そして信号線ボンディングワイヤ３１，３２，３５，３６の信号線トレース７側の第２端部３１Ｃ，３２Ｃ，３５Ｃ，３６Ｃを、信号線トレース７に対してセカンドボンディング接続（第３ボンディング接続部、後のボンディング接続部とも言う。）をする部分である。   Here, the positive bonding wire means that the first end portions 31B, 32B, 35B, and 36B on the terminal side of the IC chip 1 of the signal line bonding wires 31, 32, 35, and 36 are first with respect to the terminal of the IC chip 1. Bonding connection (first bonding connection portion, also referred to as the previous bonding connection portion), and second end portions 31C, 32C, 35C, of the signal line bonding wires 31, 32, 35, 36 on the signal line trace 7 side are performed. 36C is a portion for making a second bonding connection (also referred to as a third bonding connection portion or a subsequent bonding connection portion) to the signal line trace 7.

また、逆ボンディングワイヤとは、信号線ボンディングワイヤ３３，３４の信号線トレース７側の第１端部３３Ｂ，３４Ｂを、信号線トレース７に対してファーストボンディング接続（第１ボンディング接続部、先のボンディング接続部とも言う。）をすることであり、そして信号線ボンディングワイヤ３３，３４のＩＣチップ１の端子側の第２端部３３Ｃ，３４ＣをＩＣチップ１の端子に対して、セカンドボンディング接続（第２ボンディング接続部、後のボンディング接続部とも言う。）をする部分である。   The reverse bonding wire means that the first end portions 33B and 34B on the signal line trace 7 side of the signal line bonding wires 33 and 34 are fast-bonded to the signal line trace 7 (the first bonding connection portion, the previous bonding wire). The second end portions 33C and 34C on the terminal side of the IC chip 1 of the signal line bonding wires 33 and 34 are connected to the terminals of the IC chip 1 by the second bonding connection (also referred to as bonding connection portions). A second bonding connection portion, also referred to as a subsequent bonding connection portion).

信号線ボンディングワイヤ３１，３２，３５，３６の第１端部３１Ｂ，３２Ｂ，３５Ｂ，３６Ｂと、信号線ボンディングワイヤ３３，３４の第１端部３３Ｂ，３４Ｂは、ボールボンディング部で接続されている。また、信号線ボンディングワイヤ３１，３２，３５，３６の第２端部３１Ｃ，３２Ｃ，３５Ｃ，３６Ｃと、信号線ボンディングワイヤ３３，３４の第２端部３３Ｃ，３４Ｃは、ウェッジボンディング部で接続されている。   The first end portions 31B, 32B, 35B, 36B of the signal line bonding wires 31, 32, 35, 36 and the first end portions 33B, 34B of the signal line bonding wires 33, 34 are connected by a ball bonding portion. . The second end portions 31C, 32C, 35C, and 36C of the signal line bonding wires 31, 32, 35, and 36 and the second end portions 33C and 34C of the signal line bonding wires 33 and 34 are connected by a wedge bonding portion. ing.

従って、図３（Ａ）に示すように、信号線トレース７の各差動ペア７Ｐ、７Ｓに対応する信号線ボンディングワイヤ３１，３２，３５，３６と、隣接する信号線トレース７の各差動ペア７Ｒに対応する信号線ボンディングワイヤ３３，３４とは、ボンディング方向が逆になっている。すわなち、隣接する信号線トレース７の各差動ペア７Ｐ、７Ｒ、７Ｓの信号線ボンディングワイヤ３１，３２，３３，３４，３５，３６は、正ボンディングワイヤと逆ボンディングワイヤが交互にくるように配列されている。差動ペア７Ｐと差動ペア７Ｓは、ＩＣチップ１と信号線トレース７との間で正ボンディングワイヤにより接続された第１差動配線の一例であり、差動ペア７Ｒは、信号線トレース７とＩＣチップ１との間で逆ボンディングワイヤにより接続された第２差動配線の一例である。   Therefore, as shown in FIG. 3A, the signal line bonding wires 31, 32, 35, 36 corresponding to the differential pairs 7P, 7S of the signal line trace 7 and the differentials of the adjacent signal line trace 7 The bonding direction of the signal line bonding wires 33 and 34 corresponding to the pair 7R is reversed. That is, the signal line bonding wires 31, 32, 33, 34, 35, and 36 of the differential pairs 7P, 7R, and 7S of the adjacent signal line traces 7 are arranged so that the positive bonding wires and the reverse bonding wires are alternately arranged. Is arranged. The differential pair 7P and the differential pair 7S are an example of a first differential wiring connected by a positive bonding wire between the IC chip 1 and the signal line trace 7, and the differential pair 7R is the signal line trace 7 3 is an example of a second differential wiring connected between the IC chip 1 and the IC chip 1 by a reverse bonding wire.

これにより、隣接する信号線ボンディングワイヤ３１，３２同士、隣接する信号線ボンディングワイヤ３３，３４同士、そして隣接する信号線ボンディングワイヤ３５，３６同士は、それぞれ誘導性結合を強くできる。なお、この実施形態では、例えば信号線ボンディングワイヤ３１のリターンパスは信号線ボンディングワイヤ３２である。   Thereby, the adjacent signal line bonding wires 31 and 32, the adjacent signal line bonding wires 33 and 34, and the adjacent signal line bonding wires 35 and 36 can strengthen inductive coupling, respectively. In this embodiment, for example, the return path of the signal line bonding wire 31 is the signal line bonding wire 32.

しかし、隣接する信号線ボンディングワイヤ３１，３２の差動ペア７Ｐ、隣接する信号線ボンディングワイヤ３３，３４の差動ペア７Ｒ、そして隣接する信号線ボンディングワイヤ３５，３６の差動ペア７Ｓは、交互にワイヤの軌跡が異なり平行ではないので、誘導性同士の誘導性結合が弱くなり、クロストークを低減することができる。信号線ボンディングワイヤの間隔を離すことなく配線密度の低下を防ぎ、信号線ボンディングワイヤのボンディング順序を変更するだけで信号線ボンディングワイヤ間に生じるクロストークノイズを減少することができる。   However, the differential pair 7P of the adjacent signal line bonding wires 31 and 32, the differential pair 7R of the adjacent signal line bonding wires 33 and 34, and the differential pair 7S of the adjacent signal line bonding wires 35 and 36 are alternately arranged. Since the trajectories of the wires are different and not parallel, the inductive coupling between the inductives becomes weak and crosstalk can be reduced. It is possible to prevent a decrease in wiring density without separating the signal line bonding wires, and to reduce crosstalk noise generated between the signal line bonding wires only by changing the bonding order of the signal line bonding wires.

次に、図４〜図６を参照して、本発明の実施形態であるシングル配線を有する半導体装置と、本発明の範囲外である比較例の半導体装置について、電磁界解析と電気回路解析によってクロストークノイズを検証した結果を説明する。   Next, referring to FIG. 4 to FIG. 6, an electromagnetic field analysis and an electric circuit analysis are performed on a semiconductor device having a single wiring that is an embodiment of the present invention and a semiconductor device of a comparative example that is outside the scope of the present invention The result of verifying the crosstalk noise will be described.

図４は、比較例の半導体装置におけるクロストークノイズを解析するための電磁界解析モデルを示しており、比較例の半導体装置は、８本の信号線ボンディングワイヤ５１〜５８が設けられている。信号線ボンディングワイヤ５１〜５８は、全てが正ボンディングワイヤである。図４では、信号入力点４０と信号波形観測点４１〜４３を示している。   FIG. 4 shows an electromagnetic field analysis model for analyzing crosstalk noise in the semiconductor device of the comparative example. The semiconductor device of the comparative example is provided with eight signal line bonding wires 51 to 58. All of the signal line bonding wires 51 to 58 are positive bonding wires. In FIG. 4, a signal input point 40 and signal waveform observation points 41 to 43 are shown.

図５は、本発明の半導体装置の実施形態におけるクロストークノイズを解析するための電磁界解析モデルを示している。図５に示す半導体装置では、８本の信号線ボンディングワイヤ７１〜７８は、交互に正ボンディングワイヤと逆ボンディングワイヤで接続されている。すなわち、図５の実線で示す信号線ボンディングワイヤ７１，７３，７５，７７は正ボンディングワイヤであり、図５の破線で示す信号線ボンディングワイヤ７２，７４，７６，７８は逆ボンディングワイヤである。図５では、信号入力点６０と信号波形観測点６１〜６３を示している。   FIG. 5 shows an electromagnetic field analysis model for analyzing crosstalk noise in the embodiment of the semiconductor device of the present invention. In the semiconductor device shown in FIG. 5, the eight signal line bonding wires 71 to 78 are alternately connected by a normal bonding wire and a reverse bonding wire. That is, the signal line bonding wires 71, 73, 75, and 77 shown by solid lines in FIG. 5 are normal bonding wires, and the signal line bonding wires 72, 74, 76, and 78 shown by broken lines in FIG. 5 are reverse bonding wires. In FIG. 5, a signal input point 60 and signal waveform observation points 61 to 63 are shown.

なお、図面を単純化するために、図４の比較例と図５の本発明の実施形態のいずれにおいても、電源パッドと電源ワイヤのいずれも設けられていない。   To simplify the drawing, neither the power supply pad nor the power supply wire is provided in either the comparative example of FIG. 4 or the embodiment of the present invention of FIG.

図６は、上述した図４の比較例と図５の本発明の実施形態におけるクロストークノイズ波形例を示している。   FIG. 6 shows a crosstalk noise waveform example in the comparative example of FIG. 4 and the embodiment of the present invention shown in FIG.

ここで、図４に示す比較例の半導体装置と、図５に示す本発明の半導体装置の実施形態では、インターポーザ基板のＧＮＤパッドと信号線トレースの配線の材質はＣｕであり、ボンディングワイヤの材質はＡｕ、インターポーザ基板は比誘電率４．４の誘電体とした。信号線ボンディングワイヤ５１〜５８、７１〜７８の長さは４ｍｍ、信号線ボンディングワイヤ５１〜５８、７１〜７８の間隔は１２０μｍであり、ＧＮＤワイヤ１２の長さは、２．３ｍｍで、信号線ボンディングワイヤとＧＮＤワイヤ１２の間隔は、６０μｍである。この条件で電磁界解析を行い、信号線ボンディングワイヤ５１〜５８、７１〜７８の等価ＬＣＲ回路を抽出した。信号線トレース７の特性インピーダンスは６０Ω、遅延は６．３ｎｓ／ｍ、長さが５０ｍｍの無損失伝送線路とした。   Here, in the semiconductor device of the comparative example shown in FIG. 4 and the embodiment of the semiconductor device of the present invention shown in FIG. 5, the material of the GND pad of the interposer substrate and the wiring of the signal line trace is Cu, and the material of the bonding wire Is a dielectric having a relative dielectric constant of 4.4. The length of the signal line bonding wires 51 to 58 and 71 to 78 is 4 mm, the distance between the signal line bonding wires 51 to 58 and 71 to 78 is 120 μm, and the length of the GND wire 12 is 2.3 mm. The distance between the bonding wire and the GND wire 12 is 60 μm. Electromagnetic field analysis was performed under these conditions, and equivalent LCR circuits of the signal line bonding wires 51 to 58 and 71 to 78 were extracted. The signal line trace 7 was a lossless transmission line having a characteristic impedance of 60Ω, a delay of 6.3 ns / m, and a length of 50 mm.

図４に示す８本の信号線ボンディングワイヤ５１〜５８の内の１本のボンディングワイヤ先端の信号入力点４０と、図５に示す信号線ボンディングワイヤ７１〜７８の内の１本のボンディングワイヤ先端の信号入力点６０からそれぞれ８００ＭＨｚのクロック信号を入力して、図４に示す受信端側の信号波形観測点４１〜４３と、図５に示す受信端側の信号波形観測点６１〜６３での波形を観測した結果を図６に示す。   The signal input point 40 at the tip of one of the eight signal wire bonding wires 51 to 58 shown in FIG. 4 and the tip of one bonding wire of the signal wire bonding wires 71 to 78 shown in FIG. A clock signal of 800 MHz is input from each of the signal input points 60, and the signal waveform observation points 41 to 43 on the reception end side shown in FIG. 4 and the signal waveform observation points 61 to 63 on the reception end side shown in FIG. The result of observing the waveform is shown in FIG.

図６（Ｂ）に示すように信号波形観測点４２，６２には入力信号Ｓが伝達され、図６（Ａ）に示すように隣接する信号線トレースの受信端側の信号波形観測点４１，６１では、それぞれ遠端クロストーク波形Ｄ１，Ｄ２が観測され、図６（Ｃ）に示すように隣接する信号線トレースの受信端側の信号波形観測点４３，６３では、それぞれ遠端クロストーク波形Ｈ１，Ｈ２が観測された。   As shown in FIG. 6B, the input signal S is transmitted to the signal waveform observation points 42 and 62, and as shown in FIG. 6A, the signal waveform observation points 41 and 41 on the receiving end side of the adjacent signal line traces. 61, far-end crosstalk waveforms D1 and D2 are observed, respectively, and as shown in FIG. 6C, the far-end crosstalk waveforms are received at signal waveform observation points 43 and 63 on the receiving end side of adjacent signal line traces. H1 and H2 were observed.

クロストークノイズ振幅は、図６（Ａ）に示す比較例の信号波形観測点４１では３０５ｍＶｐ−ｐであり、図６（Ｃ）に示す比較例の信号波形観測点４３では３００ｍＶｐ−ｐであるのに対して、図６（Ａ）に示す本発明の実施形態での信号波形観測点６１では１６６ｍＶｐ−ｐであり、図６（Ｃ）に示す本発明の実施形態での信号波形観測点６３では１６９ｍＶｐ−ｐとなった。この結果から、本発明の実施形態は、比較例に比べてクロストークノイズ振幅が減少していることが認められる。   The crosstalk noise amplitude is 305 mVp-p at the signal waveform observation point 41 of the comparative example shown in FIG. 6A, and 300 mVp-p at the signal waveform observation point 43 of the comparative example shown in FIG. On the other hand, the signal waveform observation point 61 in the embodiment of the present invention shown in FIG. 6A is 166 mVp-p, and the signal waveform observation point 63 in the embodiment of the present invention shown in FIG. It was 169 mVp-p. From this result, it is recognized that the crosstalk noise amplitude is reduced in the embodiment of the present invention as compared with the comparative example.

本発明の半導体装置は、集積回路チップと、複数の信号配線を有する基板と、集積回路チップと信号配線とを電気的に接続する複数本のボンディングワイヤと、を備え、ボンディングワイヤは、第１端部を集積回路チップに接続するボールボンディング部と、第２端部を信号配線に接続するウェッジボンディング部とを有する正ボンディングワイヤと、第１端部を信号配線に接続するボールボンディング部と、第２端部を集積回路チップに接続するウェッジボンディング部とを有する逆ボンディングワイヤと、を有し、正ボンディングワイヤと逆ボンディングワイヤとを交互に隣接して並置したことを特徴とする。これにより、信号線ボンディングワイヤの間隔を離すことなく配線密度の低下を防ぎ、信号線ボンディングワイヤのボンディング順序を変更するだけで信号線ボンディングワイヤ間に生じるクロストークノイズを減少することができる。   The semiconductor device of the present invention includes an integrated circuit chip, a substrate having a plurality of signal wirings, and a plurality of bonding wires that electrically connect the integrated circuit chip and the signal wirings. A positive bonding wire having a ball bonding portion connecting an end to the integrated circuit chip, a wedge bonding portion connecting the second end to the signal wiring, a ball bonding portion connecting the first end to the signal wiring, And a reverse bonding wire having a wedge bonding portion that connects the second end portion to the integrated circuit chip, and the normal bonding wire and the reverse bonding wire are arranged alternately adjacent to each other. As a result, it is possible to prevent a decrease in wiring density without separating the signal line bonding wires, and to reduce crosstalk noise generated between the signal line bonding wires only by changing the bonding order of the signal line bonding wires.

また、各前記信号配線は１つの情報信号を伝送するシングルエンド配線ある。これにより、複数の信号配線がシングルエンド配線形式であっても、信号線ボンディングワイヤ間に生じるクロストークノイズを減少することができる。   Each of the signal lines is a single-end line that transmits one information signal. Thereby, even if a plurality of signal wirings are in a single end wiring format, crosstalk noise generated between the signal line bonding wires can be reduced.

さらに隣接の２つの前記信号配線が差動配線であり、
前記差動配線は、前記集積回路チップと前記信号配線に対して前記正ボンディングワイヤにより接続される第１差動配線部と、もしくは前記信号配線と前記集積回路チップに対して前記逆ボンディングワイヤにより接続される第２差動配線部とのいずれか一方の正ボンディングワイヤにより接続されている。これにより、複数の信号配線が差動配線形式であっても、信号線ボンディングワイヤ間に生じるクロストークノイズを減少することができる。 Further, the two adjacent signal wires are differential wires,
The differential wiring includes a first differential wiring portion connected to the integrated circuit chip and the signal wiring by the positive bonding wire, or a reverse bonding wire to the signal wiring and the integrated circuit chip. It is connected by any one positive bonding wire to the second differential wiring portion to be connected. As a result, even when the plurality of signal wirings are in the form of differential wiring, crosstalk noise generated between the signal line bonding wires can be reduced.

なお、本発明は、上記実施の形態そのままに限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具体化できる。ＩＣチップの端子は電極とも言う。図示例のようにＩＣチップ１の直下にグランドパターン部を配置し、グランドパターン部の周囲に電源パッドを配置している。しかし、例えばグランドパターン部は、ＩＣチップ１の周囲に配置し、グランドパターン部の間に電源パッドを配置しても良い。また、例えばＩＣチップ１の直下にグランドパターン部を配置し、信号線トレース間に電源パッドを配置しても良い。   Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. The terminals of the IC chip are also called electrodes. As shown in the drawing, a ground pattern portion is disposed immediately below the IC chip 1 and a power supply pad is disposed around the ground pattern portion. However, for example, the ground pattern portion may be disposed around the IC chip 1 and a power supply pad may be disposed between the ground pattern portions. Further, for example, a ground pattern portion may be disposed immediately below the IC chip 1 and a power supply pad may be disposed between signal line traces.

また、上記実施の形態に開示されている複数の構成要素を適宜組み合わせることにより種々の発明を形成できる。例えば、実施の形態に示される全構成要素から幾つかの構成要素を削除してもよい。更に、異なる実施の形態に亘る構成要素を適宜組み合わせてもよい。   Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine the component covering different embodiment suitably.

本発明の半導体装置の好ましい第１実施形態を示す図である。1 is a diagram showing a first preferred embodiment of a semiconductor device of the present invention. 図１に示す半導体装置を示す斜視図である。FIG. 2 is a perspective view showing the semiconductor device shown in FIG. 1. 本発明の半導体装置の好ましい第２実施形態を示す図である。It is a figure which shows preferable 2nd Embodiment of the semiconductor device of this invention. 比較例の半導体装置におけるクロストークノイズを解析するための電磁界解析モデルを示す図である。It is a figure which shows the electromagnetic field analysis model for analyzing the crosstalk noise in the semiconductor device of a comparative example. 本発明の実施形態の半導体装置におけるクロストークノイズを解析するための電磁界解析モデルを示す図である。It is a figure which shows the electromagnetic field analysis model for analyzing the crosstalk noise in the semiconductor device of embodiment of this invention. 本発明の実施形態と比較例におけるクロストークノイズ波形例を比較して示す図である。It is a figure which compares and shows the crosstalk noise waveform example in embodiment and the comparative example of this invention. 従来のボンディングワイヤを有するＩＣパッケージの断面図である。It is sectional drawing of the IC package which has the conventional bonding wire. 図７に示す従来のボンディングワイヤを有するＩＣパッケージの平面図である。FIG. 8 is a plan view of an IC package having the conventional bonding wire shown in FIG. 7.

符号の説明Explanation of symbols

１…ＩＣチップ（集積回路チップ）、２…ＧＮＤパッド（グランドパターン部）、３…電源パッド（電源導体部）、７…信号線トレース（信号配線の一例）、差動ペア７Ｐ、７Ｒ、７Ｓ（差動配線の一例）、１１…電源ワイヤ、１２…ＧＮＤワイヤ（グランドワイヤ）、１３…ＧＮＤプレーン、１４…誘導体、２１〜２６…信号線ボンディングワイヤ、２１Ｂ〜２６Ｂ…信号線ボンディングワイヤの第１端部、２１Ｃ〜２６Ｃ…信号線ボンディングワイヤの第２端部、３１〜３６…信号線ボンディングワイヤ、３１Ｂ〜３６Ｂ…信号線ボンディングワイヤの第１端部、３１Ｃ〜３６Ｃ…信号線ボンディングワイヤの第２端部、５１〜５８…信号線ボンディングワイヤ、７１〜７８…信号線ボンディングワイヤ、８０…ボールボンディング部８０、９０…ウェッジボンディング部、９５…インターポーザ基板   DESCRIPTION OF SYMBOLS 1 ... IC chip (integrated circuit chip), 2 ... GND pad (ground pattern part), 3 ... Power supply pad (power supply conductor part), 7 ... Signal line trace (an example of signal wiring), Differential pair 7P, 7R, 7S (Example of differential wiring), 11... Power wire, 12... GND wire (ground wire), 13... GND plane, 14 .. derivative, 21 to 26... Signal line bonding wire, 21B to 26B. 1 end, 21C-26C ... second end of signal line bonding wire, 31-36 ... signal line bonding wire, 31B-36B ... first end of signal line bonding wire, 31C-36C ... of signal line bonding wire Second end portion, 51 to 58... Signal line bonding wire, 71 to 78... Signal line bonding wire, 80. , 90 ... wedge bonding unit, 95 ... interposer substrate

Claims (3)

集積回路チップと、
複数の信号配線を有する基板と、
前記集積回路チップと前記信号配線とを電気的に接続する複数本のボンディングワイヤと、を備え、
前記ボンディングワイヤは、
第１端部を前記集積回路チップに接続するボールボンディング部と、第２端部を前記信号配線に接続するウェッジボンディング部とを有する正ボンディングワイヤと、
第１端部を前記信号配線に接続するボールボンディング部と、第２端部を前記集積回路チップに接続するウェッジボンディング部とを有する逆ボンディングワイヤと、を有し、
前記正ボンディングワイヤと前記逆ボンディングワイヤとを交互に隣接して並置したことを特徴とする半導体装置。 An integrated circuit chip;
A substrate having a plurality of signal wirings;
A plurality of bonding wires that electrically connect the integrated circuit chip and the signal wiring;
The bonding wire is
A positive bonding wire having a ball bonding portion connecting a first end to the integrated circuit chip and a wedge bonding portion connecting a second end to the signal wiring;
A reverse bonding wire having a ball bonding portion connecting a first end to the signal wiring and a wedge bonding portion connecting a second end to the integrated circuit chip;
A semiconductor device, wherein the normal bonding wires and the reverse bonding wires are arranged alternately adjacent to each other. 各前記信号配線は１つの情報信号を伝送するシングルエンド配線あることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein each of the signal wirings is a single-end wiring that transmits one information signal. 隣接の２つの前記信号配線が差動配線であり、
前記差動配線は、前記集積回路チップと前記信号配線に対して前記正ボンディングワイヤにより接続される第１差動配線部と、もしくは前記信号配線と前記集積回路チップに対して前記逆ボンディングワイヤにより接続される第２差動配線部とのいずれか一方の正ボンディングワイヤにより接続されていることを特徴とする請求項１に記載の半導体装置。 The two adjacent signal wires are differential wires,
The differential wiring includes a first differential wiring portion connected to the integrated circuit chip and the signal wiring by the positive bonding wire, or a reverse bonding wire to the signal wiring and the integrated circuit chip. The semiconductor device according to claim 1, wherein the semiconductor device is connected by any one positive bonding wire to the second differential wiring portion to be connected.
JP2008152798A 2008-06-11 2008-06-11 Semiconductor device Pending JP2009302180A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013214546A (en) * 2012-03-30 2013-10-17 Fujitsu Ten Ltd Semiconductor device and semiconductor device manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013214546A (en) * 2012-03-30 2013-10-17 Fujitsu Ten Ltd Semiconductor device and semiconductor device manufacturing method

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