JP2009296072A - Wireless receiver - Google Patents
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Abstract
Description
本発明は、ディジタル無線通信の無線受信機に関するもので、移動無線通信方式への利用に適する。二つの異なる種類の復調回路を並行して動作させ、受信入力低下および遅延分散に起因する回線品質劣化を比較的小規模な回路で監視し、いずれか一方の出力を切換えることにより良好な回線品質を確保する。 The present invention relates to a wireless receiver for digital wireless communication, and is suitable for use in a mobile wireless communication system. Two different types of demodulator circuits are operated in parallel, and the line quality degradation caused by a decrease in received input and delay dispersion is monitored with a relatively small circuit. By switching one of the outputs, good line quality is achieved. To secure.
回路構成が比較的単純で経済性や信頼性等の面で優れた遅延検波復調方式と、回路構成がやや複雑で動作速度や消費電力などの面では遅延検波復調方式に若干劣るが、マルチパスフェージング゛等による符号間干渉がある伝搬条件下でも良好な回線品質を維持できる等化復調方式の、二つの異なる復調方式による復調回路を備え、伝搬路の状況によりいずれか一方の復調回路の出力を選択する方式が実用化されている。 Delay detection demodulation method with relatively simple circuit configuration and excellent economy and reliability, and slightly inferior to delay detection demodulation method in terms of operation speed and power consumption due to slightly complicated circuit configuration. Equipped with demodulation circuits based on two different demodulation methods of equalization demodulation method that can maintain good channel quality even under propagation conditions with intersymbol interference due to fading, etc., and output of one of the demodulation circuits depending on the propagation path conditions The method of selecting is in practical use.
しかしながら、移動無線通信方式の機器に実装する受信機は、回路規模および消費電力が、より小さいことが求められることから、二つの復調回路を備えながらも、回路規模および消費電力を抑制しつつ如何に所要の回線品質を確保するかが重要な課題となる。 However, since a receiver to be mounted on a mobile radio communication system device is required to have a smaller circuit scale and power consumption, it is possible to reduce the circuit scale and power consumption while providing two demodulation circuits. The important issue is how to ensure the required line quality.
本発明はこのような背景で行われたものであり、比較的小規模な回線品質監視部で伝搬路状況を判断し、回路規模、経済性、消費電力などと回線品質との調和がとれた無線受信機を提供することを目的とする。 The present invention has been carried out in such a background, and a relatively small circuit quality monitoring unit judges a propagation path condition, and circuit quality, economy, power consumption, etc. are harmonized with circuit quality. An object is to provide a wireless receiver.
移動局設備は基地局からの信号を連続的に受信し、一方、基地局設備は移動局からの信号を間歇的に受信する。本発明は、このような特質を踏まえた解決手段を提示する。 The mobile station equipment continuously receives signals from the base station, while the base station equipment receives signals from the mobile station intermittently. The present invention presents a solution based on such characteristics.
受信高周波部と、等化復調回路と、遅延検波復調回路と、前記等化復調回路または前記遅延検波復調回路のいずれか一方の出力を切換選択する切換回路と、前記遅延検波復調回路の軟判定値と同期ワード情報とから伝搬状況を監視する回線品質監視部と、前記受信高周波部よりの受信入力レベル情報、前記回線品質監視部からの誤り率情報、前記等化復調回路の同期ワード情報および前記遅延検波復調回路の軟判定値とから伝搬路状況を推定し前記切換回路を制御する伝搬状況推定・切換制御回路とをそなえた無線受信機による。
A reception high-frequency unit, an equalization demodulation circuit, a delay detection demodulation circuit, a switching circuit that switches and selects an output of either the equalization demodulation circuit or the delay detection demodulation circuit, and a soft decision of the delay detection demodulation circuit A line quality monitoring unit that monitors the propagation status from the value and the synchronization word information, received input level information from the reception high frequency unit, error rate information from the line quality monitoring unit, synchronization word information of the equalization demodulation circuit, and A radio receiver including a propagation state estimation / switching control circuit for estimating a propagation path state from a soft decision value of the delay detection demodulation circuit and controlling the switching circuit.
受信高周波部と、等化復調回路と、遅延検波復調回路と、前記等化復調回路または前記遅延検波復調回路のいずれか一方の出力を切換選択する切換回路と、前記遅延検波復調回路の軟判定値と同期ワード情報とから伝搬状況を監視する回線品質監視部と、前記受信高周波部よりの受信入力レベル情報、前記回線品質監視部からの誤り率情報、前記等化復調回路の同期ワード情報および前記遅延検波復調回路の軟判定値とから伝搬路状況を推定し前記切換回路を制御する伝搬状況推定・切換制御回路とをそなえ、等化復調回路と遅延検波復調回路が並行して動作し、回線品質監視部が遅延検波復調回路の同期ワードの誤り率および軟判定値を監視するのに際し、そのフレーム数、誤り率の閾値、誤り率が閾値を超えることを容認するフレーム数、誤り率が閾値を連続して超えることを容認するフレーム数について、その全てまたは一部を、遅延検波復調回路の軟判定値にもとづき設定することを特徴とする無線受信機による。 A reception high-frequency unit, an equalization demodulation circuit, a delay detection demodulation circuit, a switching circuit that switches and selects an output of either the equalization demodulation circuit or the delay detection demodulation circuit, and a soft decision of the delay detection demodulation circuit A line quality monitoring unit that monitors the propagation status from the value and the synchronization word information, received input level information from the reception high frequency unit, error rate information from the line quality monitoring unit, synchronization word information of the equalization demodulation circuit, and Providing a propagation state estimation / switching control circuit that estimates the propagation path state from the soft decision value of the delay detection demodulation circuit and controls the switching circuit, the equalization demodulation circuit and the delay detection demodulation circuit operate in parallel, When the line quality monitoring unit monitors the error rate and soft decision value of the synchronization word of the delay detection demodulation circuit, the number of frames, the error rate threshold, and the number of frames that allow the error rate to exceed the threshold For the number of frames that an admission that the error rate exceeds continuously the threshold, all or part, by the wireless receiver and setting based on a soft decision value of the delay detection demodulation circuit.
受信高周波部と、等化復調回路と、遅延検波復調回路と、前記等化復調回路または前記遅延検波復調回路のいずれか一方の出力を切換選択する切換回路と、前記遅延検波復調回路の軟判定値と同期ワード情報とから伝搬状況を監視する回線品質監視部と、前記受信高周波部よりの受信入力レベル情報、前記回線品質監視部からの誤り率情報、前記等化復調回路の同期ワード情報および前記遅延検波復調回路の軟判定値とから伝搬路状況を推定し前記切換回路を制御する伝搬状況推定・切換制御回路とをそなえ、回線品質監視部が遅延検波復調回路の同期ワードの誤り率があらかじめ回線品質の許容限界として設定した閾値以下であると判定した場合、伝搬状況推定・切換制御回路が遅延検波復調回路または等化復調回路の同期ワードの誤り率が小さい復調回路の出力を切換選択し、伝搬状況監視回路が同期ワードの誤り率が前記のあらかじめ回線品質の許容限界として設定した閾値を超えていると判定した場合は、伝搬状況監視回路が、同期ワードの誤り率、受信入力レベル情報、および(または)遅延検波復調回路の軟判定情報にもとづき、遅延検波復調回路または等化復調回路のいずれか一方の出力を切換選択し、受信機出力とすることを特徴とする無線受信機による。 A reception high-frequency unit, an equalization demodulation circuit, a delay detection demodulation circuit, a switching circuit that switches and selects an output of either the equalization demodulation circuit or the delay detection demodulation circuit, and a soft decision of the delay detection demodulation circuit A line quality monitoring unit that monitors the propagation status from the value and the synchronization word information, received input level information from the reception high frequency unit, error rate information from the line quality monitoring unit, synchronization word information of the equalization demodulation circuit, and Providing a propagation state estimation / switching control circuit for estimating a propagation path state from a soft decision value of the delay detection demodulation circuit and controlling the switching circuit, the line quality monitoring unit has an error rate of a synchronization word of the delay detection demodulation circuit If it is determined that the transmission quality estimation / switching control circuit is less than the threshold set in advance as the acceptable limit of the line quality, the error rate of the synchronization word of the delay detection demodulation circuit or equalization demodulation circuit If the propagation status monitoring circuit determines that the error rate of the synchronization word exceeds the threshold set in advance as the allowable limit of the line quality, the propagation status monitoring circuit Based on the word error rate, the received input level information, and / or the soft decision information of the delay detection demodulation circuit, the output of either the delay detection demodulation circuit or the equalization demodulation circuit is switched and selected as the receiver output. By the wireless receiver characterized by this.
本発明の装置では、比較的小規模な回線品質監視回路による誤り率または誤り数と、受信高周波部が監視する受信入力レベルと、軟判定情報とから、マルチパスフェージング発生などの伝搬路状況を推測し、遅延検波復調路と等化復調回路の出力を使い分けることで良好な回線品質を維持できる。 In the apparatus of the present invention, the propagation path condition such as the occurrence of multipath fading is determined from the error rate or number of errors by a relatively small circuit quality monitoring circuit, the reception input level monitored by the reception high-frequency unit, and soft decision information. A good channel quality can be maintained by estimating and using the delay detection demodulation path and the output of the equalization demodulation circuit properly.
本発明の実施例について図面を参照して説明する。なお、本実施例では、同期ワードを含むARIB−STD79のフレームフォーマットを引用して説明を行なうが、同期ワードを含むフレームフォーマットによる通信方式であれば、他の方式でも適用可能であることを明記しておく。 Embodiments of the present invention will be described with reference to the drawings. In this embodiment, the description will be made with reference to the ARIB-STD79 frame format including the synchronization word. However, it is clearly stated that other systems can be applied as long as the communication format is based on the frame format including the synchronization word. Keep it.
図1は本発明の実施例としての無線受信機のブロック構成図である。図1の無線受信機において、受信入力100は、受信高周波部101にて復調回路の動作に適した周波数並びにレベルへ変換・増幅された後、2分配され、一方は等化復調回路102へ、他の一方は遅延検波復調回路103へと導かれる。等化復調回路102の同期ワードは同期ワード情報110として、また、遅延検波復調回路の同期ワードと軟判定情報は同期ワード情報108と軟判定情報109として、伝搬状況推定・切換制御回路105により監視されている。 FIG. 1 is a block diagram of a radio receiver as an embodiment of the present invention. In the radio receiver of FIG. 1, the reception input 100 is converted and amplified to a frequency and level suitable for the operation of the demodulation circuit by the reception high-frequency unit 101, and then divided into two, and one is supplied to the equalization demodulation circuit 102. The other one is led to the delay detection demodulation circuit 103. The propagation word estimation / switching control circuit 105 monitors the synchronization word of the equalization demodulation circuit 102 as synchronization word information 110, and the synchronization word and soft decision information of the delay detection demodulation circuit as synchronization word information 108 and soft decision information 109. Has been.
図2は、回線品質監視回路205が、1フレームが4スロットで構成されるフレームフォーマット(ARIB STD−79)の信号列の第1スロットの誤り率を監視している様子を示す。ここで、監視フレーム設定回路204は監視するフレーム数を設定するものであり、この例では連続する3フレームを監視するように設定され、連続する3つのフレーム内の♯1(夫々201、202、203)の同期ワードを監視している。 FIG. 2 shows a state in which the channel quality monitoring circuit 205 monitors the error rate of the first slot of a signal sequence of a frame format (ARIB STD-79) in which one frame is composed of four slots. Here, the monitoring frame setting circuit 204 sets the number of frames to be monitored. In this example, the monitoring frame setting circuit 204 is set to monitor three consecutive frames, and # 1 (201, 202, 203).
図3は、本発明の実施例の受信機が、遅延検波復調回路の出力または等化復調回路の出力のいずれか一方を選択する様子をフローチャートにより示したものである。動作を開始する301と、遅延検波復調回路の同期ワードの誤り率(Eg)の計測302と遅延検波復調回路の軟判定値の誤り率(Ef)の計測303を行う。つぎに、Egの計測結果とあらかじめ設定した閾値(K1)との大小関係を判定304する。Eg<K1の場合は、Efの計測結果とあらかじめ設定した閾値(K3)との大小関係を判定305する。Ef<K3であれば、当該スロットの遅延検波復調回路の復調出力の同期ワードを正しく検出しているか否かを判定306する。判定結果が正常であれば、遅延検波復調回路の出力を選択307する。判定結果に異常があれば、当該スロット等化復調回路の復調出力の同期ワードを正しく検出しているか否かを判定310するフローへ進む。Eg≧K1の場合は、受信入力レベルの確認308へと進む。同様に、Ef≧K3の場合も、受信入力レベルの確認308へと進む。受信入力レベルがあらかじめ設定した閾値(K2)よりも高いか否かを判定309する。判定の結果、受信入力レベル≧K2の場合は、当該スロットの等化復調回路の復調出力の同期ワードを正しく検出しているか否かの判定310へ進む。受信入力レベル<K2の場合は、当該スロット等化復調回路の復調出力の同期ワードを正しく検出しているか否かを判定310するフローへの進み、判定結果に異常あれば遅延検波復調回路の出力を選択307する。判定結果が正常であれば等化復調回路出力を選択する。
このようにして、1スロット毎に遅延検波復調回路と等化復調回路の誤り率の判定がおこなわれ、いずれか一方の復調回路の出力が切換選択される。
FIG. 3 is a flowchart showing how the receiver according to the embodiment of the present invention selects either the output of the delay detection demodulation circuit or the output of the equalization demodulation circuit. When the operation is started 301, the error rate (Eg) measurement 302 of the synchronous word of the delay detection demodulator circuit and the error rate (Ef) 303 of the soft decision value of the delay detection demodulator circuit are performed. Next, the magnitude relationship between the Eg measurement result and a preset threshold value (K1) is determined 304. When Eg <K1, the magnitude relationship between the measurement result of Ef and a preset threshold value (K3) is determined 305. If Ef <K3, it is determined 306 whether or not the synchronization word of the demodulated output of the delay detection demodulating circuit in the slot is correctly detected. If the determination result is normal, the output of the delay detection demodulation circuit is selected 307. If there is an abnormality in the determination result, the flow proceeds to a flow for determining 310 whether or not the synchronization word of the demodulated output of the slot equalizing / demodulating circuit is correctly detected. If Eg ≧ K1, the process proceeds to the reception input level confirmation 308. Similarly, if Ef ≧ K3, the process proceeds to the reception input level confirmation 308. It is determined 309 whether the received input level is higher than a preset threshold value (K2). As a result of the determination, if the received input level ≧ K2, the process proceeds to determination 310 whether or not the synchronization word of the demodulated output of the equalization demodulating circuit of the slot is correctly detected. If the received input level <K2, the process proceeds to a flow for determining 310 whether or not the synchronization word of the demodulated output of the slot equalizing demodulator is correctly detected. If the determination result is abnormal, the output of the delay detection demodulator is detected. Select 307. If the determination result is normal, the equalization demodulation circuit output is selected.
In this way, the error rate of the delay detection demodulation circuit and the equalization demodulation circuit is determined for each slot, and the output of one of the demodulation circuits is switched and selected.
図4は、ARIB STD−79の制御用物理チャンネルの信号フォーマットの1スロットの内訳を示したものである。上り回線のビット構成41では同期信号(Synchronization Word:20ビット)42が、下り回線のビット構成43では同期信号(Synchronization Word:20ビット)44が誤り率の監視対象となっている。 FIG. 4 shows the breakdown of one slot of the signal format of the control physical channel of ARIB STD-79. In the uplink bit configuration 41, the synchronization signal (Synchronization Word: 20 bits) 42 is the error rate monitoring target, and in the downlink bit configuration 43, the synchronization signal (Synchronization Word: 20 bits) 44 is the monitoring target.
図5は、ARIB STD−79の通信用物理チャンネルの信号フォーマットの1スロットの内訳を示したものである。上り回線のビット構成51では同期信号(Synchronization Word:20ビット)52、下り回線のビット構成53では同期信号(Synchronization Word:20ビット)54が誤り率または誤り数の監視対象となっている。 FIG. 5 shows the breakdown of one slot of the signal format of the communication physical channel of ARIB STD-79. In the uplink bit configuration 51, the synchronization signal (Synchronization Word: 20 bits) 52 is monitored, and in the downlink bit configuration 53, the synchronization signal (Synchronization Word: 20 bits) 54 is monitored.
図6は、ARIB STD−79の同期バーストの信号フォーマットの1スロットの内訳を示したものである。上り回線のビット構成61では同期信号(Synchronization Word:32ビット)62が、下り回線のビット構成63では同期信号(Synchronization Word:32ビット)64が誤り率または誤り数の監視対象となっている。
FIG. 6 shows the breakdown of one slot of the ARIB STD-79 synchronous burst signal format. In the uplink bit configuration 61, the synchronization signal (Synchronization Word: 32 bits) 62 is monitored, and in the downlink bit configuration 63, the synchronization signal (Synchronization Word: 32 bits) 64 is monitored.
100…受信入力、101…受信高周波部、102…等化復調回路、103…遅延検波復調回路、104…回線品質監視回路、105…伝搬状況推定・切換制御回路、106…切換回路、107…受信入力レベル情報、108…同期ワード情報、109…軟判定情報、110…同期ワード情報、201…第1フレーム、202…第2フレーム、203…第3フレーム、204…監視フレーム設定回路、205…回線品質監視回路、206…同期ワード情報、207…軟判定情報、208…同期ワード情報、209…軟判定情報、210…同期ワード情報、211…軟判定情報、212…誤り率情報、301…開始、302…遅延検波復調回路の同期ワード誤り率(Eg)の計測、212…遅延検波復調回路の軟判定値の誤り率(Ef)の計測、304…Egと閾値(K1)との大小比較、305…Efと閾値(K3)の大小比較、306…当該スロットの遅延検波復調結果の同期ワードの正検出、307…遅延検波復調回路出力の選択、308…受信入力レベルの確認、309…受信入力レベルと閾値(K2)の大小比較、310…当該スロットの復調結果の同期ワードの正検出、311…等化復調回路出力の選択、41…上り回線フレーム構成、42…同期ワード、43…下り回線フレーム構成、44…同期ワード、51…上り回線フレーム構成、52…同期ワード、53…下り回線フレーム構成、54…同期ワード、51…上り回線フレーム構成、62…同期ワード、63…下り回線フレーム構成、64…同期ワード、
DESCRIPTION OF SYMBOLS 100 ... Reception input, 101 ... Reception high frequency part, 102 ... Equalization demodulation circuit, 103 ... Delay detection demodulation circuit, 104 ... Line quality monitoring circuit, 105 ... Propagation condition estimation / switching control circuit, 106 ... Switching circuit, 107 ... Reception Input level information 108... Synchronized word information 109. Soft decision information 110. Synchronized word information 201. First frame 202. Second frame 203 203 Third frame 204 Monitor frame setting circuit 205 Line Quality monitoring circuit, 206 ... synchronization word information, 207 ... soft decision information, 208 ... synchronization word information, 209 ... soft decision information, 210 ... synchronization word information, 211 ... soft decision information, 212 ... error rate information, 301 ... start, 302 ... Measurement of synchronous word error rate (Eg) of delay detection demodulation circuit, 212 ... Measurement of error rate (Ef) of soft decision value of delay detection demodulation circuit 304... Eg and threshold value (K1) size comparison, 305... Ef and threshold value (K3) size comparison, 306... Positive detection of synchronous word of delay detection demodulation result of the slot, 307. 308: Confirmation of received input level, 309: Comparison between received input level and threshold (K2), 310: Positive detection of synchronization word in demodulation result of relevant slot, 311: Selection of equalization demodulation circuit output, 41: Uplink Line frame configuration, 42 ... synchronization word, 43 ... downlink frame configuration, 44 ... synchronization word, 51 ... uplink frame configuration, 52 ... synchronization word, 53 ... downlink frame configuration, 54 ... synchronization word, 51 ... uplink frame Configuration, 62 ... synchronization word, 63 ... downlink frame configuration, 64 ... synchronization word,
Claims (3)
When the line quality monitoring unit determines that the error rate of the synchronization word of the delay detection demodulation circuit is equal to or lower than the threshold set in advance as the allowable limit of the line quality, the propagation state estimation / switching control circuit performs the delay detection demodulation circuit or equalization demodulation. When the output of the demodulator circuit with a small error rate of the synchronization word of the circuit is switched and the propagation status monitoring circuit determines that the error rate of the synchronization word exceeds the threshold set in advance as the allowable limit of the line quality, The propagation status monitoring circuit switches the output of either the delay detection demodulation circuit or the equalization demodulation circuit based on the error rate of the synchronous word, the received input level information, and / or the soft decision information of the delay detection demodulation circuit. The radio receiver according to claim 1, wherein the radio output is selected to be a receiver output.
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JP2008145148A JP5102702B2 (en) | 2008-06-02 | 2008-06-02 | Wireless receiver |
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JP2008145148A JP5102702B2 (en) | 2008-06-02 | 2008-06-02 | Wireless receiver |
Publications (2)
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JP2009296072A true JP2009296072A (en) | 2009-12-17 |
JP5102702B2 JP5102702B2 (en) | 2012-12-19 |
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0697973A (en) * | 1992-09-14 | 1994-04-08 | N T T Idou Tsuushinmou Kk | Radio receiver |
JPH06164661A (en) * | 1992-11-24 | 1994-06-10 | N T T Idou Tsuushinmou Kk | Radio receiver |
WO1995010888A1 (en) * | 1993-10-12 | 1995-04-20 | Ntt Mobile Communications Network Inc. | Delay spread sensor and detection switching circuit using it |
JPH08111696A (en) * | 1994-10-11 | 1996-04-30 | Kyocera Corp | Error rate estimating device |
JP2000216843A (en) * | 1999-01-22 | 2000-08-04 | Oki Electric Ind Co Ltd | Digital demodulator |
JP2004048637A (en) * | 2002-05-20 | 2004-02-12 | Mitsubishi Electric Corp | Device and program for switching modulation system of digital radio machine |
JP2008124661A (en) * | 2006-11-09 | 2008-05-29 | Mitsubishi Electric Corp | Line quality measurement apparatus, base station and terminal |
JP2009044571A (en) * | 2007-08-10 | 2009-02-26 | Japan Radio Co Ltd | Wireless receiver |
-
2008
- 2008-06-02 JP JP2008145148A patent/JP5102702B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0697973A (en) * | 1992-09-14 | 1994-04-08 | N T T Idou Tsuushinmou Kk | Radio receiver |
JPH06164661A (en) * | 1992-11-24 | 1994-06-10 | N T T Idou Tsuushinmou Kk | Radio receiver |
WO1995010888A1 (en) * | 1993-10-12 | 1995-04-20 | Ntt Mobile Communications Network Inc. | Delay spread sensor and detection switching circuit using it |
JPH08111696A (en) * | 1994-10-11 | 1996-04-30 | Kyocera Corp | Error rate estimating device |
JP2000216843A (en) * | 1999-01-22 | 2000-08-04 | Oki Electric Ind Co Ltd | Digital demodulator |
JP2004048637A (en) * | 2002-05-20 | 2004-02-12 | Mitsubishi Electric Corp | Device and program for switching modulation system of digital radio machine |
JP2008124661A (en) * | 2006-11-09 | 2008-05-29 | Mitsubishi Electric Corp | Line quality measurement apparatus, base station and terminal |
JP2009044571A (en) * | 2007-08-10 | 2009-02-26 | Japan Radio Co Ltd | Wireless receiver |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011078268A1 (en) | 2009-12-25 | 2011-06-30 | サントリーホールディングス株式会社 | Bottle and bottle having content |
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