JP2009283582A - Bonded wafer manufacturing method and bonded wafer - Google Patents
Bonded wafer manufacturing method and bonded wafer Download PDFInfo
- Publication number
- JP2009283582A JP2009283582A JP2008132651A JP2008132651A JP2009283582A JP 2009283582 A JP2009283582 A JP 2009283582A JP 2008132651 A JP2008132651 A JP 2008132651A JP 2008132651 A JP2008132651 A JP 2008132651A JP 2009283582 A JP2009283582 A JP 2009283582A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- temperature
- peeling
- heat treatment
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 238000010438 heat treatment Methods 0.000 claims abstract description 85
- 239000010408 film Substances 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000005468 ion implantation Methods 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 27
- 239000010409 thin film Substances 0.000 claims abstract description 26
- 239000010453 quartz Substances 0.000 claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- 230000007547 defect Effects 0.000 claims description 14
- 239000013078 crystal Substances 0.000 claims description 7
- 239000001257 hydrogen Substances 0.000 claims description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims description 7
- -1 hydrogen ions Chemical class 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 239000004579 marble Substances 0.000 abstract description 14
- 238000000926 separation method Methods 0.000 abstract description 8
- 235000012431 wafers Nutrition 0.000 description 224
- 239000004065 semiconductor Substances 0.000 description 15
- 238000004140 cleaning Methods 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 7
- 238000005498 polishing Methods 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 3
- 238000004299 exfoliation Methods 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 238000011835 investigation Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
- 125000005372 silanol group Chemical group 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
本発明は、イオン注入剥離法を用いた、貼り合わせウェーハの製造において、ウェーハをイオン注入層で剥離する際の熱処理に関するものである。 The present invention relates to a heat treatment for peeling a wafer with an ion implantation layer in the manufacture of a bonded wafer using an ion implantation peeling method.
高性能デバイス用のウエーハとして、半導体ウエーハを他のウエーハ等と接合させた後、素子を作製する側のウエーハを薄膜化した貼り合わせウエーハが使用されている。
具体的には、例えば、鏡面研磨された２枚のシリコンウエーハを用意し、少なくとも一方のウエーハに酸化膜を形成させる。そして、これらのウエーハを接合させた後、２００〜１２００℃の温度で熱処理して結合強度を高める。その後、素子作製側ウエーハ（ボンドウエーハ）を研削及び研磨等して所望の厚さまで薄膜化することにより、ＳＯＩ（Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎｓｕｌａｔｏｒ）層が形成された貼り合わせＳＯＩウエーハを製造することができる。
As a wafer for a high-performance device, a bonded wafer is used in which a semiconductor wafer is bonded to another wafer, and then a wafer on the side on which an element is manufactured is thinned.
Specifically, for example, two mirror-polished silicon wafers are prepared, and an oxide film is formed on at least one of the wafers. And after bonding these wafers, it heat-processes at the temperature of 200-1200 degreeC, and raises bond strength. Thereafter, a bonded SOI wafer in which an SOI (Silicon On Insulator) layer is formed can be manufactured by grinding and polishing the element fabrication side wafer (bond wafer) to a desired thickness.
ボンドウエーハを薄膜化する方法としては、上記の研削・研磨による方法のほか、貼り合わせる前のボンドウエーハに予め水素イオンなどのイオン注入層を形成しておき、ベースウエーハと貼り合わせた後に例えば５００℃で１０分間程度の熱処理を施して（特許文献１参照）、そのイオン注入層で剥離することによりボンドウエーハを薄膜化する方法（スマートカット（登録商標）とも呼ばれる。）がある。 As a method for thinning the bond wafer, in addition to the above-described grinding and polishing method, an ion implantation layer such as hydrogen ions is formed in advance on the bond wafer before bonding, and after bonding to the base wafer, for example, 500 There is a method (also referred to as Smart Cut (registered trademark)) in which a bond wafer is thinned by performing a heat treatment at about 10 ° C. for about 10 minutes (see Patent Document 1) and peeling off the ion-implanted layer.
このような方法で貼り合わせウエーハを製造する場合、貼り合わせられる２枚の鏡面ウエーハの周辺部には厚さが僅かに薄くなった研磨ダレと呼ばれる部分や面取り部が存在し、その部分は結合されないか、結合力が弱い未結合部分として残ってしまう。このような未結合部分が存在したまま熱処理により薄膜化を行うと、その薄膜化工程中に未結合部分の一部が剥がれることになる。従って、薄膜化されたボンドウエーハは、基台となるウエーハ（ベースウエーハ）よりも小径となり、また、周辺部には微小な凹凸が連続的に形成されることになる。 When a bonded wafer is manufactured by such a method, there is a part called a polishing sag and a chamfered part that are slightly thinner in the peripheral part of the two mirror-finished wafers to be bonded. Otherwise, it remains as an unbonded portion with weak bonding strength. If the thin film is formed by heat treatment while such an unbonded portion exists, a part of the unbonded portion is peeled off during the thinning process. Accordingly, the thinned bond wafer has a smaller diameter than the base wafer (base wafer), and minute irregularities are continuously formed in the peripheral portion.
このような薄膜が転写されない周辺部をテラスといい、テラス幅が大きいと最終的に得られる半導体デバイスのチップ数を低減させてしまうことになる。このようなテラス幅の問題は、ボンドウェーハとベースウェーハ両方に酸化膜が形成され、その酸化膜を介して貼り合わせる場合、酸化膜同士は結合力が弱くなるため、特に顕著な問題であった。 Such a peripheral portion where the thin film is not transferred is called a terrace, and if the terrace width is large, the number of chips of the semiconductor device finally obtained is reduced. Such a terrace width problem is a particularly significant problem because an oxide film is formed on both the bond wafer and the base wafer, and when the oxide films are bonded together, the bonding strength between the oxide films becomes weak. .
また、このようなテラス幅を小さくする為に、熱処理時の温度を高くして、ウェーハ周辺部の結合力を高めようとしても、マーブル模様の膜厚ムラが一部にできてしまっていた。 Further, in order to reduce such a terrace width, even if an attempt was made to increase the bonding force at the periphery of the wafer by increasing the temperature during the heat treatment, the film thickness unevenness of the marble pattern was partially formed.
そこで本発明は、上記問題点に鑑みてなされたものであって、イオン注入剥離法において剥離熱処理の際に薄膜が転写されないテラス幅の低減と、マーブル模様の膜厚ムラを抑制することができる貼り合わせウェーハの製造方法を提供することを目的とする。 Therefore, the present invention has been made in view of the above problems, and can reduce the terrace width where the thin film is not transferred during the peeling heat treatment in the ion implantation peeling method, and can suppress the film thickness unevenness of the marble pattern. It aims at providing the manufacturing method of a bonded wafer.
上記目的を達成するために、本発明は、少なくとも、ボンドウェーハの表面から水素イオン、希ガスイオンの少なくとも一種類のガスイオンをイオン注入してウェーハ内部にイオン注入層を形成し、前記ボンドウェーハのイオン注入した表面とベースウェーハの表面とを直接あるいは絶縁膜を介して貼り合わせた後、剥離熱処理を行うことによって前記イオン注入層で前記ボンドウェーハを剥離させて貼り合わせウェーハを作製する貼り合わせウェーハの製造方法において、前記剥離熱処理においてウェーハを保持するボートの少なくともウェーハ保持部の材質を、石英よりも熱伝導率が高い材質のものを用い、剥離温度より低い温度の熱処理炉内にウェーハを投入した後、少なくとも前記イオン注入層で前記ボンドウェーハが剥離するまで昇温し続けることを特徴とする貼り合わせウェーハの製造方法を提供する（請求項１）。 In order to achieve the above object, the present invention provides an ion-implanted layer formed inside a wafer by ion-implanting at least one kind of gas ions of hydrogen ions and rare gas ions from the surface of the bond wafer. Bonding is performed by bonding the surface of the ion-implanted surface and the surface of the base wafer directly or through an insulating film, and then performing a peeling heat treatment to peel off the bond wafer at the ion-implanted layer to produce a bonded wafer. In the wafer manufacturing method, the material of at least the wafer holding portion of the boat holding the wafer in the peeling heat treatment is made of a material having a higher thermal conductivity than quartz, and the wafer is placed in a heat treatment furnace having a temperature lower than the peeling temperature. After the injection, until the bond wafer is peeled off at least in the ion implantation layer To provide a method for producing a bonded wafer, characterized in that continues to warm (claim 1).
このような貼り合わせウェーハの製造方法であれば、剥離熱処理の際に剥離温度より低い温度の熱処理炉内にウェーハを投入し、剥離するまで昇温し続けることで、剥離が生じる温度を従来の剥離する際の温度より高くすることができる。これにより、ウェーハ面内、特に結合強度の低いウェーハ周辺部の結合強度が高くなっているときに剥離するため、テラス幅を低減することができる。また、少なくともウェーハ保持部を石英より熱伝導率が高い材質にすることで、熱処理時の昇温の際にウェーハの温度が上がるのと同様にウェーハ保持部の温度も上がるため、ウェーハとウェーハ保持部の接触によるウェーハ面内での部分的な温度ムラを防止できるため、当該接触部分においても良好な剥離が生じてマーブル模様の膜厚ムラの発生を防止し、剥離面の欠陥が低減された良質な薄膜にすることができる。このため、品質の良い薄膜の幅が広がり、最終的に得られる半導体デバイスのチップ数を多くすることができるため、製品歩留まりが向上する。 With such a method for manufacturing a bonded wafer, the wafer is placed in a heat treatment furnace having a temperature lower than the peeling temperature at the time of the peeling heat treatment, and the temperature at which the peeling occurs is maintained by raising the temperature until peeling. It can be made higher than the temperature at the time of peeling. Thereby, since it peels when the bond strength in the wafer surface, especially the wafer peripheral part with low bond strength is high, the terrace width can be reduced. Also, at least the wafer holding part is made of a material having a higher thermal conductivity than quartz, so that the temperature of the wafer holding part rises in the same way as the temperature of the wafer rises when the temperature rises during heat treatment. As a result, it is possible to prevent partial temperature unevenness in the wafer surface due to the contact of the part, so that favorable peeling occurs even in the contact part, and the occurrence of unevenness of the film thickness of the marble pattern is prevented, and the defect of the peeling surface is reduced. A high-quality thin film can be obtained. For this reason, the width of the thin film with high quality is widened, and the number of chips of the finally obtained semiconductor device can be increased, so that the product yield is improved.
このとき、前記剥離熱処理において、５００℃未満の温度の前記熱処理炉内にウェーハを投入し、少なくとも前記イオン注入層で前記ボンドウェーハが剥離するまで５００℃以上の温度へ昇温し続けることが好ましい（請求項２）。
このように、ウェーハ投入時の温度を５００℃未満とすることで、熱処理炉内に投入直後に剥離が生じることはなく、また、出来るだけ高い温度で剥離を発生させたほうが結合強度も高くなるため５００℃以上の温度で剥離が生じるように昇温することが好ましい。
At this time, in the exfoliation heat treatment, it is preferable that the wafer is put into the heat treatment furnace having a temperature of less than 500 ° C. and the temperature is continuously raised to a temperature of 500 ° C. or more until the bond wafer is exfoliated at least in the ion implantation layer. (Claim 2).
Thus, by setting the temperature at the time of wafer introduction to less than 500 ° C., peeling does not occur immediately after being put into the heat treatment furnace, and the bond strength is higher when peeling is generated at the highest possible temperature. Therefore, it is preferable to raise the temperature so that peeling occurs at a temperature of 500 ° C. or higher.
このとき、前記剥離熱処理において、４００℃以下の温度の前記熱処理炉内にウェーハを投入し、少なくとも前記イオン注入層で前記ボンドウェーハが剥離するまで２℃／分以上で昇温し続けることが好ましい（請求項３）。
このように、４００℃以下の温度の時に熱処理炉内に投入することによって、剥離がすぐに生じるのを確実に防止でき、ウェーハ投入後に２℃／分以上で昇温することによって、より高い温度で結合強度が高まっている時に剥離が生じるようにすることができる。
At this time, in the exfoliation heat treatment, it is preferable that the wafer is put into the heat treatment furnace having a temperature of 400 ° C. or lower and the temperature is continuously increased at 2 ° C./min or more until the bond wafer is exfoliated at least in the ion implantation layer. (Claim 3).
In this way, when the temperature is 400 ° C. or lower, it can be surely prevented that peeling occurs immediately by introducing it into the heat treatment furnace. By raising the temperature at 2 ° C./min or higher after the wafer is charged, a higher temperature can be obtained. Thus, peeling can occur when the bond strength is increased.
このとき、前記ボンドウェーハ及びベースウェーハとしてシリコン単結晶ウェーハを用い、前記ボートの少なくともウェーハ保持部の材質を、Ｓｉ又はＳｉＣとすることが好ましい（請求項４）。
このように、ボンドウェーハ及びベースウェーハがシリコン単結晶ウェーハである場合に、Ｓｉ又はＳｉＣの材質のウェーハ保持部とすれば、シリコンと熱伝導率が近いため、昇温時に接触部とウェーハ面内のその他の部分とで温度差が生じにくく、ウェーハ面内で温度ムラが少ないため均一に剥離してマーブル模様の膜厚ムラを防止することができる。
At this time, it is preferable that a silicon single crystal wafer is used as the bond wafer and the base wafer, and the material of at least the wafer holding portion of the boat is Si or SiC.
Thus, when the bond wafer and the base wafer are silicon single crystal wafers, if the wafer holding part is made of Si or SiC material, the thermal conductivity is close to that of silicon. A temperature difference is unlikely to occur between the other portions of the wafer and there is little temperature unevenness in the wafer surface.
このとき、前記ボンドウェーハ及びベースウェーハの表面に、予め絶縁膜を形成させて、前記貼り合わせの際に、前記絶縁膜同士を介して貼り合わせることが好ましい（請求項５）。
本発明の貼り合わせウェーハの製造方法であれば、特に結合強度の低くなる絶縁膜同士を介して貼り合わせる場合でも、結合強度が高い状態で良好な剥離を行うことができるため、膜厚均一性の高い薄膜にすることができ、テラス幅も低減される。
At this time, it is preferable that an insulating film is formed in advance on the surfaces of the bond wafer and the base wafer, and bonded together via the insulating films during the bonding.
The method for producing a bonded wafer according to the present invention can achieve good peeling even in the case where the bonding strength is high, even when bonding is performed through insulating films having low bonding strength, so that the film thickness is uniform. And a terrace width is reduced.
また、本発明の貼り合わせウェーハの製造方法によって製造されたベースウェーハ上に薄膜を有する貼り合わせウェーハであって、該薄膜を選択エッチングして検出される欠陥密度が１０個／ｃｍ２以下であることを特徴とする貼り合わせウェーハを提供する（請求項６）。
本発明の製造方法で製造された貼り合わせウェーハであれば、剥離の際の温度が高くなるため、結合強度が高い状態で剥離が生じ、またウェーハ面内で温度が均一であり、良好な剥離が行われて剥離面の面粗さが向上されるため、薄膜を選択エッチングして検出される欠陥密度が１０個／ｃｍ２以下という良質な薄膜を有する貼り合わせウェーハとなる。
Moreover, it is a bonded wafer which has a thin film on the base wafer manufactured by the manufacturing method of the bonded wafer of this invention, Comprising: The defect density detected by selectively etching this thin film is 10 pieces / cm < 2 > or less. A bonded wafer characterized by the above is provided.
If it is a bonded wafer manufactured by the manufacturing method of the present invention, since the temperature at the time of peeling becomes high, peeling occurs in a state where the bonding strength is high, and the temperature is uniform within the wafer surface, and good peeling Since the surface roughness of the peeled surface is improved, a bonded wafer having a high-quality thin film with a defect density of 10 pieces / cm 2 or less detected by selective etching of the thin film is obtained.
以上のように、本発明の貼り合わせウェーハの製造方法によれば、剥離熱処理の際に剥離温度より低い温度の熱処理炉にウェーハを投入し、その後剥離するまで昇温し続けることで、従来よりも高い温度で剥離が生じる。この高い温度によりウェーハ面内、特に従来では結合強度の低いウェーハ周辺部においても結合強度が高まっているときに剥離が生じるため、テラス幅が小さくボイド等の欠陥が少ない剥離面にすることができる。また、この剥離熱処理時のウェーハを保持するボートのウェーハ保持部が石英より熱伝導率の高い材質であるため、熱処理炉内の昇温を行ってもウェーハとウェーハ保持部の温度が比較的近い温度で昇温するため、接触部分とウェーハ面内のその他の部分で温度差がほとんど生じず、面内均一に剥離が生じるためマーブル模様の膜厚不均一な部分が発生せず、膜厚均一性の高い薄膜にすることができる。このため、品質の良い薄膜の幅が広がり、最終的に得られる半導体デバイスのチップ数を多くすることができるため、製品歩留まりが向上する。 As described above, according to the method for manufacturing a bonded wafer of the present invention, the wafer is put into a heat treatment furnace having a temperature lower than the peeling temperature during the peeling heat treatment, and then the temperature is continuously raised until peeling, thereby making the conventional method Peeling occurs at higher temperatures. Due to this high temperature, peeling occurs when the bonding strength is increased in the wafer surface, particularly in the periphery of the wafer having a low bonding strength in the past, so that a separation surface having a small terrace width and few defects such as voids can be obtained. . In addition, since the wafer holding part of the boat that holds the wafers during the peeling heat treatment is made of a material having a higher thermal conductivity than quartz, the temperature of the wafer and the wafer holding part is relatively close even if the temperature in the heat treatment furnace is increased. Since the temperature is raised by the temperature, there is almost no temperature difference between the contact portion and the other portion of the wafer surface, and the in-plane uniform peeling occurs, so the uneven portion of the marble pattern does not occur and the film thickness is uniform. It can be a highly thin film. For this reason, the width of the thin film with high quality is widened, and the number of chips of the finally obtained semiconductor device can be increased, so that the product yield is improved.
貼り合わせウェーハの製造において、剥離される薄膜の膜厚均一性を高い状態でテラス幅を小さくすることが困難であった。
このようなテラス幅を狭くする為には、剥離が生ずる温度における貼り合わせ界面の結合強度が少しでも高い状態でウェーハを剥離する必要がある。つまり、剥離が生ずる温度における結合強度が強ければ、研磨ダレがある周辺部分も密着性が高まるため、より周辺部まで転写されることになる。酸化膜同士の貼り合わせの場合は、半導体と酸化膜の貼り合わせや半導体同士の貼り合わせに比べて結合強度が低いので、テラス幅が拡大しやすくなる傾向がある。
In the manufacture of bonded wafers, it has been difficult to reduce the terrace width with high film thickness uniformity of the thin film to be peeled.
In order to narrow such a terrace width, it is necessary to peel the wafer in a state where the bond strength at the bonding interface at a temperature at which peeling occurs is as high as possible. That is, if the bond strength at the temperature at which peeling occurs is strong, the peripheral portion where the polishing sagging is also improved in adhesion, so that the peripheral portion is further transferred. In the case of bonding oxide films, since the bonding strength is lower than that of bonding of a semiconductor and an oxide film or bonding of semiconductors, the terrace width tends to be easily increased.
発明者らは、鋭意調査を行った結果、貼り合わせ界面の結合強度は熱処理温度に強く依存し、温度が高いほど強くなるが、熱処理を行うウェーハと熱伝導率が大きく異なる材質の熱処理ボートを用いて剥離熱処理を行うと、昇温中、ウェーハが熱処理ボートと接触する部分の温度が他の領域と異なり、ウェーハ面内で温度が不均一となってしまうことを見出した。 As a result of intensive investigations, the inventors determined that the bond strength at the bonding interface strongly depends on the heat treatment temperature, and becomes stronger as the temperature is higher. It has been found that when the peeling heat treatment is performed, the temperature of the portion where the wafer contacts the heat treatment boat is different from the other regions during the temperature rise, and the temperature becomes nonuniform within the wafer surface.
例えば、半導体シリコンで貼り合わせウェーハを作製する際、石英製の熱処理ボートを用いて剥離熱処理を行うと、シリコンの熱伝導率１５６Ｗ／ｍＫに対し、石英は２Ｗ／ｍＫと小さく、かつ、石英は透明で熱を吸収し難い為、昇温中、ウェーハのボートと接触する部分の温度は、他の領域と比較して低くなると考えられる。この状態でウェーハの剥離が起きると、ボートと接触している付近の温度は、他の領域と比較して低い為、貼り合わせ界面の結合強度が低く、イオン注入層で剥離の原動力となるキャビティの成長が進まなくなる。この結果、ウェーハのボートとの接触部付近の領域では、無理に剥離が起きた状態となるため、縞模様状の膜厚ムラが形成されてしまう（以下、マーブル模様という）。 For example, when a bonded wafer is manufactured using semiconductor silicon, if a heat treatment for peeling is performed using a quartz heat treatment boat, the thermal conductivity of silicon is 156 W / mK, quartz is as small as 2 W / mK, and quartz is Since it is transparent and hardly absorbs heat, the temperature of the portion of the wafer that contacts the boat during the temperature rise is considered to be lower than in other regions. When wafer peeling occurs in this state, the temperature in the vicinity of contact with the boat is lower than in other areas, so the bond strength at the bonding interface is low, and the cavity that is the driving force for peeling in the ion implantation layer Growth will not progress. As a result, in the region in the vicinity of the contact portion of the wafer with the boat, the film is forcibly peeled off, and striped film thickness unevenness is formed (hereinafter referred to as a marble pattern).
これを避ける為、通常のイオン注入剥離法では、半導体シリコンを剥離する場合、例えば５００℃に昇温後、炉内温度を５００℃で３０分程度一定時間保持し、ウェーハ面内の温度が可能な限り均一になった状態で剥離を発生させることで、転写された半導体シリコン層にマーブル模様が発生することを避け、膜厚均一性を高めている。これは、炉内温度が５００℃に到達した直後はウェーハの剥離は発生しないが、その温度で一定時間保持する間にウェーハ面内の温度が均一になるのと同時に、剥離が発生するのに必要な熱量が半導体シリコンに加わることによって、マーブル模様が発生せずに剥離が生じていると考えられる。
しかしながらこの方法は、転写される半導体シリコン層の膜厚均一性を高めること（すなわち、マーブル模様の発生を抑制すること）にのみ着目しているため、この方法で剥離された半導体シリコン層を有する貼り合わせウェーハのテラス幅は比較的大きくなってしまうという欠点があった。
In order to avoid this, in the normal ion implantation delamination method, when semiconductor silicon is delaminated, for example, after raising the temperature to 500 ° C., the temperature in the furnace is kept at 500 ° C. for about 30 minutes for a temperature within the wafer surface. By causing peeling in a state that is as uniform as possible, the occurrence of a marble pattern in the transferred semiconductor silicon layer is avoided and the film thickness uniformity is improved. This is because the wafer peeling does not occur immediately after the furnace temperature reaches 500 ° C., but the temperature in the wafer surface becomes uniform while maintaining the temperature for a certain period of time, and at the same time peeling occurs. It is considered that peeling occurs without causing a marble pattern by applying a necessary amount of heat to the semiconductor silicon.
However, since this method focuses only on improving the film thickness uniformity of the transferred semiconductor silicon layer (that is, suppressing the occurrence of a marble pattern), the semiconductor silicon layer peeled off by this method is included. There is a disadvantage that the terrace width of the bonded wafer is relatively large.
テラス幅を低減するためには、貼り合わせ界面の結合強度を可能な限り高めた状態で剥離を行うことが必要であり、そのためには、少しでも高い温度で剥離を発生させる必要がある。このためには、昇温中、又は、通常よりも高い温度で一定に保持してから、短時間、例えば数分以内にウェーハの剥離が起きるように熱処理をする必要がある。
しかしながら、熱的性質が異なる熱処理ボートを用いると、ウェーハ面内で剥離時のボートとの接触部付近の温度が他の領域と異なり、マーブル模様などの不良を引き起こしてしまう。
In order to reduce the terrace width, it is necessary to perform peeling in a state where the bonding strength at the bonding interface is as high as possible. For that purpose, it is necessary to cause peeling at a temperature as high as possible. For this purpose, it is necessary to perform heat treatment so that the wafer is peeled off within a short time, for example, within a few minutes after the temperature is raised or held constant at a higher temperature than usual.
However, when heat-treated boats having different thermal properties are used, the temperature in the vicinity of the contact portion with the boat at the time of peeling in the wafer surface is different from that in other regions, causing a defect such as a marble pattern.
本発明者らは、鋭意検討を重ねたところ、イオン注入剥離法における剥離熱処理において、熱伝導率や熱吸収特性が異なる材質を剥離熱処理用ボートとして用いることで発生する問題点を見出し、これを回避しつつテラス幅を低減することのできる剥離熱処理方法を見出すことで、本発明を完成させるに至った。
すなわち、本発明は、イオン注入剥離法を用いた貼り合わせウェーハの製造における、剥離熱処理方法であって、剥離熱処理の際にウェーハと接触する部分であるウェーハ保持部の材質を、ボートとして多用されている石英より熱伝導率が高いものとし、熱伝導率や熱吸収特性が、作製する半導体ウェーハの材質と同等または近いものとするとともに、昇温中にウェーハの剥離を行うことを特徴とするものである。
As a result of extensive investigations, the present inventors have found a problem that arises when a material having different thermal conductivity and heat absorption characteristics is used as a peeling heat treatment boat in the peeling heat treatment in the ion implantation peeling method. The present invention has been completed by finding a peeling heat treatment method capable of reducing the terrace width while avoiding it.
That is, the present invention is a peeling heat treatment method in the production of bonded wafers using the ion implantation peeling method, and the material of the wafer holding part, which is a part that comes into contact with the wafer during the peeling heat treatment, is frequently used as a boat. It has a higher thermal conductivity than quartz, and its thermal conductivity and heat absorption characteristics are the same as or close to those of the semiconductor wafer to be manufactured, and the wafer is peeled off during temperature rise. Is.
一般的なシリコンウェーハを用いた貼り合わせウェーハ（室温で貼り合わせ後に高温の結合熱処理を行い、その後、研削・研磨により薄膜化を行う貼り合わせウェーハ）は、結合熱処理を１０００℃以上とすることで、貼り合わせ界面の結合を強力なシロキサン結合としている。しかしながら、イオン注入剥離法では、貼り合わせウェーハを剥離する際の熱処理温度が５００℃程度と低い。この時、貼り合わせ界面の結合状態は、シラノール基を中心とする弱い結合であるため、貼り合わせ界面の結合力が剥離する力に負けて、テラス幅が広がったり、ボイド不良やブリスター不良を引き起こす可能性が高かった。それゆえ、イオン注入剥離法では、剥離が起きる際の貼り合わせ界面の結合強度を少しでも高める必要がある。 A bonded wafer using a general silicon wafer (a bonded wafer in which a high-temperature bonding heat treatment is performed after bonding at room temperature and then thinned by grinding and polishing) is performed by setting the bonding heat treatment to 1000 ° C. or higher. The bond at the bonding interface is a strong siloxane bond. However, in the ion implantation peeling method, the heat treatment temperature when peeling the bonded wafer is as low as about 500 ° C. At this time, since the bonding state of the bonding interface is a weak bond centered on a silanol group, the bonding force of the bonding interface is defeated by the peeling force, and the terrace width is widened, causing void defects and blister defects. The possibility was high. Therefore, in the ion implantation separation method, it is necessary to increase the bond strength at the bonding interface when separation occurs.
少しでも貼り合わせ界面結合強度が高い状態でウェーハを剥離するには、昇温中に剥離を起こさせることが望ましい。そこで、本発明では、ウェーハと熱伝導率が同等の材質（石英より熱伝導率が高い材質）からなる熱処理ボートを用いる事で、たとえ、昇温中であっても、ウェーハ面内の温度均一性を比較的高いレベルで維持することが可能となる。 In order to exfoliate the wafer in a state where the bonding interface bond strength is as high as possible, it is desirable to cause exfoliation during the temperature rise. Therefore, in the present invention, by using a heat treatment boat made of a material having the same thermal conductivity as that of the wafer (a material having a higher thermal conductivity than quartz), the temperature in the wafer surface is uniform even during the temperature rise. It is possible to maintain the property at a relatively high level.
つまり、昇温中であっても、ボートとの接触部付近のウェーハ温度の低下を抑制出来、剥離熱処理中のウェーハ温度を面内でほぼ均一に保つ事が出来る。これにより、可能な限り高い温度でウェーハの剥離をすることができるので、貼り合わせ界面の結合力が最も高い状態で剥離を行うことが出来、テラス幅の低減、ボイド不良の低減など、ＳＯＩの品質が向上し、生産性が向上するメリットが得られる。 That is, even during the temperature rise, a decrease in the wafer temperature in the vicinity of the contact portion with the boat can be suppressed, and the wafer temperature during the peeling heat treatment can be kept substantially uniform in the plane. As a result, the wafer can be peeled off at the highest possible temperature, so that the peeling can be carried out with the highest bonding force at the bonding interface, and the SOI width can be reduced by reducing the terrace width and void defects. The quality is improved and the merit of improving productivity is obtained.
以下、本発明の貼り合わせウェーハの製造方法について、実施態様の一例として、図１を参照しながら、イオン注入剥離法により貼り合わせウエーハを製造する場合について詳細に説明するが、本発明はこれに限定されるものではない。
尚、図１は本発明の貼り合わせウェーハの製造方法の実施態様の一例を示すフロー図である。
Hereinafter, the method for manufacturing a bonded wafer according to the present invention will be described in detail with reference to FIG. 1 as an example of the embodiment, in which a bonded wafer is manufactured by an ion implantation separation method. It is not limited.
FIG. 1 is a flowchart showing an example of an embodiment of a method for producing a bonded wafer according to the present invention.
まず、図１の工程（ａ）では、ボンドウェーハ１０とベースウェーハ２０として、例えば、シリコン単結晶のベアウェーハを２枚用意する。ベアウェーハには、ポリッシュドウェーハ（ＰＷ）、エピタキシャルウェーハ、熱処理ウェーハ等、様々なウェーハが存在するが、その種類に関係なく本発明に適用することが出来る。ウェーハ材料としても、シリコンに限られず、化合物半導体、あるいは半導体材料以外に石英、金属等の場合にも本発明は適用できるし、また、デバイス等のパターン付ウェーハにも適用することができる。
このとき、図１では、予めボンドウェーハ１０及びベースウェーハ２０の両ウェーハに絶縁膜１２、２１が形成されているが、絶縁膜はどちらか一方にのみ形成されていてもよいし、また両ウェーハともに形成されていなくてもよい。
First, in the step (a) of FIG. 1, for example, two silicon single crystal bare wafers are prepared as the bond wafer 10 and the base wafer 20. There are various types of wafers such as polished wafers (PW), epitaxial wafers, heat-treated wafers, etc., but they can be applied to the present invention regardless of their types. The wafer material is not limited to silicon, and the present invention can be applied to a compound semiconductor or a semiconductor, quartz, metal, or the like, and can also be applied to a patterned wafer such as a device.
At this time, in FIG. 1, the insulating films 12 and 21 are formed on both the bond wafer 10 and the base wafer 20 in advance. However, the insulating films may be formed on only one of the wafers. Both may not be formed.
なお、本発明の製造方法であれば、図１のように、両ウェーハに絶縁膜が形成されその絶縁膜同士を介して貼り合わせる場合のような、特に結合強度の低くなる貼り合わせウェーハでも、剥離熱処理の際に結合強度を高くして剥離させることができるため、テラス幅の低減された膜厚均一性の高い貼り合わせウェーハを製造することができる。
このとき形成させる絶縁膜としては、例えば熱酸化膜、ＣＶＤ酸化膜等を形成させることができる。なお、それぞれのウェーハに形成される絶縁膜は、裏面も含めたウェーハの全面に形成される他、貼り合わせ面のみに形成されていてもよい。
In addition, if it is the manufacturing method of this invention, as shown in FIG. 1, even if it is a bonded wafer with low bonding strength, such as when an insulating film is formed on both wafers and bonded via the insulating films, Since the bonding strength can be increased and the separation can be performed at the time of the separation heat treatment, a bonded wafer having a reduced film thickness and a high film thickness uniformity can be manufactured.
As the insulating film formed at this time, for example, a thermal oxide film, a CVD oxide film, or the like can be formed. In addition, the insulating film formed on each wafer may be formed only on the bonding surface in addition to being formed on the entire surface of the wafer including the back surface.
次に工程（ｂ）では、ボンドウェーハ１０の絶縁膜１２の表面から水素イオン、希ガスイオンの少なくとも一種類のガスイオンをイオン注入してウェーハ内部にイオン注入層１１を形成する。この際、注入エネルギー、注入量、注入温度等その他のイオン注入条件を、所定の厚さの薄膜を得ることができるように適宜選択することができる。また、このイオン注入時の主に注入量によって、後の剥離熱処理での剥離時の温度が変わってくるため、注入量を適宜調整することで、ある程度は剥離時の温度を調整することができる。 Next, in step (b), at least one kind of gas ion of hydrogen ions and rare gas ions is ion-implanted from the surface of the insulating film 12 of the bond wafer 10 to form the ion-implanted layer 11 inside the wafer. At this time, other ion implantation conditions such as implantation energy, implantation amount, and implantation temperature can be appropriately selected so that a thin film having a predetermined thickness can be obtained. In addition, since the temperature at the time of peeling in the subsequent peeling heat treatment changes mainly depending on the implantation amount at the time of ion implantation, the temperature at the time of peeling can be adjusted to some extent by appropriately adjusting the implantation amount. .
次に工程（ｃ）では、ボンドウェーハ１０の絶縁膜１２とベースウェーハ２０の絶縁膜２１とを密着させて貼り合わせる。
この貼り合わせ前に、どちらか一方又は両方のウェーハの貼り合わせ面にプラズマ処理を施して、結合強度を高めることもできる。また、貼り合わせ前に例えばＲＣＡ洗浄を行い、ウェーハ表面に付着しているパーティクルや有機物を除去してより良好な貼り合わせを行うことができる。この場合は、貼り合わせ工程の雰囲気やウェーハを保管したＢＯＸからパーティクル汚染等を受けることもあるため、洗浄後できる限り早く貼り合わせを行うことが好ましい。
Next, in the step (c), the insulating film 12 of the bond wafer 10 and the insulating film 21 of the base wafer 20 are adhered and bonded together.
Prior to this bonding, the bonding strength of either or both wafers can be increased by plasma treatment. Further, for example, RCA cleaning can be performed before bonding to remove particles and organic substances adhering to the wafer surface, thereby performing better bonding. In this case, it is preferable to perform bonding as soon as possible after cleaning because particle contamination or the like may be received from the atmosphere of the bonding process or the BOX storing the wafer.
次に工程（ｄ）では、剥離熱処理を行うことによって、ボンドウェーハ１０をイオン注入層１１にて剥離してベースウェーハ２０上に絶縁膜１２、２１を介して薄膜３１が形成された貼り合わせウェーハ３０を作製する。
この剥離熱処理によって、ボンドウェーハ１０内のイオン注入層１１にキャビティと呼ばれる欠陥層が形成され、この欠陥層がボンドウェーハ１０内部で水平方向に繋がることで、ボンドウェーハ１０の剥離が行われる。これにより、ボンドウェーハ１０の一部がベースウェーハ２０に転写して薄膜３１になり、貼り合わせウェーハ３０が形成される。
Next, in the step (d), a bonded wafer in which the bond wafer 10 is peeled off by the ion implantation layer 11 and a thin film 31 is formed on the base wafer 20 via the insulating films 12 and 21 by performing a peeling heat treatment. 30 is produced.
By this peeling heat treatment, a defect layer called a cavity is formed in the ion implantation layer 11 in the bond wafer 10, and this defect layer is connected in the horizontal direction inside the bond wafer 10, whereby the bond wafer 10 is peeled off. Thereby, a part of the bond wafer 10 is transferred to the base wafer 20 to become the thin film 31, and the bonded wafer 30 is formed.
本発明では、この剥離熱処理においてウェーハを保持するボートの少なくともウェーハ保持部の材質を、石英よりも熱伝導率が高い材質のものを用い、剥離温度より低い温度の熱処理炉内にウェーハを投入した後、少なくともイオン注入層でボンドウェーハが剥離するまで昇温し続ける。
このように、ボンドウェーハが剥離するまで昇温し続けることで、できるだけ高い温度で剥離を生じさせることができ、すなわち貼り合わせの結合強度が高まっているときに剥離を生じさせることができるため、結合強度が弱く薄膜が転写されにくいウェーハ周辺部のテラス幅を低減することができる。また、ウェーハ保持部を石英よりも熱伝導率が高い材質にすることで、昇温時においてウェーハとの接触部における温度差が小さくなり、ウェーハ面内で接触部とその他の部分の温度が均一になり、良好な剥離が生じ、膜厚均一性の高い薄膜にすることができる。
In the present invention, the material of at least the wafer holding portion of the boat that holds the wafer in the peeling heat treatment is a material having a higher thermal conductivity than quartz, and the wafer is put into a heat treatment furnace having a temperature lower than the peeling temperature. Thereafter, the temperature is continued to rise until the bond wafer is peeled off at least by the ion implantation layer.
In this way, by continuing to raise the temperature until the bond wafer peels, it is possible to cause peeling at the highest possible temperature, that is, when the bonding strength of bonding is increased, it is possible to cause peeling. It is possible to reduce the terrace width at the wafer peripheral portion where the bonding strength is weak and the thin film is difficult to be transferred. In addition, by making the wafer holding part a material with higher thermal conductivity than quartz, the temperature difference at the contact part with the wafer at the time of temperature rise is reduced, and the temperature of the contact part and other parts within the wafer surface is uniform. Thus, good peeling occurs and a thin film with high film thickness uniformity can be obtained.
ここで、ウェーハを熱処理炉内に投入する際の剥離温度より低い温度とは、少なくともウェーハ投入直後に剥離が生じない程度の温度であり、また、常温のようなあまり低い温度であると昇温に必要以上に時間がかかり、さらには温度が高くなりきらない間に剥離が生じてしまうおそれがあるため、従来は５００℃で１０〜３０分保持することで剥離を生じさせていたのに対し、２００〜５００℃程度の温度の熱処理炉内にウェーハを投入することが望ましい。また、昇温し続けて、剥離が生じる時の温度としては、熱処理条件等によって異なるが、６００℃程度まで昇温した時点で概ね熱処理炉内の全てのウェーハの剥離が生じる。
また、ボンドウェーハの剥離の確認方法としては、特に限定されないが、剥離音によって剥離したことを確認することができる。
Here, the temperature lower than the peeling temperature when the wafer is put into the heat treatment furnace is a temperature at which peeling does not occur at least immediately after the wafer is charged, and the temperature rises when the temperature is too low such as room temperature. However, it takes longer than necessary, and there is a possibility that peeling may occur while the temperature does not become sufficiently high, so conventionally, peeling was caused by holding at 500 ° C. for 10 to 30 minutes. It is desirable to put the wafer into a heat treatment furnace having a temperature of about 200 to 500 ° C. Further, the temperature at which the temperature rises and peeling occurs varies depending on the heat treatment conditions and the like, but when the temperature is raised to about 600 ° C., almost all wafers in the heat treatment furnace are peeled off.
Further, the method for confirming the peeling of the bond wafer is not particularly limited, but it can be confirmed that the peeling is performed by the peeling sound.
このとき、５００℃未満の温度の熱処理炉内にウェーハを投入し、少なくともイオン注入層１１でボンドウェーハ１０が剥離するまで５００℃以上の温度へ昇温し続けることが好ましい。
従来は５００℃程度で所定の時間保持することにより剥離させていたことから、５００℃未満の温度の熱処理炉へ投入してもすぐには剥離せず、また、昇温し続けて５００℃以上の温度で剥離を生じさせることで、従来より高い温度で剥離が生じ、より結合強度が高い状態で剥離を生じさせることができる。
At this time, it is preferable that the wafer is put into a heat treatment furnace having a temperature of less than 500 ° C., and the temperature is continuously increased to a temperature of 500 ° C. or more until at least the ion-implanted layer 11 peels the bond wafer 10.
Conventionally, it was peeled off by holding at about 500 ° C. for a predetermined time. Therefore, even if it was put into a heat treatment furnace having a temperature of less than 500 ° C., it was not peeled off immediately, and the temperature was continuously raised to 500 ° C. or higher. By causing peeling at a temperature of, peeling can occur at a higher temperature than before, and peeling can be caused in a state where the bond strength is higher.
また、４００℃以下の温度の熱処理炉内にウェーハを投入し、少なくともイオン注入層１１でボンドウェーハ１０が剥離するまで２℃／分以上で昇温し続けることが好ましい。
４００℃以下の温度の熱処理炉内にウェーハを投入するのであれば、すぐには剥離が生じず高い温度まで昇温することができ、また、２℃／分以上であれば熱処理炉内の温度均一性を保ちながら、結合強度がより高まる温度まで昇温することができる。
In addition, it is preferable that the wafer is placed in a heat treatment furnace having a temperature of 400 ° C. or lower, and the temperature is continuously increased at 2 ° C./min or higher until the bond wafer 10 is peeled off at least by the ion implantation layer 11.
If the wafer is put into a heat treatment furnace having a temperature of 400 ° C. or lower, the temperature can be increased to a high temperature without causing separation immediately. The temperature can be raised to a temperature at which the bond strength is further increased while maintaining uniformity.
また、ボンドウェーハ１０及びベースウェーハ２０がシリコン単結晶ウェーハである場合に、剥離熱処理用のボートの少なくともウェーハ保持部の材質を、Ｓｉ又はＳｉＣとすることが望ましい。
シリコン単結晶ウェーハとＳｉ又はＳｉＣは熱伝導率が近い値であるため、昇温時の温度差が生じず、ウェーハ保持部との接触部でもその他のウェーハ面内と同じ温度になり、良好な剥離が生じてマーブル模様のない膜厚均一性の高い薄膜にすることができる。また、ウェーハ保持部のみならずボート全体の材質を、石英よりも熱伝導率が高い材質（Ｓｉ又はＳｉＣ等）のものとすれば、熱処理炉内全体の昇温時における温度均一性も高くなるためより好ましい。
Further, when the bond wafer 10 and the base wafer 20 are silicon single crystal wafers, it is desirable that the material of at least the wafer holding portion of the boat for peeling heat treatment is Si or SiC.
Since the silicon single crystal wafer and Si or SiC are close in thermal conductivity, there is no temperature difference at the time of temperature rise, and the temperature at the contact part with the wafer holding part is the same temperature as in other wafer surfaces, which is good. Peeling occurs and a thin film with high film thickness uniformity without a marble pattern can be obtained. In addition, if the material of the entire boat as well as the wafer holding part is made of a material (Si or SiC) having a higher thermal conductivity than quartz, the temperature uniformity during the temperature rise in the entire heat treatment furnace is also improved. Therefore, it is more preferable.
このように作製された貼り合わせウェーハ３０に、例えば貼り合わせ界面の結合強度を高めるための結合熱処理を酸化性雰囲気又は非酸化性雰囲気で１０００℃以上で行い、薄膜３１側を熱処理や微量研磨などの平坦化処理を行う等して、最終的な貼り合わせウェーハが完成する。 The bonded wafer 30 thus manufactured is subjected to, for example, a bonding heat treatment for increasing the bonding strength at the bonding interface at 1000 ° C. or higher in an oxidizing atmosphere or a non-oxidizing atmosphere, and the thin film 31 side is subjected to heat treatment, micro polishing, etc. The final bonded wafer is completed by performing the flattening process.
上記のように製造された貼り合わせウェーハ３０は、薄膜３１を選択エッチングして検出される欠陥密度が１０個／ｃｍ２以下のものとなる。
本発明の貼り合わせウェーハの製造方法により製造された貼り合わせウェーハは、結合強度が高められた状態で良好な剥離が生じているため、剥離面の欠陥が低減された膜厚均一性の高い薄膜を有する貼り合わせウェーハになる。
The bonded wafer 30 manufactured as described above has a defect density of 10 pieces / cm 2 or less detected by selectively etching the thin film 31.
The bonded wafer manufactured by the method for manufacturing a bonded wafer according to the present invention has a good peeling property in a state where the bonding strength is increased. A bonded wafer having
以下、本発明を実施例、比較例によりさらに具体的に説明するが、本発明はこれに限定されない。 EXAMPLES Hereinafter, although an Example and a comparative example demonstrate this invention further more concretely, this invention is not limited to this.
（実施例）：ＳｉＣボート使用、昇温中に６００℃付近で剥離、酸化膜同士の結合
まず、材料ウェーハとして、直径８インチ（２００ｍｍ）の鏡面研磨されたシリコン単結晶ウェーハを２５組用意した。ボンドウェーハに２００ｎｍの酸化膜を形成し、ベースウェーハに５００ｎｍの酸化膜を形成した。ボンドウェーハに、加速電圧８０ｋｅＶ、注入量７×１０１６／ｃｍ２の水素イオンを注入し、ＲＣＡ洗浄等から構成される貼り合わせ前洗浄を行った後、室温にてベースウェーハと貼り合わせを行った。
(Example): Use of SiC boat, peeling at around 600 ° C. during heating, bonding of oxide films First, 25 sets of mirror-polished silicon single crystal wafers having a diameter of 8 inches (200 mm) were prepared as material wafers. . A 200 nm oxide film was formed on the bond wafer, and a 500 nm oxide film was formed on the base wafer. A bond wafer is injected with hydrogen ions at an acceleration voltage of 80 keV and an injection amount of 7 × 10 16 / cm 2 , and is subjected to pre-bonding cleaning including RCA cleaning, and then bonded to the base wafer at room temperature. It was.
次に、シリコンと熱伝導率が近いＳｉＣ製熱処理ボートを用意し、一度に多数枚の熱処理が可能な抵抗加熱式の熱処理炉（バッチ炉）である横型炉にて剥離熱処理を行った。剥離熱処理は窒素雰囲気下３００℃でウェーハを投入し、６００℃まで５℃／ｍｉｎで昇温し、昇温中に、イオン注入層にてボンドウェーハの剥離、ベースウェーハへの転写を行い、ＳＯＩウェーハを作製した。この際、剥離音を検出することで、５００〜６００℃の昇温中に剥離が発生していることを確認した。このときの温度と時間の関係を図３に示す。 Next, a SiC heat treatment boat having a thermal conductivity close to that of silicon was prepared, and peeling heat treatment was performed in a horizontal furnace which is a resistance heating heat treatment furnace (batch furnace) capable of performing heat treatment on a large number of sheets at once. In the peeling heat treatment, a wafer is introduced at 300 ° C. in a nitrogen atmosphere, and the temperature is raised to 600 ° C. at 5 ° C./min. During the temperature rising, the bond wafer is peeled off by the ion implantation layer and transferred to the base wafer. A wafer was produced. At this time, it was confirmed that peeling occurred during the temperature increase of 500 to 600 ° C. by detecting the peeling sound. The relationship between temperature and time at this time is shown in FIG.
剥離したＳＯＩウェーハのテラス部の幅を調査したところ、従来の剥離熱処理（下記の比較例１に相当）では、各ウェーハのテラス幅の最も広い部分が２．２ｍｍ〜３．２ｍｍと場所によってバラツキがあったが、本結果では最大でも２．６ｍｍに低減することが出来た。これにより、テラス幅が３ｍｍに規定されたユーザーに対して、テラス幅起因の不良を無くす事が出来た。剥離したウェーハの膜厚均一性を膜厚測定器で評価した結果、膜厚均一性は５００℃で所定時間保持して剥離したデータと比較して、膜厚バラツキに差は見られなかった。また、図２（ａ）に示すように、ボートとの接触部分付近に、薄膜の膜厚が不均一になって縞模様状となるマーブル模様が発生しないことを確認する事が出来た。 When the width of the terrace portion of the peeled SOI wafer was examined, in the conventional peeling heat treatment (corresponding to Comparative Example 1 below), the widest portion of the terrace width of each wafer varies from 2.2 mm to 3.2 mm depending on the location. However, in this result, it could be reduced to 2.6 mm at the maximum. As a result, it was possible to eliminate defects caused by the terrace width for users whose terrace width was defined as 3 mm. As a result of evaluating the film thickness uniformity of the peeled wafer with a film thickness measuring device, the film thickness uniformity was kept at 500 ° C. for a predetermined time, and no difference was found in the film thickness variation compared to the peeled data. Moreover, as shown to Fig.2 (a), it was able to confirm that the marble pattern which becomes the striped pattern shape by the film thickness of the thin film becoming non-uniform | heterogenous does not generate | occur | produce in the vicinity of a contact part with a boat.
剥離後のＳＯＩウェーハに９５０℃の結合熱処理を行った後、ＳＯＩ層表面の平坦化処理（微量研磨及び犠牲酸化）を行って完成したＳＯＩウェーハのＳＯＩ層（薄膜）の最終品質は、ＳＯＩ層を混酸エッチングし、そのピットの個数で評価を行った。ピット密度を評価した結果、ピット密度は最大でも１０個／ｃｍ２と非常に低くなることが分かった。これは、シリコンと熱伝導率が近いＳｉＣ製熱処理ボートを用いて昇温中に剥離を行ったため、面内温度の均一性が高く、かつ、できるだけ高い温度（すなわち、結合強度ができるだけ高い状態）で剥離が行われた結果、剥離面の面粗さが向上し局部的な深いピットや面粗れが抑制されたことに起因すると考えられる。 After the bonded SOI wafer is subjected to a bonding heat treatment at 950 ° C., the SOI layer surface is planarized (trace polishing and sacrificial oxidation). The final quality of the SOI layer (thin film) of the completed SOI wafer is the SOI layer. The mixed acid etching was performed, and the number of pits was evaluated. As a result of evaluating the pit density, it was found that the pit density was as low as 10 pieces / cm 2 at the maximum. This is because, during the temperature rise using a SiC heat treatment boat having a thermal conductivity close to that of silicon, the in-plane temperature is highly uniform and as high as possible (ie, the bond strength is as high as possible). As a result of peeling, the surface roughness of the peeling surface is improved, and local deep pits and surface roughness are suppressed.
以上の結果より、作製する材料と同等の熱伝導率の材質の剥離熱処理ボートを用いることで、可能な限り貼り合わせ界面の結合力を高めた状態でウェーハの剥離が起きる為、テラス幅が狭くなると同時に、最終品質が向上し、製品歩留まりが向上することが分かった。 From the above results, by using a peeling heat treatment boat made of a material having the same thermal conductivity as the material to be manufactured, wafer peeling occurs with the bonding force at the bonding interface as high as possible, so the terrace width is narrow. At the same time, it was found that the final quality was improved and the product yield was improved.
（比較例１）：石英ボート使用、５００℃で３０分保持、酸化膜同士の結合
まず、材料ウェーハとして、８インチのシリコンベアウェーハを２５組用意した。ボンドウェーハに２００ｎｍの酸化膜を形成し、ベースウェーハに５００ｎｍの酸化膜を形成した。ボンドウェーハに、加速電圧８０ｋｅＶ、注入量７×１０１６／ｃｍ２の水素イオンを注入し、ＲＣＡ洗浄等から構成される貼り合わせ前洗浄を行った後、室温にてベースウェーハと貼り合わせを行った。
(Comparative example 1): Quartz boat use, hold | maintained at 500 degreeC for 30 minutes, the coupling | bonding of oxide films First, 25 sets of 8-inch silicon bare wafers were prepared as a material wafer. A 200 nm oxide film was formed on the bond wafer, and a 500 nm oxide film was formed on the base wafer. A bond wafer is injected with hydrogen ions at an acceleration voltage of 80 keV and an injection amount of 7 × 10 16 / cm 2 , and is subjected to pre-bonding cleaning including RCA cleaning, and then bonded to the base wafer at room temperature. It was.
次に、シリコンよりも熱伝導率が低い石英製熱処理ボートを用意し、横型炉にて剥離熱処理を行った。剥離熱処理は窒素雰囲気下で行い、５００℃まで５℃／ｍｉｎで昇温し、５００℃で３０分間保持した状態で、イオン注入層にてボンドウェーハの剥離、ベースウェーハへの転写を行った。熱伝導率が低い石英ボートを用いても、５００℃でしばらく保持する事で炉内の温度分布を均一化することが出来る。このときの温度と時間の関係を図３に示す。 Next, a quartz heat treatment boat having a thermal conductivity lower than that of silicon was prepared, and peeling heat treatment was performed in a horizontal furnace. The peeling heat treatment was performed in a nitrogen atmosphere, the temperature was raised to 500 ° C. at 5 ° C./min, and held at 500 ° C. for 30 minutes, and the bond wafer was peeled off and transferred to the base wafer by the ion implantation layer. Even if a quartz boat having a low thermal conductivity is used, the temperature distribution in the furnace can be made uniform by maintaining the temperature at 500 ° C. for a while. The relationship between temperature and time at this time is shown in FIG.
剥離したウェーハのテラス部の幅を調査したところ、各ウェーハのテラス幅の最も広い部分が２．２ｍｍ〜３．２ｍｍとバラツキが生じていた。これにより、テラス幅が３ｍｍに規定されたユーザーに対して、テラス幅起因の不良が多発し、製造歩留まりが悪化した。また、ＳＯＩ層の最終品質は、ＳＯＩ層を混酸エッチングし、そのピットの個数で評価を行った。ピット密度を評価した結果、ピット密度は１０〜４０個／ｃｍ２の範囲で変動し、ＳＯＩ層の品質は、不良ではないがその数値レベルが増加した。
以上の結果より、５００℃における貼り合わせ界面結合強度で、イオン注入層にて剥離が起きる為、テラス幅が広くなると同時に、最終品質が低下し、製品歩留まりが低下することが分かった。
When the width of the terrace portion of the peeled wafer was examined, the widest portion of the terrace width of each wafer was found to vary from 2.2 mm to 3.2 mm. As a result, for the users whose terrace width is defined as 3 mm, defects due to the terrace width frequently occur and the manufacturing yield deteriorates. The final quality of the SOI layer was evaluated by the number of pits obtained by etching the SOI layer with mixed acid. As a result of evaluating the pit density, the pit density fluctuated within a range of 10 to 40 pieces / cm 2 , and the quality of the SOI layer was not defective, but its numerical level increased.
From the above results, it was found that peeling occurs in the ion-implanted layer at the bonding interface bond strength at 500 ° C., so that the terrace width is widened, the final quality is lowered, and the product yield is lowered.
（比較例２）：石英ボート使用、昇温中に６００℃付近で剥離、酸化膜同士の結合
まず、材料ウェーハとして、８インチのシリコンベアウェーハを２５組用意した。ボンドウェーハに２００ｎｍの酸化膜を形成し、ベースウェーハに５００ｎｍの酸化膜を形成した。ボンドウェーハに、加速電圧８０ｋｅＶ、注入量７×１０１６／ｃｍ２の水素イオンを注入し、ＲＣＡ洗浄等から構成される貼り合わせ前洗浄を行った後、室温にてベースウェーハと貼り合わせを行った。
(Comparative Example 2): Using quartz boat, peeling at around 600 ° C. during temperature rise, bonding of oxide films First, 25 sets of 8 inch silicon bare wafers were prepared as material wafers. A 200 nm oxide film was formed on the bond wafer, and a 500 nm oxide film was formed on the base wafer. A bond wafer is injected with hydrogen ions at an acceleration voltage of 80 keV and an injection amount of 7 × 10 16 / cm 2 , and is subjected to pre-bonding cleaning including RCA cleaning, and then bonded to the base wafer at room temperature. It was.
次に、シリコンよりも熱伝導率が低い石英製熱処理ボートを用意し、横型炉にて剥離熱処理を行った。剥離熱処理は窒素雰囲気下で行い、６００℃まで５℃／ｍｉｎで昇温し、昇温中にイオン注入層にてボンドウェーハの剥離、および、ベースウェーハへの転写が起きるようにした。このときの温度と時間の関係を図３に示す。
これにより、５００℃で剥離を行うよりは、貼り合わせ界面結合強度が高い状態で剥離熱処理が起きるが、ウェーハのボートに接触する領域の温度が、他の領域よりも低下してしまう。
Next, a quartz heat treatment boat having a thermal conductivity lower than that of silicon was prepared, and peeling heat treatment was performed in a horizontal furnace. The peeling heat treatment was performed in a nitrogen atmosphere, and the temperature was raised to 600 ° C. at 5 ° C./min. During the temperature rising, peeling of the bond wafer and transfer to the base wafer occurred. The relationship between temperature and time at this time is shown in FIG.
As a result, the peeling heat treatment occurs in a state where the bonding interface bond strength is higher than the peeling at 500 ° C., but the temperature of the region in contact with the boat of the wafer is lower than the other regions.
剥離したウェーハの膜厚均一性を膜厚測定器で評価した結果、ボートとの接触部分付近に、ＳＯＩ層厚が縞模様状となる、図２（ｂ）に示すようなマーブル模様が、炉に投入した殆どのウェーハに発生してしまった。
以上の結果より、たとえ、ウェーハ剥離時の熱処理温度を５００℃より高くしても、熱伝導率の低い、石英製の熱処理ボートを使用すると、昇温中のウェーハ面内温度が不均一となるため、マーブル模様が発生してしまうことが分かった。
As a result of evaluating the film thickness uniformity of the peeled wafer with a film thickness measuring instrument, the marble pattern as shown in FIG. It occurred in most of the wafers put in the process.
From the above results, even if the heat treatment temperature at the time of wafer peeling is higher than 500 ° C., if a heat treatment boat made of quartz having a low thermal conductivity is used, the temperature in the wafer surface during temperature rise becomes non-uniform. Therefore, it turned out that a marble pattern will occur.
なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は、例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。 The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.
１０…ボンドウェーハ、 １１…イオン注入層、 １２…絶縁膜、
２０…ベースウェーハ、 ２１…絶縁膜、
３０…貼り合わせウェーハ、 ３１…薄膜。
10 ... Bond wafer, 11 ... Ion implantation layer, 12 ... Insulating film,
20 ... Base wafer, 21 ... Insulating film,
30 ... bonded wafer, 31 ... thin film.
Claims (6)
前記剥離熱処理においてウェーハを保持するボートの少なくともウェーハ保持部の材質を、石英よりも熱伝導率が高い材質のものを用い、剥離温度より低い温度の熱処理炉内にウェーハを投入した後、少なくとも前記イオン注入層で前記ボンドウェーハが剥離するまで昇温し続けることを特徴とする貼り合わせウェーハの製造方法。 At least one of hydrogen ions and rare gas ions is ion-implanted from the surface of the bond wafer to form an ion-implanted layer inside the wafer. The surface of the bond wafer and the surface of the base wafer are In a method for manufacturing a bonded wafer in which a bonded wafer is manufactured by peeling the bond wafer from the ion implantation layer by performing a peeling heat treatment after bonding directly or through an insulating film,
The material of at least the wafer holding portion of the boat holding the wafer in the peeling heat treatment is a material having a higher thermal conductivity than quartz, and after placing the wafer in a heat treatment furnace having a temperature lower than the peeling temperature, at least the A method for producing a bonded wafer, wherein the temperature is continuously increased until the bond wafer is peeled off at the ion-implanted layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008132651A JP2009283582A (en) | 2008-05-21 | 2008-05-21 | Bonded wafer manufacturing method and bonded wafer |
| PCT/JP2009/001647 WO2009141954A1 (en) | 2008-05-21 | 2009-04-09 | Bonded wafer manufacturing method, and bonded wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008132651A JP2009283582A (en) | 2008-05-21 | 2008-05-21 | Bonded wafer manufacturing method and bonded wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2009283582A true JP2009283582A (en) | 2009-12-03 |
Family
ID=41339898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008132651A Pending JP2009283582A (en) | 2008-05-21 | 2008-05-21 | Bonded wafer manufacturing method and bonded wafer |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2009283582A (en) |
| WO (1) | WO2009141954A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014091670A1 (en) | 2012-12-14 | 2014-06-19 | 信越半導体株式会社 | Soi wafer manufacturing method |
| KR20160052551A (en) * | 2013-09-05 | 2016-05-12 | 신에쯔 한도타이 가부시키가이샤 | Bonded wafer manufacturing method |
| JP2021519512A (en) * | 2018-03-28 | 2021-08-10 | ソワテク | A method for detecting the division of the substrate weakened by the injection of atomic species |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103370800A (en) * | 2010-12-29 | 2013-10-23 | Gtat公司 | A method and apparatus for forming a thin lamina |
| US10679908B2 (en) | 2017-01-23 | 2020-06-09 | Globalwafers Co., Ltd. | Cleave systems, mountable cleave monitoring systems, and methods for separating bonded wafer structures |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10335616A (en) * | 1997-05-29 | 1998-12-18 | Mitsubishi Materials Shilicon Corp | Manufacture of soi substrate |
| JPH11251563A (en) * | 1997-12-26 | 1999-09-17 | Canon Inc | Method and furnace for heat treating soi substrate and production of soi substrate employing them |
| JP2000294754A (en) * | 1999-04-07 | 2000-10-20 | Denso Corp | Semiconductor substrate, manufacture thereof, and manufacturing apparatus thereof |
| JP2002353082A (en) * | 2001-05-28 | 2002-12-06 | Shin Etsu Handotai Co Ltd | Method of manufacturing laminated wafer |
| JP2003347526A (en) * | 2002-05-02 | 2003-12-05 | Soi Tec Silicon On Insulator Technologies | Method for peeling off two layers of material |
| JP2007019303A (en) * | 2005-07-08 | 2007-01-25 | Sumco Corp | Semiconductor substrate and manufacturing method thereof |
| JP2007317988A (en) * | 2006-05-29 | 2007-12-06 | Shin Etsu Handotai Co Ltd | Manufacturing method of laminated wafer |
-
2008
- 2008-05-21 JP JP2008132651A patent/JP2009283582A/en active Pending
-
2009
- 2009-04-09 WO PCT/JP2009/001647 patent/WO2009141954A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10335616A (en) * | 1997-05-29 | 1998-12-18 | Mitsubishi Materials Shilicon Corp | Manufacture of soi substrate |
| JPH11251563A (en) * | 1997-12-26 | 1999-09-17 | Canon Inc | Method and furnace for heat treating soi substrate and production of soi substrate employing them |
| JP2000294754A (en) * | 1999-04-07 | 2000-10-20 | Denso Corp | Semiconductor substrate, manufacture thereof, and manufacturing apparatus thereof |
| JP2002353082A (en) * | 2001-05-28 | 2002-12-06 | Shin Etsu Handotai Co Ltd | Method of manufacturing laminated wafer |
| JP2003347526A (en) * | 2002-05-02 | 2003-12-05 | Soi Tec Silicon On Insulator Technologies | Method for peeling off two layers of material |
| JP2007019303A (en) * | 2005-07-08 | 2007-01-25 | Sumco Corp | Semiconductor substrate and manufacturing method thereof |
| JP2007317988A (en) * | 2006-05-29 | 2007-12-06 | Shin Etsu Handotai Co Ltd | Manufacturing method of laminated wafer |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014091670A1 (en) | 2012-12-14 | 2014-06-19 | 信越半導体株式会社 | Soi wafer manufacturing method |
| US9337080B2 (en) | 2012-12-14 | 2016-05-10 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing SOI wafer |
| KR20160052551A (en) * | 2013-09-05 | 2016-05-12 | 신에쯔 한도타이 가부시키가이샤 | Bonded wafer manufacturing method |
| KR102022507B1 (en) * | 2013-09-05 | 2019-09-18 | 신에쯔 한도타이 가부시키가이샤 | Bonded wafer manufacturing method |
| JP2021519512A (en) * | 2018-03-28 | 2021-08-10 | ソワテク | A method for detecting the division of the substrate weakened by the injection of atomic species |
| JP7426551B2 (en) | 2018-03-28 | 2024-02-02 | ソワテク | Method for detecting splitting of a substrate weakened by implantation of atomic species |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2009141954A1 (en) | 2009-11-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6373354B2 (en) | Method of manufacturing a semiconductor on insulator wafer for reducing write point defects and surface roughness | |
| EP1635396B1 (en) | Laminated semiconductor substrate and process for producing the same | |
| US8236667B2 (en) | Silicon on insulator (SOI) wafer and process for producing same | |
| JP5673572B2 (en) | Manufacturing method of bonded SOI wafer | |
| TWI357101B (en) | Method for producing bonded wafer | |
| WO2013102968A1 (en) | Method for manufacturing bonded silicon-on-insulator (soi) wafer | |
| EP1868230B1 (en) | Manufacting method of soi wafer and soi wafer manufactured by this method | |
| JP6036732B2 (en) | Manufacturing method of bonded wafer | |
| JP2006210899A (en) | Process for producing soi wafer, and soi wafer | |
| US7276427B2 (en) | Method for manufacturing SOI wafer | |
| US8703580B2 (en) | Silicon on insulator (SOI) wafer and process for producing same | |
| WO2009141954A1 (en) | Bonded wafer manufacturing method, and bonded wafer | |
| JP6380245B2 (en) | Manufacturing method of SOI wafer | |
| JP4624812B2 (en) | Manufacturing method of SOI wafer | |
| WO2003079447A1 (en) | Process for producing bonding wafer | |
| WO2016059748A1 (en) | Method for manufacturing bonded wafer | |
| JP5339785B2 (en) | Manufacturing method of bonded wafer | |
| JP5710429B2 (en) | Manufacturing method of bonded wafer | |
| TW201005883A (en) | Method for manufacturing soi wafer | |
| JP5531642B2 (en) | Manufacturing method of bonded wafer | |
| JP2006013179A (en) | Method for manufacturing soi wafer | |
| JP2004087767A (en) | Method of manufacturing soi wafer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100415 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120918 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121112 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130403 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20131029 |