JP2009267714A - Demodulator circuit - Google Patents

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JP2009267714A
JP2009267714A JP2008114213A JP2008114213A JP2009267714A JP 2009267714 A JP2009267714 A JP 2009267714A JP 2008114213 A JP2008114213 A JP 2008114213A JP 2008114213 A JP2008114213 A JP 2008114213A JP 2009267714 A JP2009267714 A JP 2009267714A
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JP4985535B2 (en
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Shuichi Hayashi
修一 林
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Mitsubishi Electric Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To solve such problems that frequency synchronization information and phase synchronization information need to be observed so as to eliminate frequency uncertainty by an AFC circuit and a CR circuit in a demodulator circuit for achieving synchronous detection, and thus, a gain adjustable parameter is added and convergence time of feedback loop gain is lengthened so as to reflect the observation result to the gain of the feedback loop. <P>SOLUTION: The AFC circuit 2 and the CR circuit 3 in the demodulator circuit are converged while a phase error remains behind. In the converged state, a reception modulating signal and a given pattern are correlated by a phase uncertainty elimination circuit 4 so that the remaining phase error is detected, and the detected phase error is corrected. Therefore, the adjustable parameter with respect to the feedback loop is reduced, and the feedback loop is simplified. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

この発明は、衛星通信や移動体通信などの無線通信において、同期検波を実現する復調回路に関するものである。   The present invention relates to a demodulation circuit that realizes synchronous detection in wireless communication such as satellite communication and mobile communication.

無線通信装置では、送信装置側の周波数と受信装置側の周波数との間に偏差（誤差）が存在し、この周波数偏差の影響でビット・エラー・レート（ＢＥＲ）特性が劣化することが知られている。そこで、受信側の復調回路では自動周波数制御（ＡＦＣ：Automatic Frequency Controller）回路などにより、送受信間の周波数偏差を除去している。また、同様に送受信間で位相誤差または位相ずれが存在し、復調回路ではキャリア再生（ＣＲ：Carrier Recovery）回路などにより、その位相誤差を除去している。   In wireless communication devices, there is a deviation (error) between the frequency on the transmission device side and the frequency on the reception device side, and it is known that the bit error rate (BER) characteristics deteriorate due to the influence of this frequency deviation. ing. Therefore, the receiving side demodulation circuit removes frequency deviation between transmission and reception by an automatic frequency controller (AFC) circuit or the like. Similarly, there is a phase error or phase shift between transmission and reception, and the demodulation circuit removes the phase error by a carrier recovery (CR) circuit or the like.

このような周波数偏差を除去する方法については、例えば特許文献１に記載されている。図８は、特許文献１に記載された従来の復調回路を概略化して記載したもので、フィードバック型の自動周波数制御回路（以下、ＡＦＣ回路と称す）２と、フィードバック型のキャリア再生回路（以下、ＣＲ回路と称す）３により構成されている。   A method for removing such a frequency deviation is described in Patent Document 1, for example. FIG. 8 schematically shows a conventional demodulation circuit described in Patent Document 1, and includes a feedback type automatic frequency control circuit (hereinafter referred to as an AFC circuit) 2 and a feedback type carrier recovery circuit (hereinafter referred to as an AFC circuit). (Referred to as a CR circuit).

ＡＦＣ回路２は、入力端子１から入力される受信変調信号の位相を周波数誤差（偏差）成分に応じて複素乗算を行う複素乗算器２１と、複素乗算器２１の出力信号が有する周波数誤差（偏差）を検出する周波数誤差検出器２２と、検出された周波数誤差を積分するループフィルタ２３と、積分された周波数誤差に基づいて、その周波数誤差を位相成分とするＡＦＣ基準信号を生成する数値制御発振器２４と、信号フレームに含まれるユニークワード（ＵＷ：Unique Word）などの既知パターンを使って、周波数同期・非同期を検出する同期判定回路２６とを備えている。   The AFC circuit 2 includes a complex multiplier 21 that performs complex multiplication on the phase of the received modulation signal input from the input terminal 1 according to a frequency error (deviation) component, and a frequency error (deviation) included in the output signal of the complex multiplier 21. ), A loop filter 23 that integrates the detected frequency error, and a numerically controlled oscillator that generates an AFC reference signal having the frequency error as a phase component based on the integrated frequency error. 24 and a synchronization determination circuit 26 that detects frequency synchronization / asynchronization using a known pattern such as a unique word (UW) included in the signal frame.

ＣＲ回路３は、ＡＦＣ回路２と同様に、ＡＦＣ回路２の出力信号を位相差に応じて複素乗算を行う複素乗算器３１と、複素乗算器３１の出力信号に含まれる位相誤差を検出する位相誤差検出器３２と、検出された位相誤差を積分するループフィルタ３３と、積分された位相誤差に対応するＣＲ基準信号を生成する数値制御発振器３４と、信号フレームに含まれるユニークワード（ＵＷ：Unique Word）などの既知パターンを使って、位相同期・非同期を検出する同期判定回路３７とを備えている。   Similar to the AFC circuit 2, the CR circuit 3 performs complex multiplication on the output signal of the AFC circuit 2 in accordance with the phase difference, and a phase for detecting a phase error included in the output signal of the complex multiplier 31. An error detector 32, a loop filter 33 for integrating the detected phase error, a numerically controlled oscillator 34 for generating a CR reference signal corresponding to the integrated phase error, and a unique word (UW: Unique) included in the signal frame And a synchronization determination circuit 37 that detects phase synchronization / asynchronization using a known pattern such as Word).

図８の構成において、ＡＦＣ回路２で送受信機間の周波数偏差を補正し、ＣＲ回路３で周波数偏差補正後、残留した位相誤差を補正し、出力端子５から復調信号を出力している。
このような構成で、上記のＡＦＣ回路２およびＣＲ回路３を動作させると、位相成分に情報が乗せられた変調の場合、受信変調信号において位相誤差を含んだ状態で安定することがある。この状態を位相不確定性と呼び、正確に信号を受信するためには位相誤差を含んだ状態であるかどうかを判定するための回路が必要となる。そのため、図８に示すようにＡＦＣ回路２およびＣＲ回路３にそれぞれ同期判定回路２６、３７を設け、信号フレームに含まれるユニークワード（ＵＷ）などの既知パターンを使って、周波数同期および位相同期が確立するようにフィードバックループを制御することで、ＣＲ回路３の出力において、位相不確定性が取り除かれた信号を得るようにしている。 In the configuration of FIG. 8, the AFC circuit 2 corrects the frequency deviation between the transceivers, the CR circuit 3 corrects the frequency deviation, corrects the remaining phase error, and outputs a demodulated signal from the output terminal 5.
When the AFC circuit 2 and the CR circuit 3 are operated with such a configuration, in the case of modulation in which information is added to the phase component, the received modulation signal may be stabilized in a state including a phase error. This state is called phase uncertainty, and a circuit for determining whether or not the state includes a phase error is necessary to accurately receive a signal. Therefore, as shown in FIG. 8, synchronization determination circuits 26 and 37 are provided in the AFC circuit 2 and the CR circuit 3, respectively, and frequency synchronization and phase synchronization are performed using a known pattern such as a unique word (UW) included in the signal frame. By controlling the feedback loop so as to be established, a signal from which phase uncertainty has been removed is obtained at the output of the CR circuit 3.

特開２００６−２１７０５４号公報（図８、図１３）JP 2006-217054 A (FIGS. 8 and 13)

以上のように、従来の復調回路は、信号フレーム中の既知パターンを使って周波数同期状態と位相同期状態を観測し、同期が確立するようにＡＦＣ回路及びＣＲ回路のフィードバックループのゲインを調整することでＣＲ回路出力として位相不確定性が除去された受信データが得られる。しかしながら、周波数同期状態と位相同期状態を観測し、観測結果をフィードバックループのゲインに反映させるため、ゲイン調整パラメータが増え、フィードバックループゲインの収束時間が長くなるという問題点があった。
また、フィードバックループのゲイン調整パラメータ増大により、フィードバックループの安定性が低下する問題があった。 As described above, the conventional demodulation circuit observes the frequency synchronization state and the phase synchronization state using the known pattern in the signal frame, and adjusts the gains of the feedback loops of the AFC circuit and the CR circuit so that synchronization is established. Thus, received data from which phase uncertainty is removed is obtained as the CR circuit output. However, since the frequency synchronization state and the phase synchronization state are observed and the observation result is reflected in the gain of the feedback loop, there are problems that the gain adjustment parameter increases and the convergence time of the feedback loop gain becomes long.
Further, there is a problem that the stability of the feedback loop is lowered due to an increase in the gain adjustment parameter of the feedback loop.

この発明は上記のような問題点を解決するためになされたもので、フィードバックループのゲイン調整パラメータを減らし、ＡＦＣ回路およびＣＲ回路におけるフィードバックループ収束時間の短縮とフィードバックループ安定性の向上を実現することを目的とするものである。   The present invention has been made to solve the above-described problems, and reduces the gain adjustment parameter of the feedback loop, and realizes shortening of the feedback loop convergence time and improvement of the feedback loop stability in the AFC circuit and the CR circuit. It is for the purpose.

この発明の復調回路は、受信変調信号に含まれる送信側と受信側との間の搬送波の周波数誤差成分を検出し、受信変調信号から周波数誤差成分を除去する自動周波数制御回路と、この自動周波数制御回路からの出力を入力して、受信変調信号に含まれる送信側と受信側との間の搬送波の位相誤差成分を検出し、受信変調信号から位相誤差成分を除去するキャリア再生回路と、このキャリア再生回路で残留した位相誤差を補正する位相不確定性除去回路とを備えたものである。   The demodulation circuit of the present invention includes an automatic frequency control circuit that detects a frequency error component of a carrier wave between a transmission side and a reception side included in a reception modulation signal and removes the frequency error component from the reception modulation signal, and the automatic frequency A carrier recovery circuit that inputs an output from the control circuit, detects a phase error component of the carrier wave between the transmission side and the reception side included in the reception modulation signal, and removes the phase error component from the reception modulation signal; and And a phase uncertainty removing circuit for correcting a phase error remaining in the carrier reproducing circuit.

この発明によれば、ＡＦＣ回路およびＣＲ回路は、同期情報を監視せずに位相誤差が残留する状態で収束するようにしたので、フィードバックループゲイン調整パラメータが減ることにより、フィードバックループの収束時間が短縮されるという効果を奏する。また、フィードバックループゲイン調整パラメータが減ることにより、フィードバックループ安定性が向上する。   According to the present invention, since the AFC circuit and the CR circuit converge in a state where the phase error remains without monitoring the synchronization information, the feedback loop gain adjustment parameter is reduced, so that the convergence time of the feedback loop is reduced. There is an effect that it is shortened. Further, the feedback loop stability is improved by reducing the feedback loop gain adjustment parameter.

実施の形態１．
以下、この発明の実施の形態１における復調回路を図面に基づいて説明する。図１はこの発明の実施の形態１における復調回路のブロック図、図２は復調回路を構成するＡＦＣ回路における周波数誤差の補正方法を示す図、図３は復調回路を構成するＣＲ回路における位相誤差の補正方法を示す図、図４は復調回路を構成するＣＲ回路の出力である位相不確定性の発生例を示す図、図５は復調回路を構成する位相不確定性除去回路の一構成例を示すブロック図である。 Embodiment 1 FIG.
Hereinafter, a demodulation circuit according to Embodiment 1 of the present invention will be described with reference to the drawings. 1 is a block diagram of a demodulation circuit according to Embodiment 1 of the present invention, FIG. 2 is a diagram showing a method of correcting a frequency error in an AFC circuit constituting the demodulation circuit, and FIG. 3 is a phase error in a CR circuit constituting the demodulation circuit. FIG. 4 is a diagram illustrating an example of occurrence of phase uncertainty, which is an output of a CR circuit that constitutes a demodulation circuit, and FIG. 5 is a configuration example of a phase uncertainty removal circuit that constitutes the demodulation circuit. FIG.

図１に示す復調回路のブロック図において、復調回路は、入力端子１から入力される受信変調信号に含まれる送信側と受信側との間の搬送波の周波数誤差成分を検出し、受信変調信号から周波数誤差成分をゼロに近い状態まで除去する自動周波数制御回路（以下、ＡＦＣ回路と称す）２と、このＡＦＣ回路２からの出力を入力して、受信変調信号に含まれる送信側と受信側との間の搬送波の位相誤差成分を検出し、受信変調信号から位相誤差成分をゼロに近い状態まで除去するキャリア再生回路（以下、ＣＲ回路と称す）３と、このＣＲ回路３で残留した位相誤差を補正して出力端子５に出力する位相不確定性除去回路４とを備えている。   In the block diagram of the demodulation circuit shown in FIG. 1, the demodulation circuit detects a frequency error component of the carrier wave between the transmission side and the reception side included in the reception modulation signal input from the input terminal 1, and detects the frequency error component from the reception modulation signal. An automatic frequency control circuit (hereinafter referred to as an AFC circuit) 2 that removes frequency error components to a state close to zero, an output from the AFC circuit 2 is input, and a transmission side and a reception side included in the received modulation signal A carrier recovery circuit (hereinafter referred to as a CR circuit) 3 that detects a phase error component of a carrier wave between the two and removes the phase error component from the received modulation signal to a state close to zero, and a phase error remaining in the CR circuit 3 And a phase uncertainty removing circuit 4 that outputs the output to the output terminal 5.

ＡＦＣ回路２は、受信変調信号の位相を周波数誤差（偏差）成分に応じて複素乗算を行う複素乗算器２１と、複素乗算器２１の出力信号に含まれる周波数誤差（偏差）を検出す
る周波数誤差検出器２２と、周波数誤差検出器２２で検出された周波数誤差を平均化するループフィルタ２３と、ループフィルタ２３で平均化された周波数誤差を複素数に変換する数値制御発振器（ＮＣＯ）２４とを備えている。
この発明のＡＦＣ回路２は、従来の復調回路で設けられていた周波数同期・非同期を検出する同期判定回路は備えられていない。 The AFC circuit 2 includes a complex multiplier 21 that performs complex multiplication on the phase of the received modulation signal according to a frequency error (deviation) component, and a frequency error that detects a frequency error (deviation) included in the output signal of the complex multiplier 21. A detector 22, a loop filter 23 that averages the frequency error detected by the frequency error detector 22, and a numerically controlled oscillator (NCO) 24 that converts the frequency error averaged by the loop filter 23 into a complex number. ing.
The AFC circuit 2 of the present invention is not provided with a synchronization determination circuit for detecting frequency synchronization / asynchronism provided in a conventional demodulation circuit.

ＣＲ回路３は、ＡＦＣ回路２と同様に、ＡＦＣ回路２の出力信号を位相差に応じて複素乗算を行う複素乗算器３１と、複素乗算器３１の出力信号に含まれる位相誤差を検出する位相誤差検出器３２と、位相誤差検出器３２で検出された位相誤差を平均化するループフィルタ３３と、ループフィルタ３３で平均化された位相誤差を複素数に変換する数値制御発振器（ＮＣＯ）３４とを備えている。
この発明のＣＲ回路３は、従来の復調回路で設けられていた位相同期・非同期を検出する同期判定回路は備えられていない。 Similar to the AFC circuit 2, the CR circuit 3 performs complex multiplication on the output signal of the AFC circuit 2 in accordance with the phase difference, and a phase for detecting a phase error included in the output signal of the complex multiplier 31. An error detector 32; a loop filter 33 that averages the phase error detected by the phase error detector 32; and a numerically controlled oscillator (NCO) 34 that converts the phase error averaged by the loop filter 33 into a complex number. I have.
The CR circuit 3 of the present invention is not provided with a synchronization determination circuit for detecting phase synchronization / asynchronism provided in a conventional demodulation circuit.

次に、ＡＦＣ回路２の動作について説明する。まず入力端子１に入力されたＩチャンネルとＱチャンネルの受信変調信号はＡＦＣ回路２において周波数誤差がゼロに近づいた状態にまで補正される。ここで、周波数誤差検出器２２は例えば入力された最新の受信変調信号とメモリに保存した過去の受信変調信号との比較により１シンボル当たりの位相回転量（周波数誤差）を検出する。次に、ループフィルタ２３は入力された周波数誤差を平均化する。次に、数値制御発振器(ＮＣＯ)２４は平均化された周波数誤差をテーブルなどにより複素数に変換する。最後に、複素乗算器２１において、入力された受信変調信号と平均化された周波数誤差情報との複素乗算を行い、周波数誤差を補正した受信変調信号を得る。ＡＦＣ回路２では、上記の動作を繰り返すことにより、補正後の受信変調信号における残留周波数誤差をゼロに近づける。   Next, the operation of the AFC circuit 2 will be described. First, the received modulation signals of the I channel and the Q channel input to the input terminal 1 are corrected by the AFC circuit 2 until the frequency error approaches zero. Here, the frequency error detector 22 detects the amount of phase rotation (frequency error) per symbol by, for example, comparing the latest received received modulation signal inputted with the past received modulation signal stored in the memory. Next, the loop filter 23 averages the input frequency error. Next, the numerically controlled oscillator (NCO) 24 converts the averaged frequency error into a complex number using a table or the like. Finally, the complex multiplier 21 performs complex multiplication of the received reception modulation signal and the averaged frequency error information to obtain a reception modulation signal in which the frequency error is corrected. In the AFC circuit 2, the residual frequency error in the received modulation signal after correction is brought close to zero by repeating the above operation.

図２はＡＦＣ回路２における周波数誤差の補正方法を示す図で、ここではＱＰＳＫ変調を例に説明する。受信シンボルを複素平面で表現したとき、理想時は図２（ａ）に示すように第１象限から第４象限において受信シンボルは４点に収束するが、ＡＦＣ前の周波数誤差が存在する状態では図２（ｂ）に示すとおり、シンボル点の回転速度が速く、短時間観測しただけでも円状に信号が並んだように見える。一方、ＡＦＣ回路２において周波数誤差を補正することにより、シンボル点の回転速度が下がるため、監視時間をＡＦＣ前と同一とした場合、図２（ｃ）に示すとおり、ＡＦＣ前に比べて回転量が小さくなる。   FIG. 2 is a diagram showing a method for correcting a frequency error in the AFC circuit 2. Here, QPSK modulation will be described as an example. When the received symbols are represented by a complex plane, the received symbols converge to four points in the first quadrant to the fourth quadrant as shown in FIG. 2A in an ideal time, but in a state where a frequency error before AFC exists. As shown in FIG. 2B, the rotation speed of the symbol points is high, and it appears that the signals are arranged in a circle even when observed for a short time. On the other hand, by correcting the frequency error in the AFC circuit 2, the rotation speed of the symbol point is reduced. Therefore, when the monitoring time is the same as that before AFC, as shown in FIG. Becomes smaller.

次に、ＣＲ回路３の動作について説明する。ＡＦＣ回路２において周波数誤差を補正された受信変調信号は、ＣＲ回路３に入力される。ＡＦＣ後も周波数誤差が残留するため、受信シンボル点がゆっくりと回転し、特性の劣化を招く。そこで、ＣＲ回路３において、残留した周波数誤差（位相誤差）の補正が行われる。
まず、位相誤差検出器３２は入力された周波数誤差補正後の受信変調信号と基準点（受信シンボルが第１象限から第４象限において４点に収束した状態）との比較を行い、受信変調信号と基準点との位相誤差を算出する。次に、ループフィルタ３３は入力された位相誤差を平均化する。続いて、数値制御発振器(ＮＣＯ)３４は平均化された位相誤差をテーブルなどにより複素数に変換する。最後に、複素乗算器３１において、入力された受信変調信号と平均化された位相誤差情報との複素乗算を行い、残留位相誤差を補正した受信変調信号を得る。ＣＲ回路３では、上記の動作を繰り返すことにより、補正後の受信変調信号における残留位相誤差をゼロに近づける。 Next, the operation of the CR circuit 3 will be described. The received modulation signal whose frequency error has been corrected in the AFC circuit 2 is input to the CR circuit 3. Since the frequency error remains even after AFC, the received symbol point rotates slowly, resulting in deterioration of characteristics. Therefore, the remaining frequency error (phase error) is corrected in the CR circuit 3.
First, the phase error detector 32 compares the inputted received modulation signal after frequency error correction with a reference point (a state where received symbols converge to four points in the first quadrant to the fourth quadrant), and receives the received modulated signal. And the phase error between the reference point and the reference point is calculated. Next, the loop filter 33 averages the input phase error. Subsequently, the numerically controlled oscillator (NCO) 34 converts the averaged phase error into a complex number using a table or the like. Finally, the complex multiplier 31 performs complex multiplication of the received reception modulation signal and the averaged phase error information to obtain a reception modulation signal in which the residual phase error is corrected. The CR circuit 3 repeats the above operation to bring the residual phase error in the received modulated signal after correction close to zero.

図３はＣＲ回路３における位相誤差の補正方法を示す図で、図３に示すようにＣＲ回路３においては位相誤差を補正する際に、受信信号と基準点との比較を行う。図３は基準点として４点の候補のうち第１象限にある(1)を選択した例を示す。このとき、受信信号は基準点(1)に近づくように補正されるが、この受信信号の理想点が必ず基準点(1)にあると
は限らず、本受信信号の理想点が基準点(1)〜(4)のいずれであるかはＣＲ回路動作時には確定しない。 FIG. 3 is a diagram showing a method of correcting the phase error in the CR circuit 3. As shown in FIG. 3, the CR circuit 3 compares the received signal with the reference point when correcting the phase error. FIG. 3 shows an example in which (1) in the first quadrant is selected as a reference point from among four candidates. At this time, the received signal is corrected so as to approach the reference point (1), but the ideal point of the received signal is not always at the reference point (1), and the ideal point of the received signal is not the reference point (1). Which of 1) to 4) is not determined when the CR circuit is operating.

即ち、ＡＦＣ回路２の出力において周波数誤差が残留していることから、ＣＲ回路３で位相誤差を補正した際に、完全に位相誤差が無い状態でＣＲ回路３から出力されることはない。したがって、ＣＲ回路３の出力信号は、後で説明する図４に示すように位相が確定しない位相不確定性（位相誤差）を有し、この位相不確定性を取り除く必要がある。この位相不確定性を取り除く回路が図１に示す位相不確定性除去回路４である。   That is, since the frequency error remains in the output of the AFC circuit 2, when the phase error is corrected by the CR circuit 3, it is not output from the CR circuit 3 without any phase error. Therefore, the output signal of the CR circuit 3 has a phase uncertainty (phase error) in which the phase is not fixed as shown in FIG. 4 described later, and it is necessary to remove this phase uncertainty. A circuit for removing this phase uncertainty is a phase uncertainty removing circuit 4 shown in FIG.

図４は、ＱＰＳＫ変調波を受信した際のＣＲ回路３の出力である位相不確定性を有する位相誤差発生例を示す図である。図４の左図は伝送路における歪みがない送信時の状態、真中の図は伝送路における歪みのため位相不確定性が発生している状態、右図は位相不確定性除去回路４の出力で、位相不確定性が除去された状態を示したものである。
また図４の各象限にある黒丸は、受信信号をシンボルレート（伝送速度）周波数でサンプリングしたものを複素平面で表現したもので、シンボル点である。 FIG. 4 is a diagram illustrating an example of occurrence of a phase error having phase uncertainty, which is an output of the CR circuit 3 when a QPSK modulated wave is received. The left figure in FIG. 4 shows a transmission state without distortion in the transmission line, the middle figure shows a state in which phase uncertainty is generated due to distortion in the transmission line, and the right figure shows the output of the phase uncertainty removal circuit 4. This shows a state where the phase uncertainty is removed.
Also, the black circles in each quadrant of FIG. 4 represent a sampled received signal sampled at a symbol rate (transmission rate) frequency and expressed in a complex plane, and are symbol points.

ＡＦＣ回路２およびＣＲ回路３の動作後、ＣＲ回路３の出力信号は、(1)位相回転なし、(2)位相π／２回転、(3)位相π回転、(4)位相３π／２回転の４状態のうちいずれかで安定する。ここで、受信変調信号中にユニークワードなどの既知パターンを含んでいる場合、既知パターンと実際の受信変調信号との相関を取ることで実際の受信変調信号が基準点に対してどれだけの位相誤差を含んでいるかを推定することが可能である。図１に示す位相不確定性除去回路４は、既知パターンと受信変調信号との相関を取り、位相誤差量を推定する。そして推定した位相誤差量を補正することで位相不確定性を取り除くものである。   After the operation of the AFC circuit 2 and the CR circuit 3, the output signal of the CR circuit 3 is (1) no phase rotation, (2) phase π / 2 rotation, (3) phase π rotation, (4) phase 3π / 2 rotation It is stable in any of the four states. Here, if the received modulation signal contains a known pattern such as a unique word, the phase of the actual received modulation signal relative to the reference point can be determined by correlating the known pattern with the actual received modulation signal. It is possible to estimate whether an error is included. The phase uncertainty removal circuit 4 shown in FIG. 1 takes a correlation between the known pattern and the received modulation signal and estimates the phase error amount. Then, the phase uncertainty is removed by correcting the estimated phase error amount.

ここで、既知パターンと実際の受信変調信号との相関を取るとは、既知パターン、既知パターンをπ／２回転させたもの、既知パターンをπ回転させたもの、既知パターンを３π／２回転させたものを準備し、各々の既知パターンと受信変調信号との複素乗算の演算を行うもので、このとき、相関が最も大きいものが演算結果の実数部が最大となる。
また、位相誤差量を推定するとは、(1)位相回転なし、(2)位相π／２回転、(3)位相π回転、(4)位相３π／２回転の４状態のうち、いずれか１つを推定することである。
また、推定した位相誤差量を補正するとは、理想点に対する回転量（位相誤差量）が推定できたとき、受信変調信号を位相誤差量分だけ逆回転すれば理想の受信信号が得られ、この処理が「推定した位相誤差量を補正する」処理である。位相誤差量の補正は通常複素乗算により行うが、この発明の実施形態では、位相誤差量の補正は、回転なし、−π／２回転、−π回転、−３π／２回転のいずれかとなるので、後述するように選択回路と反転回路で実現している。 Here, taking the correlation between the known pattern and the actual received modulation signal means that the known pattern, the known pattern rotated by π / 2, the known pattern rotated by π, or the known pattern rotated by 3π / 2. Are prepared and the complex multiplication of each known pattern and the received modulation signal is performed. At this time, the real part of the calculation result is maximized for the one having the largest correlation.
The phase error amount is estimated by any one of four states of (1) no phase rotation, (2) phase π / 2 rotation, (3) phase π rotation, and (4) phase 3π / 2 rotation. Is to estimate one.
Also, correcting the estimated phase error amount means that when the rotation amount (phase error amount) with respect to the ideal point can be estimated, the ideal reception signal can be obtained by rotating the reception modulation signal by the amount of the phase error. The process is a process of “correcting the estimated phase error amount”. The correction of the phase error amount is usually performed by complex multiplication, but in the embodiment of the present invention, the correction of the phase error amount is any one of no rotation, −π / 2 rotation, −π rotation, and −3π / 2 rotation. As will be described later, this is realized by a selection circuit and an inverting circuit.

以下、位相不確定性除去回路４の詳細を図５に示すブロック図に基づいて説明する。図５において、位相不確定性除去回路４は、ＩチャンネルとＱチャンネルの受信変調信号を反転する反転回路４１ａ〜４１ｄと、既知パターンと実際の受信変調信号との相関を取る相関回路４２と、相関回路４２で取られた相関に基づき受信変調信号およびその反転信号のいずれかを選択する選択回路（セレクタ）４３ａ、４３ｂを備えている。受信変調信号はＱＰＳＫ変調波を例に挙げ説明する。   Hereinafter, the details of the phase uncertainty removing circuit 4 will be described with reference to the block diagram shown in FIG. In FIG. 5, the phase uncertainty removing circuit 4 includes inverting circuits 41a to 41d that invert the received modulation signals of the I channel and the Q channel, a correlation circuit 42 that correlates the known pattern and the actual received modulation signal, Selection circuits (selectors) 43a and 43b are provided for selecting either the received modulated signal or its inverted signal based on the correlation taken by the correlation circuit. The received modulation signal will be described by taking a QPSK modulated wave as an example.

次に、位相不確定性除去回路４の動作について説明する。まず、相関回路４２において、既知パターンと受信変調信号との相関をとることで、(1)位相回転なし、(2)位相π／２回転、(3)位相π回転、(4)位相３π／２回転のいずれであるかを推定する。つぎに反転回路４１ａ〜４１ｄおよび選択回路４３ａ、４３ｂを用いて、推定した位相回転量を補正する。位相不確定性除去回路４の入力をＩin、Ｑin、出力をＩout、Ｑoutとすると、位相回転量＝０のとき（Ｉout，Ｑout）＝（Ｉin，Ｑin）、位相回転量＝＋π／２のとき（Ｉout，Ｑout）＝（Ｑin，−Ｉin）、位相回転量＝＋πのとき（Ｉout，Ｑout）＝（−Ｉin，−Ｑin）、位相回転量＝＋３π／２のとき（Ｉout，Ｑout）＝（−Ｑin，Ｉin）となるように選択回路４３ａ、４３ｂを動作させればよい。
即ち、位相回転量＝０のとき、選択回路４３ａ、４３ｂは両方とも端子「１」を選択、位相回転量＝＋π／２のとき、選択回路４３ａ、４３ｂは両方とも端子「２」を選択、位相回転量＝＋πのとき、選択回路４３ａ、４３ｂは両方とも端子「３」を選択、位相回転量＝＋３π／２のとき、選択回路４３ａ、４３ｂは両方とも端子「４」を選択する。 Next, the operation of the phase uncertainty removal circuit 4 will be described. First, the correlation circuit 42 correlates the known pattern and the received modulation signal to (1) no phase rotation, (2) phase π / 2 rotation, (3) phase π rotation, (4) phase 3π / Estimate which of the two rotations. Next, the estimated phase rotation amount is corrected using the inverting circuits 41a to 41d and the selection circuits 43a and 43b. When the input of the phase uncertainty removal circuit 4 is Iin, Qin, and the output is Iout, Qout, when the phase rotation amount = 0 (Iout, Qout) = (Iin, Qin), when the phase rotation amount = + π / 2 (Iout, Qout) = (Qin, −Iin), phase rotation amount = + π (Iout, Qout) = (− Iin, −Qin), phase rotation amount = + 3π / 2 (Iout, Qout) = ( The selection circuits 43a and 43b may be operated so that −Qin, Iin).
That is, when the phase rotation amount = 0, both the selection circuits 43a and 43b select the terminal “1”, and when the phase rotation amount = + π / 2, both the selection circuits 43a and 43b select the terminal “2”. When the phase rotation amount = + π, both the selection circuits 43a and 43b select the terminal “3”, and when the phase rotation amount = + 3π / 2, both the selection circuits 43a and 43b select the terminal “4”.

以上の説明において、受信変調信号がＱＰＳＫ変調波の場合を例に説明したが、既知パターンとしてＱＰＳＫ変調波を用いれば、既知パターン以外のデータが別の変調方式であっても、同じ位相不確定性除去回路を用いることが可能である。   In the above description, the case where the received modulation signal is a QPSK modulated wave has been described as an example. However, if a QPSK modulated wave is used as a known pattern, the same phase indeterminacy is obtained even if data other than the known pattern is in another modulation scheme It is possible to use a sex removal circuit.

以上説明したように、この実施の形態１の発明は、まず信号フレーム中の既知パターンを使って、ＡＦＣ回路２およびＣＲ回路３を動作させ、一旦、位相不確定性（位相誤差）が残留した状態にＡＦＣ回路２及びＣＲ回路３を収束させる。次にＣＲ回路３の後段に設けた位相不確定性除去回路４により、既知パターンと収束結果の相関を取ることにより残留位相誤差を観測し、残留位相誤差を打ち消すように位相回転して位相不確定性を取り除くようにしている。
したがって、この発明によれば、ＡＦＣ回路２やＣＲ回路３におけるフィードバックループに対するパラメータが減り、フィードバックループ収束時間の短縮とフィードバックループ安定性の向上を同時に実現することができる。 As described above, according to the first embodiment, the AFC circuit 2 and the CR circuit 3 are first operated using the known pattern in the signal frame, and the phase uncertainty (phase error) once remains. The AFC circuit 2 and the CR circuit 3 are converged to the state. Next, the residual phase error is observed by correlating the known pattern with the convergence result by the phase uncertainty removing circuit 4 provided at the subsequent stage of the CR circuit 3, and the phase rotation is performed so as to cancel the residual phase error. The determinism is removed.
Therefore, according to the present invention, the parameters for the feedback loop in the AFC circuit 2 and the CR circuit 3 are reduced, and the feedback loop convergence time can be shortened and the feedback loop stability can be improved at the same time.

実施の形態２．
次に、この発明の実施の形態２における復調回路を図面に基づいて説明する。図６はこの発明の実施の形態２における復調回路のブロック図である。
実施の形態１の発明では、ＡＦＣ回路としてフィードバック型回路を用いていたが、実施の形態２における発明はフィードバック型ＡＦＣ回路の代わりに、フィードフォワード型ＡＦＣ回路を用いたものである。 Embodiment 2. FIG.
Next, a demodulation circuit according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 6 is a block diagram of a demodulation circuit according to the second embodiment of the present invention.
In the invention of the first embodiment, the feedback type circuit is used as the AFC circuit, but the invention in the second embodiment uses a feedforward type AFC circuit instead of the feedback type AFC circuit.

図６に示す復調回路のブロック図において、復調回路は実施の形態１の発明と同様に、入力端子１から入力される受信変調信号に含まれる送信側と受信側との間の搬送波の周波数誤差成分をゼロに近い状態まで除去するＡＦＣ回路２と、このＡＦＣ回路２からの出力を入力して、受信変調信号に含まれる送信側と受信側との間の搬送波の位相誤差成分をゼロに近い状態まで除去するＣＲ回路３と、このＣＲ回路３で残留した位相誤差を補正して出力端子５に出力する位相不確定性除去回路４とを備えている。   In the block diagram of the demodulating circuit shown in FIG. 6, the demodulating circuit is a frequency error of the carrier wave between the transmitting side and the receiving side included in the received modulation signal input from the input terminal 1, as in the first embodiment. The AFC circuit 2 that removes the component to near zero and the output from the AFC circuit 2 are input, and the phase error component of the carrier wave between the transmitting side and the receiving side included in the received modulation signal is close to zero. A CR circuit 3 that removes the state, and a phase uncertainty removing circuit 4 that corrects a phase error remaining in the CR circuit 3 and outputs the corrected phase error to the output terminal 5.

ここで、ＡＦＣ回路２は、図１に示す実施の形態１のＡＦＣ回路２における周波数誤差検出器２２およびループフィルタ２３の代わりに、周波数偏差推定回路２５を設け、ＡＦＣ回路２をフィードバックループではなく、フィードフォワードループとして動作させるようにしている。
周波数偏差推定回路２５は、例えば、受信変調信号における最新のシンボルと、記憶した過去のシンボルとの遅延検波を実施することで、最新シンボルと過去シンボルとの位相差を検出し、検出した位相差を１シンボルあたりの位相差に変換することで周波数偏差を推定する。なお、複素乗算器２１および数値制御発振器（ＮＣＯ）２４は、実施の形態１の発明と同じにつき、説明は省略する。この実施の形態２における発明のＡＦＣ回路２も、従来の復調回路で設けられていた周波数同期・非同期を検出する同期判定回路は備えられていない。
また、ＣＲ回路３および位相不確定性除去回路４も、実施の形態１の発明と同じにつき、説明は省略する。 Here, the AFC circuit 2 is provided with a frequency deviation estimation circuit 25 instead of the frequency error detector 22 and the loop filter 23 in the AFC circuit 2 of the first embodiment shown in FIG. 1, and the AFC circuit 2 is not a feedback loop. It is made to operate as a feed forward loop.
For example, the frequency deviation estimation circuit 25 detects the phase difference between the latest symbol and the past symbol by performing delay detection between the latest symbol in the received modulation signal and the stored past symbol, and detects the detected phase difference. Is converted into a phase difference per symbol to estimate the frequency deviation. The complex multiplier 21 and the numerically controlled oscillator (NCO) 24 are the same as those in the first embodiment, and the description thereof is omitted. The AFC circuit 2 of the invention according to the second embodiment also does not include a synchronization determination circuit for detecting frequency synchronization / asynchronism provided in the conventional demodulation circuit.
The CR circuit 3 and the phase uncertainty removing circuit 4 are also the same as those in the first embodiment, and the description thereof is omitted.

次に、ＡＦＣ回路２の動作について説明する。ＡＦＣ回路２において、入力端子１に入力されたＩチャンネルとＱチャンネルの受信変調信号は周波数誤差がゼロに近づいた状態にまで補正される。
まず、周波数偏差推定回路２５は、回路内にメモリを設け、入力された受信変調信号を必要分だけ過去に遡って保存できるようにしておく。次に、入力された最新の受信変調信号とメモリに保存しておいた過去の受信変調信号との遅延検波を実施する。ここで過去とはＮシンボル前とする。この処理により、Ｎシンボル前から現在までの時間で位相がどれだけ回転したかを検出できる。検出した位相回転量を１シンボルあたりの位相差に変換することで周波数偏差を推定する。 Next, the operation of the AFC circuit 2 will be described. In the AFC circuit 2, the received modulation signals of the I channel and the Q channel inputted to the input terminal 1 are corrected to a state where the frequency error approaches zero.
First, the frequency deviation estimation circuit 25 is provided with a memory in the circuit so that the input received modulation signal can be stored retroactively by a necessary amount. Next, delayed detection of the latest received modulation signal input and the past received modulation signal stored in the memory is performed. Here, the past is N symbols before. By this processing, it is possible to detect how much the phase has rotated in the time from N symbols before to the present. The frequency deviation is estimated by converting the detected phase rotation amount into a phase difference per symbol.

次に、数値制御発振器(ＮＣＯ)２４は、周波数偏差推定回路２５で推定された周波数偏差（誤差）をテーブルなどにより複素数に変換する。最後に、複素乗算器２１において、入力された受信変調信号と複素数に変換された周波数偏差情報との複素乗算を行い、周波数偏差（誤差）を補正した受信変調信号を得る。ＡＦＣ回路２では、上記の動作を繰り返すことにより、補正後の受信変調信号における残留周波数誤差をゼロに近づける。
ＡＦＣ回路２において周波数誤差がゼロに近づいた状態にまで補正された後、後段のＣＲ回路３に出力される。ＣＲ回路３において位相誤差の補正が行なわれ、さらにＣＲ回路３で残留した位相誤差を位相不確定性除去回路４で取り除く動作は実施の形態１と同様である。 Next, the numerically controlled oscillator (NCO) 24 converts the frequency deviation (error) estimated by the frequency deviation estimation circuit 25 into a complex number using a table or the like. Finally, the complex multiplier 21 performs complex multiplication of the received reception modulation signal and the frequency deviation information converted into a complex number to obtain a reception modulation signal in which the frequency deviation (error) is corrected. In the AFC circuit 2, the residual frequency error in the received modulation signal after correction is brought close to zero by repeating the above operation.
After the AFC circuit 2 corrects the frequency error to near zero, it is output to the subsequent CR circuit 3. The operation in which the phase error is corrected in the CR circuit 3 and the phase error remaining in the CR circuit 3 is removed by the phase uncertainty removing circuit 4 is the same as in the first embodiment.

この実施の形態２の発明によれば、周波数誤差情報をフィードバックすることなく周波数偏差を推定するため、フィードバック型ＡＦＣ回路に比べて収束時間が短縮され、復調回路としての収束時間も短縮することができる。   According to the second embodiment, since the frequency deviation is estimated without feeding back the frequency error information, the convergence time is shortened compared with the feedback type AFC circuit, and the convergence time as the demodulation circuit can be shortened. it can.

実施の形態３．
次に、この発明の実施の形態３における復調回路を図面に基づいて説明する。図７はこの発明の実施の形態３における復調回路のブロック図である。
実施の形態１の発明では、ＣＲ回路として位相誤差を検出し、その情報をフィードバックすることで位相誤差を減らしていくフィードバック型ＣＲ回路を用いていたが、実施の形態３における発明は適応フィルタを応用したＣＲ回路３を用いたものである。このＣＲ回路３は、位相誤差だけでなく振幅誤差もフィードバックさせることで、位相誤差と同時に振幅誤差を補正する。 Embodiment 3 FIG.
Next, a demodulation circuit according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram of a demodulation circuit according to Embodiment 3 of the present invention.
In the invention of the first embodiment, the feedback type CR circuit that detects the phase error as the CR circuit and reduces the phase error by feeding back the information is used. However, the invention in the third embodiment uses an adaptive filter. The applied CR circuit 3 is used. The CR circuit 3 corrects the amplitude error simultaneously with the phase error by feeding back not only the phase error but also the amplitude error.

図７に示す復調回路のブロック図において、復調回路は実施の形態１の発明と同様に、入力端子１から入力される受信変調信号に含まれる送信側と受信側との間の搬送波の周波数誤差成分をゼロに近い状態まで除去するＡＦＣ回路２と、このＡＦＣ回路２からの出力を入力して、受信変調信号に含まれる送信側と受信側との間の搬送波の位相誤差成分をゼロに近い状態まで除去するＣＲ回路３と、このＣＲ回路３で残留した位相誤差を補正して出力端子５に出力する位相不確定性除去回路４とを備えている。   In the block diagram of the demodulating circuit shown in FIG. 7, the demodulating circuit is a frequency error of the carrier wave between the transmitting side and the receiving side included in the received modulation signal input from the input terminal 1, as in the first embodiment. The AFC circuit 2 that removes the component to near zero and the output from the AFC circuit 2 are input, and the phase error component of the carrier wave between the transmitting side and the receiving side included in the received modulation signal is close to zero. A CR circuit 3 that removes the state, and a phase uncertainty removing circuit 4 that corrects a phase error remaining in the CR circuit 3 and outputs the corrected phase error to the output terminal 5.

ここで、ＣＲ回路３は、図１に示す実施の形態１のＣＲ回路３における位相誤差検出器３２およびループフィルタ３３の代わりに、基準点との比較回路３５および適応フィルタ３６を備えている。基準点との比較回路３５は、既知パターンを基準点とし、実際の受信変調信号との位相誤差および振幅誤差を同時に検出する。また適応フィルタ３６は、基準点との比較回路３５にて検出された振幅誤差および位相誤差をゼロに近づけるための振幅補正値および位相補正値を生成する。   Here, the CR circuit 3 includes a reference point comparison circuit 35 and an adaptive filter 36 instead of the phase error detector 32 and the loop filter 33 in the CR circuit 3 of the first embodiment shown in FIG. The reference point comparison circuit 35 uses the known pattern as a reference point, and simultaneously detects the phase error and amplitude error from the actual received modulation signal. The adaptive filter 36 generates an amplitude correction value and a phase correction value for bringing the amplitude error and the phase error detected by the reference point comparison circuit 35 close to zero.

なお、複素乗算器３１は、実施の形態１の発明と同じにつき、説明は省略する。この実施の形態３における発明のＣＲ回路３も、従来の復調回路で設けられていた位相同期・非
同期を検出する同期判定回路は備えられていない。
また、ＡＦＣ回路２は実施の形態２の発明と同じものを用いているが、実施の形態１のＡＦＣ回路を用いてもよい。更に位相不確定性除去回路４も実施の形態１と同じにつき、それらの説明は省略する。 The complex multiplier 31 is the same as that of the first embodiment and will not be described. The CR circuit 3 of the invention according to the third embodiment also does not include a synchronization determination circuit for detecting phase synchronization / asynchronism provided in the conventional demodulation circuit.
Further, although the same AFC circuit 2 as that of the invention of the second embodiment is used, the AFC circuit of the first embodiment may be used. Further, since the phase uncertainty removing circuit 4 is the same as that of the first embodiment, the description thereof is omitted.

次に、ＣＲ回路３の動作について説明する。図７に示した構成において、ＡＦＣ回路２において周波数誤差がゼロに近づいた状態にまで補正された後、後段のＣＲ回路３に出力される。ＣＲ回路３では、基準点との比較回路３５において、既知パターンを基準点とし、実際の受信信号との位相誤差および振幅誤差を同時に検出する。   Next, the operation of the CR circuit 3 will be described. In the configuration shown in FIG. 7, after the AFC circuit 2 corrects the frequency error to near zero, it is output to the CR circuit 3 in the subsequent stage. In the CR circuit 3, the comparison circuit 35 with the reference point detects the phase error and the amplitude error with respect to the actual received signal at the same time using the known pattern as the reference point.

つづいて、適応フィルタ３６において、基準点との比較回路３５にて検出された受信信号と基準点との振幅誤差および位相誤差をゼロに近づけるための振幅補正値および位相補正値を生成する。ここで、適応フィルタ３６におけるアルゴリズムとしてＬＭＳアルゴリズムを用いることとし、適応フィルタ３６は受信フレーム中の既知パターン領域のみで動作させることとする。適応フィルタ３６が収束するに従い、複素乗算器３１の出力として、固定の位相回転量を有する信号が得られる。この固定の位相回転量が位相不確定性（位相誤差）であり、次の位相不確定性除去回路４で取り除く。ＣＲ回路３で残留した位相誤差を位相不確定性除去回路４で取り除く動作は実施の形態１と同様であるので、説明は省略する。   Subsequently, the adaptive filter 36 generates an amplitude correction value and a phase correction value for making the amplitude error and phase error between the received signal detected by the reference point comparison circuit 35 and the reference point close to zero. Here, the LMS algorithm is used as the algorithm in the adaptive filter 36, and the adaptive filter 36 is operated only in the known pattern region in the received frame. As the adaptive filter 36 converges, a signal having a fixed amount of phase rotation is obtained as the output of the complex multiplier 31. This fixed amount of phase rotation is phase uncertainty (phase error), which is removed by the next phase uncertainty removal circuit 4. Since the operation of removing the phase error remaining in the CR circuit 3 by the phase uncertainty removing circuit 4 is the same as that of the first embodiment, the description thereof is omitted.

この実施の形態３の発明によれば、ＣＲ回路３において、基準点と受信変調信号との位相誤差だけなく振幅誤差を検出し、位相誤差および振幅誤差がゼロに近づくように動作するので、振幅方向への誤差を含んだ伝送路において、その振幅方向への変動に追従することができ、受信特性の改善を実現できる。   According to the third embodiment of the present invention, the CR circuit 3 detects not only the phase error between the reference point and the received modulation signal but also the amplitude error, and operates so that the phase error and the amplitude error approach zero. In a transmission line including an error in the direction, it is possible to follow the fluctuation in the amplitude direction, and it is possible to improve reception characteristics.

この発明の実施の形態１における復調回路のブロック図である。It is a block diagram of the demodulation circuit in Embodiment 1 of this invention. この発明の復調回路を構成するＡＦＣ回路における周波数誤差の補正方法を示す図である。It is a figure which shows the correction method of the frequency error in the AFC circuit which comprises the demodulation circuit of this invention. この発明の復調回路を構成するＣＲ回路における位相誤差の補正方法を示す図である。It is a figure which shows the correction method of the phase error in CR circuit which comprises the demodulation circuit of this invention. この発明の復調回路を構成するＣＲ回路の出力である位相不確定性の発生例を示す図である。It is a figure which shows the example of generation | occurrence | production of the phase uncertainty which is an output of CR circuit which comprises the demodulation circuit of this invention. この発明の復調回路を構成する位相不確定性除去回路の一構成例を示すブロック図である。It is a block diagram which shows one structural example of the phase uncertainty removal circuit which comprises the demodulation circuit of this invention. この発明の実施の形態２における復調回路のブロック図である。It is a block diagram of the demodulation circuit in Embodiment 2 of this invention. この発明の実施の形態３における復調回路のブロック図である。It is a block diagram of the demodulation circuit in Embodiment 3 of this invention. 従来の復調回路の一構成例を示す概略ブロック図である。It is a schematic block diagram which shows the example of 1 structure of the conventional demodulation circuit.

符号の説明Explanation of symbols

１．入力端子、 ２．ＡＦＣ回路、
３．ＣＲ回路、 ４．位相不確定性除去回路、
５．出力端子、 ２１．複素乗算器、
２２．周波数誤差検出器、 ２３．ループフィルタ、
２４．数値制御発振器（ＮＣＯ）、 ２５．周波数偏差推定回路、
３１．複素乗算器、 ３２．位相誤差検出器、
３３．ループフィルタ、 ３４．数値制御発振器（ＮＣＯ）、
３５．基準点との比較回路、 ３６．適応フィルタ。 1. 1. Input terminal AFC circuit,
3. CR circuit, 4. Phase uncertainty removal circuit,
5. Output terminal, 21. Complex multiplier,
22. Frequency error detector, 23. Loop filter,
24. Numerically controlled oscillator (NCO), 25. Frequency deviation estimation circuit,
31. Complex multiplier, 32. Phase error detector,
33. Loop filter, 34. Numerically controlled oscillator (NCO),
35. 35. Comparison circuit with reference point Adaptive filter.

Claims (7)

受信変調信号に含まれる送信側と受信側との間の搬送波の周波数誤差成分を検出し、前記受信変調信号から周波数誤差成分を除去する自動周波数制御回路と、この自動周波数制御回路からの出力を入力して、前記受信変調信号に含まれる送信側と受信側との間の搬送波の位相誤差成分を検出し、前記受信変調信号から位相誤差成分を除去するキャリア再生回路と、このキャリア再生回路で残留した位相誤差を補正する位相不確定性除去回路とを備えたことを特徴とする復調回路。   An automatic frequency control circuit that detects a frequency error component of a carrier wave between the transmission side and the reception side included in the reception modulation signal and removes the frequency error component from the reception modulation signal, and an output from the automatic frequency control circuit A carrier recovery circuit that detects a phase error component of a carrier wave between the transmission side and the reception side included in the reception modulation signal and removes the phase error component from the reception modulation signal; and A demodulation circuit comprising: a phase uncertainty removing circuit that corrects a residual phase error. 位相不確定性除去回路は、受信変調信号に含まれる既知パターンと受信変調信号との相関を取ることで位相誤差量を推定し、この推定した位相誤差量を補正することで位相不確定性を除去するようにした請求項１に記載の復調回路。   The phase uncertainty removal circuit estimates the phase error amount by correlating the known pattern included in the received modulation signal with the received modulation signal, and corrects the estimated phase error amount to correct the phase uncertainty. 2. The demodulation circuit according to claim 1, wherein the demodulation circuit is eliminated. 位相不確定性除去回路は、受信変調信号に含まれる既知パターンと受信変調信号との相関を取り、１）位相回転なし、２）位相π／２回転、３）位相π回転、４）位相３π／２回転の４つの位相誤差量を推定する相関回路と、この相関回路で推定した位相誤差量に基づき、前記受信変調信号およびこの受信変調信号を反転した反転受信変調信号から推定した位相誤差量を補正して出力する選択回路とを備えてなる請求項２に記載の復調回路。   The phase uncertainty removing circuit correlates the known pattern included in the received modulation signal with the received modulation signal, 1) no phase rotation, 2) phase π / 2 rotation, 3) phase π rotation, and 4) phase 3π. A correlation circuit that estimates four phase error amounts of two rotations, and a phase error amount estimated from the received modulation signal and an inverted reception modulation signal obtained by inverting the received modulation signal based on the phase error amount estimated by the correlation circuit The demodulation circuit according to claim 2, further comprising: a selection circuit that corrects and outputs the signal. 自動周波数制御回路は、入力された受信変調信号と過去の受信変調信号との比較により１シンボル当たりの周波数誤差を検出する周波数誤差検出器と、この周波数誤差検出器で検出された周波数誤差を平均化するループフィルタと、このループフィルタで平均化された周波数誤差を複素数に変換する数値制御発振器と、前記入力された受信変調信号と前記数値制御発振器で変換された複素数の平均化周波数誤差との複素乗算を行い、前記周波数誤差を補正する複素乗算器とを備えてなる請求項１または請求項２に記載の復調回路。   The automatic frequency control circuit detects a frequency error per symbol by comparing the input received modulation signal with a past received modulation signal, and averages the frequency error detected by the frequency error detector. A loop filter to be converted, a numerically controlled oscillator that converts a frequency error averaged by the loop filter into a complex number, and an input received modulation signal and a complex averaged frequency error converted by the numerically controlled oscillator. The demodulation circuit according to claim 1, further comprising a complex multiplier that performs complex multiplication and corrects the frequency error. 自動周波数制御回路は、入力された受信変調信号における最新のシンボルと過去の受信変調信号におけるシンボルとの遅延検波を実施して、最新シンボルと過去シンボルとの位相差を検出し、この検出した位相差を１シンボル当たりの位相差に変換することで周波数誤差を推定する周波数偏差推定回路と、この周波数偏差推定回路で推定した周波数誤差を複素数に変換する数値制御発振器と、前記入力された受信変調信号と前記数値制御発振器で複素数に変換された周波数誤差との複素乗算を行い、前記周波数誤差を補正する複素乗算器とを備えてなる請求項１または請求項２に記載の復調回路。   The automatic frequency control circuit detects the phase difference between the latest symbol and the past symbol by performing delay detection between the latest symbol in the input received modulation signal and the symbol in the past received modulation signal. A frequency deviation estimation circuit that estimates a frequency error by converting a phase difference into a phase difference per symbol, a numerically controlled oscillator that converts a frequency error estimated by the frequency deviation estimation circuit into a complex number, and the received reception modulation The demodulation circuit according to claim 1, further comprising: a complex multiplier that performs complex multiplication of a signal and a frequency error converted into a complex number by the numerically controlled oscillator, and corrects the frequency error. キャリア再生回路は、入力された周波数誤差補正後の受信変調信号と基準点との比較を行い、前記受信変調信号と基準点との位相誤差を算出する位相誤差検出器と、この位相誤差検出器で算出された位相誤差を平均化するループフィルタと、このループフィルタで平均化された位相誤差を複素数に変換する数値制御発振器と、前記入力された周波数誤差補正後の受信変調信号と前記数値制御発振器で変換された複素数の平均化位相誤差との複素乗算を行い、前記位相誤差を補正する複素乗算器とを備えてなる請求項１または請求項２に記載の復調回路。   The carrier recovery circuit compares the input received modulation signal after frequency error correction with a reference point, calculates a phase error between the received modulation signal and the reference point, and the phase error detector A loop filter that averages the phase error calculated in step (b), a numerically controlled oscillator that converts the phase error averaged by the loop filter into a complex number, the received reception signal after frequency error correction, and the numerical control The demodulation circuit according to claim 1, further comprising a complex multiplier that performs complex multiplication with an averaged phase error of a complex number converted by an oscillator and corrects the phase error. キャリア再生回路は、入力された周波数誤差補正後の受信変調信号と基準点との比較を行い、前記受信変調信号と基準点との位相誤差および振幅誤差を検出する比較回路と、この比較回路で検出された前記受信変調信号と基準点との位相誤差および振幅誤差をゼロに近づけるための位相補正値および振幅補正値を生成する適応フィルタと、この適応フィルタで生成した位相補正値および振幅補正値と前記入力された周波数誤差補正後の受信変調信号との複素乗算を行い、前記位相誤差および振幅誤差を補正する複素乗算器とを備えてなる請求項１または請求項２に記載の復調回路。   The carrier recovery circuit compares the received modulated signal after frequency error correction with a reference point and detects a phase error and an amplitude error between the received modulated signal and the reference point. An adaptive filter for generating a phase correction value and an amplitude correction value for bringing the detected phase error and amplitude error between the received modulation signal and a reference point close to zero, and a phase correction value and an amplitude correction value generated by the adaptive filter The demodulation circuit according to claim 1, further comprising: a complex multiplier that performs complex multiplication between the received frequency-corrected received modulation signal and the phase error and amplitude error.
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