JP2009267224A - Laminated type semiconductor device and its manufacturing method - Google Patents

Laminated type semiconductor device and its manufacturing method Download PDF

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JP2009267224A
JP2009267224A JP2008117088A JP2008117088A JP2009267224A JP 2009267224 A JP2009267224 A JP 2009267224A JP 2008117088 A JP2008117088 A JP 2008117088A JP 2008117088 A JP2008117088 A JP 2008117088A JP 2009267224 A JP2009267224 A JP 2009267224A
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wiring
semiconductor device
post
mother substrate
stacked
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Masamichi Ishihara
政道 石原
Hirotaka Ueda
弘孝 上田
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Kyushu Institute of Technology NUC
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Abstract

<P>PROBLEM TO BE SOLVED: To allow small profile without the need for securing height space by a wire loop, by adopting a metal particle wiring, rather than a wire bond for the wiring of the semiconductor element, at least on the uppermost layer. <P>SOLUTION: On a mother board, there are formed a bonding pad region and a wiring connecting therebetween. A plurality of semiconductor elements are shifted by layer, at least in one direction to be laminated and adhered. The level difference parts that are formed by shifting each layer are coated with an insulating material to make the level differences reduce. On the inclined parts where the level differences are reduced, necessary parts in the bonding pad regions that are formed respectively in each layer of semiconductor elements and the mother board are wired. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、複数個の半導体素子をマザー基板上に積層搭載した積層型半導体装置及びその製造方法に関する。   The present invention relates to a stacked semiconductor device in which a plurality of semiconductor elements are stacked and mounted on a mother substrate, and a manufacturing method thereof.

基板上に、複数の半導体素子を積層搭載して、樹脂封止した積層型半導体装置が公知である（特許文献１，２参照）。図１０は、従来技術による積層型半導体装置を説明する図である。図において、下段LSIチップが、有機基板上にダイボンド材により接着されて、有機基板上の配線層とはボンディングワイヤにより接続されている。この下段LSIチップの上には、上段LSIチップが、スペーサチップ（或いはチップマウントのためのフィルムであるダイアタッチフィルム）を介して接着されている。この上段LSIチップもまた、基板上の配線層にボンディングワイヤにより接続されている。   A stacked semiconductor device in which a plurality of semiconductor elements are stacked and mounted on a substrate and sealed with a resin is known (see Patent Documents 1 and 2). FIG. 10 is a diagram for explaining a stacked semiconductor device according to the prior art. In the figure, a lower LSI chip is bonded to an organic substrate with a die bonding material, and is connected to a wiring layer on the organic substrate by a bonding wire. On the lower LSI chip, the upper LSI chip is bonded via a spacer chip (or a die attach film which is a film for chip mounting). This upper LSI chip is also connected to a wiring layer on the substrate by bonding wires.

しかし、従来技術では、ボンディングワイヤを用いることにより、上段LSIチップのワイヤループ高さが生じて、パッケージ高さが高くなるという問題があった。さらに、上段LSIチップのワイヤループ高さだけでなく、下段LSIチップのワイヤループ高さに相当する間隔を、積層するＬＳＩチップの間に開ける必要もあった。   However, the conventional technique has a problem that the wire loop height of the upper LSI chip is generated by using the bonding wire, and the package height is increased. Furthermore, not only the wire loop height of the upper LSI chip but also an interval corresponding to the wire loop height of the lower LSI chip needs to be opened between the stacked LSI chips.

また、有機基板を用いることにより、裏面の外部電極との接続が容易になるが、有機基板は、金属粒子配線（特許文献４参照）とは熱膨張係数が異なり温度サイクルの信頼度が確保できないために、有機基板上の配線層に金属粒子配線を用いることもできないという問題が生じる。一方、シリコン基板は、外部電極の形成のために、それを貫通する貫通電極を形成する必要があるが（特許文献３参照）、現在の貫通電極形成は低抵抗金属を充填するために低温処理が要求される一方、貫通孔の絶縁方法は、高温処理が必要となる。このように、半導体基板への貫通電極の形成とその絶縁方法にはまだ課題が残されていて、貫通電極を必要とせずに配線することが望まれる。
特開２００２−２９９５４７号公報 特開２００３−２４９６２１号公報 特開２００１−１２７２４３号公報 特開２００６−２１０８７２号公報 In addition, the use of the organic substrate facilitates connection with the external electrode on the back surface, but the organic substrate has a thermal expansion coefficient different from that of the metal particle wiring (see Patent Document 4), and cannot ensure the reliability of the temperature cycle. Therefore, there arises a problem that the metal particle wiring cannot be used for the wiring layer on the organic substrate. On the other hand, in order to form an external electrode, a silicon substrate needs to have a through electrode penetrating therethrough (see Patent Document 3). However, the current through electrode formation is performed at a low temperature in order to fill a low-resistance metal. On the other hand, the through hole insulation method requires high temperature treatment. As described above, there is still a problem in the formation of the through electrode on the semiconductor substrate and the insulation method thereof, and it is desired to perform wiring without requiring the through electrode.
JP 2002-299547 A JP 2003-249621 A JP 2001-127243 A JP 2006-210872 A

本発明は、少なくとも最上段のＬＳＩチップの配線にワイヤボンドではなく直描方式による金属粒子（インクジェットやペースト）配線を採用することにより、ワイヤループによる高さ空間を確保する必要がなく、低背化を可能にすることを目的としている。さらに、下段LSIチップの配線に、金属粒子配線を採用することにより、ワイヤループ高さに相当する間隔を、積層するＬＳＩチップの間に開ける必要を無くすことを目的としている。   The present invention employs metal particle (inkjet or paste) wiring by a direct drawing method instead of wire bonding for wiring of at least the uppermost LSI chip, so that it is not necessary to secure a height space by a wire loop and has a low profile. It aims to make it possible. Another object of the present invention is to eliminate the need to open an interval corresponding to the wire loop height between the stacked LSI chips by using metal particle wiring for the wiring of the lower LSI chip.

本発明の積層型半導体装置及びその製造方法は、複数個の半導体素子をマザー基板上に積層搭載して構成される。マザー基板上には、ボンディングパッド領域、及びそれらの間を接続する配線を形成する。複数個の半導体素子はそれぞれ、半導体基板面上にボンディングパッド領域を形成する。この複数個の半導体素子は、少なくとも一方向に、或いはそれに直交する方向との両方向に、１段ずつずらせながら複数段の半導体素子を積層して接着する。１段ずつずらせたことにより生じた段差部に絶縁材料を塗布して、段差を軽減させる。絶縁材料を塗布して段差を軽減させた傾斜部上で、各段半導体素子及びマザー基板のそれぞれに形成されているボンディングパッド領域の必要箇所間を配線する。   The stacked semiconductor device and the manufacturing method thereof of the present invention are configured by stacking and mounting a plurality of semiconductor elements on a mother substrate. On the mother substrate, bonding pad regions and wirings connecting them are formed. Each of the plurality of semiconductor elements forms a bonding pad region on the semiconductor substrate surface. The plurality of semiconductor elements are stacked and bonded while being shifted one step at least in one direction or in both directions orthogonal to the one direction. The step is reduced by applying an insulating material to the step formed by shifting by one step. Wiring is made between necessary portions of the bonding pad regions formed in each of the semiconductor elements and the mother substrate on the inclined portion where the step is reduced by applying an insulating material.

絶縁材料の塗布はインクジェット法或いはディスペンサーで行う。傾斜部上での各段半導体素子間の配線を、直描方式を用いて金属粒子配線で行ない、かつ、最下段半導体素子とマザー基板との間の配線は、金属粒子配線或いはボンディングワイヤにより行う。直描方式により形成された銅配線に対して、原子状水素により金属表面酸化膜の還元、及び又は有機物の除去の処理をすることにより、配線描画後の低抵抗化を図ることができる。   The insulating material is applied by an ink jet method or a dispenser. Wiring between each stage semiconductor element on the inclined portion is performed by metal particle wiring using a direct drawing method, and wiring between the lowermost semiconductor element and the mother substrate is performed by metal particle wiring or bonding wire. . By reducing the metal surface oxide film and / or removing organic substances with atomic hydrogen on the copper wiring formed by the direct drawing method, the resistance after wiring drawing can be reduced.

マザー基板上にはポスト領域を形成し、かつ、このポスト領域に、外部接続用の外部電極を接続したポスト電極を接続する。このポスト電極は、その複数個を支持部により一体に連結して構成した後、この一体に連結されているポスト電極をマザー基板のポスト領域に固定する。この状態で、マザー基板の上面を支持部の下面まで樹脂封止し、その後、支持部を剥離することにより、ポスト電極が電気的に個々に分離される。また、ポスト電極に接続される水平配線部を形成し、該水平配線部に外部電極が接続される。マザー基板は、シリコン基板或いは有機基板により構成される。   A post region is formed on the mother substrate, and a post electrode to which an external electrode for external connection is connected is connected to the post region. A plurality of the post electrodes are integrally connected by a support portion, and the integrally connected post electrodes are fixed to the post region of the mother substrate. In this state, the upper surface of the mother substrate is resin-sealed to the lower surface of the support portion, and then the support portion is peeled, whereby the post electrodes are electrically separated from each other. Further, a horizontal wiring portion connected to the post electrode is formed, and an external electrode is connected to the horizontal wiring portion. The mother substrate is composed of a silicon substrate or an organic substrate.

本発明によれば、ＬＳＩチップを斜めに配置し、階段状になる端部に金属粒子配線をするために、ワイヤループによる高さ空間を確保する必要がなく、積層ＬＳＩチップ間の間隔を最小にして、低背化が可能となる。さらに、下段LSIチップの配線に、金属粒子配線を採用することにより、ワイヤループ高さに相当する間隔を、積層するＬＳＩチップの間に開ける必要が無い。   According to the present invention, since the LSI chips are arranged obliquely and the metal particle wiring is provided at the stepped ends, it is not necessary to secure a height space by the wire loop, and the interval between the stacked LSI chips is minimized. Thus, it is possible to reduce the height. Further, by adopting the metal particle wiring for the wiring of the lower LSI chip, it is not necessary to open an interval corresponding to the wire loop height between the stacked LSI chips.

従来のシリコン基板では、マザー基板から外部電極を取り出すためには貫通電極かあるいは別のパッケージ構造を用いるしかなかったが、ポスト電極部品を適用することにより、シリコン基板に対して簡潔に外部電極が形成できる。   In the conventional silicon substrate, in order to take out the external electrode from the mother substrate, a through electrode or another package structure must be used. Can be formed.

マザー基板にシリコン基板を使うことにより、ＬＳＩチップとの熱膨張係数の差が少なく、信頼度が格段に向上する。また、マザー基板に有機基板を使うとＬＳＩチップ（シリコン）との熱膨張係数の差により、金属粒子配線が温度サイクル等で断線し易いが、マザー基板と最下段のＬＳＩチップの間の接続にワイヤボンドを用いることにより、マザー基板として有機基板の使用も可能になる。   By using a silicon substrate as the mother substrate, the difference in thermal expansion coefficient from the LSI chip is small, and the reliability is greatly improved. In addition, if an organic substrate is used as the mother substrate, the metal particle wiring is likely to be disconnected due to a temperature cycle due to the difference in thermal expansion coefficient from the LSI chip (silicon). However, the connection between the mother substrate and the lowermost LSI chip is difficult. By using a wire bond, an organic substrate can be used as a mother substrate.

以下、例示に基づき本発明を説明する。図１は、マザー基板上面の配線層を例示する図である。シリコン基板として例示したマザー基板上には、ポスト領域、ボンディングパッド領域、及びそれらの間を接続する配線が形成されている。最初に、マザー基板となるシリコン基板上に、ウエハ状態でウエハプロセス（すなわちリソグラフィ）を用いて配線層の形成をする。例えば、この配線層の形成は、シリコン基板上面にシード層を形成する（例えばスパッタ層あるいはナノ金属材料を塗膜）。その後にレジストを塗り、配線パターンに現像し、エッチングし、レジストを除去する。ポスト領域及びボンディングパッド領域は、配線層（通常複数層ある最上層）と一緒に形成する。そして、保護膜で覆った後に、これら領域を開口する。或いは、配線層を、ナノ金属粒子を用いた金属粒子配線で直接パターンニングすることもできる。この場合は、ポスト領域及びボンディングパッド領域も金属粒子配線で一緒に描画する。   Hereinafter, the present invention will be described based on examples. FIG. 1 is a diagram illustrating a wiring layer on the upper surface of the mother board. On the mother substrate exemplified as the silicon substrate, a post region, a bonding pad region, and a wiring connecting them are formed. First, a wiring layer is formed on a silicon substrate to be a mother substrate using a wafer process (that is, lithography) in a wafer state. For example, in the formation of this wiring layer, a seed layer is formed on the upper surface of the silicon substrate (for example, a sputtered layer or a nano metal material is coated). Thereafter, a resist is applied, developed into a wiring pattern, etched, and the resist is removed. The post region and the bonding pad region are formed together with a wiring layer (usually a plurality of uppermost layers). Then, after covering with a protective film, these regions are opened. Alternatively, the wiring layer can be directly patterned with metal particle wiring using nano metal particles. In this case, the post region and the bonding pad region are also drawn together with metal particle wiring.

図２（Ａ）は、マザー基板上に複数個（５段として例示）の半導体素子（ＬＳＩチップ）を接着し、かつ配線した状態で示す平面図であり、（Ｂ）はその側面図である。マザー基板（シリコン基板）上に、まず第１（最下段）のＬＳＩチップがダイボンド材により接着される。ＬＳＩチップは、半導体（例えばシリコン）基板上に、通常の半導体プロセス技術を用いて形成される。半導体基板上面（おもて面）には、アクティブ領域及び配線領域を含むＬＳＩ領域と、その周辺部にボンディングパッド領域が形成される。ボンディングパッド領域は、ウエハ製造完成時には、アルミニューム配線また銅配線であるため、ウエハ完成後にバリアメタル（例えば金スパッタ、或いは金メッキ）を施した後に、メッキ、半田等を行う。   FIG. 2A is a plan view showing a state in which a plurality of semiconductor elements (LSI chips are illustrated as five steps) are bonded and wired on a mother substrate, and FIG. 2B is a side view thereof. . First, the first (lowermost) LSI chip is bonded to the mother substrate (silicon substrate) with a die bond material. The LSI chip is formed on a semiconductor (for example, silicon) substrate using a normal semiconductor process technology. On the upper surface (front surface) of the semiconductor substrate, an LSI region including an active region and a wiring region, and a bonding pad region in the periphery thereof are formed. Since the bonding pad region is an aluminum wiring or a copper wiring at the completion of wafer manufacture, plating, soldering, etc. are performed after barrier metal (for example, gold sputtering or gold plating) is applied after the wafer is completed.

以下、同様にして、複数段のLSIチップを、１段ずつ接着する。この際、少なくとも一方向に、若しくはその両方向に少しずつずらせながら積み重ねる。図２は、横方向のみの傾斜部に配線した例を示すが、横方向に加えて、それに直交する方向の縦方向にも、或いは両方向の傾斜部に配線をすることもできる。全段を積層した後、段差部に絶縁材料（例えば、エポキシ系の材料）をインクジェット法或いはディスペンサー（絶縁材料を定量塗布する液体定量吐出装置）で塗布して、段差を軽減させる（傾斜した平坦面にする）。このインクジェット法は、後述する配線層形成のためのインクジェット法と同様な方法で、絶縁材料を塗布するものである。配線は、絶縁材料を塗布して段差を軽減させた傾斜部上で、各段LSIチップ及びマザー基板のそれぞれに形成されているボンディングパッド領域の必要箇所間を接続するように行う。配線は、金属粒子配線で行う。   Thereafter, similarly, a plurality of stages of LSI chips are bonded one by one. At this time, stacking is performed while shifting slightly in at least one direction or in both directions. FIG. 2 shows an example in which wiring is performed on the inclined portion only in the horizontal direction. However, in addition to the horizontal direction, wiring can also be performed in the vertical direction in the direction perpendicular to the horizontal direction, or in the inclined portions in both directions. After all the layers are stacked, an insulating material (for example, an epoxy-based material) is applied to the step portion by an ink jet method or a dispenser (a liquid quantitative dispensing device that applies a constant amount of the insulating material) to reduce the step (an inclined flat surface Face). In this ink jet method, an insulating material is applied in the same manner as the ink jet method for forming a wiring layer described later. Wiring is performed so as to connect between the necessary portions of the bonding pad regions formed on each of the LSI chips and the mother substrate on the inclined portion where the step is reduced by applying an insulating material. Wiring is performed by metal particle wiring.

金属粒子配線とは、インクジェット法或いはスクリーン印刷法のような直描方式で、配線層を、ナノ金属粒子で直接パターンニングする方法である（特許文献４参照）。有機溶媒中にナノ金属（銅、銀、金など）粒子が含有されており、それをプリンターで実用されているインクジェット法で所望のパターンを描く。その後、有機溶剤を蒸発させる熱処理が行われる。或いは、スクリーン印刷法の場合は、有機溶媒中にナノ金属粒子を含有させたナノペーストを、基板上にスクリーン印刷法で塗布した後、加熱焼成することにより、回路配線を形成することができる。   Metal particle wiring is a method of directly patterning a wiring layer with nano metal particles by a direct drawing method such as an ink jet method or a screen printing method (see Patent Document 4). Nano metal (copper, silver, gold, etc.) particles are contained in an organic solvent, and a desired pattern is drawn by an ink jet method that is practically used in a printer. Thereafter, a heat treatment for evaporating the organic solvent is performed. Alternatively, in the case of the screen printing method, a circuit wiring can be formed by applying a nano paste containing nano metal particles in an organic solvent on a substrate by a screen printing method, followed by heating and baking.

また、特許文献４に記載されているように、このような直描方式により形成された銅配線に対して、原子状水素により金属表面酸化膜の還元、及び又は有機物の除去の処理をすることにより、配線描画後の低抵抗化を図ることができる。   Further, as described in Patent Document 4, a copper wiring formed by such a direct drawing method is subjected to reduction of the metal surface oxide film and / or removal of organic substances by atomic hydrogen. Thus, it is possible to reduce the resistance after wiring drawing.

図３は、ポスト電極部品の例を示す図であり、（Ａ）及び（Ｂ）はそれぞれ単体パターンの側面断面図及び斜視図を示している。ポスト電極部品は、電鋳法を用いて、複数のポスト電極を導電性材料の支持部により一体に連結して構成される。なお、単体パターンとして例示したが、実際の製造においては、複数個連結した連結パターンとして作成して、製品完成直前に、チップ個片化のための切断を行って、製品として完成させることができる。ポスト電極は、例示したような円柱形状に限らず、矩形、多角形状等を含む柱状（棒状）形状であれば良い。   FIG. 3 is a view showing an example of a post electrode component, and (A) and (B) show a side sectional view and a perspective view of a single pattern, respectively. The post electrode component is configured by integrally connecting a plurality of post electrodes with a support portion made of a conductive material using an electroforming method. In addition, although illustrated as a single pattern, in actual manufacturing, it can be created as a connected pattern in which a plurality are connected, and can be completed as a product by cutting for chip separation immediately before product completion. . The post electrode is not limited to the cylindrical shape as illustrated, and may be a columnar (bar-shaped) shape including a rectangular shape, a polygonal shape, and the like.

電鋳法自体は、周知の加工法である。電鋳法とは「電気メッキ法による金属製品の製造・補修又は複製法」であって、基本的には電気メッキと同様であるが、メッキ厚、メッキ皮膜の分離操作を行う点が、電気メッキとは異なる。また、母型よりメッキ皮膜を剥離して使用する場合、メッキ皮膜の物性の制御・管理が重要ポイントとなる。本発明で用いる電鋳法により成長させる導電性材料のメッキ金属としては、ニッケルまたは銅とか、ニッケル合金、或いは銅合金を含む材料を用いることができる。本発明で用いる母型材質としては、一般的な導電性材料であるステンレスを用いることができるが、それ以外に、例えばベースにシリコン基板を用いて、その表面をメッキパターンが剥離し易いようにメッキ用の電気を通す程度の薄い酸化膜等の材料で覆ったものを用いることができる。内部応力の生じないようなメッキ浴の組成やメッキ条件を選定する必要があり、ニッケルメッキの場合、メッキ浴として、スルファミン酸ニッケル浴が利用されている。   The electroforming method itself is a well-known processing method. Electroforming is a method of manufacturing, repairing, or replicating metal products by electroplating, which is basically the same as electroplating, but the plating thickness and plating film are separated. Different from plating. Also, when the plating film is peeled off from the matrix, it is important to control and manage the physical properties of the plating film. As the plating metal of the conductive material grown by the electroforming method used in the present invention, nickel or copper, a nickel alloy, or a material containing a copper alloy can be used. As the matrix material used in the present invention, stainless steel, which is a general conductive material, can be used. In addition, for example, a silicon substrate is used as a base so that the plating pattern can be easily peeled off. A material covered with a material such as an oxide film that is thin enough to conduct electricity for plating can be used. It is necessary to select a plating bath composition and plating conditions that do not cause internal stress. In the case of nickel plating, a nickel sulfamate bath is used as the plating bath.

図１１は、フォトレジストを用いた電鋳部品の製造方法を示す工程図である。電鋳法は、図１１（ａ）に示すように、ステンレス等の母型の上面に、フォトレジスト（不導体被膜）を塗布する。次いで、パターンフィルムを通して露光するパターン焼き付け及びその後の現像により、非メッキ部分をフォトレジストパターンで覆った電鋳用原版を形成する（図１１（ｂ））。電鋳用原版のフォトレジストパターンの厚さは、製品（ポスト電極、或いは水平配線部）の厚さ以上であり、ポスト電極の場合は、ICのチップ厚より厚い、例えば50μｍから300μ前後の厚さとする。続いて、フォトレジストパターンの開口部にメッキ金属が形成される（図１１（ｃ））。適性温度に維持されたメッキ浴（例えば、スルフォミン酸ニッケル液）中に、陽極側に電鋳させようとする電鋳金属を入れ、陰極側にステンレス等の電鋳母型を配置する。陰極側の電鋳母型の表面上には、図１１（ｃ）に示すように、フォトレジストパターンが予め形成されている。電流を流すと、陽極側の電鋳金属が溶け出して、電鋳母型上のフォトレジストパターン開口部にメッキされる。   FIG. 11 is a process diagram showing a method for manufacturing an electroformed part using a photoresist. In the electroforming method, as shown in FIG. 11A, a photoresist (non-conductive coating) is applied to the upper surface of a mother die such as stainless steel. Next, an electroforming original plate in which the non-plated portion is covered with a photoresist pattern is formed by pattern printing exposed through a pattern film and subsequent development (FIG. 11B). The thickness of the photoresist pattern of the electroforming master is equal to or greater than the thickness of the product (post electrode or horizontal wiring part). In the case of the post electrode, it is thicker than the chip thickness of the IC, for example, a thickness of about 50 μm to about 300 μm. Say it. Subsequently, a plated metal is formed in the opening of the photoresist pattern (FIG. 11C). An electroformed metal to be electroformed on the anode side is placed in a plating bath (for example, nickel sulfamate solution) maintained at an appropriate temperature, and an electroforming mother mold such as stainless steel is disposed on the cathode side. On the surface of the electroforming mother mold on the cathode side, a photoresist pattern is formed in advance as shown in FIG. When a current is passed, the electroformed metal on the anode side melts and is plated on the opening of the photoresist pattern on the electroformed mother die.

次に、図１１（ｄ）に示すように、平坦化加工が行われる。次に、レジストを除去すると（図１１（ｅ））、レジスト部分以外がそのまま水平配線部やポスト電極のような配線部となる。そして、このメッキ金属を電鋳母型から剥離する（図１１（ｆ））。形成されたメッキ金属と支持部の剥がしが、熱や圧力で容易に行うことができるのが、電鋳法の特徴である。   Next, as shown in FIG. 11D, flattening is performed. Next, when the resist is removed (FIG. 11E), the portion other than the resist portion becomes a wiring portion such as a horizontal wiring portion or a post electrode as it is. Then, the plated metal is peeled off from the electroforming mother mold (FIG. 11 (f)). It is a feature of the electroforming method that the formed plated metal and the supporting part can be easily peeled off by heat or pressure.

水平配線部を必要としないときは、図１１（ａ）〜（ｄ）に示す工程によりポスト電極が作成可能であるが、図３に例示のように、水平配線部付きのポスト電極部品の製造のためには、図１１（ａ）〜（ｄ）に示す工程を２回繰り返し、最初の工程で、支持部上に水平配線部パターンを形成した後、２回目の工程で、水平配線部パターンに接続されるポスト電極を形成する。   When the horizontal wiring portion is not required, the post electrode can be created by the steps shown in FIGS. 11A to 11D. However, as illustrated in FIG. 3, the manufacture of the post electrode component with the horizontal wiring portion is illustrated. For this purpose, the steps shown in FIGS. 11A to 11D are repeated twice, and after the horizontal wiring pattern is formed on the support portion in the first step, the horizontal wiring portion pattern is formed in the second step. A post electrode connected to is formed.

図４は、図２に示すマザー基板上に、図３に示したポスト電極部品のポスト電極を固定し、接続した状態で示す図である。ポスト電極は、マザー基板の所定のポスト領域に、半田接続或いは銀ペースト等の導電性ペーストによる接続等により、固定されかつ電気的に接続される。ポスト電極がマザー基板の所定の位置に固定された段階では、全てのポスト電極が、板状の支持部により一体に連結されている。一体に連結されているポスト電極が固定された後、この状態で、マザー基板の上面は、支持部の下面までトランスファーモールドされ、或いは液状樹脂（材質は、例えばエポキシ系）を用いて樹脂封止される。   4 is a view showing a state in which the post electrode of the post electrode component shown in FIG. 3 is fixed and connected to the mother substrate shown in FIG. The post electrode is fixed and electrically connected to a predetermined post region of the mother substrate by solder connection or connection with a conductive paste such as silver paste. At the stage where the post electrodes are fixed at predetermined positions on the mother substrate, all the post electrodes are integrally connected by a plate-like support portion. After the integrally connected post electrodes are fixed, in this state, the upper surface of the mother substrate is transfer-molded to the lower surface of the support portion, or is resin-sealed using a liquid resin (material is, for example, epoxy) Is done.

図５は、支持部（電鋳母型）を剥離した後の状態で示す図である。支持部を剥離することにより、ポスト電極及びそれに接続された水平配線部が電気的に個々に分離される。   FIG. 5 is a view showing a state after the support portion (electroformed mother die) is peeled off. By peeling the support portion, the post electrode and the horizontal wiring portion connected to the post electrode are electrically separated from each other.

図６は、配線パターンの所定の位置（水平配線部の端部）に、外部接続用の外部電極（バンプ電極）を形成した後、上下反転させた状態で示す図である。但し、水平配線部を形成すること無く、ポスト電極の露出端を外部電極として用いること、或いはポスト電極の露出端にバンプ電極を形成して外部電極とすることも可能である。実際の製造においては、この後、チップ個片化のための切断を行って、製品として完成させる。これによって、ポスト電極の端面が水平配線部を介して外部電極に接続され、かつ複数段のLSIチップを積層搭載した積層型半導体装置が形成される。   FIG. 6 is a diagram showing a state in which an external electrode (bump electrode) for external connection is formed at a predetermined position (an end portion of the horizontal wiring portion) of the wiring pattern and is turned upside down. However, the exposed end of the post electrode can be used as an external electrode without forming a horizontal wiring portion, or a bump electrode can be formed on the exposed end of the post electrode to form an external electrode. In actual manufacturing, after that, cutting for chip separation is performed to complete the product. Thus, a stacked semiconductor device is formed in which the end surfaces of the post electrodes are connected to the external electrodes via the horizontal wiring portion, and a plurality of stages of LSI chips are stacked and mounted.

次に、本発明の積層型半導体装置の別の例を、図７〜図９を参照して説明する。図７は、図１に示すようなマザー基板上に最下段ＬＳＩチップを接着して配線した状態で示す図である。図７において、最下段LSIチップとマザー基板の間は、ボンディングワイヤにより接続（ワイヤボンド接続）されている。図８は、２段目以降最上段までのＬＳＩチップを積層した状態で示す図である。図２を参照して上述した方法と同様にして、全てのＬＳＩチップを積層した後、インクジェット法で段差部を絶縁材料により塗布し、その後、ＬＳＩチップ間の必要な配線を直描方式による金属粒子配線で3次元に行う。   Next, another example of the stacked semiconductor device of the present invention will be described with reference to FIGS. FIG. 7 is a diagram showing a state in which the lowermost LSI chip is bonded and wired on the mother substrate as shown in FIG. In FIG. 7, the lowermost LSI chip and the mother substrate are connected by a bonding wire (wire bond connection). FIG. 8 is a diagram showing a state in which LSI chips from the second stage to the uppermost stage are stacked. In the same manner as described above with reference to FIG. 2, after all the LSI chips are stacked, the stepped portion is coated with an insulating material by the ink jet method, and then the necessary wiring between the LSI chips is formed by a direct drawing method. 3D with particle wiring.

図９は、図６と同様に外部電極を形成した完成製品を示す図である。このように、最下段のＬＳＩチップのみワイヤボンド接続することにより、有機基板とシリコン基板（ＬＳＩチップ）との熱膨張係数差を緩和することが可能となるので、マザー基板に有機基板を用いることもできる。   FIG. 9 is a view showing a completed product in which external electrodes are formed as in FIG. Thus, by wire bonding only the bottom LSI chip, it becomes possible to alleviate the difference in thermal expansion coefficient between the organic substrate and the silicon substrate (LSI chip), so the organic substrate is used as the mother substrate. You can also.

多層または単層有機基板は、単層２層配線構造や複数層から成る基板の各層に、それぞれ配線パターンを形成した後これらの基板を貼り合わせ、必要に応じて各層の配線パターンを接続するためのスルーホールを形成したものである。このスルーホールの内部には導体層が形成され、この導体層が裏面側に形成された端面電極部であるランドと接続されている。基板裏面に外部電極を備えて、ランドを外部電極と接続することができる。このような有機基板を用いることにより、有機基板上の配線層と裏面の外部電極との接続が容易になる。   Multi-layer or single-layer organic substrates are used to form a wiring pattern on each layer of a single-layer two-layer wiring structure or a substrate composed of a plurality of layers, and then bond these substrates together to connect the wiring patterns of each layer as necessary. Through-holes are formed. A conductor layer is formed inside the through hole, and this conductor layer is connected to a land which is an end face electrode portion formed on the back surface side. An external electrode is provided on the back surface of the substrate, and the land can be connected to the external electrode. By using such an organic substrate, connection between the wiring layer on the organic substrate and the external electrode on the back surface is facilitated.

マザー基板上面の配線層を例示する図である。It is a figure which illustrates the wiring layer of a mother substrate upper surface. （Ａ）はマザー基板上に複数個（５段として例示）のＬＳＩチップを接着し、かつ配線した状態で示す平面図であり、（Ｂ）はその側面図である。(A) is a plan view showing a state in which a plurality of LSI chips (illustrated as five steps) are bonded and wired on a mother substrate, and (B) is a side view thereof. （Ａ）及び（Ｂ）はそれぞれポスト電極部品の単体パターンの側面断面図及び斜視図を示している。(A) And (B) has shown the side sectional drawing and perspective view of the single-piece | unit pattern of a post electrode component, respectively. 図２に示すマザー基板上に、図３に示したポスト電極部品のポスト電極を固定し、接続した状態で示す図である。FIG. 4 is a view showing a state in which the post electrodes of the post electrode parts shown in FIG. 3 are fixed and connected on the mother board shown in FIG. 2. 支持部（電鋳母型）を剥離した後の状態で示す図である。It is a figure shown in the state after peeling a support part (electrocasting mother mold). 配線パターンの所定の位置に、外部接続用の外部電極を形成した後、上下反転させた状態で示す図である。It is a figure shown in the state turned upside down after forming an external electrode for external connection at a predetermined position of a wiring pattern. 図１に示すようなマザー基板上に最下段ＬＳＩチップを接着して配線した状態で示す図である。FIG. 2 is a diagram showing a state in which a lowermost LSI chip is bonded and wired on a mother substrate as shown in FIG. 1. ２段目以降最上段までのＬＳＩチップを積層した状態で示す図である。It is a figure which shows in the state which laminated | stacked the LSI chip from the 2nd level to the highest level. 図６と同様にバンプ電極を形成した完成製品を示す図である。It is a figure which shows the completed product which formed the bump electrode similarly to FIG. 従来技術による積層型半導体装置を説明する図である。It is a figure explaining the laminated semiconductor device by a prior art. フォトレジストを用いた電鋳部品の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the electroformed part using a photoresist.

Claims (14)

複数個の半導体素子をマザー基板上に積層搭載した積層型半導体装置において、
マザー基板上には、ボンディングパッド領域及びそれらの間を接続する配線を形成し、
前記複数個の半導体素子はそれぞれ、ボンディングパッド領域を形成し、
前記複数個の半導体素子は、少なくとも一方向に、或いはそれに直交する方向との両方向に、１段ずつずらせながら複数段の半導体素子を積層して接着し、
１段ずつずらせたことにより生じた段差部に絶縁材料を塗布して、段差を軽減させ、
絶縁材料を塗布して段差を軽減させた傾斜部上で、各段半導体素子及びマザー基板のそれぞれに形成されているボンディングパッド領域の必要箇所間を配線することから成る積層型半導体装置。 In a stacked semiconductor device in which a plurality of semiconductor elements are stacked and mounted on a mother substrate,
On the mother substrate, a bonding pad region and wiring connecting them are formed,
Each of the plurality of semiconductor elements forms a bonding pad region,
The plurality of semiconductor elements are stacked and bonded to each other while shifting one step at a time in at least one direction or both directions perpendicular to the semiconductor element,
Applying an insulating material to the stepped part that is caused by shifting one step at a time, reducing the step,
A laminated semiconductor device comprising wiring between necessary portions of bonding pad regions formed on each of the semiconductor elements and the mother substrate on an inclined portion in which a step is reduced by applying an insulating material. 前記絶縁材料の塗布をインクジェット法或いはディスペンサーで行い、かつ、前記傾斜部上での配線を、直描方式を用いて金属粒子配線で行う請求項１に記載の積層型半導体装置。 The stacked semiconductor device according to claim 1, wherein the insulating material is applied by an ink jet method or a dispenser, and wiring on the inclined portion is performed by metal particle wiring using a direct drawing method. 前記傾斜部上での各段半導体素子間の配線を、直描方式を用いて金属粒子配線で行ない、かつ、最下段半導体素子とマザー基板との間の配線をボンディングワイヤにより接続する請求項２に記載の積層型半導体装置。 3. The wiring between the respective stage semiconductor elements on the inclined portion is performed by metal particle wiring using a direct drawing method, and the wiring between the lowermost semiconductor element and the mother substrate is connected by a bonding wire. 2. A stacked semiconductor device according to 1. 前記直描方式により形成された銅配線に対して、原子状水素により金属表面酸化膜の還元、及び又は有機物の除去の処理をすることにより、配線描画後の低抵抗化を図る請求項２に記載の積層型半導体装置。 3. The resistance after post-wiring is reduced by subjecting the copper wiring formed by the direct drawing method to reduction of the metal surface oxide film and removal of organic substances by atomic hydrogen. The stacked semiconductor device described. 前記マザー基板上にはポスト領域を形成し、かつ、このポスト領域に、外部接続用の外部電極を接続したポスト電極を接続し、該ポスト電極は、その複数個を支持部により一体に連結して構成した後、支持部を剥離することにより、ポスト電極が電気的に個々に分離される請求項１に記載の積層型半導体装置。 A post region is formed on the mother substrate, and a post electrode to which an external electrode for external connection is connected is connected to the post region, and a plurality of the post electrodes are integrally connected by a support portion. 2. The stacked semiconductor device according to claim 1, wherein the post electrodes are electrically separated from each other by peeling off the support portion after being configured. 前記ポスト電極に接続される水平配線部を形成し、該水平配線部に前記外部電極が接続される請求項５に記載の積層型半導体装置。 The stacked semiconductor device according to claim 5, wherein a horizontal wiring portion connected to the post electrode is formed, and the external electrode is connected to the horizontal wiring portion. 前記マザー基板は、シリコン基板或いは有機基板により構成される請求項１に記載の積層型半導体装置。 The stacked semiconductor device according to claim 1, wherein the mother substrate is formed of a silicon substrate or an organic substrate. 複数個の半導体素子をマザー基板上に積層搭載した積層型半導体装置の製造方法において、
マザー基板上には、ボンディングパッド領域及びそれらの間を接続する配線を形成し、
前記複数個の半導体素子はそれぞれ、ボンディングパッド領域を形成し、
前記複数個の半導体素子は、少なくとも一方向に、或いはそれに直交する方向との両方向に、１段ずつずらせながら複数段の半導体素子を積層して接着し、
１段ずつずらせたことにより生じた段差部に絶縁材料を塗布して、段差を軽減させ、
絶縁材料を塗布して段差を軽減させた傾斜部上で、各段半導体素子及びマザー基板のそれぞれに形成されているボンディングパッド領域の必要箇所間を配線することから成る積層型半導体装置の製造方法。 In a manufacturing method of a stacked semiconductor device in which a plurality of semiconductor elements are stacked and mounted on a mother substrate,
On the mother substrate, a bonding pad region and wiring connecting them are formed,
Each of the plurality of semiconductor elements forms a bonding pad region,
The plurality of semiconductor elements are stacked and bonded to each other while shifting one step at a time in at least one direction or both directions perpendicular to the semiconductor element,
Applying an insulating material to the stepped part that is caused by shifting one step at a time, reducing the step,
A method of manufacturing a stacked semiconductor device comprising wiring between necessary portions of bonding pad regions formed on each step semiconductor element and a mother substrate on an inclined portion in which a step is reduced by applying an insulating material . 前記絶縁材料の塗布をインクジェット法或いはディスペンサーで行い、かつ、前記傾斜部上での配線を、直描方式を用いて金属粒子配線で行う請求項８に記載の積層型半導体装置の製造方法。 The method for manufacturing a stacked semiconductor device according to claim 8, wherein the insulating material is applied by an inkjet method or a dispenser, and wiring on the inclined portion is performed by metal particle wiring using a direct drawing method. 前記傾斜部上での各段半導体素子間の配線を、直描方式を用いて金属粒子配線で行ない、かつ、最下段半導体素子とマザー基板との間の配線をボンディングワイヤにより接続する請求項９に記載の積層型半導体装置の製造方法。 10. The wiring between the respective stage semiconductor elements on the inclined portion is performed by metal particle wiring using a direct drawing method, and the wiring between the lowermost semiconductor element and the mother substrate is connected by a bonding wire. A method for manufacturing a stacked semiconductor device as described in 1. above. 前記直描方式により形成された銅配線に対して、原子状水素により金属表面酸化膜の還元、及び又は有機物の除去の処理をすることにより、配線描画後の低抵抗化を図る請求項９に記載の積層型半導体装置の製造方法。 The copper wiring formed by the direct drawing method is subjected to reduction of the metal surface oxide film and / or removal of organic substances by atomic hydrogen, thereby reducing resistance after wiring drawing. The manufacturing method of the laminated semiconductor device of description. 前記マザー基板上にはポスト領域を形成し、かつ、このポスト領域に、外部接続用の外部電極を接続したポスト電極を接続し、このポスト電極は、その複数個を支持部により一体に連結して構成した後、この一体に連結されているポスト電極を前記マザー基板のポスト領域に固定し、この状態で、マザー基板の上面を支持部の下面まで樹脂封止し、その後、支持部を剥離することにより、ポスト電極が電気的に個々に分離される請求項８に記載の積層型半導体装置の製造方法。 A post region is formed on the mother substrate, and a post electrode to which an external electrode for external connection is connected is connected to the post region, and a plurality of the post electrodes are integrally connected by a support portion. After this configuration, the integrally connected post electrode is fixed to the post region of the mother substrate, and in this state, the upper surface of the mother substrate is sealed with resin to the lower surface of the support portion, and then the support portion is peeled off. The method for manufacturing a stacked semiconductor device according to claim 8, wherein the post electrodes are electrically separated individually. 前記ポスト電極に接続される水平配線部を形成し、該水平配線部に前記外部電極が接続される請求項１２に記載の積層型半導体装置の製造方法。 The method for manufacturing a stacked semiconductor device according to claim 12, wherein a horizontal wiring portion connected to the post electrode is formed, and the external electrode is connected to the horizontal wiring portion. 前記マザー基板は、シリコン基板或いは有機基板により構成される請求項８に記載の積層型半導体装置の製造方法。 The method for manufacturing a stacked semiconductor device according to claim 8, wherein the mother substrate is formed of a silicon substrate or an organic substrate.
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