JP2009105163A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2009105163A
JP2009105163A JP2007274302A JP2007274302A JP2009105163A JP 2009105163 A JP2009105163 A JP 2009105163A JP 2007274302 A JP2007274302 A JP 2007274302A JP 2007274302 A JP2007274302 A JP 2007274302A JP 2009105163 A JP2009105163 A JP 2009105163A
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semiconductor layer
crystal
semiconductor
layer
semiconductor device
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Naoki Kusunoki
直樹 楠
Nobuaki Yasutake
信昭 安武
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Toshiba Corp
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    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66568—Lateral single gate silicon transistors
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having high carrier mobility in a channel region. <P>SOLUTION: The semiconductor device 1 is provided with a semiconductor substrate 2, a semiconductor layer 3 which is formed on the semiconductor substrate and is formed of first crystal whose inner carrier mobility is higher than a Si crystal, a gate insulting film 4 formed on the semiconductor layer, a gate electrode formed on the gate insulating film and source/drain regions which are formed by sandwiching the semiconductor layer, include second crystal giving distortion to the semiconductor layer in a direction where carrier mobility in the semiconductor layer rises and have source/drain extension regions being shallow regions which are brought into contact with the semiconductor layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

従来の半導体装置として、ｎ型トランジスタのチャネル領域を挟む位置に、Ｓｉ結晶よりも格子定数の小さいＳｉＣ結晶をエピタキシャル成長させることにより、チャネル領域に引張応力を加えて歪みを生じさせた半導体装置がある（例えば、特許文献１参照）。この特許文献１に記載の半導体装置によれば、チャネル領域を構成するＳｉ結晶に引張歪みを生じさせることにより、チャネル領域中の電子の移動度を向上させ、ｎ型トランジスタの動作速度を向上させることができる。   As a conventional semiconductor device, there is a semiconductor device in which strain is generated by applying tensile stress to the channel region by epitaxially growing a SiC crystal having a lattice constant smaller than that of the Si crystal at a position sandwiching the channel region of the n-type transistor. (For example, refer to Patent Document 1). According to the semiconductor device described in Patent Document 1, tensile strain is generated in the Si crystal constituting the channel region, thereby improving the mobility of electrons in the channel region and improving the operation speed of the n-type transistor. be able to.

また、従来の他の半導体装置として、内部の電子の移動度がＳｉ結晶よりも大きいＧｅ結晶をチャネル領域に使用する技術が知られている（例えば、非特許文献１参照）。
米国特許第６６２１１３１号明細書 S. Takagi et al., SSDM, p. 1056-1057 (2006). As another conventional semiconductor device, a technique is known in which a Ge crystal whose internal electron mobility is larger than that of a Si crystal is used for a channel region (see, for example, Non-Patent Document 1).
US Pat. No. 6,621,131 S. Takagi et al., SSDM, p. 1056-1057 (2006).

本発明の目的は、チャネル領域における高いキャリア移動度を有する半導体装置を提供することにある。   An object of the present invention is to provide a semiconductor device having high carrier mobility in a channel region.

本発明の一態様は、半導体基板と、前記半導体基板上に形成され、内部におけるキャリアの移動度がＳｉ結晶よりも大きい第１の結晶からなる半導体層と、前記半導体層上に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成されたゲート電極と、前記半導体層を挟んで形成され、前記半導体層に前記半導体層内のキャリアの移動度が上昇する方向に歪みを与える第２の結晶を含み、前記半導体層に接する深さの浅い領域であるソース・ドレインエクステンション領域を有するソース・ドレイン領域と、を有することを特徴とする半導体装置を提供する。   One embodiment of the present invention is a semiconductor substrate, a semiconductor layer formed over the semiconductor substrate and including a first crystal in which carrier mobility inside the Si crystal is larger than that of a Si crystal, and a gate formed over the semiconductor layer An insulating film, a gate electrode formed on the gate insulating film, and the semiconductor layer are sandwiched therebetween, and a second strain is applied to the semiconductor layer in a direction in which the mobility of carriers in the semiconductor layer increases. And a source / drain region having a source / drain extension region which is a shallow region in contact with the semiconductor layer.

本発明によれば、チャネル領域における高いキャリア移動度を有する半導体装置を提供することができる。   According to the present invention, a semiconductor device having high carrier mobility in a channel region can be provided.

〔第１の実施の形態〕
（半導体装置の構成）
図１は、本発明の第１の実施の形態に係る半導体装置の断面図である。半導体装置１は、半導体基板２と、半導体基板２上に形成された半導体層３と、半導体層３上に形成されたゲート絶縁膜４と、ゲート絶縁膜４上に形成されたゲート電極５と、ゲート電極５の側面に形成されたオフセットスペーサ６およびゲート側壁８と、半導体層３を挟んで形成されたエクステンション領域７ｅを含むエピタキシャル層７と、半導体基板２内に形成された素子分離領域１０と、を有して概略構成される。 [First Embodiment]
(Configuration of semiconductor device)
FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention. The semiconductor device 1 includes a semiconductor substrate 2, a semiconductor layer 3 formed on the semiconductor substrate 2, a gate insulating film 4 formed on the semiconductor layer 3, and a gate electrode 5 formed on the gate insulating film 4. The offset spacer 6 and the gate sidewall 8 formed on the side surface of the gate electrode 5, the epitaxial layer 7 including the extension region 7 e formed with the semiconductor layer 3 interposed therebetween, and the element isolation region 10 formed in the semiconductor substrate 2. And is schematically configured.

半導体基板２は、例えば、Ｓｉ基板が用いられる。   For example, a Si substrate is used as the semiconductor substrate 2.

半導体層３は、ＳｉＧｅ、Ｇｅ、ＧａＡｓ、ＩｎＰ、ＩｎＡｓ、ＩｎＳｂ等の、内部におけるキャリアの移動度がＳｉ結晶よりも大きい結晶からなる。なお、半導体層３がＳｉＧｅ結晶からなる場合は、Ｇｅ濃度が１０〜３０原子％であることが好ましい。ＳｉＧｅ結晶のＧｅ濃度が１０原子％未満の場合は、キャリアの移動度が効果的に上昇せず、３０原子％を超える場合は、隣接する結晶等に結晶欠陥を発生させ、リーク電流の原因となるおそれがある。   The semiconductor layer 3 is made of a crystal such as SiGe, Ge, GaAs, InP, InAs, InSb, or the like, in which the carrier mobility inside is larger than that of the Si crystal. When the semiconductor layer 3 is made of SiGe crystal, the Ge concentration is preferably 10 to 30 atomic%. When the Ge concentration of the SiGe crystal is less than 10 atomic%, the carrier mobility does not increase effectively, and when it exceeds 30 atomic%, a crystal defect is generated in an adjacent crystal or the like, causing a leakage current. There is a risk.

また、半導体層３は、半導体装置１の動作時に発生する反転層の厚さ以下の厚さを有することが好ましい。半導体層３を反転層よりも厚くしても、キャリアは反転層よりも厚い領域は移動せず、半導体装置１の動作速度はほとんど変わらないためである。また、半導体層３が、半導体基板２から受ける応力により内部におけるキャリアの移動度が低下する方向に歪みが生じる結晶である場合は、半導体層３を厚くするほどこの歪みが大きくなってキャリアの移動度が低下するためである。なお、反転層の厚さは、例えば２〜３ｎｍである。   The semiconductor layer 3 preferably has a thickness equal to or less than the thickness of the inversion layer generated during the operation of the semiconductor device 1. This is because even if the semiconductor layer 3 is thicker than the inversion layer, the carrier does not move in a region thicker than the inversion layer, and the operation speed of the semiconductor device 1 hardly changes. Further, when the semiconductor layer 3 is a crystal that is distorted in the direction in which the carrier mobility in the interior decreases due to the stress received from the semiconductor substrate 2, the thickness of the semiconductor layer 3 increases as the semiconductor layer 3 increases in thickness. This is because the degree decreases. Note that the thickness of the inversion layer is, for example, 2 to 3 nm.

ゲート絶縁膜４は、例えば、ＳｉＯ２、ＳｉＮ、ＳｉＯＮや、高誘電材料（例えば、ＨｆＳｉＯＮ、ＨｆＳｉＯ、ＨｆＯ等のＨｆ系材料、ＺｒＳｉＯＮ、ＺｒＳｉＯ、ＺｒＯ等のＺｒ系材料、Ｙ２Ｏ３等のＹ系材料）からなる。 The gate insulating film 4 is made of, for example, SiO 2 , SiN, SiON, high dielectric material (for example, Hf-based material such as HfSiON, HfSiO, HfO, Zr-based material such as ZrSiON, ZrSiO, ZrO, Y 2 O 3, etc. Y-based material).

ゲート電極５は、例えば、導電型不純物を含む多結晶Ｓｉまたは多結晶ＳｉＧｅからなる。ゲート電極５に含まれる導電型不純物には、ｐ型トランジスタの場合はＢ、ＢＦ２等のｐ型不純物イオン、ｎ型トランジスタの場合はＡｓ、Ｐ等のｎ型不純物イオンが用いられる。また、ゲート電極４は、Ｗ、Ｔａ、Ｔｉ、Ｈｆ、Ｚｒ、Ｒｕ、Ｐｔ、Ｉｒ、Ｍｏ、Ａｌ等やこれらの化合物等からなるメタルゲート電極であってもよい。また、メタルゲート電極と多結晶Ｓｉ系電極を積層した構造であってもよい。また、ゲート電極５の上面にシリサイド層が形成されてもよい。 The gate electrode 5 is made of, for example, polycrystalline Si or polycrystalline SiGe containing a conductive impurity. As the conductive impurities contained in the gate electrode 5, p-type impurity ions such as B and BF 2 are used in the case of a p-type transistor, and n-type impurity ions such as As and P are used in the case of an n-type transistor. Further, the gate electrode 4 may be a metal gate electrode made of W, Ta, Ti, Hf, Zr, Ru, Pt, Ir, Mo, Al or the like or a compound thereof. Moreover, the structure which laminated | stacked the metal gate electrode and the polycrystal Si type | system | group electrode may be sufficient. A silicide layer may be formed on the upper surface of the gate electrode 5.

オフセットスペーサ６は、例えば、ＳｉＯ２、ＳｉＮ等からなる。 The offset spacer 6 is made of, for example, SiO 2 or SiN.

ゲート側壁８は、例えばＳｉＮからなる単層構造や、ＳｉＮ、ＳｉＯ２、ＴＥＯＳ（Tetraethoxysilane）等の複数種の絶縁材料からなる２層構造、更には３層以上の構造であってもよい。 The gate sidewall 8 may have a single-layer structure made of, for example, SiN, a two-layer structure made of a plurality of kinds of insulating materials such as SiN, SiO 2 , TEOS (Tetraethoxysilane), or a structure having three or more layers.

エピタキシャル層７およびそのエクステンション領域７ｅは、ｐ型トランジスタの場合は、半導体基板２を構成する結晶よりも大きい格子定数を有する結晶をエピタキシャル成長させることにより形成する。例えば、半導体基板２がＳｉ結晶からなる場合は、ＳｉＧｅ結晶等をエピタキシャル成長させる。一方、ｎ型トランジスタの場合は、半導体基板２を構成する結晶よりも小さい格子定数を有する結晶をエピタキシャル成長させることにより形成する。例えば、半導体基板２がＳｉ結晶からなる場合は、ＳｉＣ結晶等をエピタキシャル成長させる。   In the case of a p-type transistor, the epitaxial layer 7 and its extension region 7e are formed by epitaxially growing a crystal having a lattice constant larger than that of the crystal constituting the semiconductor substrate 2. For example, when the semiconductor substrate 2 is made of Si crystal, SiGe crystal or the like is epitaxially grown. On the other hand, the n-type transistor is formed by epitaxially growing a crystal having a lattice constant smaller than that of the crystal constituting the semiconductor substrate 2. For example, when the semiconductor substrate 2 is made of Si crystal, SiC crystal or the like is epitaxially grown.

ここで、エピタキシャル層７およびエクステンション領域７ｅが半導体基板２を構成する結晶よりも大きい格子定数を有する結晶からなる場合は、エピタキシャル層７およびエクステンション領域７ｅがチャネル領域として働く半導体層３に圧縮歪みを与えて、半導体層３の内部の正孔の移動度を向上させることができる。一方、エピタキシャル層７およびエクステンション領域７ｅが半導体基板２を構成する結晶よりも小さい格子定数を有する結晶からなる場合は、エピタキシャル層７およびエクステンション領域７ｅがチャネル領域として働く半導体層３に引張歪みを与えて、半導体層３における電子の移動度を向上させることができる。   Here, when the epitaxial layer 7 and the extension region 7e are made of a crystal having a larger lattice constant than the crystal constituting the semiconductor substrate 2, the epitaxial layer 7 and the extension region 7e cause compressive strain on the semiconductor layer 3 that functions as a channel region. Thus, the mobility of holes inside the semiconductor layer 3 can be improved. On the other hand, when the epitaxial layer 7 and the extension region 7e are made of a crystal having a lattice constant smaller than that of the crystal constituting the semiconductor substrate 2, the epitaxial layer 7 and the extension region 7e give tensile strain to the semiconductor layer 3 serving as a channel region. Thus, the mobility of electrons in the semiconductor layer 3 can be improved.

なお、エピタキシャル層７およびエクステンション領域７ｅに用いられるＳｉＧｅ結晶のＧｅ濃度は１０〜３０原子％、ＳｉＣ結晶のＣ濃度は１〜３原子％であることが好ましい。ＳｉＧｅ結晶のＧｅ濃度が１０原子％未満の場合は、半導体層３に与える歪みが不十分となり、３０原子％を超える場合は、隣接する結晶等に結晶欠陥を発生させ、リーク電流の原因となるおそれがある。また、同様に、ＳｉＣ結晶のＣ濃度が１原子％未満の場合は、半導体層３に与える歪みが不十分となり、３原子％を超える場合は、隣接する結晶等に結晶欠陥を発生させ、リーク電流の原因となるおそれがある。   The Ge concentration of the SiGe crystal used for the epitaxial layer 7 and the extension region 7e is preferably 10 to 30 atomic%, and the C concentration of the SiC crystal is preferably 1 to 3 atomic%. When the Ge concentration of the SiGe crystal is less than 10 atomic%, the strain applied to the semiconductor layer 3 is insufficient, and when it exceeds 30 atomic%, a crystal defect is generated in an adjacent crystal or the like, causing a leakage current. There is a fear. Similarly, when the C concentration of the SiC crystal is less than 1 atomic%, the strain applied to the semiconductor layer 3 is insufficient, and when it exceeds 3 atomic%, a crystal defect is generated in an adjacent crystal or the like, causing leakage. May cause current.

また、エピタキシャル層７およびエクステンション領域７ｅは、導電型不純物を含み、ソース・ドレイン領域およびソース・ドレインエクステンション領域として機能する。エピタキシャル層７およびエクステンション領域７ｅに含まれる導電型不純物には、ｐ型トランジスタの場合はＢ、ＢＦ２等のｐ型不純物イオン、ｎ型トランジスタの場合はＡｓ、Ｐ等のｎ型不純物イオンが用いられる。また、エピタキシャル層７の上面にシリサイド層が形成されてもよい。 The epitaxial layer 7 and the extension region 7e contain a conductive impurity and function as a source / drain region and a source / drain extension region. As the conductive impurities contained in the epitaxial layer 7 and the extension region 7e, p-type impurity ions such as B and BF 2 are used for p-type transistors, and n-type impurity ions such as As and P are used for n-type transistors. It is done. A silicide layer may be formed on the upper surface of the epitaxial layer 7.

また、エピタキシャル層７から半導体層３へ効果的に応力が加わるようにするためには、エクステンション領域７ｅの下端が半導体層３の下端よりも深い位置にあることが好ましい。   In order to effectively apply stress from the epitaxial layer 7 to the semiconductor layer 3, the lower end of the extension region 7 e is preferably deeper than the lower end of the semiconductor layer 3.

また、エピタキシャル層７をエクステンション領域７ｅとそれ以外の深い領域の二段構造とする、すなわちソース・ドレイン領域のエクステンション領域とそれ以外の深い領域（ディープ領域）の両方にエピタキシャル結晶を含めることにより、ソース・ドレイン領域のディープ領域のみをエピタキシャル結晶で形成する場合と比較して、半導体層３により効果的に応力を加えることができる。   Further, the epitaxial layer 7 has a two-stage structure of the extension region 7e and the other deep region, that is, by including an epitaxial crystal in both the extension region of the source / drain region and the other deep region (deep region), Compared with the case where only the deep regions of the source / drain regions are formed by epitaxial crystals, stress can be applied more effectively by the semiconductor layer 3.

さらに、エピタキシャル層をエクステンション領域とそれ以外の深い領域の二段構造とする場合、一般的に、エクステンション領域の幅、深さ等を調節することにより、エピタキシャル層から半導体基板のゲート電極下の領域に加わる応力の大きさを変えることができる。   Furthermore, when the epitaxial layer has a two-stage structure of an extension region and a deep region other than that, generally, the region under the gate electrode of the semiconductor substrate is adjusted from the epitaxial layer by adjusting the width, depth, etc. of the extension region. The magnitude of the stress applied to can be changed.

図２（ａ）、（ｂ）は、参考例としての、半導体層３を有さない半導体装置１と等しい半導体装置１００における、エクステンション領域７ｅの幅、深さとエピタキシャル層７から半導体基板２のゲート電極５下の領域に加わる応力の大きさの関係を概略的に示す図およびグラフである。   2A and 2B show, as a reference example, the width and depth of the extension region 7e and the gate of the semiconductor substrate 2 from the epitaxial layer 7 in the semiconductor device 100 equal to the semiconductor device 1 that does not have the semiconductor layer 3. It is the figure and graph which show roughly the relationship of the magnitude | size of the stress added to the area | region under the electrode 5. FIG.

図２（ａ）に示すように、エクステンション領域７ｅのチャネル方向の幅をＸ、エクステンション領域７ｅの半導体基板２とゲート絶縁膜４との界面からの深さをＹとする。   As shown in FIG. 2A, the width of the extension region 7e in the channel direction is X, and the depth of the extension region 7e from the interface between the semiconductor substrate 2 and the gate insulating film 4 is Y.

図２（ｂ）のグラフは、横軸がＹ、縦軸がエピタキシャル層７から半導体基板２のゲート電極５下の領域に加わる応力の大きさである。この縦軸の応力の大きさは、ｎ型トランジスタの場合は引張応力の大きさ、ｐ型トランジスタの場合は、圧縮応力の大きさを表す。また、図中の２曲線は、それぞれＸを異なる所定の値に固定してＹを変化させたときの応力の大きさの変化を表している。   In the graph of FIG. 2B, the horizontal axis represents Y, and the vertical axis represents the magnitude of stress applied from the epitaxial layer 7 to the region under the gate electrode 5 of the semiconductor substrate 2. The magnitude of the stress on the vertical axis represents the magnitude of tensile stress in the case of an n-type transistor, and the magnitude of compressive stress in the case of a p-type transistor. In addition, two curves in the figure represent changes in the magnitude of stress when X is fixed at different predetermined values and Y is changed.

図２（ｂ）からわかるように、２曲線にはそれぞれ極大値があり、Ｘが大きくなるほど、極大値をとるＹの値が大きくなる。すなわち、エクステンション領域７ｅの幅（Ｘ）が大きくなるほど、エピタキシャル層７から半導体基板２のゲート電極５下の領域に加わる応力の大きさが最も大きくなるエクステンション領域７ｅの深さ（Ｙ）が大きくなる。   As can be seen from FIG. 2B, each of the two curves has a maximum value, and as X increases, the value of Y that takes the maximum value increases. That is, as the width (X) of the extension region 7e is increased, the depth (Y) of the extension region 7e at which the magnitude of the stress applied from the epitaxial layer 7 to the region under the gate electrode 5 of the semiconductor substrate 2 is the largest is increased. .

ここで、本実施の形態のように半導体層３が形成された場合の、半導体層３の下端の、半導体層３とゲート絶縁膜４との界面からの深さをＹ０とし、図２（ｂ）中に示す。上述したように、エピタキシャル層７から半導体層３へ効果的に応力が加わるようにするためには、エクステンション領域７ｅの下端が半導体層３の下端よりも深い位置にあることが好ましいため、ＹがＹ０よりも大きくなるような構成であることが好ましい。 Here, when the semiconductor layer 3 is formed as in the present embodiment, the depth from the interface between the semiconductor layer 3 and the gate insulating film 4 at the lower end of the semiconductor layer 3 is Y 0, and FIG. Shown in b). As described above, in order to effectively apply stress from the epitaxial layer 7 to the semiconductor layer 3, it is preferable that the lower end of the extension region 7 e is located deeper than the lower end of the semiconductor layer 3. it is preferred Y 0 is larger configuration than.

すなわち、エピタキシャル層７をエクステンション領域７ｅとそれ以外の深い領域の二段構造とし、エピタキシャル層７から半導体基板２のゲート電極５下の領域に加わる応力の大きさが最も大きくなるエクステンション領域７ｅの深さ（Ｙ）が、半導体層３の下端の、半導体層３とゲート絶縁膜４との界面からの深さ（Ｙ０）よりも大きくなるような構造を形成することが好ましい。 That is, the epitaxial layer 7 has a two-stage structure of the extension region 7e and other deep regions, and the depth of the extension region 7e where the magnitude of the stress applied from the epitaxial layer 7 to the region under the gate electrode 5 of the semiconductor substrate 2 is the largest. It is preferable to form a structure in which the length (Y) is larger than the depth (Y 0 ) from the interface between the semiconductor layer 3 and the gate insulating film 4 at the lower end of the semiconductor layer 3.

素子分離領域１０は、例えば、ＳｉＯ２等の絶縁材料からなり、ＳＴＩ（Shallow Trench Isolation）構造を有する。 The element isolation region 10 is made of an insulating material such as SiO 2 and has an STI (Shallow Trench Isolation) structure.

なお、半導体層３と、エクステンション領域７ｅを含むエピタキシャル層７の好ましい組み合わせは、半導体層３がＳｉＧｅ結晶等のＳｉ結晶よりも格子定数が大きく、内部のキャリア移動度がＳｉ結晶よりも大きい結晶、エピタキシャル層７がＳｉＣ結晶等のＳｉ結晶よりも格子定数が小さい結晶である組み合わせである。   A preferable combination of the semiconductor layer 3 and the epitaxial layer 7 including the extension region 7e is a crystal in which the semiconductor layer 3 has a larger lattice constant than a Si crystal such as a SiGe crystal, and has a larger internal carrier mobility than the Si crystal, The combination is such that the epitaxial layer 7 is a crystal having a lattice constant smaller than that of a Si crystal such as a SiC crystal.

以下に、特に好ましい例である、半導体層３がＳｉＧｅ結晶、エピタキシャル層７がＳｉＣ結晶である場合の、ｎ型トランジスタである半導体装置１についての詳細を以下に述べる。   Details of the semiconductor device 1 that is an n-type transistor when the semiconductor layer 3 is a SiGe crystal and the epitaxial layer 7 is a SiC crystal, which is a particularly preferable example, will be described below.

チャネル領域として働く半導体層３がＳｉＧｅ結晶である場合、ＳｉＧｅ結晶はＳｉ結晶よりも内部における電子の移動度が大きいため、トランジスタの駆動速度を向上させることができる。   When the semiconductor layer 3 serving as the channel region is a SiGe crystal, the SiGe crystal has higher electron mobility inside than the Si crystal, and thus the driving speed of the transistor can be improved.

しかし、一方、ＳｉＧｅ結晶はＳｉ結晶よりも格子定数が大きいため、Ｓｉ結晶からなる半導体基板２から応力を受けて圧縮歪みが発生する。圧縮歪みが発生すると、内部の電子の移動度が下がるため、ＳｉＧｅ結晶が本来有していた内部の電子の移動度が大きいという性質が弱まる、または打ち消されるおそれがある。   However, since the SiGe crystal has a larger lattice constant than the Si crystal, compressive strain is generated by receiving stress from the semiconductor substrate 2 made of Si crystal. When compressive strain occurs, the mobility of electrons inside decreases, so that the nature of the mobility of electrons inside the SiGe crystal originally is weakened or may be canceled.

図３（ａ）は、半導体層３に発生する歪みの大きさと、半導体層３の内部の電子の移動度との関係を概略的に表した模式図である。エピタキシャル層７がＳｉＣ結晶である場合、ＳｉＣ結晶はＳｉＧｅ結晶よりも格子定数が小さいため、半導体層３に引張歪みを発生させる。半導体層３に発生する引張歪みが大きくなるに伴い、内部の電子の移動度が大きくなるが、移動度の上昇はあるところで飽和する。この電子の移動度が飽和するときの歪みの大きさをδｍａｘとする。 FIG. 3A is a schematic diagram schematically illustrating the relationship between the magnitude of strain generated in the semiconductor layer 3 and the mobility of electrons inside the semiconductor layer 3. When the epitaxial layer 7 is a SiC crystal, the SiC crystal has a lattice constant smaller than that of the SiGe crystal, so that tensile strain is generated in the semiconductor layer 3. As the tensile strain generated in the semiconductor layer 3 increases, the mobility of electrons inside increases, but the increase in mobility saturates at some point. Let δ max be the magnitude of distortion when the electron mobility is saturated.

図３（ｂ）は、エピタキシャル層７に含まれるＣの濃度と、半導体層３に発生する歪みの大きさとの関係を概略的に表した模式図である。図中の直線αが、半導体層３がＳｉＧｅ結晶である場合の関係を表す。直線βは、半導体層３の代わりにＳｉ結晶を用いた場合の関係を比較例として表したものである。なお、半導体基板２等に結晶欠陥を発生させずに済むエピタキシャル層７のＣ濃度の限界は、３原子％程度である。直線α、β上のδｍａｘとなる点のＣ濃度ｃ１、ｃ２は、半導体装置１の構成により変化するが、ゲート長が所定の長さよりも短くなる等の場合には、図３（ｂ）に示すように、ｃ１、ｃ２は３原子％以下になる。また、図３（ｂ）は模式図であり、α、βは直線でなくてもよい。 FIG. 3B is a schematic diagram schematically showing the relationship between the concentration of C contained in the epitaxial layer 7 and the magnitude of strain generated in the semiconductor layer 3. A straight line α in the figure represents the relationship when the semiconductor layer 3 is a SiGe crystal. A straight line β represents a relationship when a Si crystal is used instead of the semiconductor layer 3 as a comparative example. The limit of the C concentration of the epitaxial layer 7 that does not cause crystal defects in the semiconductor substrate 2 or the like is about 3 atomic%. Although the C concentrations c 1 and c 2 at points δ max on the straight lines α and β vary depending on the configuration of the semiconductor device 1, in the case where the gate length becomes shorter than a predetermined length or the like, FIG. As shown in b), c 1 and c 2 are 3 atomic% or less. FIG. 3B is a schematic diagram, and α and β may not be straight lines.

同図の直線βからわかるように、半導体層３の代わりにＳｉ結晶を用いた場合は、エピタキシャル層７のＣ濃度が３原子％に達する前に、Ｓｉ結晶内の電子の移動度の上昇が飽和する大きさの歪みδｍａｘが発生する。一方、上述したように、半導体層３がＳｉＧｅ結晶である場合は、エピタキシャル層７から応力を受けていない状態において、電子の移動度が低下する圧縮歪みが内部に発生している。しかし、同図の直線αからわかるように、エピタキシャル層７のＣ濃度を増加させ、エピタキシャル層７から半導体層３に引張応力を加えることにより、半導体層３内の電子の移動度の上昇が飽和する大きさの歪みδｍａｘを発生させることができる。 As can be seen from the straight line β in the figure, when the Si crystal is used instead of the semiconductor layer 3, the mobility of electrons in the Si crystal increases before the C concentration of the epitaxial layer 7 reaches 3 atomic%. A distortion δ max having a saturation magnitude is generated. On the other hand, as described above, when the semiconductor layer 3 is a SiGe crystal, a compressive strain in which the mobility of electrons is reduced is generated inside the semiconductor layer 3 in a state where no stress is received from the epitaxial layer 7. However, as can be seen from the straight line α in the figure, the increase in the electron mobility in the semiconductor layer 3 is saturated by increasing the C concentration of the epitaxial layer 7 and applying a tensile stress from the epitaxial layer 7 to the semiconductor layer 3. It is possible to generate a distortion δ max having a magnitude of

つまり、半導体層３がＳｉＧｅ結晶である場合も、半導体層３の代わりにＳｉ結晶を用いた場合も、内部の電子の移動度の上昇が飽和する歪みの大きさδｍａｘはほぼ等しいため、当初ＳｉＧｅ結晶からなる半導体層３に圧縮応力が発生していたとしても、結局、歪みによる電子の移動度の上昇の効果を同程度に得ることができる。 That is, in both cases where the semiconductor layer 3 is a SiGe crystal and a Si crystal is used instead of the semiconductor layer 3, the magnitude of strain δ max at which the increase in the mobility of electrons inside is saturated is substantially equal. Even if compressive stress is generated in the semiconductor layer 3 made of SiGe crystal, the effect of increasing electron mobility due to strain can be obtained to the same extent.

また、上述したように、元来（歪みが発生していない状態において）ＳｉＧｅ結晶はＳｉ結晶よりも内部の電子の移動度が大きい。このため、歪みによる電子の移動度の上昇の効果と併せれば、半導体層３がＳｉＧｅ結晶である場合は、半導体層３の代わりにＳｉ結晶を用いた場合と比べて、電子の移動度をより大きくすることができる。   Moreover, as described above, the SiGe crystal originally has a higher electron mobility than the Si crystal (in a state where no distortion is generated). For this reason, when combined with the effect of increasing electron mobility due to strain, the semiconductor mobility is higher when the semiconductor layer 3 is a SiGe crystal than when a Si crystal is used instead of the semiconductor layer 3. Can be larger.

以下に、本実施の形態に係る半導体装置１の製造方法の一例を示す。   Below, an example of the manufacturing method of the semiconductor device 1 which concerns on this Embodiment is shown.

（半導体装置の製造）
図４Ａ（ａ）〜（ｃ）、図４Ｂ（ｄ）〜（ｆ）、図４Ｃ（ｇ）〜（ｈ）は、本発明の第１の実施の形態に係る半導体装置の製造工程を示す断面図である。 (Manufacture of semiconductor devices)
4A (a) to 4 (c), 4B (d) to (f), and 4C (g) to (h) are cross-sectional views showing the manufacturing steps of the semiconductor device according to the first embodiment of the present invention. FIG.

まず、図４Ａ（ａ）に示すように、半導体基板２内に素子分離領域１０を形成し、半導体基板２上に半導体膜１１、ゲート絶縁膜４、ゲート電極５およびキャップ膜１２を形成する。   First, as shown in FIG. 4A (a), the element isolation region 10 is formed in the semiconductor substrate 2, and the semiconductor film 11, the gate insulating film 4, the gate electrode 5, and the cap film 12 are formed on the semiconductor substrate 2.

ここで、半導体膜１１は、エピタキシャル成長法等により形成される。また、半導体膜１１には導電型不純物が注入されるが、エピタキシャル成長時にインサイチュで注入されてもよいし、エピタキシャル成長後にイオン注入法等により注入されてもよい。ここで、半導体膜１１に注入される導電型不純物は、ｐ型トランジスタを形成する場合は、Ｂ、ＢＦ２等のｐ型不純物イオンを用い、ｎ型トランジスタを形成する場合は、Ａｓ、Ｐ等のｎ型不純物イオンを用いる。その後、ＲＴＡ（Rapid Thermal Annealing）等の熱処理を行い、注入した導電型不純物を活性化させる。 Here, the semiconductor film 11 is formed by an epitaxial growth method or the like. Moreover, although the conductivity type impurity is implanted into the semiconductor film 11, it may be implanted in situ at the time of epitaxial growth, or may be implanted by an ion implantation method or the like after the epitaxial growth. Here, the conductive impurities implanted into the semiconductor film 11 use p-type impurity ions such as B and BF 2 when forming a p-type transistor, and As and P when forming an n-type transistor. N-type impurity ions are used. Thereafter, heat treatment such as RTA (Rapid Thermal Annealing) is performed to activate the implanted conductive impurities.

また、ゲート絶縁膜４、ゲート電極５およびキャップ膜１２は、それぞれの材料膜をＣＶＤ法等により半導体膜１１上に積層した後、これらの材料膜を、例えば、フォトリソグラフィー法とＲＩＥ（Reactive Ion Etching）法によりパターニングすることにより形成される。   The gate insulating film 4, the gate electrode 5, and the cap film 12 are formed by laminating the respective material films on the semiconductor film 11 by the CVD method or the like, and then, for example, photolithography and RIE (Reactive Ion). Etching) is performed by patterning.

なお、半導体膜１１、ゲート絶縁膜４、ゲート電極５およびキャップ膜１２を形成する前に、半導体膜１１に注入する導電型不純物と異なる導電型の不純物をイオン注入法により半導体基板２に注入し、ウェル（図示しない）を形成してもよい。その後、ＲＴＡ等の熱処理を行い、注入した導電型不純物を活性化させる。   Before forming the semiconductor film 11, the gate insulating film 4, the gate electrode 5, and the cap film 12, an impurity having a conductivity type different from that implanted into the semiconductor film 11 is implanted into the semiconductor substrate 2 by an ion implantation method. Wells (not shown) may be formed. Thereafter, heat treatment such as RTA is performed to activate the implanted conductivity type impurities.

次に、図４Ａ（ｂ）に示すように、ゲート絶縁膜４、ゲート電極５およびキャップ膜１２の側面にオフセットスペーサ６を形成する。   Next, as shown in FIG. 4A (b), offset spacers 6 are formed on the side surfaces of the gate insulating film 4, the gate electrode 5, and the cap film 12.

ここで、オフセットスペーサ６は、オフセットスペーサ６の材料膜をＣＶＤ法等により半導体基板２、ゲート絶縁膜４、ゲート電極５およびキャップ膜１２の表面を覆うように形成した後、これをＲＩＥ法等によりエッチング加工することにより形成する。   Here, the offset spacer 6 is formed by covering the surface of the semiconductor substrate 2, the gate insulating film 4, the gate electrode 5 and the cap film 12 with the material film of the offset spacer 6 by the CVD method or the like, and then forming the material film by the RIE method or the like. It is formed by etching.

次に、図４Ａ（ｃ）に示すように、オフセットスペーサ６およびキャップ膜１２をマスクとして用いて、ＲＩＥ法等により半導体膜１１をエッチングし、半導体層３に加工する。   Next, as shown in FIG. 4A (c), using the offset spacer 6 and the cap film 12 as a mask, the semiconductor film 11 is etched by the RIE method or the like to be processed into the semiconductor layer 3.

次に、図４Ｂ（ｄ）に示すように、オフセットスペーサ６およびキャップ膜１２をマスクとして用いて、ＲＩＥ法等により半導体基板２上面をエッチングし、溝１３を形成する。なお、図４Ａ（ｃ）に示した半導体層３の加工と、図４Ｂ（ｄ）に示した溝１３の形成は、ＲＩＥ法等により連続的に行うことができる。   Next, as shown in FIG. 4B (d), the upper surface of the semiconductor substrate 2 is etched by the RIE method or the like using the offset spacer 6 and the cap film 12 as a mask to form a groove 13. Note that the processing of the semiconductor layer 3 shown in FIG. 4A (c) and the formation of the groove 13 shown in FIG. 4B (d) can be performed continuously by the RIE method or the like.

次に、図４Ｂ（ｅ）に示すように、オフセットスペーサ６および半導体層３の側面、および半導体基板２の溝１３の内側面に相当する部分上にダミー側壁１４を形成する。   Next, as shown in FIG. 4B (e), dummy sidewalls 14 are formed on portions corresponding to the side surfaces of the offset spacer 6 and the semiconductor layer 3 and the inner surface of the groove 13 of the semiconductor substrate 2.

ここで、ダミー側壁１４は、ダミー側壁１４の材料膜をＣＶＤ法等により半導体基板２、オフセットスペーサ６、およびキャップ膜１２の表面を覆うように形成した後、これをＲＩＥ法等によりエッチング加工することにより形成する。   Here, the dummy sidewall 14 is formed by covering the surfaces of the semiconductor substrate 2, the offset spacer 6 and the cap film 12 with the material film of the dummy sidewall 14 by the CVD method or the like, and then etching it by the RIE method or the like. To form.

次に、図４Ｂ（ｆ）に示すように、ダミー側壁１４およびキャップ膜１２をマスクとして用いて、ＲＩＥ法等により半導体基板２上面をエッチングし、溝１３の一部をより深くする。   Next, as shown in FIG. 4B (f), the upper surface of the semiconductor substrate 2 is etched by the RIE method or the like using the dummy side wall 14 and the cap film 12 as a mask to make a part of the groove 13 deeper.

次に、図４Ｃ（ｇ）に示すように、ダミー側壁１４を除去した後、半導体基板２の溝１３により露出した表面を下地として導電型不純物を含んだ結晶であるエピタキシャル層７をエピタキシャル成長させる。ここで、エピタキシャル層７は、半導体層３の側面に接する高さまで成長させる。   Next, as shown in FIG. 4C (g), after removing the dummy side wall 14, the epitaxial layer 7 which is a crystal containing a conductive impurity is epitaxially grown on the surface exposed by the groove 13 of the semiconductor substrate 2 as a base. Here, the epitaxial layer 7 is grown to a height in contact with the side surface of the semiconductor layer 3.

ここで、ｐ型トランジスタを形成する場合、例えば、Ｓｉの原料としてモノシラン（ＳｉＨ４）またはジクロロシラン（ＳｉＨ２Ｃｌ２）、Ｇｅの原料として水素化ゲルマニウム（ＧｅＨ４）、Ｂの原料としてジボラン（Ｂ２Ｈ６）を用いて、水素ガス等の雰囲気中で７００〜８５０℃の温度条件下でＢを含んだＳｉＧｅ結晶を気相エピタキシャル成長させ、ｐ型のエピタキシャル層７を形成する。 Here, when forming a p-type transistor, for example, monosilane (SiH 4 ) or dichlorosilane (SiH 2 Cl 2 ) as a Si source, germanium hydride (GeH 4 ) as a Ge source, and diborane (B) as a B source. Using B 2 H 6 ), a SiGe crystal containing B is vapor-phase epitaxially grown at 700 to 850 ° C. in an atmosphere of hydrogen gas or the like to form a p-type epitaxial layer 7.

一方、ｎ型トランジスタを形成する場合、例えば、Ｓｉの原料としてモノシラン（ＳｉＨ４）またはジクロロシラン（ＳｉＨ２Ｃｌ２）、Ｃの原料としてアセチレン（Ｃ２Ｈ２）、Ａｓの原料としてアルシン（ＡｓＨ３）を用いて、水素ガス等の雰囲気中で７００〜８５０℃の温度条件下でＡｓを含んだＳｉＣ結晶を気相エピタキシャル成長させ、ｎ型のエピタキシャル層７を形成する。 On the other hand, when forming an n-type transistor, for example, monosilane (SiH 4 ) or dichlorosilane (SiH 2 Cl 2 ) as a Si source, acetylene (C 2 H 2 ) as a C source, and arsine (AsH) as an As source. 3 ), an SiC crystal containing As is vapor-phase epitaxially grown under a temperature condition of 700 to 850 ° C. in an atmosphere of hydrogen gas or the like to form an n-type epitaxial layer 7.

なお、導電型不純物を含まないエピタキシャル層７をエピタキシャル成長させた後、イオン注入法等により導電型不純物を注入してもよい。   In addition, after epitaxially growing the epitaxial layer 7 containing no conductive impurities, the conductive impurities may be implanted by an ion implantation method or the like.

次に、図４Ｃ（ｈ）に示すように、キャップ層１２を除去し、オフセットスペーサ６の側面にゲート側壁８を形成する。   Next, as shown in FIG. 4C (h), the cap layer 12 is removed, and the gate sidewall 8 is formed on the side surface of the offset spacer 6.

ここで、キャップ層１２は、リン酸を用いたウェットエッチング等により除去される。なお、このときに、オフセットスペーサ６が同時に除去されてもよい。この場合、ゲート側壁８はゲート電極５の側面に形成される。   Here, the cap layer 12 is removed by wet etching or the like using phosphoric acid. At this time, the offset spacer 6 may be removed at the same time. In this case, the gate sidewall 8 is formed on the side surface of the gate electrode 5.

また、ゲート側壁８は、ゲート側壁８の材料膜をエピタキシャル層７、オフセットスペーサ６およびキャップ層１２の表面を覆うように堆積させた後、これをＲＩＥ法等によりエッチング加工することにより形成する。   Further, the gate sidewall 8 is formed by depositing the material film of the gate sidewall 8 so as to cover the surfaces of the epitaxial layer 7, the offset spacer 6 and the cap layer 12, and then etching this by the RIE method or the like.

（第１の実施の形態の効果）
本発明の第１の実施の形態によれば、Ｓｉ結晶よりも内部におけるキャリア移動度が大きい半導体層３と、半導体層３に内部のキャリア移動度が上昇する方向の歪みを与えるエピタキシャル層７を組み合わせて用いることにより、半導体層３が半導体基板２から受ける歪みによる内部のキャリア移動度が低下する効果を打ち消し、大きなキャリア移動度を得ることができる。これにより、半導体装置１の駆動速度を向上させることができる。 (Effects of the first embodiment)
According to the first embodiment of the present invention, the semiconductor layer 3 having higher carrier mobility inside than the Si crystal, and the epitaxial layer 7 that imparts strain to the semiconductor layer 3 in the direction in which the internal carrier mobility increases are provided. By using in combination, it is possible to cancel the effect of reducing the internal carrier mobility due to the strain that the semiconductor layer 3 receives from the semiconductor substrate 2 and to obtain a large carrier mobility. Thereby, the drive speed of the semiconductor device 1 can be improved.

〔第２の実施の形態〕
本発明の第２の実施の形態は、第１の実施の形態における半導体層３に対応する第１の半導体層１５とゲート絶縁膜４の間に第２の半導体層が形成される点において第１の実施の形態と異なる。なお、他の部材の構成や製造工程等、第１の実施の形態と同様の点については、簡単のために説明を省略する。 [Second Embodiment]
The second embodiment of the present invention is different in that a second semiconductor layer is formed between the first semiconductor layer 15 corresponding to the semiconductor layer 3 in the first embodiment and the gate insulating film 4. Different from the first embodiment. In addition, about the point similar to 1st Embodiment, such as a structure of another member and a manufacturing process, description is abbreviate | omitted for simplicity.

（半導体装置の構成）
図５は、本発明の第２の実施の形態に係る半導体装置の断面図である。 (Configuration of semiconductor device)
FIG. 5 is a sectional view of a semiconductor device according to the second embodiment of the present invention.

第１の半導体層１５は、第１の実施の形態における半導体層３と同様の材料からなり、半導体層３と同様にチャネル領域として働く。   The first semiconductor layer 15 is made of the same material as that of the semiconductor layer 3 in the first embodiment, and functions as a channel region like the semiconductor layer 3.

第２の半導体層１６は、Ｓｉ結晶等の半導体層３よりも内部のキャリア移動度が小さい材料からなる。また、第２の半導体層１６は、第１の半導体層１５とゲート絶縁膜４の間に形成される。   The second semiconductor layer 16 is made of a material having lower internal carrier mobility than the semiconductor layer 3 such as Si crystal. The second semiconductor layer 16 is formed between the first semiconductor layer 15 and the gate insulating film 4.

なお、第２の半導体層１６の厚さは２ｎｍ以下であることが好ましい。第２の半導体層１６の厚さが２ｎｍを超えると、チャネル領域の第２の半導体層１６内に形成される割合が大きくなりすぎるためである。   Note that the thickness of the second semiconductor layer 16 is preferably 2 nm or less. This is because if the thickness of the second semiconductor layer 16 exceeds 2 nm, the ratio of the channel region formed in the second semiconductor layer 16 becomes too large.

また、第１の半導体層１５の厚さと第２の半導体層１６の厚さの合計は、半導体装置１の動作時に発生する反転層の厚さ以下であることが好ましい。第１の半導体層１５の厚さと第２の半導体層１６の厚さの合計が反転層の厚さよりも厚い場合、第１の半導体層１５の反転層よりも下方にある領域をキャリアは移動しないため、半導体装置１の動作速度はほとんど変わらないためである。また、第１の半導体層１５が、半導体基板２から受ける応力により内部におけるキャリアの移動度が低下する方向に歪みが生じる結晶である場合は、第１の半導体層１５を厚くするほどこの歪みが大きくなってキャリアの移動度が低下する。なお、反転層の厚さは、例えば２〜３ｎｍである。   The total thickness of the first semiconductor layer 15 and the second semiconductor layer 16 is preferably equal to or less than the thickness of the inversion layer generated during the operation of the semiconductor device 1. When the sum of the thickness of the first semiconductor layer 15 and the thickness of the second semiconductor layer 16 is thicker than the thickness of the inversion layer, carriers do not move in a region below the inversion layer of the first semiconductor layer 15. Therefore, the operation speed of the semiconductor device 1 is hardly changed. In addition, when the first semiconductor layer 15 is a crystal that is distorted in a direction in which the mobility of carriers in the interior decreases due to the stress received from the semiconductor substrate 2, the distortion increases as the thickness of the first semiconductor layer 15 increases. It becomes larger and the mobility of the carrier decreases. Note that the thickness of the inversion layer is, for example, 2 to 3 nm.

以下に、本実施の形態に係る半導体装置１の製造方法の一例を示す。   Below, an example of the manufacturing method of the semiconductor device 1 which concerns on this Embodiment is shown.

（半導体装置の製造）
図６Ａ（ａ）〜（ｃ）、図６Ｂ（ｄ）〜（ｆ）、図６Ｃ（ｇ）〜（ｈ）は、本発明の第２の実施の形態に係る半導体装置の製造工程を示す断面図である。 (Manufacture of semiconductor devices)
6A (a) to (c), FIGS. 6B (d) to (f), and FIGS. 6C (g) to (h) are cross sections showing manufacturing steps of the semiconductor device according to the second embodiment of the present invention. FIG.

まず、図６Ａ（ａ）に示すように、半導体基板２内に素子分離領域１０を形成し、半導体基板２上に第１の半導体膜１７、第２の半導体膜１８、ゲート絶縁膜４、ゲート電極５およびキャップ膜１２を形成する。   First, as shown in FIG. 6A (a), an element isolation region 10 is formed in a semiconductor substrate 2, and a first semiconductor film 17, a second semiconductor film 18, a gate insulating film 4, a gate are formed on the semiconductor substrate 2. Electrode 5 and cap film 12 are formed.

ここで、第１の半導体膜１７および第２の半導体膜１８は、エピタキシャル成長法等により形成される。また、第１の半導体膜１７および第２の半導体膜１８には導電型不純物が注入されるが、エピタキシャル成長時にインサイチュで注入されてもよいし、エピタキシャル成長後にイオン注入法等により注入されてもよい。ここで、第１の半導体膜１７および第２の半導体膜１８に注入される導電型不純物は、ｐ型トランジスタを形成する場合は、Ｂ、ＢＦ２等のｐ型不純物イオンを用い、ｎ型トランジスタを形成する場合は、Ａｓ、Ｐ等のｎ型不純物イオンを用いる。その後、ＲＴＡ等の熱処理を行い、注入した導電型不純物を活性化させる。 Here, the first semiconductor film 17 and the second semiconductor film 18 are formed by an epitaxial growth method or the like. The first semiconductor film 17 and the second semiconductor film 18 are implanted with conductive impurities, but may be implanted in situ during epitaxial growth, or may be implanted after the epitaxial growth by an ion implantation method or the like. Here, when forming a p-type transistor, the p-type impurity ions such as B and BF 2 are used as the conductive impurities implanted into the first semiconductor film 17 and the second semiconductor film 18, and the n-type transistor is used. Is used, n-type impurity ions such as As and P are used. Thereafter, heat treatment such as RTA is performed to activate the implanted conductivity type impurities.

また、ゲート絶縁膜４、ゲート電極５およびキャップ膜１２は、それぞれの材料膜をＣＶＤ法等により半導体膜１１上に積層した後、これらの材料膜を、例えば、フォトリソグラフィー法とＲＩＥ法によりパターニングすることにより形成される。   The gate insulating film 4, the gate electrode 5, and the cap film 12 are formed by laminating respective material films on the semiconductor film 11 by a CVD method or the like, and then patterning these material films by, for example, a photolithography method and an RIE method. It is formed by doing.

なお、第１の半導体膜１７、第２の半導体膜１８、ゲート絶縁膜４、ゲート電極５およびキャップ膜１２を形成する前に、半導体膜１１に注入する導電型不純物と異なる導電型の不純物をイオン注入法により半導体基板２に注入し、ウェル（図示しない）を形成してもよい。その後、ＲＴＡ等の熱処理を行い、注入した導電型不純物を活性化させる。   Note that before forming the first semiconductor film 17, the second semiconductor film 18, the gate insulating film 4, the gate electrode 5, and the cap film 12, impurities having a conductivity type different from that implanted into the semiconductor film 11 are introduced. A well (not shown) may be formed by implanting into the semiconductor substrate 2 by ion implantation. Thereafter, heat treatment such as RTA is performed to activate the implanted conductivity type impurities.

次に、図６Ａ（ｂ）に示すように、ゲート絶縁膜４、ゲート電極５およびキャップ膜１２の側面にオフセットスペーサ６を形成する。   Next, as shown in FIG. 6A (b), offset spacers 6 are formed on the side surfaces of the gate insulating film 4, the gate electrode 5, and the cap film 12.

ここで、オフセットスペーサ６は、オフセットスペーサ６の材料膜をＣＶＤ法等により半導体基板２、ゲート絶縁膜４、ゲート電極５およびキャップ膜１２の表面を覆うように形成した後、これをＲＩＥ法等によりエッチング加工することにより形成する。   Here, the offset spacer 6 is formed by covering the surface of the semiconductor substrate 2, the gate insulating film 4, the gate electrode 5 and the cap film 12 with the material film of the offset spacer 6 by the CVD method or the like, and then forming the material film by the RIE method or the like. It is formed by etching.

次に、図６Ａ（ｃ）に示すように、オフセットスペーサ６およびキャップ膜１２をマスクとして用いて、ＲＩＥ法等により第１の半導体膜１７および第２の半導体膜１８をエッチングし、第１の半導体層１５および第２の半導体層１６にそれぞれ加工する。   Next, as shown in FIG. 6A (c), the first semiconductor film 17 and the second semiconductor film 18 are etched by the RIE method or the like using the offset spacer 6 and the cap film 12 as a mask. The semiconductor layer 15 and the second semiconductor layer 16 are processed.

次に、図６Ｂ（ｄ）に示すように、オフセットスペーサ６およびキャップ膜１２をマスクとして用いて、ＲＩＥ法等により半導体基板２上面をエッチングし、溝１３を形成する。なお、図６Ａ（ｃ）に示した第１の半導体層１５および第２の半導体層１６の加工と、図６Ｂ（ｄ）に示した溝１３の形成は、ＲＩＥ法等により連続的に行うことができる。   Next, as shown in FIG. 6B (d), the upper surface of the semiconductor substrate 2 is etched by the RIE method or the like using the offset spacer 6 and the cap film 12 as a mask to form the grooves 13. Note that the processing of the first semiconductor layer 15 and the second semiconductor layer 16 shown in FIG. 6A (c) and the formation of the groove 13 shown in FIG. 6B (d) are performed continuously by the RIE method or the like. Can do.

次に、図６Ｂ（ｅ）に示すように、オフセットスペーサ６、第１の半導体層１５および第２の半導体層１６の側面、および半導体基板２の溝１３の内側面に相当する部分上にダミー側壁１４を形成する。   Next, as shown in FIG. 6B (e), the dummy is formed on portions corresponding to the side surfaces of the offset spacer 6, the first semiconductor layer 15 and the second semiconductor layer 16, and the inner side surface of the groove 13 of the semiconductor substrate 2. Sidewall 14 is formed.

ここで、ダミー側壁１４は、ダミー側壁１４の材料膜をＣＶＤ法等により半導体基板２、第１の半導体層１５、第２の半導体層１６、オフセットスペーサ６およびキャップ膜１２の表面を覆うように形成した後、これをＲＩＥ法等によりエッチング加工することにより形成する。   Here, the dummy sidewall 14 covers the surface of the semiconductor substrate 2, the first semiconductor layer 15, the second semiconductor layer 16, the offset spacer 6, and the cap film 12 by a CVD method or the like. After the formation, this is formed by etching using the RIE method or the like.

次に、図６Ｂ（ｆ）に示すように、ダミー側壁１４およびキャップ膜１２をマスクとして用いて、ＲＩＥ法等により半導体基板２上面をエッチングし、溝１３の一部をより深くする。   Next, as shown in FIG. 6B (f), the upper surface of the semiconductor substrate 2 is etched by the RIE method or the like using the dummy side wall 14 and the cap film 12 as a mask to make a part of the groove 13 deeper.

次に、図６Ｃ（ｇ）に示すように、ダミー側壁１４を除去した後、半導体基板２の溝１３により露出した表面を下地として導電型不純物を含んだ結晶であるエピタキシャル層７をエピタキシャル成長させる。ここで、エピタキシャル層７は、第１の半導体層１５および第２の半導体層１６の側面に接する高さまで成長させる。   Next, as shown in FIG. 6C (g), after removing the dummy side wall 14, the epitaxial layer 7 which is a crystal containing conductive impurities is epitaxially grown on the surface exposed by the groove 13 of the semiconductor substrate 2 as a base. Here, the epitaxial layer 7 is grown to a height in contact with the side surfaces of the first semiconductor layer 15 and the second semiconductor layer 16.

次に、図６Ｃ（ｈ）に示すように、キャップ層１２を除去し、オフセットスペーサ６の側面にゲート側壁８を形成する。   Next, as shown in FIG. 6C (h), the cap layer 12 is removed, and the gate sidewall 8 is formed on the side surface of the offset spacer 6.

ここで、キャップ層１２は、リン酸を用いたウェットエッチング等により除去される。なお、このときに、オフセットスペーサ６が同時に除去されてもよい。この場合、ゲート側壁８はゲート電極５の側面に形成される。   Here, the cap layer 12 is removed by wet etching or the like using phosphoric acid. At this time, the offset spacer 6 may be removed at the same time. In this case, the gate sidewall 8 is formed on the side surface of the gate electrode 5.

また、ゲート側壁８は、ゲート側壁８の材料膜をエピタキシャル層７、オフセットスペーサ６およびキャップ層１２の表面を覆うように堆積させた後、これをＲＩＥ法等によりエッチング加工することにより形成する。   Further, the gate sidewall 8 is formed by depositing the material film of the gate sidewall 8 so as to cover the surfaces of the epitaxial layer 7, the offset spacer 6 and the cap layer 12, and then etching this by the RIE method or the like.

（第２の実施の形態の効果）
本発明の第２の実施の形態によれば、第１の半導体層１５とゲート絶縁膜４との間に、第１の半導体層１５よりも内部のキャリア移動度が小さい第２の半導体層１６を形成することにより、ゲート絶縁膜４と接触しない第２の半導体層１６がチャネル領域として働く。このため、チャネル領域とゲート絶縁膜４との界面における表面ラフネスに起因するチャネル領域内のキャリアの散乱を抑え、移動度の低下を抑えることができる。 (Effect of the second embodiment)
According to the second embodiment of the present invention, the second semiconductor layer 16 having lower internal carrier mobility than the first semiconductor layer 15 between the first semiconductor layer 15 and the gate insulating film 4. As a result, the second semiconductor layer 16 not in contact with the gate insulating film 4 serves as a channel region. For this reason, the scattering of carriers in the channel region due to the surface roughness at the interface between the channel region and the gate insulating film 4 can be suppressed, and the decrease in mobility can be suppressed.

〔他の実施の形態〕
本発明は、上記各実施の形態に限定されず、発明の主旨を逸脱しない範囲内において種々変形実施が可能である。 [Other Embodiments]
The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention.

また、発明の主旨を逸脱しない範囲内において上記各実施の形態の構成要素を任意に組み合わせることができる。   In addition, the constituent elements of the above embodiments can be arbitrarily combined without departing from the spirit of the invention.

本発明の第１の実施の形態に係る半導体装置の断面図である。1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. （ａ）、（ｂ）は、参考例としての、エクステンション領域の幅、深さとエピタキシャル層から半導体基板のゲート電極下の領域に加わる応力の大きさの関係を概略的に示す図およびグラフである。(A), (b) is the figure and graph which show roughly the relationship of the magnitude | size of the stress added to the area | region under the gate electrode of a semiconductor substrate from the width of an extension area | region, and an epitaxial layer as a reference example. . （ａ）は、半導体層に発生する歪みの大きさと、半導体層の内部の電子の移動度との関係を概略的に表した模式図であり、（ｂ）は、エピタキシャル層に含まれるＣの濃度と、半導体層に発生する歪みの大きさとの関係を概略的に表した模式図である。(A) is the schematic diagram showing the relationship between the magnitude | size of the distortion which generate | occur | produces in a semiconductor layer, and the mobility of the electron inside a semiconductor layer, (b) is C of C contained in an epitaxial layer. It is the schematic diagram which represented roughly the relationship between the density | concentration and the magnitude | size of the distortion generate | occur | produced in a semiconductor layer. （ａ）〜（ｃ）は、本発明の第１の実施の形態に係る半導体装置の製造工程を示す断面図である。(A)-(c) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. （ｄ）〜（ｆ）は、本発明の第１の実施の形態に係る半導体装置の製造工程を示す断面図である。(D)-(f) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. （ｇ）、（ｈ）は、本発明の第１の実施の形態に係る半導体装置の製造工程を示す断面図である。(G), (h) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第２の実施の形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. （ａ）〜（ｃ）は、本発明の第２の実施の形態に係る半導体装置の製造工程を示す断面図。(A)-(c) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. （ｄ）〜（ｆ）は、本発明の第２の実施の形態に係る半導体装置の製造工程を示す断面図。(D)-(f) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. （ｇ）、（ｈ）は、本発明の第２の実施の形態に係る半導体装置の製造工程を示す断面図。(G), (h) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention.

符号の説明Explanation of symbols

１ 半導体装置
２ 半導体基板
３ 半導体層
４ ゲート絶縁膜
５ ゲート電極
７ エピタキシャル層
１５ 第１の半導体層
１６ 第２の半導体層
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 3 Semiconductor layer 4 Gate insulating film 5 Gate electrode 7 Epitaxial layer 15 1st semiconductor layer 16 2nd semiconductor layer

Claims (5)

半導体基板と、
前記半導体基板上に形成され、内部におけるキャリアの移動度がＳｉ結晶よりも大きい第１の結晶からなる半導体層と、
前記半導体層上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート電極と、
前記半導体層を挟んで形成され、前記半導体層に前記半導体層内のキャリアの移動度が上昇する方向に歪みを与える第２の結晶を含み、前記半導体層に接する深さの浅い領域であるソース・ドレインエクステンション領域を有するソース・ドレイン領域と、
を有することを特徴とする半導体装置。 A semiconductor substrate;
A semiconductor layer formed on the semiconductor substrate and made of a first crystal in which the mobility of carriers inside is larger than that of the Si crystal;
A gate insulating film formed on the semiconductor layer;
A gate electrode formed on the gate insulating film;
A source that is formed with the semiconductor layer in between and includes a second crystal that distorts the semiconductor layer in a direction in which the mobility of carriers in the semiconductor layer increases, and is a shallow region in contact with the semiconductor layer A source / drain region having a drain extension region;
A semiconductor device comprising: 前記第１の結晶は、Ｓｉ結晶上に形成した場合に、内部におけるキャリアの移動度が低下する方向に歪みが生じる結晶であることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein when the first crystal is formed over a Si crystal, the first crystal is a crystal that is distorted in a direction in which the mobility of carriers inside the first crystal decreases. 前記第１の結晶はＳｉＧｅ結晶であり、前記第２の結晶はＳｉＣ結晶であることを特徴とする請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein the first crystal is a SiGe crystal, and the second crystal is a SiC crystal. 前記ソース・ドレインエクステンション領域の下端は、前記半導体層の下端よりも深い位置にあることを特徴とする請求項１から３のいずれかに記載の半導体装置。   4. The semiconductor device according to claim 1, wherein a lower end of the source / drain extension region is deeper than a lower end of the semiconductor layer. 5. 前記半導体層と前記ゲート絶縁膜の間に、内部におけるキャリアの移動度が前記第１の結晶よりも小さい結晶からなる他の半導体層が形成されたことを特徴とする請求項１から４のいずれかに記載の半導体装置。   5. The semiconductor layer according to claim 1, wherein another semiconductor layer made of a crystal having carrier mobility therein smaller than that of the first crystal is formed between the semiconductor layer and the gate insulating film. A semiconductor device according to claim 1.
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JP2011103434A (en) * 2009-11-10 2011-05-26 Taiwan Semiconductor Manufacturing Co Ltd Source/drain engineering of devices with high-mobility channels
JP2013513945A (en) * 2009-12-23 2013-04-22 インテル コーポレイション Techniques and configurations for distorting integrated circuit devices
US8455860B2 (en) 2009-04-30 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing source/drain resistance of III-V based transistors
US8617976B2 (en) 2009-06-01 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain re-growth for manufacturing III-V based transistors
US8674341B2 (en) 2009-04-01 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. High-mobility multiple-gate transistor with improved on-to-off current ratio
US8816391B2 (en) 2009-04-01 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain engineering of devices with high-mobility channels
US9768305B2 (en) 2009-05-29 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Gradient ternary or quaternary multiple-gate transistor

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Publication number Priority date Publication date Assignee Title
US9590068B2 (en) 2009-04-01 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. High-mobility multiple-gate transistor with improved on-to-off current ratio
US10109748B2 (en) 2009-04-01 2018-10-23 Taiwan Semiconductor Manufacturing Company, Ltd. High-mobility multiple-gate transistor with improved on-to-off current ratio
US8674341B2 (en) 2009-04-01 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. High-mobility multiple-gate transistor with improved on-to-off current ratio
US8816391B2 (en) 2009-04-01 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain engineering of devices with high-mobility channels
US8927371B2 (en) 2009-04-01 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. High-mobility multiple-gate transistor with improved on-to-off current ratio
US8455860B2 (en) 2009-04-30 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing source/drain resistance of III-V based transistors
US8674408B2 (en) 2009-04-30 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing source/drain resistance of III-V based transistors
US10269970B2 (en) 2009-05-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Gradient ternary or quaternary multiple-gate transistor
US9768305B2 (en) 2009-05-29 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Gradient ternary or quaternary multiple-gate transistor
US8617976B2 (en) 2009-06-01 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain re-growth for manufacturing III-V based transistors
US9006788B2 (en) 2009-06-01 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain re-growth for manufacturing III-V based transistors
TWI451552B (en) * 2009-11-10 2014-09-01 Taiwan Semiconductor Mfg Integrated circuit structures
JP2011103434A (en) * 2009-11-10 2011-05-26 Taiwan Semiconductor Manufacturing Co Ltd Source/drain engineering of devices with high-mobility channels
JP2013513945A (en) * 2009-12-23 2013-04-22 インテル コーポレイション Techniques and configurations for distorting integrated circuit devices

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