JP2009081208A - Method for manufacturing printed wiring board - Google Patents

Method for manufacturing printed wiring board Download PDF

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JP2009081208A
JP2009081208A JP2007248124A JP2007248124A JP2009081208A JP 2009081208 A JP2009081208 A JP 2009081208A JP 2007248124 A JP2007248124 A JP 2007248124A JP 2007248124 A JP2007248124 A JP 2007248124A JP 2009081208 A JP2009081208 A JP 2009081208A
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plating
resist
groove
metal
wiring board
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Hiroaki Fujiwara
弘明 藤原
Shingo Yoshioka
愼悟 吉岡
Tomoaki Watanabe
朋亮 渡辺
Mana Yamaguchi
真魚 山口
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Panasonic Electric Works Co Ltd
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Panasonic Electric Works Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a printed wiring board in which a circuit finer than a conventional one can be formed with higher reliability while reducing an environmental load. <P>SOLUTION: A base 3 is formed of a resin composition prepared by distributing plating nuclei 2 into insulating resin 1. The surface of the base 3 is then coated with a resist 6. A groove 4 is formed at the base 3 to penetrate the resist 6. The plating nuclei 2 exposed to the inner surface of the trench 4 are activated. A circuit 5 is formed in the groove 4 by electroless plating. Thereafter, the resist 6 is removed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、各種電子機器に用いられるプリント配線板を製造する方法に関するものである。   The present invention relates to a method of manufacturing a printed wiring board used for various electronic devices.

電子機器の高性能化を図るためにはプリント配線板に形成される回路５の微細化が必要とされるが、従来、このような微細回路を形成するにあたっては、図２のようなセミアディティブ法（ＳＡＰ：semi-additive process）が使用されてきた（例えば、特許文献１参照。）。   In order to improve the performance of electronic equipment, it is necessary to miniaturize the circuit 5 formed on the printed wiring board. Conventionally, in forming such a fine circuit, a semi-additive as shown in FIG. The method (SAP: semi-additive process) has been used (for example, refer to Patent Document 1).

この方法ではまず図２（ａ）（ｂ）のように、絶縁樹脂１で形成された基材３の表面を過マンガン酸処理によって粗化した後、触媒化処理によってこの粗化面７にＰｄ（パラジウム）を析出させる。次に図２（ｃ）のように、Ｐｄで触媒化された表面に無電解めっき処理（化学めっき処理）を行って厚み１μｍ程度の無電解めっき層８を形成した後、図２（ｄ）のように回路５を形成しない部分をめっきレジスト９で被覆する。そして、図２（ｅ）のように無電解めっき層８を給電層として電解めっき処理を行って電解めっき層１０を形成し、図２（ｆ）のようにめっきレジスト９を除去した後、フラッシュエッチング（ソフトエッチング）を行うことによって、図２（ｇ）のような回路５が形成されたプリント配線板を得ることができるものである。
特許流通支援チャート、［online］、［平成１９年９月２１日検索］、インターネット＜URL:http://www.ryutu.inpit.go.jp/chart/H13/dennki04/1/pdf/1-1-4.pdf、http://www.ryutu.inpit.go.jp/chart/tokumapf.htm＞ In this method, as shown in FIGS. 2 (a) and 2 (b), the surface of the base material 3 formed of the insulating resin 1 is first roughened by permanganic acid treatment, and then the roughened surface 7 is formed on the roughened surface 7 by catalytic treatment. (Palladium) is precipitated. Next, as shown in FIG. 2C, an electroless plating process (chemical plating process) is performed on the surface catalyzed by Pd to form an electroless plating layer 8 having a thickness of about 1 μm, and then FIG. The portion where the circuit 5 is not formed is covered with the plating resist 9 as described above. Then, as shown in FIG. 2E, the electroplating process is performed using the electroless plating layer 8 as a power feeding layer to form the electrolytic plating layer 10, and after removing the plating resist 9 as shown in FIG. By performing the etching (soft etching), a printed wiring board on which the circuit 5 as shown in FIG. 2G is formed can be obtained.
Patent distribution support chart, [online], [Search September 21, 2007], Internet <URL: http://www.ryutu.inpit.go.jp/chart/H13/dennki04/1/pdf/1- 1-4.pdf, http://www.ryutu.inpit.go.jp/chart/tokumapf.htm>

しかし、図２のようなセミアディティブ法を使用したプリント配線板の製造方法にあっては、次のような問題がある。すなわち、この方法で用いられる過マンガン酸処理液やエッチング液などの薬液が環境負荷増大の原因となっている。また、電解めっき処理では回路５の厚みの均一化などが困難である。また、フラッシュエッチングではＰｄを完全に除去するのが困難であるため、回路５間にＰｄが残存してしまい、このＰｄが絶縁信頼性を低下させるので、回路５の微細化には限界がある。具体的には、従来の方法ではＬ（ライン）／Ｓ（スペース）＝１０μｍ／１０μｍが限界である。さらに、従来の方法では回路５の微細化と密着性の向上を両立させるのが困難である。   However, the printed wiring board manufacturing method using the semi-additive method as shown in FIG. 2 has the following problems. That is, chemical solutions such as permanganic acid treatment solution and etching solution used in this method cause an increase in environmental load. Further, it is difficult to make the thickness of the circuit 5 uniform in the electrolytic plating process. Further, since it is difficult to completely remove Pd by flash etching, Pd remains between the circuits 5, and this Pd lowers the insulation reliability. Therefore, there is a limit to miniaturization of the circuit 5. . Specifically, in the conventional method, L (line) / S (space) = 10 μm / 10 μm is the limit. Furthermore, it is difficult for the conventional method to achieve both miniaturization of the circuit 5 and improvement in adhesion.

本発明は上記の点に鑑みてなされたものであり、環境負荷を低減しつつ、従来よりも微細かつ信頼性の高い回路が形成されたプリント配線板を製造することができるプリント配線板の製造方法を提供することを目的とするものである。   The present invention has been made in view of the above points, and is capable of manufacturing a printed wiring board on which a finer and more reliable circuit than conventional ones can be manufactured while reducing environmental burden. It is intended to provide a method.

本発明の請求項１に係るプリント配線板の製造方法は、絶縁樹脂１にめっき核２を分散させて調製されためっき核入り絶縁樹脂組成物で基材３を形成し、この基材３の表面をレジスト６で被覆すると共にこのレジスト６を貫通してこの基材３に溝４を形成し、溝４の内面に露出しためっき核２を活性化すると共に無電解めっき処理によって溝４に回路５を形成した後にレジスト６を除去することを特徴とするものである。   In the method for manufacturing a printed wiring board according to claim 1 of the present invention, a base material 3 is formed of an insulating resin composition containing a plating core prepared by dispersing a plating core 2 in an insulating resin 1. The surface is covered with a resist 6 and a groove 4 is formed in the base material 3 through the resist 6. The plating nucleus 2 exposed on the inner surface of the groove 4 is activated and a circuit is formed in the groove 4 by electroless plating. 5 is formed, the resist 6 is removed.

請求項２に係る発明は、請求項１において、めっき核２として、金属酸化物、有機物で表面が被覆された金属粒子、金属錯体、金属が担持された多孔体、金属ナノ粒子の中から選ばれるものを用いることを特徴とするものである。   The invention according to claim 2 is the method according to claim 1, wherein the plating nucleus 2 is selected from metal oxides, metal particles whose surfaces are coated with organic substances, metal complexes, porous bodies carrying metals, and metal nanoparticles. It is characterized by using what is used.

本発明の請求項１に係るプリント配線板の製造方法によれば、環境負荷を低減しつつ、従来よりも微細かつ信頼性の高い回路が形成されたプリント配線板を製造することができるものである。   According to the method for manufacturing a printed wiring board according to claim 1 of the present invention, it is possible to manufacture a printed wiring board on which a finer and more reliable circuit is formed than before while reducing the environmental load. is there.

請求項２に係る発明によれば、さらに微細かつ信頼性の高い回路を形成することができるものである。   According to the invention of claim 2, a finer and more reliable circuit can be formed.

以下、本発明の実施の形態を説明する。   Embodiments of the present invention will be described below.

図１は本発明の実施の形態の一例を示すものであり、プリント配線板を製造するにあたってはまずめっき核入り絶縁樹脂組成物で図１（ａ）のような基材３を形成する。   FIG. 1 shows an example of an embodiment of the present invention. When a printed wiring board is manufactured, a substrate 3 as shown in FIG. 1A is first formed from an insulating resin composition containing a plating nucleus.

めっき核入り絶縁樹脂組成物は、絶縁樹脂１にめっき核２を分散させることによって調製することができる。   The insulating resin composition containing the plating nucleus can be prepared by dispersing the plating nucleus 2 in the insulating resin 1.

ここで、絶縁樹脂１としては、エポキシ樹脂等の熱硬化性樹脂や、ポリイミド樹脂、ポリフェニレンオキサイド樹脂、ポリエチレンテレフタレート樹脂等の熱可塑性樹脂を用いることができる。   Here, as the insulating resin 1, a thermosetting resin such as an epoxy resin, or a thermoplastic resin such as a polyimide resin, a polyphenylene oxide resin, or a polyethylene terephthalate resin can be used.

まためっき核２としては、Ｃｕ（銅）やＰｄ等の金属微粒子を用いることができるが、より微細かつ信頼性の高い回路５を形成するためには、金属酸化物、有機物で表面が被覆された金属粒子、金属錯体、金属が担持された多孔体、金属ナノ粒子の中から選ばれるものを用いるのが好ましい。なお、ＣｕやＰｄ等の単なる金属微粒子は絶縁樹脂１中で凝集して導通するおそれがある。ただし、金属ナノ粒子は後述するようにその添加量を低く抑えれば絶縁樹脂１中での導通を防止することができる。   Further, as the plating nucleus 2, metal fine particles such as Cu (copper) and Pd can be used. In order to form a finer and more reliable circuit 5, the surface is coated with a metal oxide or an organic substance. It is preferable to use a metal particle, a metal complex, a porous body on which a metal is supported, or a metal nanoparticle. Note that simple metal particles such as Cu and Pd may aggregate in the insulating resin 1 and become conductive. However, conduction in the insulating resin 1 can be prevented if the addition amount of the metal nanoparticles is kept low as will be described later.

ここで、金属酸化物は、酸化銅等であり、通常は不活性（絶縁性）な状態であるが、ジメチルアミノボラン（ＤＭＡＢ）等の還元剤で処理すると、金属銅が表面に露出して、活性（導電性）な状態となるものである。   Here, the metal oxide is copper oxide or the like and is normally in an inactive (insulating) state, but when treated with a reducing agent such as dimethylaminoborane (DMAB), the metal copper is exposed on the surface. It becomes an active (conductive) state.

また有機物で表面が被覆された金属粒子は、乳化重合等によってＣｕやＰｄ等の金属粒子の表面が有機物で被覆されたコアシェル構造を持つものである。これも通常は不活性状態であるが、ＹＡＧレーザ等のレーザで有機物を焼き飛ばすと、金属粒子が露出して、活性状態となるものである。   The metal particles whose surface is coated with an organic substance have a core-shell structure in which the surfaces of metal particles such as Cu and Pd are coated with an organic substance by emulsion polymerization or the like. This is also usually in an inactive state, but when an organic substance is burned off with a laser such as a YAG laser, the metal particles are exposed and become an active state.

また金属錯体は、Ｃｕ等の金属原子を中心として周囲にエチレンジアミン四酢酸（ＥＤＴＡ）等の有機物が配位子として結合した構造を持つものである。これも通常は不活性状態であるが、ＹＡＧレーザ等のレーザで周囲の有機物を焼き飛ばすと、中心金属が露出して、活性状態となるものである。   The metal complex has a structure in which an organic substance such as ethylenediaminetetraacetic acid (EDTA) is bound as a ligand around a metal atom such as Cu. Although this is also usually in an inactive state, when a surrounding organic substance is burned off with a laser such as a YAG laser, the central metal is exposed and becomes an active state.

また金属が担持された多孔体は、ゼオライト等の多孔体の微細孔にＣｕやＰｄ等の金属を担持させたものであり、これも通常は不活性状態であるが、無機物である多孔体をアルカリで除去すると、金属が露出して、活性状態となるものである。   Further, the porous body on which a metal is supported is a porous body such as zeolite in which a metal such as Cu or Pd is supported, which is usually in an inactive state, but an inorganic porous body is used. When removed with an alkali, the metal is exposed and becomes active.

また金属ナノ粒子は、ＣｕやＰｄ等のナノサイズの金属粒子であるが、これは通常活性状態である。   The metal nanoparticles are nano-sized metal particles such as Cu and Pd, which are usually in an active state.

まためっき核２の粒径は１０ｎｍ〜１μｍであるが、特に金属ナノ粒子の場合はその粒径は１０〜５００ｎｍである。これより粒径が大きくなると、微細回路の形成が困難であると共に基材３の絶縁性を確保できなくなるおそれがある。なお、粒径を１０ｎｍ未満にするのは今のところ困難である。まためっき核入り絶縁樹脂組成物全量に対してめっき核２の添加量は０．０１〜５質量％である。これより添加量が少ないと、後述する溝４の内面に十分な量のめっき核２を露出させることができないおそれがあり、逆に添加量が多いと、基材３の絶縁性を確保できないおそれがある。ただし、金属ナノ粒子の場合は通常活性状態であるので基材３の絶縁性を確保するためにその添加量の上限は０．５質量％に設定する。   In addition, the particle size of the plating nucleus 2 is 10 nm to 1 μm, but in the case of metal nanoparticles, the particle size is 10 to 500 nm. If the particle size is larger than this, it is difficult to form a fine circuit and the insulation of the base material 3 may not be ensured. It is difficult to make the particle size less than 10 nm at present. Moreover, the addition amount of the plating nucleus 2 is 0.01-5 mass% with respect to the insulating resin composition containing a plating nucleus. If the amount added is smaller than this, a sufficient amount of the plating nucleus 2 may not be exposed on the inner surface of the groove 4 to be described later. Conversely, if the amount added is large, the insulating property of the substrate 3 may not be ensured. There is. However, since metal nanoparticles are usually in an active state, the upper limit of the amount added is set to 0.5% by mass in order to ensure the insulation of the substrate 3.

そして図１（ａ）のように基材３を形成した後は、図１（ｂ）のようにこの基材３の表面をレジスト６で被覆する。レジスト６としては、めっきに強いものであれば特に限定されるものではないが、例えば液状のものやフィルム状のものを用いることができ、また感光性のあるものを用いることができる。またレジスト６はアルカリ除去タイプと溶剤除去タイプに分けられるが、環境負荷の低減という観点から、アルカリ除去タイプが好ましい。   Then, after the base material 3 is formed as shown in FIG. 1A, the surface of the base material 3 is covered with a resist 6 as shown in FIG. The resist 6 is not particularly limited as long as it is resistant to plating. For example, a liquid or film-like resist can be used, and a photosensitive one can be used. The resist 6 can be divided into an alkali removal type and a solvent removal type, but the alkali removal type is preferable from the viewpoint of reducing environmental burden.

次に図１（ｃ）のようにこのレジスト６を貫通してレーザ加工等によりこの基材３に回路形成用の溝４（トレンチ）を形成する。図示省略しているが、感光性の絶縁樹脂１を用いている場合には、溝４を形成する部分をマスクで被覆し露光した後に現像することによって、溝４を形成することができる。   Next, as shown in FIG. 1C, a groove 4 (trench) for circuit formation is formed in the base material 3 through the resist 6 by laser processing or the like. Although not shown in the drawings, when the photosensitive insulating resin 1 is used, the groove 4 can be formed by covering the portion where the groove 4 is to be formed with a mask and developing the exposed portion.

このようにして溝４が形成されると、図１（ｃ）のように基材３中のめっき核２の一部が溝４の内面に露出するようになる。これらのめっき核２は通常不活性状態で露出しているので、図１（ｄ）のようにこれらのめっき核２を活性化して、後述する無電解めっき処理に備えるものである。なお、図１では不活性状態のめっき核２を白抜きで、活性状態のめっき核２を黒塗りで示している。そして、めっき核２として金属酸化物を用いている場合には、ジメチルアミノボラン等の還元剤で処理することによって活性化することができる。まためっき核２として有機物で表面が被覆された金属粒子や金属錯体を用いている場合には、ＹＡＧレーザ等のレーザで有機物を焼き飛ばすことによって活性化することができる。特にこの場合は溝４の形成とめっき核２の活性化を同時に行うことができる。まためっき核２として金属が担持された多孔体を用いている場合には、無機物である多孔体をアルカリで除去することによって活性化することができる。まためっき核２として金属ナノ粒子を用いている場合には、活性化処理は特に不要であるが、金属ナノ粒子の表面が絶縁樹脂１の薄膜で被覆されているおそれがあるので、万全を期すために、酸で軽く処理することによって活性化するのが好ましい。   When the groove 4 is formed in this way, a part of the plating nucleus 2 in the substrate 3 is exposed to the inner surface of the groove 4 as shown in FIG. Since these plating nuclei 2 are normally exposed in an inactive state, the plating nuclei 2 are activated as shown in FIG. 1D to prepare for an electroless plating process to be described later. In FIG. 1, the plating nucleus 2 in an inactive state is shown in white, and the plating nucleus 2 in an active state is shown in black. And when the metal oxide is used as the plating nucleus 2, it can be activated by treating with a reducing agent such as dimethylaminoborane. In addition, when metal particles or metal complexes whose surfaces are coated with an organic substance are used as the plating nucleus 2, the plating nucleus 2 can be activated by burning off the organic substance with a laser such as a YAG laser. Particularly in this case, the formation of the groove 4 and the activation of the plating nucleus 2 can be performed simultaneously. Moreover, when the porous body with which the metal was carry | supported is used as the plating nucleus 2, it can activate by removing the porous body which is an inorganic substance with an alkali. Further, when metal nanoparticles are used as the plating nucleus 2, the activation treatment is not particularly necessary, but since the surface of the metal nanoparticles may be covered with a thin film of the insulating resin 1, it is ensured. Therefore, it is preferable to activate by lightly treating with an acid.

その後、図１（ｅ）のように無電解銅めっき処理などの無電解めっき処理によって溝４に回路５を形成した後にレジスト６を除去すると、図１（ｆ）に示すようなプリント配線板を得ることができる。   Thereafter, when the resist 6 is removed after the circuit 5 is formed in the groove 4 by electroless plating such as electroless copper plating as shown in FIG. 1E, a printed wiring board as shown in FIG. Obtainable.

このように、本発明ではめっき核２の活性化の際に還元剤、アルカリ、酸を少量用いるだけであり、過マンガン酸処理液、エッチング液などの薬液は一切用いないので、環境負荷を低減することができるものである。また本発明では回路５の形成の際に電解めっき処理を行う必要がないので、回路５の厚みが不均一になるのを防止することができるものである。また本発明では溝４の内部に回路５を形成するので、基材３に対する回路５の密着性が向上し、高い信頼性を得ることができるものである。また本発明では不活性状態のめっき核２を絶縁樹脂１に分散させているので、回路５間の絶縁信頼性が高くなり、従来よりも微細な回路５を形成することができるものである。さらに本発明では溝４の形成の前に基材３の表面をレジスト６で被覆しているので、仮に溝４以外の基材３の表面にめっき核２が露出していても、このめっき核２が活性化されるのをレジスト６で防止することができるものである。よって、溝４以外の基材３の表面に露出しているめっき核２を不活性状態に保持することができ、これにより回路５間の絶縁信頼性が高くなり、従来よりも微細な回路５を形成することができるものである。なお、金属ナノ粒子は通常活性状態であるが、その添加量を０．５質量％以下に設定することによって、同様の効果を得ることができるものである。   As described above, in the present invention, only a small amount of reducing agent, alkali, and acid are used when activating the plating nucleus 2, and no chemical solution such as permanganic acid treatment solution or etching solution is used. Is something that can be done. Further, in the present invention, it is not necessary to perform an electroplating process when forming the circuit 5, so that the thickness of the circuit 5 can be prevented from becoming uneven. Further, in the present invention, since the circuit 5 is formed inside the groove 4, the adhesion of the circuit 5 to the base material 3 is improved, and high reliability can be obtained. Further, in the present invention, since the plating nucleus 2 in an inactive state is dispersed in the insulating resin 1, the insulation reliability between the circuits 5 is increased, and the circuit 5 that is finer than the prior art can be formed. Furthermore, in the present invention, since the surface of the base material 3 is coated with the resist 6 before the formation of the groove 4, even if the plating nucleus 2 is exposed on the surface of the base material 3 other than the groove 4, this plating nucleus The resist 6 can prevent 2 from being activated. Therefore, the plating nucleus 2 exposed on the surface of the base material 3 other than the groove 4 can be kept in an inactive state, thereby increasing the insulation reliability between the circuits 5 and making the circuit 5 finer than before. Can be formed. The metal nanoparticles are usually in an active state, but the same effect can be obtained by setting the addition amount to 0.5% by mass or less.

本発明の実施の形態の一例を示すものであり、（ａ）〜（ｆ）は断面図である。An example of embodiment of this invention is shown and (a)-(f) is sectional drawing. 従来の技術の一例を示すものであり、（ａ）〜（ｇ）は断面図である。An example of the prior art is shown, and (a) to (g) are cross-sectional views.

符号の説明Explanation of symbols

１ 絶縁樹脂
２ めっき核
３ 基材
４ 溝
５ 回路
６ レジスト DESCRIPTION OF SYMBOLS 1 Insulating resin 2 Plating nucleus 3 Base material 4 Groove 5 Circuit 6 Resist

Claims (2)

絶縁樹脂にめっき核を分散させて調製されためっき核入り絶縁樹脂組成物で基材を形成し、この基材の表面をレジストで被覆すると共にこのレジストを貫通してこの基材に溝を形成し、溝の内面に露出しためっき核を活性化すると共に無電解めっき処理によって溝に回路を形成した後にレジストを除去することを特徴とするプリント配線板の製造方法。   A base material is formed with an insulating resin composition containing a plating core prepared by dispersing plating nuclei in an insulating resin, and the surface of the base material is covered with a resist and a groove is formed in the base material through the resist. And a method for producing a printed wiring board, wherein the plating nucleus exposed on the inner surface of the groove is activated and a resist is removed after forming a circuit in the groove by electroless plating. めっき核として、金属酸化物、有機物で表面が被覆された金属粒子、金属錯体、金属が担持された多孔体、金属ナノ粒子の中から選ばれるものを用いることを特徴とする請求項１に記載のプリント配線板の製造方法。   The plating nucleus is selected from metal oxides, metal particles whose surfaces are coated with an organic substance, metal complexes, porous bodies carrying metals, and metal nanoparticles. Manufacturing method of printed wiring board.
JP2007248124A 2007-09-25 2007-09-25 Method for manufacturing printed wiring board Pending JP2009081208A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011029494A (en) * 2009-07-28 2011-02-10 Panasonic Electric Works Co Ltd Circuit board and method of manufacturing the same
JP2011091353A (en) * 2009-10-26 2011-05-06 Kinko Denshi Kofun Yugenkoshi Circuit structure
JP2011096993A (en) * 2009-10-29 2011-05-12 Kinko Denshi Kofun Yugenkoshi Method of manufacturing circuit structure
JP2011100797A (en) * 2009-11-04 2011-05-19 Panasonic Electric Works Co Ltd Circuit board
US9070393B2 (en) 2009-01-27 2015-06-30 Panasonic Corporation Three-dimensional structure in which wiring is provided on its surface
EP3886147A1 (en) * 2020-03-24 2021-09-29 STMicroelectronics S.r.l. Method of manufacturing semiconductor devices and corresponding device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05195235A (en) * 1992-01-17 1993-08-03 Tekunia Iwate Kyodo Kumiai Plating method of nonconductive material
JPH05218621A (en) * 1992-02-04 1993-08-27 Ibiden Co Ltd Manufacture of printed wiring board
JPH05235508A (en) * 1992-02-21 1993-09-10 Matsushita Electric Works Ltd Manufacture of ceramic wiring board
JPH0936522A (en) * 1995-07-14 1997-02-07 Fuji Kiko Denshi Kk Formation of circuit of printed-wiring board
JP2006005068A (en) * 2004-06-16 2006-01-05 Seiko Epson Corp Semiconductor device and its manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05195235A (en) * 1992-01-17 1993-08-03 Tekunia Iwate Kyodo Kumiai Plating method of nonconductive material
JPH05218621A (en) * 1992-02-04 1993-08-27 Ibiden Co Ltd Manufacture of printed wiring board
JPH05235508A (en) * 1992-02-21 1993-09-10 Matsushita Electric Works Ltd Manufacture of ceramic wiring board
JPH0936522A (en) * 1995-07-14 1997-02-07 Fuji Kiko Denshi Kk Formation of circuit of printed-wiring board
JP2006005068A (en) * 2004-06-16 2006-01-05 Seiko Epson Corp Semiconductor device and its manufacturing method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9070393B2 (en) 2009-01-27 2015-06-30 Panasonic Corporation Three-dimensional structure in which wiring is provided on its surface
JP2011029494A (en) * 2009-07-28 2011-02-10 Panasonic Electric Works Co Ltd Circuit board and method of manufacturing the same
JP2011091353A (en) * 2009-10-26 2011-05-06 Kinko Denshi Kofun Yugenkoshi Circuit structure
JP2011096993A (en) * 2009-10-29 2011-05-12 Kinko Denshi Kofun Yugenkoshi Method of manufacturing circuit structure
TWI392419B (en) * 2009-10-29 2013-04-01 Unimicron Technology Corp Manufacturing method of circuit structure
JP2011100797A (en) * 2009-11-04 2011-05-19 Panasonic Electric Works Co Ltd Circuit board
EP3886147A1 (en) * 2020-03-24 2021-09-29 STMicroelectronics S.r.l. Method of manufacturing semiconductor devices and corresponding device
US11626379B2 (en) 2020-03-24 2023-04-11 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding semiconductor device

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