JP2009071253A - Isolator - Google Patents

Isolator Download PDF

Info

Publication number
JP2009071253A
JP2009071253A JP2007241136A JP2007241136A JP2009071253A JP 2009071253 A JP2009071253 A JP 2009071253A JP 2007241136 A JP2007241136 A JP 2007241136A JP 2007241136 A JP2007241136 A JP 2007241136A JP 2009071253 A JP2009071253 A JP 2009071253A
Authority
JP
Japan
Prior art keywords
primary
coil
substrate
side substrate
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007241136A
Other languages
Japanese (ja)
Other versions
JP5088059B2 (en
Inventor
Masashi Akaha
正志 赤羽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Device Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Device Technology Co Ltd filed Critical Fuji Electric Device Technology Co Ltd
Priority to JP2007241136A priority Critical patent/JP5088059B2/en
Publication of JP2009071253A publication Critical patent/JP2009071253A/en
Application granted granted Critical
Publication of JP5088059B2 publication Critical patent/JP5088059B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Coils Or Transformers For Communication (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive isolator by making unnecessary a through-hole which penetrates an upper side substrate. <P>SOLUTION: In the isolator, a primary coil 31 and a primary side pad 32 electrically connected to this are provided on a main surface of a primary side substrate 33. A secondary coil 41 and a secondary side pad 42 electrically connected to this are provided on a main surface of a secondary side substrate 43. The primary coil 31 and the secondary coil 41 are laminated so that these may be insulated each other by an insulator 51, and these may overlap up and down. In this case, the primary side pad 32 is constituted so that it may not overlap with the secondary side substrate 43 and the insulator 51, and the secondary side pad 42 is constituted so that it may not overlap with the primary side substrate 33 and the insulator 51. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

この発明は、アイソレータに関する。   The present invention relates to an isolator.

従来、アイソレータとして、信号の伝達手段に光を利用したフォトカプラが公知である。フォトカプラのパッケージ構造では、発光素子と受光素子を対向させるため、発光素子を実装したリードフレームと、受光素子を実装したリードフレームは、上下に重なるように対向して配置される（例えば、特許文献１参照。）。   Conventionally, as an isolator, a photocoupler using light as a signal transmission means is known. In the package structure of the photocoupler, the light emitting element and the light receiving element are opposed to each other. Therefore, the lead frame on which the light emitting element is mounted and the lead frame on which the light receiving element is mounted are arranged to face each other so as to overlap each other. Reference 1).

また、磁気を利用して信号を伝達する磁気カプラが公知である。磁気カプラのパッケージ構造として、一次コイルを実装したリードフレームと、二次コイルを実装したリードフレームを、上下に重ならないように同一平面内において対向させた構造が公知である（例えば、特許文献２参照。）。磁気カプラは、送信回路や受信回路とともに集積化するのに適している。その理由の一つは、通常のＩＣ（Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔ）のプロセスで半導体基板上にコイルを作製することができるからである。   Magnetic couplers that transmit signals using magnetism are known. As a package structure of a magnetic coupler, a structure in which a lead frame mounted with a primary coil and a lead frame mounted with a secondary coil are opposed to each other in the same plane so as not to overlap each other is known (for example, Patent Document 2). reference.). The magnetic coupler is suitable for integration with a transmission circuit and a reception circuit. One of the reasons is that a coil can be formed on a semiconductor substrate by a normal IC (Integrated Circuit) process.

図５は、従来のアイソレータの構成を示す断面図である。ただし、図５では、パッケージの封止樹脂が省略されている（図１〜図４においても同じ）。図５に示すように、従来のアイソレータは、一次側基板１の上面に形成された一次コイル２と、二次側基板３の下面に形成された二次コイル４を、接着テープ５，６を介して絶縁体７の両面に接着した構成となっている。   FIG. 5 is a cross-sectional view showing a configuration of a conventional isolator. However, in FIG. 5, the sealing resin of the package is omitted (the same applies to FIGS. 1 to 4). As shown in FIG. 5, the conventional isolator includes a primary coil 2 formed on the upper surface of the primary side substrate 1 and a secondary coil 4 formed on the lower surface of the secondary side substrate 3. It is configured to be bonded to both surfaces of the insulator 7 via the intermediate member.

一次側基板１は、一次側リードフレーム８のアイランド（ダイパッド）９に接着剤１０により接着されている。一次側基板１には、一次コイル２に接続された送信回路１１と、送信回路１１に接続されたパッド１２が設けられている。パッド１２と一次側リードフレーム８とは、金属ワイヤ１３により電気的に接続されている。   The primary side substrate 1 is bonded to an island (die pad) 9 of the primary side lead frame 8 with an adhesive 10. The primary substrate 1 is provided with a transmission circuit 11 connected to the primary coil 2 and a pad 12 connected to the transmission circuit 11. The pad 12 and the primary lead frame 8 are electrically connected by a metal wire 13.

二次側基板３の上面には、パッド１４が設けられている。このパッド１４と二次コイル４は、二次側基板３を貫通するスルーホール内に充填された導電体１５により電気的に接続されている。二次側リードフレーム１６のインナーリード部１７には、受信回路１８が設けられている。二次側基板３のパッド１４と受信回路１８とは、金属ワイヤ１９により電気的に接続されている。受信回路１８と二次側リードフレーム１６とは、金属ワイヤ２０により電気的に接続されている。なお、一次コイル２と二次コイル４の積層構造が上下逆の場合もある。   A pad 14 is provided on the upper surface of the secondary substrate 3. The pad 14 and the secondary coil 4 are electrically connected by a conductor 15 filled in a through hole penetrating the secondary side substrate 3. A receiving circuit 18 is provided in the inner lead portion 17 of the secondary lead frame 16. The pad 14 of the secondary substrate 3 and the receiving circuit 18 are electrically connected by a metal wire 19. The receiving circuit 18 and the secondary side lead frame 16 are electrically connected by a metal wire 20. In addition, the laminated structure of the primary coil 2 and the secondary coil 4 may be upside down.

特開平８−９７４６３号公報（段落［００１６］）JP-A-8-97463 (paragraph [0016]) 特開平１０−１８９３６８号公報（段落［００１０］）Japanese Patent Laid-Open No. 10-189368 (paragraph [0010])

しかしながら、上述した従来のアイソレータでは、二次側基板３を貫通するスルーホールを形成する必要があるため、製造コストが増大するという問題点がある。また、二次側基板３のパッド１４と受信回路１８を金属ワイヤ１９で接続し、さらに、受信回路１８と二次側リードフレーム１６を金属ワイヤ２０で接続する必要があるため、金属ワイヤによる接続箇所が増えてしまい、製造コストが増大するという問題点がある。一次コイル２と二次コイル４の積層構造が上下逆の場合も同様である。   However, in the conventional isolator described above, it is necessary to form a through hole penetrating the secondary side substrate 3, so that there is a problem that the manufacturing cost increases. Further, since it is necessary to connect the pad 14 of the secondary side substrate 3 and the receiving circuit 18 with the metal wire 19 and further connect the receiving circuit 18 and the secondary side lead frame 16 with the metal wire 20, the connection with the metal wire is required. There is a problem that the number of locations increases and the manufacturing cost increases. The same applies to the case where the laminated structure of the primary coil 2 and the secondary coil 4 is upside down.

この発明は、上述した従来技術による問題点を解消するため、安価なアイソレータを提供することを目的とする。   An object of the present invention is to provide an inexpensive isolator in order to solve the above-described problems caused by the prior art.

上述した課題を解決し、目的を達成するため、請求項１の発明にかかるアイソレータは、一次側基板の主面に一次コイルと該一次コイルに電気的に接続された一次側パッドが設けられ、二次側基板の主面に二次コイルと該二次コイルに電気的に接続された二次側パッドが設けられ、前記一次コイルと前記二次コイルが互いに絶縁された状態で積層された構造のトランスを有するアイソレータにおいて、前記一次側パッドは、前記二次側基板に重ならない領域に配置されており、前記二次側パッドは、前記一次側基板に重ならない領域に配置されていることを特徴とする。   In order to solve the above-mentioned problems and achieve the object, the isolator according to the invention of claim 1 is provided with a primary coil and a primary pad electrically connected to the primary coil on the main surface of the primary substrate, A structure in which a secondary coil and a secondary pad electrically connected to the secondary coil are provided on the main surface of the secondary substrate, and the primary coil and the secondary coil are laminated in a mutually insulated state In the isolator having the transformer, the primary pad is disposed in a region that does not overlap the secondary substrate, and the secondary pad is disposed in a region that does not overlap the primary substrate. Features.

また、請求項２の発明にかかるアイソレータは、請求項１に記載の発明において、前記一次側基板の前記主面に送信回路が設けられており、該送信回路が、前記二次側基板に重ならない領域に配置されていることを特徴とする。   An isolator according to a second aspect of the present invention is the isolator according to the first aspect, wherein a transmission circuit is provided on the main surface of the primary side substrate, and the transmission circuit overlaps the secondary side substrate. It is characterized by being arranged in a region that should not be.

また、請求項３の発明にかかるアイソレータは、請求項１または２に記載の発明において、前記二次側基板の前記主面に受信回路が設けられており、該受信回路が、前記一次側基板に重ならない領域に配置されていることを特徴とする。   An isolator according to a third aspect of the present invention is the isolator according to the first or second aspect, wherein a receiving circuit is provided on the main surface of the secondary side substrate, and the receiving circuit is connected to the primary side substrate. It is arrange | positioned in the area | region which does not overlap.

また、請求項４の発明にかかるアイソレータは、請求項１〜３のいずれか一つに記載の発明において、同一の前記一次側基板に複数の前記一次コイルが設けられており、同一の前記二次側基板に複数の前記二次コイルが設けられており、複数の前記一次コイルおよび複数の前記二次コイルにより複数のトランスが構成されていることを特徴とする。   An isolator according to a fourth aspect of the present invention is the isolator according to any one of the first to third aspects, wherein a plurality of the primary coils are provided on the same primary substrate, and the same two The secondary substrate is provided with a plurality of secondary coils, and the plurality of primary coils and the plurality of secondary coils constitute a plurality of transformers.

この発明によれば、一次側パッドおよび二次側パッドは、それぞれ、一次側リードフレームおよび二次側リードフレームとのワイヤボンディングを行うことが可能な位置にあるので、上側の基板を貫通するスルーホールが不要となる。また、既存のフォトカプラの製造ラインをそのまま利用して作製することができるので、新たな設備投資を行わずに済む。さらに、上側の基板のパッドとリードフレームとを金属ワイヤで直接、電気的に接続することができるので、ワイヤボンディングの回数および金属ワイヤの消費量が減る。   According to the present invention, the primary side pad and the secondary side pad are in positions where wire bonding with the primary side lead frame and the secondary side lead frame can be performed, respectively. A hole is not required. In addition, since existing photocoupler production lines can be used as they are, no new capital investment is required. Furthermore, since the pads of the upper substrate and the lead frame can be directly electrically connected with metal wires, the number of wire bondings and the consumption of metal wires are reduced.

本発明にかかるアイソレータによれば、安価なアイソレータが得られるという効果を奏する。   The isolator according to the present invention has an effect that an inexpensive isolator can be obtained.

以下に添付図面を参照して、この発明にかかるアイソレータの好適な実施の形態を詳細に説明する。なお、以下の各実施の形態の説明において、同様の構成には同一の符号を付して、重複する説明を省略する。   Exemplary embodiments of an isolator according to the present invention will be described below in detail with reference to the accompanying drawings. In the following description of each embodiment, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

実施の形態１．
図１は、本発明の実施の形態１にかかるアイソレータの構成を示す平面図であり、図２は、図１の切断線Ａ−Ａにおける構成を示す縦断面図である。 Embodiment 1 FIG.
FIG. 1 is a plan view showing the configuration of the isolator according to the first embodiment of the present invention, and FIG. 2 is a longitudinal sectional view showing the configuration along the cutting line AA in FIG.

これらの図に示すように、一次コイル３１と、この一次コイル３１に電気的に接続された一次側パッド３２は、一次側基板３３の同一の主面（図２では、上面）に設けられている。一次側基板３３の下面は、一次側リードフレーム３４のアイランド３５に導電性または絶縁性の接着剤３６により接着されている。なお、接着剤３６の代わりに、導電性または絶縁性の接着テープが用いられていてもよい。一次側パッド３２は、金属ワイヤ３７により一次側リードフレーム３４のインナーリード部に電気的に接続されている。一次側リードフレーム３４は、そのインナーリード部において、一次側基板３３が接着されている側と反対側に折り曲げられている。   As shown in these drawings, the primary coil 31 and the primary side pad 32 electrically connected to the primary coil 31 are provided on the same main surface (upper surface in FIG. 2) of the primary side substrate 33. Yes. The lower surface of the primary side substrate 33 is bonded to the island 35 of the primary side lead frame 34 with a conductive or insulating adhesive 36. Instead of the adhesive 36, a conductive or insulating adhesive tape may be used. The primary side pad 32 is electrically connected to the inner lead portion of the primary side lead frame 34 by a metal wire 37. The primary lead frame 34 is bent at the inner lead portion thereof on the side opposite to the side to which the primary side substrate 33 is bonded.

また、二次コイル４１と、この二次コイル４１に電気的に接続された二次側パッド４２は、二次側基板４３の同一の主面（図２では、下面）に設けられている。二次側基板４３の上面は、二次側リードフレーム４４のアイランド４５に導電性または絶縁性の接着剤４６により接着されている。なお、接着剤４６の代わりに、導電性または絶縁性の接着テープが用いられていてもよい。二次側パッド４２は、金属ワイヤ４７により二次側リードフレーム４４のインナーリード部に電気的に接続されている。二次側リードフレーム４４は、そのインナーリード部において、二次側基板４３が接着されている側に折り曲げられている。   Further, the secondary coil 41 and the secondary side pad 42 electrically connected to the secondary coil 41 are provided on the same main surface (the lower surface in FIG. 2) of the secondary side substrate 43. The upper surface of the secondary side substrate 43 is bonded to the island 45 of the secondary side lead frame 44 with a conductive or insulating adhesive 46. Instead of the adhesive 46, a conductive or insulating adhesive tape may be used. The secondary pad 42 is electrically connected to the inner lead portion of the secondary lead frame 44 by a metal wire 47. The secondary lead frame 44 is bent at the inner lead portion thereof to the side where the secondary substrate 43 is bonded.

一次コイル３１は、絶縁体５１の下面に接着テープ５２を介して接着されている。二次コイル４１は、絶縁体５１の上面に接着テープ５３を介して接着されている。絶縁体５１は、例えば、アルミナ等の無機材料や、ポリイミド等の有機材料でできている。なお、接着テープ５２，５３の代わりに、接着剤が用いられていてもよい。このように、一次コイル３１と二次コイル４１が絶縁体５１により相互に絶縁され、かつ上下に重なるように積層された構造において、一次側パッド３２は、二次側基板４３および絶縁体５１と重ならない位置に設けられている。同様に、二次側パッド４２は、一次側基板３３および絶縁体５１と重ならない位置に設けられている。   The primary coil 31 is bonded to the lower surface of the insulator 51 via an adhesive tape 52. The secondary coil 41 is bonded to the upper surface of the insulator 51 via an adhesive tape 53. The insulator 51 is made of, for example, an inorganic material such as alumina or an organic material such as polyimide. Note that an adhesive may be used instead of the adhesive tapes 52 and 53. In this way, in the structure in which the primary coil 31 and the secondary coil 41 are insulated from each other by the insulator 51 and stacked so as to overlap each other, the primary pad 32 is connected to the secondary substrate 43 and the insulator 51. It is provided in a position that does not overlap. Similarly, the secondary pad 42 is provided at a position that does not overlap the primary substrate 33 and the insulator 51.

上述した構成のアイソレータは、従来のフォトカプラの組み立て工程と同様の工程により製造される。まず、一次側基板３３の主面に一次コイル３１および一次側パッド３２を形成する。次いで、一次側リードフレーム３４のアイランド３５に一次側基板３３を接着剤３６（または、接着テープ）により接着する。そして、ワイヤボンディングを行い、一次側パッド３２と一次側リードフレーム３４に金属ワイヤ３７を接続する。   The isolator having the above-described configuration is manufactured by a process similar to a conventional photocoupler assembly process. First, the primary coil 31 and the primary side pad 32 are formed on the main surface of the primary side substrate 33. Next, the primary side substrate 33 is bonded to the island 35 of the primary side lead frame 34 with an adhesive 36 (or adhesive tape). Then, wire bonding is performed to connect a metal wire 37 to the primary side pad 32 and the primary side lead frame 34.

また、二次側基板４３の主面に二次コイル４１および二次側パッド４２を形成する。次いで、二次側リードフレーム４４のアイランド４５に二次側基板４３を接着剤４６（または、接着テープ）により接着する。そして、ワイヤボンディングを行い、二次側パッド４２と二次側リードフレーム４４に金属ワイヤ４７を接続する。   Further, the secondary coil 41 and the secondary pad 42 are formed on the main surface of the secondary substrate 43. Next, the secondary substrate 43 is bonded to the island 45 of the secondary lead frame 44 with an adhesive 46 (or adhesive tape). Then, wire bonding is performed to connect the metal wire 47 to the secondary side pad 42 and the secondary side lead frame 44.

次いで、一次コイル３１と絶縁体５１を接着テープ５２（または、接着剤）により貼り合わせる。そして、一次側リードフレーム３４と二次側リードフレーム４４の位置合わせを行い、所定の位置で、二次コイル４１と絶縁体５１を接着テープ５３（または、接着剤）により貼り合わせる。その後、樹脂で封止する。なお、先に二次コイル４１に絶縁体５１を接着しておいてから、一次コイル３１と絶縁体５１を貼り合わせるようにしてもよい。   Next, the primary coil 31 and the insulator 51 are bonded together with an adhesive tape 52 (or adhesive). Then, the primary side lead frame 34 and the secondary side lead frame 44 are aligned, and the secondary coil 41 and the insulator 51 are bonded together with an adhesive tape 53 (or adhesive) at a predetermined position. Then, it seals with resin. Note that the primary coil 31 and the insulator 51 may be bonded together after the insulator 51 is bonded to the secondary coil 41 first.

実施の形態２．
図３は、本発明の実施の形態２にかかるアイソレータの構成を示す縦断面図であり、図１の切断線Ａ−Ａにおける構成に相当する図である。図３に示すように、実施の形態２では、一次側基板３３の、一次コイル３１が設けられている面と同じ面に送信回路３８が設けられている。一次コイル３１および一次側パッド３２は、送信回路３８に接続されている。送信回路３８は、一次側基板３３と二次側基板４３を積層した構造において、二次側基板４３および絶縁体５１と重ならない位置に設けられている。 Embodiment 2. FIG.
FIG. 3 is a longitudinal sectional view showing the configuration of the isolator according to the second embodiment of the present invention, and is a diagram corresponding to the configuration taken along section line AA of FIG. As shown in FIG. 3, in the second embodiment, the transmission circuit 38 is provided on the same surface of the primary substrate 33 as the surface on which the primary coil 31 is provided. The primary coil 31 and the primary side pad 32 are connected to the transmission circuit 38. In the structure in which the primary side substrate 33 and the secondary side substrate 43 are stacked, the transmission circuit 38 is provided at a position that does not overlap the secondary side substrate 43 and the insulator 51.

また、二次側基板４３の、二次コイル４１が設けられている面と同じ面に受信回路４８が設けられている。二次コイル４１および二次側パッド４２は、受信回路４８に接続されている。受信回路４８は、一次側基板３３と二次側基板４３を積層した構造において、一次側基板３３および絶縁体５１と重ならない位置に設けられている。   The receiving circuit 48 is provided on the same surface of the secondary substrate 43 as the surface on which the secondary coil 41 is provided. The secondary coil 41 and the secondary pad 42 are connected to the receiving circuit 48. In the structure in which the primary side substrate 33 and the secondary side substrate 43 are stacked, the reception circuit 48 is provided at a position that does not overlap the primary side substrate 33 and the insulator 51.

実施の形態２では、一次側基板３３および二次側基板４３は、シリコンでできている。そして、一般的なＩＣのプロセスで一次側基板３３に送信回路３８と一次コイル３１と一次側パッド３２が形成される。同様に、一般的なＩＣのプロセスで二次側基板４３に受信回路４８と二次コイル４１と二次側パッド４２が形成される。その他の構成および製造工程は、実施の形態１と同じである。   In the second embodiment, the primary side substrate 33 and the secondary side substrate 43 are made of silicon. Then, the transmission circuit 38, the primary coil 31, and the primary side pad 32 are formed on the primary side substrate 33 by a general IC process. Similarly, the receiving circuit 48, the secondary coil 41, and the secondary pad 42 are formed on the secondary substrate 43 by a general IC process. Other configurations and manufacturing processes are the same as those in the first embodiment.

実施の形態３．
図４は、本発明の実施の形態３にかかるアイソレータの構成を示す縦断面図であり、図１の切断線Ａ−Ａにおける構成に相当する図である。図４に示すように、実施の形態３では、一次側基板３３に複数、例えば第１の一次コイル３１と第２の一次コイル３９が設けられており、二次側基板４３に複数、例えば第１の二次コイル４１と第２の二次コイル４９が設けられている。 Embodiment 3 FIG.
FIG. 4 is a longitudinal sectional view showing the structure of the isolator according to the third embodiment of the present invention, and is a view corresponding to the structure taken along the cutting line AA of FIG. As shown in FIG. 4, in the third embodiment, a plurality of, for example, the first primary coil 31 and the second primary coil 39 are provided on the primary side substrate 33, and a plurality of, for example, the first side coil 43 is provided on the secondary side substrate 43. One secondary coil 41 and a second secondary coil 49 are provided.

第１の一次コイル３１と第１の二次コイル４１は、第１のトランス６１（一点鎖線で囲む）を構成する。第２の一次コイル３９と第２の二次コイル４９は、第２のトランス６２（一点鎖線で囲む）を構成する。このように、一次側基板３３と二次側基板４３で、複数のトランスが構成されていてもよい。なお、トランスの数は、３個以上でもよい。その他の構成および製造工程は、実施の形態１と同じである。   The first primary coil 31 and the first secondary coil 41 constitute a first transformer 61 (enclosed by a one-dot chain line). The second primary coil 39 and the second secondary coil 49 constitute a second transformer 62 (enclosed by a one-dot chain line). In this way, the primary side substrate 33 and the secondary side substrate 43 may constitute a plurality of transformers. Note that the number of transformers may be three or more. Other configurations and manufacturing processes are the same as those in the first embodiment.

以上説明したように、実施の形態によれば、一次側パッド３２および二次側パッド４２が、それぞれ、一次側リードフレーム３４および二次側リードフレーム４４とのワイヤボンディングを行うことが可能な位置にあるので、二次側基板４３を貫通するスルーホールを形成する必要がない。また、既存のフォトカプラの製造ラインをそのまま利用して作製することができるので、新たに設備投資を行う必要がない。さらに、二次側パッド４２と二次側リードフレーム４４とを金属ワイヤ４７で直接、電気的に接続することができるので、ワイヤボンディングの回数および金属ワイヤの消費量が減る。従って、安価なアイソレータが得られるという効果を奏する。また、一次側基板３３側の金属ワイヤ３７と二次側基板４３の間の距離、および二次側基板４３側の金属ワイヤ４７と一次側基板３３の間の距離が長くなるので、絶縁耐圧が高くなるという効果も得られる。   As described above, according to the embodiment, the positions at which the primary side pad 32 and the secondary side pad 42 can perform wire bonding with the primary side lead frame 34 and the secondary side lead frame 44, respectively. Therefore, it is not necessary to form a through hole that penetrates the secondary side substrate 43. In addition, since existing photocoupler production lines can be used as they are, it is not necessary to make new capital investment. Further, since the secondary side pad 42 and the secondary side lead frame 44 can be directly electrically connected by the metal wire 47, the number of wire bonding and the consumption of the metal wire are reduced. Therefore, there is an effect that an inexpensive isolator can be obtained. Further, since the distance between the metal wire 37 on the primary side substrate 33 side and the secondary side substrate 43 and the distance between the metal wire 47 on the secondary side substrate 43 side and the primary side substrate 33 are increased, the withstand voltage is reduced. The effect that it becomes high is also acquired.

以上において本発明は、上述した実施の形態に限らず、種々変更可能である。例えば、一次コイル３１，３９と二次コイル４１，４９の積層構造が上下逆の場合も同様である。   As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the same applies to the case where the laminated structure of the primary coils 31 and 39 and the secondary coils 41 and 49 is upside down.

以上のように、本発明にかかるアイソレータは、ＥＳＤ（Ｅｌｅｃｔｒｏｓｔａｔｉｃ Ｄｉｓｃｈａｒｇｅ、静電気放電）対策の必要な電子回路に有用であり、特に、車両用のモジュールに適している。   As described above, the isolator according to the present invention is useful for an electronic circuit that needs countermeasures against ESD (Electrostatic Discharge), and is particularly suitable for a module for a vehicle.

本発明の実施の形態１にかかるアイソレータの構成を示す平面図である。It is a top view which shows the structure of the isolator concerning Embodiment 1 of this invention. 図１の切断線Ａ−Ａにおける構成を示す縦断面図である。It is a longitudinal cross-sectional view which shows the structure in the cutting line AA of FIG. 本発明の実施の形態２にかかるアイソレータの構成を示す縦断面図である。It is a longitudinal cross-sectional view which shows the structure of the isolator concerning Embodiment 2 of this invention. 本発明の実施の形態３にかかるアイソレータの構成を示す縦断面図である。It is a longitudinal cross-sectional view which shows the structure of the isolator concerning Embodiment 3 of this invention. 従来のアイソレータの構成を示す断面図である。It is sectional drawing which shows the structure of the conventional isolator.

符号の説明Explanation of symbols

３１，３９ 一次コイル
３２ 一次側パッド
３３ 一次側基板
３８ 送信回路
４１，４９ 二次コイル
４２ 二次側パッド
４３ 二次側基板
４８ 受信回路
６１，６２ トランス 31, 39 Primary coil 32 Primary side pad 33 Primary side board 38 Transmission circuit 41, 49 Secondary coil 42 Secondary side pad 43 Secondary side board 48 Reception circuit 61, 62 Transformer

Claims (4)

一次側基板の主面に一次コイルと該一次コイルに電気的に接続された一次側パッドが設けられ、二次側基板の主面に二次コイルと該二次コイルに電気的に接続された二次側パッドが設けられ、前記一次コイルと前記二次コイルが互いに絶縁された状態で積層された構造のトランスを有するアイソレータにおいて、
前記一次側パッドは、前記二次側基板に重ならない領域に配置されており、前記二次側パッドは、前記一次側基板に重ならない領域に配置されていることを特徴とするアイソレータ。 A primary coil and a primary pad electrically connected to the primary coil are provided on the main surface of the primary side substrate, and a secondary coil and the secondary coil are electrically connected to the main surface of the secondary side substrate. In an isolator having a transformer having a structure in which a secondary pad is provided and the primary coil and the secondary coil are laminated in a mutually insulated state,
The isolator is characterized in that the primary pad is disposed in a region that does not overlap the secondary substrate, and the secondary pad is disposed in a region that does not overlap the primary substrate. 前記一次側基板の前記主面に送信回路が設けられており、該送信回路が、前記二次側基板に重ならない領域に配置されていることを特徴とする請求項１に記載のアイソレータ。   2. The isolator according to claim 1, wherein a transmission circuit is provided on the main surface of the primary side substrate, and the transmission circuit is disposed in a region that does not overlap the secondary side substrate. 前記二次側基板の前記主面に受信回路が設けられており、該受信回路が、前記一次側基板に重ならない領域に配置されていることを特徴とする請求項１または２に記載のアイソレータ。   3. The isolator according to claim 1, wherein a receiving circuit is provided on the main surface of the secondary side substrate, and the receiving circuit is arranged in a region that does not overlap the primary side substrate. . 同一の前記一次側基板に複数の前記一次コイルが設けられており、同一の前記二次側基板に複数の前記二次コイルが設けられており、複数の前記一次コイルおよび複数の前記二次コイルにより複数のトランスが構成されていることを特徴とする請求項１〜３のいずれか一つに記載のアイソレータ。   A plurality of the primary coils are provided on the same primary side substrate, a plurality of the secondary coils are provided on the same secondary side substrate, a plurality of the primary coils and a plurality of the secondary coils The isolator according to claim 1, wherein a plurality of transformers are configured.
JP2007241136A 2007-09-18 2007-09-18 Isolator and method of manufacturing isolator Expired - Fee Related JP5088059B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007241136A JP5088059B2 (en) 2007-09-18 2007-09-18 Isolator and method of manufacturing isolator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007241136A JP5088059B2 (en) 2007-09-18 2007-09-18 Isolator and method of manufacturing isolator

Publications (2)

Publication Number Publication Date
JP2009071253A true JP2009071253A (en) 2009-04-02
JP5088059B2 JP5088059B2 (en) 2012-12-05

Family

ID=40607152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007241136A Expired - Fee Related JP5088059B2 (en) 2007-09-18 2007-09-18 Isolator and method of manufacturing isolator

Country Status (1)

Country Link
JP (1) JP5088059B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011054800A (en) * 2009-09-02 2011-03-17 Renesas Electronics Corp Semiconductor device, method of manufacturing semiconductor device, and lead frame thereof
JP2015073108A (en) * 2014-11-06 2015-04-16 ルネサスエレクトロニクス株式会社 Semiconductor device, method of manufacturing semiconductor device, and lead frame
CN104637918A (en) * 2013-11-08 2015-05-20 瑞萨电子株式会社 Semiconductor device
JP2017106931A (en) * 2011-04-01 2017-06-15 ローム株式会社 Temperature detection device
CN116110894A (en) * 2022-12-27 2023-05-12 重庆线易电子科技有限责任公司 Digital isolator and electronic equipment

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5092691A (en) * 1973-12-13 1975-07-24
JPS6236883A (en) * 1985-06-25 1987-02-17 Yokogawa Hewlett Packard Ltd Manufacture of optical isolator
JPH08149054A (en) * 1994-11-25 1996-06-07 Japan Aviation Electron Ind Ltd Non-contact connector, signal transmitting and receiving method using the connector, and device performing the method
JPH11176675A (en) * 1997-12-09 1999-07-02 Tokin Corp Small-sized noncontact transmitter
JP2007123650A (en) * 2005-10-31 2007-05-17 Matsushita Electric Works Ltd Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5092691A (en) * 1973-12-13 1975-07-24
JPS6236883A (en) * 1985-06-25 1987-02-17 Yokogawa Hewlett Packard Ltd Manufacture of optical isolator
JPH08149054A (en) * 1994-11-25 1996-06-07 Japan Aviation Electron Ind Ltd Non-contact connector, signal transmitting and receiving method using the connector, and device performing the method
JPH11176675A (en) * 1997-12-09 1999-07-02 Tokin Corp Small-sized noncontact transmitter
JP2007123650A (en) * 2005-10-31 2007-05-17 Matsushita Electric Works Ltd Semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011054800A (en) * 2009-09-02 2011-03-17 Renesas Electronics Corp Semiconductor device, method of manufacturing semiconductor device, and lead frame thereof
US8753922B2 (en) 2009-09-02 2014-06-17 Renesas Electronics Corporation Method of manufacturing a semiconductor device
US8772914B2 (en) 2009-09-02 2014-07-08 Renesas Electronics Corporation Semiconductor device
JP2017106931A (en) * 2011-04-01 2017-06-15 ローム株式会社 Temperature detection device
CN104637918A (en) * 2013-11-08 2015-05-20 瑞萨电子株式会社 Semiconductor device
JP2015073108A (en) * 2014-11-06 2015-04-16 ルネサスエレクトロニクス株式会社 Semiconductor device, method of manufacturing semiconductor device, and lead frame
CN116110894A (en) * 2022-12-27 2023-05-12 重庆线易电子科技有限责任公司 Digital isolator and electronic equipment
CN116110894B (en) * 2022-12-27 2023-11-03 重庆线易电子科技有限责任公司 Digital isolator and electronic equipment

Also Published As

Publication number Publication date
JP5088059B2 (en) 2012-12-05

Similar Documents

Publication Publication Date Title
US8772914B2 (en) Semiconductor device
US9871036B2 (en) Semiconductor device
JP2007019498A (en) Semiconductor multi-chip package
US10553341B2 (en) Coil component and module including the same
JP5088059B2 (en) Isolator and method of manufacturing isolator
TW201312723A (en) Chip packaging structure and manufacturing method for the same
JP4071782B2 (en) Semiconductor device
JP2005033201A (en) Semiconductor package
JP2010123898A (en) Semiconductor device
JP2010050150A (en) Semiconductor device, and semiconductor module
JP2008103725A (en) Flexible film, semiconductor package using the flexible film and method for manufacturing the semiconductor package
US8129826B2 (en) Semiconductor package apparatus having redistribution layer
JP2008060597A (en) Power source circuit device
JP4435074B2 (en) Semiconductor device and manufacturing method thereof
WO2020090411A1 (en) Semiconductor device
US10510636B2 (en) Electronic module
CN107958875B (en) Semiconductor device and method for designing wiring board
JP2021082794A (en) Electronic component and electronic device
JP2007123649A (en) Semiconductor device
US20230309228A1 (en) Isolator
US20230093818A1 (en) Semiconductor device
JP2013239653A (en) Semiconductor device
JP2005209899A (en) Relay member and multichip package using relay member
US20240087802A1 (en) Isolator
US20240096542A1 (en) Signal transmission device

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20091112

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20091112

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20091112

A625 Written request for application examination (by other person)

Free format text: JAPANESE INTERMEDIATE CODE: A625

Effective date: 20100615

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20110422

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20111019

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111025

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111226

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120814

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120827

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150921

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 5088059

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees