JP2009049085A - Method for manufacturing silicon nitride film - Google Patents
Method for manufacturing silicon nitride film Download PDFInfo
- Publication number
- JP2009049085A JP2009049085A JP2007211927A JP2007211927A JP2009049085A JP 2009049085 A JP2009049085 A JP 2009049085A JP 2007211927 A JP2007211927 A JP 2007211927A JP 2007211927 A JP2007211927 A JP 2007211927A JP 2009049085 A JP2009049085 A JP 2009049085A
- Authority
- JP
- Japan
- Prior art keywords
- film
- sin film
- reaction chamber
- semiconductor wafer
- sin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Chemical Vapour Deposition (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
本発明は、半導体装置の製造工程において、PCVD法を用いて半導体ウェハ上に窒化シリコン膜を成膜するときの窒化シリコン膜の製造方法に関する。 The present invention relates to a method for manufacturing a silicon nitride film when a silicon nitride film is formed on a semiconductor wafer using a PCVD method in a manufacturing process of a semiconductor device.
一般に、半導体ウェハ上に窒化シリコン(Si3N4)からなる窒化シリコン膜(SiN膜という。)を形成する場合には、プラズマ誘起化学気相成長法(PCVD法という。)により、SiN膜の構成元素であるシリコン(Si)および窒素(N)の供給源として、例えば、モノシラン(SiH4)およびアンモニア(NH3)ガスを用い、キャリアガスを窒素(N2)として反応室中に導入し、基板温度300℃、反応室真空度800mTorr、周波数13.56MHz、高周波出力150Wの高電界中でプラズマ状態を発生させ、所定の成膜速度で半導体ウェハ上にSiN膜を成膜している(例えば、非特許文献1参照。)。 In general, when a silicon nitride film (referred to as SiN film) made of silicon nitride (Si 3 N 4 ) is formed on a semiconductor wafer, the SiN film is formed by plasma-induced chemical vapor deposition (referred to as PCVD method). For example, monosilane (SiH 4 ) and ammonia (NH 3 ) gas are used as a supply source of silicon (Si) and nitrogen (N), which are constituent elements, and a carrier gas is introduced into the reaction chamber as nitrogen (N 2 ). A plasma state is generated in a high electric field with a substrate temperature of 300 ° C., a reaction chamber vacuum of 800 mTorr, a frequency of 13.56 MHz, and a high frequency output of 150 W, and a SiN film is formed on the semiconductor wafer at a predetermined film formation rate ( For example, refer nonpatent literature 1.).
このようなSiN膜等の各種絶縁性層間膜の膜応力、屈折率(誘電率)等の膜特性は半導体装置の電気特性に直接影響を及ぼすために、製造工程、素子設計の観点から種々の検討がなされ、所定の電気特性を得られる様に膜特性の改善がなされてきており、実際のSiN膜の製造工程では、所定の膜応力、屈折率(誘電率)等を得るために、供給ガス構成比、プラズマパワー等の上記の成膜条件を適宜に変更することが行われている。 Since film characteristics such as SiN film and other insulating interlayer films such as film stress and refractive index (dielectric constant) directly affect the electrical characteristics of the semiconductor device, various characteristics are required from the viewpoint of manufacturing process and element design. The film characteristics have been improved so that predetermined electrical characteristics can be obtained, and in order to obtain predetermined film stress, refractive index (dielectric constant), etc. in the actual SiN film manufacturing process, supply The above-described film forming conditions such as gas composition ratio and plasma power are appropriately changed.
上記のPCVD法によるSiN膜は、半導体装置におけるMIM(Metal Insulator Metal)キャパシタのキャパシタ膜に適用され、半導体装置の大きさの縮小に伴うキャパシタ容量向上の必要性から、キャパシタ膜の高誘電率化という手法の他に、キャパシタ膜として用いるSiN膜の膜厚を薄くすることが提案されており、MIMキャパシタのメタル1上に形成したSiN膜を60nmに薄膜化したときに、その表面粗さの標準偏差(RMS)は2.6nmであるとしている(例えば、非特許文献2参照。)
また、上記のPCVD法によるSiN膜は、半導体ウェハにダマシン構造の配線を形成する際のハードマスクとして適用され、膜厚を50nmとしたSiN膜でハードマスクを形成し、これらをマスクとしてビアホールを形成した後に、エッチングにより除去している(例えば、特許文献1参照。)
The SiN film formed by the above PCVD method is applied as a hard mask when forming damascene wiring on a semiconductor wafer, and a hard mask is formed with a SiN film having a film thickness of 50 nm, and via holes are formed using these as masks. After the formation, it is removed by etching (for example, see Patent Document 1).
しかしながら、上述した非特許文献2および特許文献1の技術においては、SiN膜の膜厚が50〜60nmであるので、SiN膜の成膜後の表面粗さが問題となることはないが、例えば、半導体装置の小型化を図るために、キャパシタ容量を維持しながらMIMキャパシタを小型化するためには、キャパシタ膜として用いるSiN膜を更に薄膜化することが必要になり、更なる薄膜化を目指したSiN膜においては、膜厚に対する表面粗さの影響が相対的に大きくなり、膜厚が不均一になると、膜厚の薄い部分では電界が集中するため、キャパシタのメタル間でリークが発生することが懸念され、SiN膜の表面平坦性の向上に対する期待が高まっている。 However, in the techniques of Non-Patent Document 2 and Patent Document 1 described above, since the thickness of the SiN film is 50 to 60 nm, the surface roughness after the formation of the SiN film does not become a problem. In order to reduce the size of the semiconductor device, in order to reduce the size of the MIM capacitor while maintaining the capacitor capacity, it is necessary to further reduce the thickness of the SiN film used as the capacitor film. In the SiN film, the influence of the surface roughness on the film thickness becomes relatively large, and when the film thickness is non-uniform, the electric field concentrates at the thin film thickness portion, and therefore leakage occurs between the capacitors metal. There is concern about this, and there is an increasing expectation for improving the surface flatness of the SiN film.
また、ハードマスクとして用いるSiN膜においても、SiN膜を薄膜化すると、ビアホール等の形成における精度の向上や、ハードマスクのエッチング除去における除去時間の短縮等を図ることが可能になるので、SiN膜の表面平坦性の向上に対する期待が高まっている。
そこで、本発明は、PCVD法によるSiN膜の成膜後の表面平坦性を向上させる手段を提供することを目的とする。
Also, in the SiN film used as a hard mask, if the SiN film is thinned, it becomes possible to improve the accuracy in forming via holes and the like, and shorten the removal time in etching removal of the hard mask. There is an increasing expectation for improving the surface flatness.
Therefore, an object of the present invention is to provide means for improving the surface flatness after the formation of a SiN film by the PCVD method.
本発明は、上記課題を解決するために、反応室内に投入した半導体ウェハに、PCVD法を用いて窒化シリコン膜を成膜する窒化シリコン膜の製造方法において、前記反応室内に、酸素を残留させた状態で、前記半導体ウェハを投入することを特徴とする。 In order to solve the above-described problems, the present invention provides a silicon nitride film manufacturing method in which a silicon nitride film is formed on a semiconductor wafer put into a reaction chamber using a PCVD method, and oxygen is left in the reaction chamber. In this state, the semiconductor wafer is loaded.
このように、本発明は、PCVD法の成膜装置の反応室内に残留させた酸素(O)により、成膜の初期段階の窒化シリコン膜の表面を改質することができ、成膜後の窒化シリコン膜の表面平坦性を向上させることができるという効果が得られる。 As described above, according to the present invention, the surface of the silicon nitride film at the initial stage of film formation can be modified by oxygen (O) remaining in the reaction chamber of the PCVD film formation apparatus. The effect that the surface flatness of the silicon nitride film can be improved is obtained.
以下に、図面を参照して本発明による窒化シリコン膜の製造方法の実施例について説明する。 Embodiments of a method for manufacturing a silicon nitride film according to the present invention will be described below with reference to the drawings.
図1は実施例の窒化シリコン膜の製造方法を示す説明図、図2は実施例の窒化シリコン膜の作用の確認方法を示す説明図である。
本実施例のSiN膜は、図1に示すように、まず、PCVD法の成膜装置の反応室に一の半導体ウェハを投入し、N2O(一酸化二窒素)ガスを原料ガスとするPCVD法によりダミーSiON(一酸化窒化シリコン)膜を成膜する(ステップS1)。
FIG. 1 is an explanatory view showing a method for manufacturing a silicon nitride film of an embodiment, and FIG. 2 is an explanatory view showing a method for confirming the action of the silicon nitride film of the embodiment.
In the SiN film of this embodiment, as shown in FIG. 1, first, one semiconductor wafer is put into a reaction chamber of a PCVD film forming apparatus, and N 2 O (dinitrogen monoxide) gas is used as a source gas. A dummy SiON (silicon monoxide nitride) film is formed by the PCVD method (step S1).
本実施例では、ダミーSiON膜を2μm程度の膜厚で成膜する。
なお、本実施例で用いる半導体ウェハは、シリコン半導体層としてのシリコン基板からなるバルク基板である。
この場合のSiON膜の成膜条件は、基板温度300℃、RFパワー45W、反応室圧力900mTorr、N2ガス流量1500sccm、20%希釈SiH4ガス流量25sccm、NH3ガス流量15sccm、N2Oガス流量45sccmであり、この成膜条件で約20nm/分の成長速度が得られる。
In this embodiment, a dummy SiON film is formed with a film thickness of about 2 μm.
The semiconductor wafer used in this embodiment is a bulk substrate made of a silicon substrate as a silicon semiconductor layer.
The deposition conditions for the SiON film in this case are as follows: substrate temperature 300 ° C., RF power 45 W, reaction chamber pressure 900 mTorr, N 2 gas flow rate 1500 sccm, 20% diluted SiH 4 gas flow rate 25 sccm, NH 3 gas flow rate 15 sccm, N 2 O gas. The flow rate is 45 sccm, and a growth rate of about 20 nm / min can be obtained under these deposition conditions.
そして、ステップS1でダミーSiON膜を成膜した半導体ウェハを反応室から取出し、その取出し後に連続して、他の半導体ウェハを同じ反応室に投入し、本実施例のSiN膜をPCVD法により所定の膜厚(本実施例では、10nm程度)に成膜する(ステップS2)。
この場合のSiN膜の成膜条件は、基板温度300℃、RFパワー150W、反応室圧力800mTorr、N2ガス流量300sccm、20%希釈SiH4ガス流量45sccm、NH3ガス流量23sccmであり、この成膜条件で約25nm/分の成長速度が得られる。
Then, the semiconductor wafer on which the dummy SiON film is formed in step S1 is taken out from the reaction chamber, and after the take-out, another semiconductor wafer is put into the same reaction chamber, and the SiN film of this embodiment is predetermined by the PCVD method. (Step S2).
The deposition conditions for the SiN film in this case are as follows: substrate temperature 300 ° C., RF power 150 W, reaction chamber pressure 800 mTorr, N 2 gas flow rate 300 sccm, 20% diluted SiH 4 gas flow rate 45 sccm, NH 3 gas flow rate 23 sccm. A growth rate of about 25 nm / min is obtained under film conditions.
上記の2つのステップ、つまりN2Oガスを用いたダミー成膜プロセス(本実施例では、ダミーSiON膜の成膜)の実施後に、通常のSiN膜の成膜プロセスを行うことによって、表面平坦性が改善された本実施例のSiN膜が得られる。
本実施例のSiN膜の表面平坦性の作用および効果を確認するために、図2にSAで示すステップに従って、以下に示す3つのSiN膜を形成した。
After performing the above-described two steps, that is, the dummy film formation process using N 2 O gas (in this embodiment, the formation of the dummy SiON film), a normal SiN film formation process is performed, thereby making the surface flat. Thus, the SiN film of this example with improved properties can be obtained.
In order to confirm the action and effect of the surface flatness of the SiN film of this example, the following three SiN films were formed according to the steps indicated by SA in FIG.
ステップSA1、PCVD法の成膜装置の反応室に第1の半導体ウェハを投入し、上記ステップS2のSiN膜の成膜条件と同じ成膜条件で、PCVD法により、表面粗さを比較する基準とする膜厚10nmの基準SiN膜を形成する。
ステップSA2、反応室から基準SiN膜を形成した第1の半導体ウェハを取出し、同じ反応室に第2の半導体ウェハを投入し、上記ステップS1のSiON膜の成膜条件と同じ成膜条件で、PCVD法により、膜厚2μmのダミーSiON膜を形成する。
Step SA1, a reference for comparing the surface roughness by the PCVD method under the same film formation conditions as those for the SiN film in Step S2 above, by putting the first semiconductor wafer into the reaction chamber of the PCVD method film formation apparatus A reference SiN film having a thickness of 10 nm is formed.
Step SA2, taking out the first semiconductor wafer on which the reference SiN film is formed from the reaction chamber, putting the second semiconductor wafer into the same reaction chamber, and under the same film formation conditions as those for the SiON film in Step S1, A dummy SiON film having a thickness of 2 μm is formed by PCVD.
ステップSA3、反応室からダミーSiON膜を形成した第2の半導体ウェハを取出し、同じ反応室に第3の半導体ウェハを投入し、上記ステップS2のSiN膜の成膜条件と同じ成膜条件で、PCVD法により、膜厚10nmの本実施例のSiN膜を形成する。
ステップSA4、反応室から本実施例のSiN膜を形成した第3の半導体ウェハを取出し、同じ反応室に第4の半導体ウェハを投入し、上記ステップS2のSiN膜の成膜条件と同じ成膜条件で、PCVD法により、膜厚100nmのダミーSiN膜を形成する。
Step SA3, taking out the second semiconductor wafer on which the dummy SiON film is formed from the reaction chamber, putting the third semiconductor wafer into the same reaction chamber, under the same film formation conditions as those for the SiN film in Step S2. A SiN film of this example having a thickness of 10 nm is formed by PCVD.
Step SA4: The third semiconductor wafer on which the SiN film of this embodiment is formed is taken out from the reaction chamber, the fourth semiconductor wafer is put into the same reaction chamber, and the film formation conditions are the same as those for the SiN film formation in Step S2. Under the conditions, a dummy SiN film having a thickness of 100 nm is formed by PCVD.
ステップSA5、反応室からダミーSiN膜を形成した第4の半導体ウェハを取出し、同じ反応室に第5の半導体ウェハを投入し、上記ステップS2のSiN膜の成膜条件と同じ成膜条件で、PCVD法により、表面粗さのモニタ用として膜厚10nmのモニタSiN膜を形成する。
なお、上記ステップSA1〜SA5の各ステップにおける膜厚の調整は、上記の各成膜条件での成膜時間を、膜厚に応じて変更して行った。
Step SA5, taking out the fourth semiconductor wafer on which the dummy SiN film is formed from the reaction chamber, putting the fifth semiconductor wafer into the same reaction chamber, and under the same film formation conditions as those for the SiN film in Step S2. A monitor SiN film having a thickness of 10 nm is formed for monitoring the surface roughness by the PCVD method.
In addition, adjustment of the film thickness in each step of said step SA1-SA5 was performed by changing the film-forming time on said each film-forming condition according to the film thickness.
このようにして形成した3つのSiN膜、つまり第1の半導体ウェハに形成した膜厚10nmの基準SiN膜、第3の半導体ウェハに形成した膜厚10nmの本実施例のSiN膜、第5の半導体ウェハに形成した膜厚10nmのモニタSiN膜をサンプルとして、原子間力顕微鏡(AFM)を用いてそれぞれのSiN膜の表面粗さを測定した。
図3は膜厚10nmの基準SiN膜の測定結果を示すAFM像である。これを解析して得られた表面粗さの標準偏差(RMS)は0.198nmであった。
The three SiN films thus formed, that is, the 10 nm-thick reference SiN film formed on the first semiconductor wafer, the 10 nm-thick SiN film of this embodiment formed on the third semiconductor wafer, the fifth Using a monitor SiN film having a thickness of 10 nm formed on a semiconductor wafer as a sample, the surface roughness of each SiN film was measured using an atomic force microscope (AFM).
FIG. 3 is an AFM image showing the measurement result of a reference SiN film having a thickness of 10 nm. The standard deviation (RMS) of the surface roughness obtained by analyzing this was 0.198 nm.
図4は本実施例の膜厚10nmのSiN膜の測定結果を示すAFM像である。これを解析して得られた表面粗さの標準偏差(RMS)は0.174nmであった。
このように、N2Oガスを原料ガスに用いたダミーSiON膜の成膜後に、同じ反応室に新たな半導体ウェハを投入して成膜した本実施例の膜厚10nmのSiN膜の表面粗さは、同じ膜厚の基準SiN膜の0.198nmから0.174nmへ、明らかに小さくなることが確認できる。
FIG. 4 is an AFM image showing the measurement results of the SiN film having a thickness of 10 nm according to this example. The standard deviation (RMS) of the surface roughness obtained by analyzing this was 0.174 nm.
As described above, after the formation of the dummy SiON film using N 2 O gas as the source gas, the surface roughness of the 10 nm-thickness SiN film of this example formed by introducing a new semiconductor wafer into the same reaction chamber. It can be confirmed that the reference SiN film having the same film thickness clearly decreases from 0.198 nm to 0.174 nm.
また、本実施例のSiN膜の形成後に、膜厚100nmのダミーSiN膜の形成プロセスを挟んで形成した膜厚10nmのモニタSiN膜の測定結果を示すAFM像を図5に示す。
これを解析して得られた表面粗さの標準偏差(RMS)は0.186nmとなり、本実施例のSiN膜の表面粗さの標準偏差(RMS)0.174nmよりも大きくなっており、モニタSiN膜の表面粗さが悪化していることが確認された。
FIG. 5 shows an AFM image showing a measurement result of a monitor SiN film having a thickness of 10 nm formed by sandwiching a process of forming a dummy SiN film having a thickness of 100 nm after the formation of the SiN film of this example.
The standard deviation (RMS) of the surface roughness obtained by analyzing this is 0.186 nm, which is larger than the standard deviation (RMS) 0.174 nm of the surface roughness of the SiN film of this example. It was confirmed that the surface roughness of the SiN film was deteriorated.
これは、PCVD法によるSiN膜の形成において、N2Oガスを原料ガスに用いたダミーSiON膜の成膜の直後にSiN膜を成膜すると、その表面粗さの改善効果は顕著に現れるが、その後に引続いて行うSiN膜の表面粗さは、ダミーSiON膜の成膜を行う前の基準SiN膜の表面粗さに漸近的に近づいていくためと考えられる。
また、本実施例の効果に装置依存性がないことを確認するために、他のPCVD法の成膜装置を用いて、同様の効果が得られることを確認した。
This is because, in the formation of a SiN film by the PCVD method, if the SiN film is formed immediately after the formation of the dummy SiON film using N 2 O gas as the source gas, the effect of improving the surface roughness appears remarkably. The subsequent surface roughness of the SiN film is considered to be asymptotically close to the surface roughness of the reference SiN film before the dummy SiON film is formed.
In addition, in order to confirm that the effect of this example is not dependent on the apparatus, it was confirmed that the same effect can be obtained by using another PCVD film forming apparatus.
すなわち、上記ステップSA2と同様にして、N2Oガスを原料ガスに用いた膜厚2μm程度のダミーSiON膜の成膜を行った後に、所定の膜厚を20nmとして本実施例のSiN膜の成膜を行い、その後に膜厚500nm程度のダミーSiN膜の形成を挟んで、膜厚20nmのモニタSiN膜を成膜した。
この場合の膜厚20nmの本実施例のSiN膜の測定結果を示すAFM像を図6に、膜厚20nmのモニタSiN膜の測定結果を示すAFM像を図7に示す。
That is, in the same manner as in step SA2, after forming a dummy SiON film having a film thickness of about 2 μm using N 2 O gas as a source gas, the predetermined film thickness is set to 20 nm and the SiN film of this embodiment is formed. After forming a film, a monitor SiN film having a thickness of 20 nm was formed with a dummy SiN film having a thickness of about 500 nm interposed therebetween.
FIG. 6 shows an AFM image showing the measurement result of the SiN film of the present example having a film thickness of 20 nm in this case, and FIG. 7 shows an AFM image showing the measurement result of the monitor SiN film having a film thickness of 20 nm.
これらを解析して得られた膜厚20nmの本実施例のSiN膜の表面粗さの標準偏差(RMS)は0.35nm、同じ膜厚のモニタSiN膜の表面粗さの標準偏差(RMS)は0.95nmになり、上記したN2Oガスを原料ガスに用いたダミーSiON膜の成膜の直後に、同じ反応室内で成膜したSiN膜の表面粗さが最も小さくなるという効果が同様に確認された。 The standard deviation (RMS) of the surface roughness of the SiN film of this example having a film thickness of 20 nm obtained by analyzing these is 0.35 nm, and the standard deviation (RMS) of the surface roughness of the monitor SiN film having the same film thickness. Has the same effect that the surface roughness of the SiN film formed in the same reaction chamber is minimized immediately after the formation of the dummy SiON film using the N 2 O gas as a source gas. Was confirmed.
上記のように、所定の膜厚のSiN膜の成膜を行う直前に、N2Oガスを原料ガスに用いたダミーSiON膜の成膜を行うことにより、そのSiN膜の表面粗さは、通常のSiN膜の表面粗さに比べて改善される。
これは、ダミーSiON膜の成膜時に、N2Oガスが分解して生成された酸素(O)の一部が、PCVD法の成膜装置の反応室内に残留し、極微量の酸素(O)が反応室内の成膜雰囲気中に残留していることが、その後に成膜されるSiN膜の平坦化に作用して、成膜後のSiN膜の表面粗さを向上させるものと考えられる。
As described above, by forming a dummy SiON film using N 2 O gas as a raw material gas immediately before forming a SiN film having a predetermined thickness, the surface roughness of the SiN film is This is improved compared to the surface roughness of a normal SiN film.
This is because a part of oxygen (O) generated by decomposition of N 2 O gas at the time of forming the dummy SiON film remains in the reaction chamber of the PCVD film forming apparatus, and a very small amount of oxygen (O ) Remains in the film-forming atmosphere in the reaction chamber, which is considered to act on the planarization of the subsequently formed SiN film and improve the surface roughness of the SiN film after film formation. .
この表面粗さの変化による膜特性への影響を確認するために、上記の基準SiN膜およびダミーSiON膜の成膜後の本実施例のSiN膜について、屈折率、膜応力、BHF(バッファーフッ酸)に対するエッチレートを測定した。その確認結果を図8に示す。
図8に示すように、屈折率、膜応力、エッチレートについて両者に有意な差異はないと判断でき、N2Oガスを原料ガスに用いたダミーSiON膜の成膜後に成膜したSiN膜の膜特性は、基準SiN膜とほとんど変わらないことが確認された。
In order to confirm the influence of the change in surface roughness on the film characteristics, the refractive index, film stress, BHF (buffer foot) of the SiN film of this example after the formation of the above-described reference SiN film and dummy SiON film were measured. The etch rate for acid) was measured. The confirmation result is shown in FIG.
As shown in FIG. 8, it can be determined that there is no significant difference between the refractive index, the film stress, and the etch rate, and the SiN film formed after the dummy SiON film using the N 2 O gas as the source gas is formed. It was confirmed that the film characteristics were almost the same as those of the reference SiN film.
なお、基準SiN膜および本実施例のSiN膜のエッチレートについて約15%の差異が見られるが、下記2つの理由によりこれら両者に本質的な差異はないと判断した。
(1)これまでの実験結果から屈折率とエッチレートは相関があることが判っており、両屈折率に差異はない。
(2)これまでの実績値から設定したエッチレートの管理値は、1700±400Åであり、この管理値のバラツキ範囲内の値であり十分許容できる。
Although there is a difference of about 15% between the etching rates of the reference SiN film and the SiN film of this example, it was determined that there is no essential difference between the two for the following two reasons.
(1) From the experimental results so far, it has been found that there is a correlation between the refractive index and the etch rate, and there is no difference between both refractive indexes.
(2) The management value of the etch rate set from the past actual values is 1700 ± 400 mm, which is a value within the variation range of the management values and is sufficiently acceptable.
更に詳細にSiN膜の膜質を調べるために、フーリエ変換赤外分光(FT−IR)測定を行った結果を図9に示す。
図9に示すように、基準SiN膜と、ダミーSiON膜の成膜後の本実施例のSiN膜とのスペクトルを比較すると、両者に顕著な差異は見られないものの、図9に丸印で示した波数1050cm−1付近で両者が交差しており、僅かな差異がありそうなことが推察されるが、断定するには非常に微小な変化量である。
FIG. 9 shows the result of Fourier transform infrared spectroscopy (FT-IR) measurement for examining the film quality of the SiN film in more detail.
As shown in FIG. 9, when the spectra of the reference SiN film and the SiN film of the present example after the formation of the dummy SiON film are compared, there is no significant difference between them. It is inferred that there is a slight difference between the two in the vicinity of the indicated wave number of 1050 cm −1 , but it is a very small amount of change for determination.
なお、SiON膜のスペクトルを重ねて見ても、SiON膜のメインピーク位置のSiN膜のスペクトルに対応するピークは存在しない。
この僅かな変化を詳しく調べるために、FT−IRスペクトルの微分解析を行った。
図10は、基準SiN膜、およびダミーSiON膜の成膜後の本実施例のSiN膜、比較のためのSiON膜の合計3種類のサンプルのFT−IR微分スペクトルを示し、図11は、図10のA部付近のダミーSiON膜の成膜後の本実施例のSiN膜、比較のためのSiON膜のFT−IR微分スペクトルを拡大して示したものである。
Note that even if the spectrum of the SiON film is overlapped, there is no peak corresponding to the spectrum of the SiN film at the main peak position of the SiON film.
In order to investigate this slight change in detail, differential analysis of the FT-IR spectrum was performed.
FIG. 10 shows FT-IR differential spectra of a total of three types of samples: a reference SiN film, a SiN film of this example after the formation of a dummy SiON film, and a SiON film for comparison. 10 is an enlarged view of the FT-IR differential spectrum of the SiN film of this example after the formation of the dummy SiON film in the vicinity of 10 and the SiON film for comparison.
図10に示すように、基準SiN膜と本実施例のSiN膜との2つのSiN膜の微分スペクトルの間には、図9のFT−IRスペクトルで示した交差部である波数1050cm−1付近に顕著な相違が見られ、これら2つのSiN膜には、図10に丸印(A部)で示した波数1050cm−1を中心とした1000〜1100cm−1の範囲に、鋭い微細構造があるか否かの相違があることが判る(本実施例のSiN膜については図11参照)。 As shown in FIG. 10, between the differential spectra of the two SiN films of the reference SiN film and the SiN film of this example, the vicinity of the wave number of 1050 cm −1, which is the intersection shown in the FT-IR spectrum of FIG. significant difference was observed at, these two SiN film, the range of 1000~1100Cm -1 to the wave number 1050 cm -1 mainly shown in FIG. 10 by a circle (a part), there is a sharp microstructure (See FIG. 11 for the SiN film of this example).
比較のために、図10、図11に示したSiON膜の微分スペクトルには、波数1050cm−1付近にこのような微細構造は存在せず、波数1050cm−1付近の微細構造はSiN膜に特有のものであり、SiON膜には存在しないことが判る。
このことから、SiN膜の屈折率や膜応力等のマクロな膜特性に相違が現れない範囲で、直前のダミーSiON膜の成膜時の原料ガスであるN2Oガスにより、SiN膜の成膜の初期段階で表面が改質され、これがSiN膜の平坦化に作用したものと考えられる。
For comparison, FIG. 10, the derivative spectra of the SiON film shown in FIG. 11, such a fine structure in the vicinity of a wave number of 1050 cm -1 is not present, the microstructure in the vicinity of wave number 1050 cm -1 is specific to the SiN film It can be seen that it is not present in the SiON film.
Therefore, the SiN film is formed by the N 2 O gas, which is a raw material gas at the time of forming the dummy SiON film, immediately before the macro film characteristics such as the refractive index and film stress of the SiN film are not different. It is considered that the surface was modified at the initial stage of the film, which acted on the flattening of the SiN film.
PCVD法による成膜プロセスおける原料ガスは、SiN膜の成膜時にはSiH4、NH3を、SiON膜の成膜時にはSiH4、NH3、N2Oを、二酸化シリコン(SiO2)からなる二酸化シリコン膜(SiO2膜という。)の成膜時にはSiH4、N2Oを用いるのが一般的である。
この場合に、SiO2あるいはSiON系の膜への酸素(O)の供給源としてN2Oガスが働いていることは良く知られている。
The source gas in the film formation process by the PCVD method is SiH 4 and NH 3 when forming the SiN film, SiH 4 , NH 3 and N 2 O when forming the SiON film, and silicon dioxide (SiO 2 ). In the formation of a silicon film (referred to as SiO 2 film), SiH 4 and N 2 O are generally used.
In this case, it is well known that N 2 O gas works as a supply source of oxygen (O) to the SiO 2 or SiON-based film.
このことからも、ダミーSiON膜の成膜時に、N2Oガスが分解して生成された酸素(O)の一部が、PCVD法の成膜装置の反応室内に残留し、極微量の酸素(O)が反応室内の成膜雰囲気中に残留していることが、その後に成膜されるSiN膜の平坦化に作用して、成膜後のSiN膜の表面粗さを向上させることが裏付けられたと考えられる。
以上説明したように、本実施例では、PCVD法をによる窒化シリコン膜の製造方法において、半導体ウェハの投入前に、同じ反応室を用いて他の半導体ウェハに一酸化窒化シリコン膜を成膜し、反応室内に一酸化二窒素ガスによる酸素を残留させた状態で半導体ウェハを投入して窒化シリコン膜を成膜するようにしたことによって、PCVD法の成膜装置の反応室内に、一酸化窒化シリコン膜の成膜時に供給された一酸化二窒素ガスが分解して生成された極微量の酸素(O)を反応室内の成膜雰囲気中に残留させることができ、反応室内に残留している酸素(O)により、窒化シリコン膜の成膜の初期段階の表面を改質して、成膜後の窒化シリコン膜の表面平坦性を向上させることができる。
This also indicates that a part of oxygen (O) generated by the decomposition of the N 2 O gas at the time of forming the dummy SiON film remains in the reaction chamber of the PCVD film forming apparatus, resulting in a very small amount of oxygen. The fact that (O) remains in the film-forming atmosphere in the reaction chamber acts on the flattening of the SiN film to be formed thereafter, thereby improving the surface roughness of the SiN film after the film formation. It is thought that it was supported.
As described above, in this embodiment, in the method of manufacturing a silicon nitride film by the PCVD method, a silicon monoxide nitride film is formed on another semiconductor wafer using the same reaction chamber before the semiconductor wafer is loaded. A silicon nitride film is formed by introducing a semiconductor wafer in a state in which oxygen due to dinitrogen monoxide gas is left in the reaction chamber, so that a monoxide oxynitride is formed in the reaction chamber of the PCVD film forming apparatus. A very small amount of oxygen (O) generated by decomposition of the nitrous oxide gas supplied during the formation of the silicon film can be left in the film formation atmosphere in the reaction chamber, and remains in the reaction chamber. Oxygen (O) can modify the surface of the initial stage of silicon nitride film deposition, and improve the surface flatness of the silicon nitride film after deposition.
なお、上記実施例においては、SiN膜を形成する前に行う、N2Oガスを原料ガスに用いるPCVD法によるダミー成膜の成膜プロセスを、SiON膜の成膜プロセスとして説明したが、SiON膜の代わりにSiO2膜の成膜プロセス等をダミー成膜として行っうようにしてもよい。要は、酸素の供給源となる原料ガスの種類や、PCVD法の成膜装置の反応室内の状態、ダミー成膜の膜種等に関らず、屈折率、膜応力、エッチレート等による膜特性の評価において、基準SiN膜の膜特性と異ならない程度の酸素の残留量を実現することができるものであれば、前記の原料ガスやダミー成膜の膜種等に限定されるものではない。 In the above-described embodiment, the dummy film formation process by the PCVD method using N 2 O gas as the source gas, which is performed before forming the SiN film, has been described as the SiON film formation process. Instead of the film, a SiO 2 film forming process or the like may be performed as a dummy film forming. In essence, regardless of the type of source gas used as the oxygen supply source, the reaction chamber state of the PCVD deposition apparatus, the film type of the dummy film formation, etc., the film by the refractive index, film stress, etch rate, etc. In the evaluation of characteristics, the material gas is not limited to the above-described source gas or dummy film type as long as it can realize a residual amount of oxygen that is not different from the film characteristics of the reference SiN film. .
前記のSiO2膜をダミー成膜として行う場合の成膜条件は、基板温度300℃、RFパワー30W、反応室圧力800mTorr、N2ガス流量400sccm、20%希釈SiH4ガス流量40sccm、N2Oガス流量700sccmにするとよい。この成膜条件で45nm/分程度の成長速度が得られる。
また、上記実施例においては、N2Oガスを原料ガスに用いたダミーSiON膜の成膜時の膜厚は2μm程度であるとして説明したが、例えば100nmのSiON膜の成膜プロセスを連続的に繰り返して積算合計の膜厚が2μm相当になるようにしてもよい。
The film forming conditions when the SiO 2 film is formed as a dummy film are as follows: substrate temperature 300 ° C., RF power 30 W, reaction chamber pressure 800 mTorr, N 2 gas flow rate 400 sccm, 20% diluted SiH 4 gas flow rate 40 sccm, N 2 O. The gas flow rate may be 700 sccm. Under this film forming condition, a growth rate of about 45 nm / min can be obtained.
In the above embodiment, the dummy SiON film using N 2 O gas as the source gas has been described as having a film thickness of about 2 μm. However, for example, a 100 nm SiON film forming process is continuously performed. It is also possible to repeat the above process so that the total film thickness becomes equivalent to 2 μm.
更に、上記実施例においては、SiN膜の所定の膜厚は10nm〜20nmとして説明したが、これより薄い、あるいは厚いSiN膜の成膜においても本発明を適用すれば、同様の効果を得ることできる。
更に、上記実施例においては、半導体ウェハは、シリコン半導体層としてのシリコン基板からなるバルク基板であるとして説明したが、半導体ウェハは前記に限らず、シリコンからなる支持基板に埋込み酸化膜を挟んでシリコン半導体層としてのシリコン薄膜層を形成したSOI(Silicon On Insulator)構造の半導体ウェハであってもよく、サファイア基板上にシリコン半導体層としてのシリコン薄膜層を形成したSOS(Silicon On Sapphire)基板や、クオーツ基板上にシリコン半導体層としてのシリコン薄膜層を形成したSOQ(Silicon On Quartz)基板等の半導体ウェハであってもよい。
Furthermore, in the above embodiment, the SiN film has been described as having a predetermined film thickness of 10 nm to 20 nm, but the same effect can be obtained by applying the present invention to the formation of a thinner or thicker SiN film. it can.
Further, in the above embodiment, the semiconductor wafer is described as a bulk substrate made of a silicon substrate as a silicon semiconductor layer. However, the semiconductor wafer is not limited to the above, and a buried oxide film is sandwiched between support substrates made of silicon. It may be an SOI (Silicon On Insulator) structure semiconductor wafer in which a silicon thin film layer as a silicon semiconductor layer is formed, or an SOS (Silicon On Sapphire) substrate in which a silicon thin film layer as a silicon semiconductor layer is formed on a sapphire substrate, A semiconductor wafer such as a SOQ (Silicon On Quartz) substrate in which a silicon thin film layer as a silicon semiconductor layer is formed on a quartz substrate may be used.
Claims (4)
前記反応室内に、酸素を残留させた状態で、前記半導体ウェハを投入することを特徴とする窒化シリコン膜の製造方法。 In a silicon nitride film manufacturing method of forming a silicon nitride film on a semiconductor wafer put into a reaction chamber using a plasma CVD method,
A method for producing a silicon nitride film, wherein the semiconductor wafer is put in a state in which oxygen remains in the reaction chamber.
前記半導体ウェハの投入前に、同じ反応室を用いて、他の半導体ウェハに一酸化窒化シリコン膜を成膜し、前記反応室内に、前記酸素を残留させることを特徴とする窒化シリコン膜の製造方法。 In claim 1,
Before the introduction of the semiconductor wafer, a silicon monoxide nitride film is formed on another semiconductor wafer using the same reaction chamber, and the oxygen is left in the reaction chamber. Method.
前記半導体ウェハの投入前に、同じ反応室を用いて、他の半導体ウェハに二酸化シリコン膜を成膜し、前記反応室内に、前記酸素を残留させることを特徴とする窒化シリコン膜の製造方法。 In claim 1,
A method for producing a silicon nitride film, wherein a silicon dioxide film is formed on another semiconductor wafer using the same reaction chamber before the semiconductor wafer is charged, and the oxygen is left in the reaction chamber.
前記半導体ウェハが、シリコン半導体層を備えていることを特徴とする窒化シリコン膜の製造方法。 In any one of Claims 1 to 3,
A method for producing a silicon nitride film, wherein the semiconductor wafer includes a silicon semiconductor layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007211927A JP2009049085A (en) | 2007-08-15 | 2007-08-15 | Method for manufacturing silicon nitride film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007211927A JP2009049085A (en) | 2007-08-15 | 2007-08-15 | Method for manufacturing silicon nitride film |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2009049085A true JP2009049085A (en) | 2009-03-05 |
Family
ID=40501060
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007211927A Pending JP2009049085A (en) | 2007-08-15 | 2007-08-15 | Method for manufacturing silicon nitride film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2009049085A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017220452A (en) * | 2016-06-06 | 2017-12-14 | セイコーエプソン株式会社 | Organic el device, method for manufacturing organic el device, and electronic instrument |
JP2020507219A (en) * | 2017-02-03 | 2020-03-05 | アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated | Plasma mitigation of nitrous oxide from semiconductor process wastewater |
DE102021128467A1 (en) | 2021-11-02 | 2022-12-08 | Schaeffler Technologies AG & Co. KG | Drive unit, geared motor system and manufacturing process |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001237243A (en) * | 1999-12-23 | 2001-08-31 | Asm America Inc | Manufacturing method and process of in-situ dielectric stack |
JP2001267315A (en) * | 1999-12-23 | 2001-09-28 | Applied Materials Inc | In situ deposition and integration of silicon nitride in high density plasm reactor |
-
2007
- 2007-08-15 JP JP2007211927A patent/JP2009049085A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001237243A (en) * | 1999-12-23 | 2001-08-31 | Asm America Inc | Manufacturing method and process of in-situ dielectric stack |
JP2001267315A (en) * | 1999-12-23 | 2001-09-28 | Applied Materials Inc | In situ deposition and integration of silicon nitride in high density plasm reactor |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017220452A (en) * | 2016-06-06 | 2017-12-14 | セイコーエプソン株式会社 | Organic el device, method for manufacturing organic el device, and electronic instrument |
JP2020507219A (en) * | 2017-02-03 | 2020-03-05 | アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated | Plasma mitigation of nitrous oxide from semiconductor process wastewater |
DE102021128467A1 (en) | 2021-11-02 | 2022-12-08 | Schaeffler Technologies AG & Co. KG | Drive unit, geared motor system and manufacturing process |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100484321B1 (en) | Semiconductor device and method of manufacturing the same | |
JP4090740B2 (en) | Integrated circuit manufacturing method and integrated circuit | |
US5068124A (en) | Method for depositing high quality silicon dioxide by pecvd | |
TW200832552A (en) | Amorphous carbon film, semiconductor device, film forming method, film forming apparatus and storage medium | |
KR102677350B1 (en) | Method of Improving Adhesion | |
US10978300B2 (en) | Methods to reduce gouging for core removal processes using thermal decomposition materials | |
JP3532830B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2009049085A (en) | Method for manufacturing silicon nitride film | |
TWI791864B (en) | Methods to reshape spacers for multi-patterning processes using thermal decomposition materials | |
US20070269646A1 (en) | Bond termination of pores in a porous diamond dielectric material | |
Blanc et al. | Patterning of silicon nitride for CMOS gate spacer technology. II. Impact of subsilicon surface carbon implantation on epitaxial regrowth | |
Su et al. | Properties and electric characterizations of tetraethyl orthosilicate-based plasma enhanced chemical vapor deposition oxide film deposited at 400° C for through silicon via application | |
US6406978B1 (en) | Method of removing silicon carbide | |
US20080207003A1 (en) | Production method of semiconductor apparatus | |
US10937659B2 (en) | Method of anisotropically etching adjacent lines with multi-color selectivity | |
US20090061329A1 (en) | Semiconductor device manufacturing method and hard mask | |
EP4009350B1 (en) | Hard mask including amorphous or nanocrystalline boron nitride film and method of fabricating the hard mask, and patterning method using the hard mask | |
KR20230055964A (en) | Method and system for depositing boron nitride using pulsed chemical vapor deposition | |
JPH0629282A (en) | Manufacture of semiconductor device | |
Xiao et al. | Surface modification of hydrogenated amorphous carbon (aC: H) films prepared by plasma enhanced chemical vapor deposition (PECVD) | |
US20190043755A1 (en) | Process for producing connections to an electronic chip | |
Joshi et al. | Low temperature processing of SiO2 thin films by HD-PECVD technique for gate dielectric applications | |
KR20190014617A (en) | Method of forming an ultra-low-k layer and the layer | |
US20150187595A1 (en) | A semiconductor device comprising a surface portion implanted with nitrogen and fluorine | |
KR20080063879A (en) | Method for manufacturing test wafer to measure flat band voltage and method for measuring flat band voltage using the test wafer manufactured by the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20081224 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20090127 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100727 |
|
A977 | Report on retrieval |
Effective date: 20110210 Free format text: JAPANESE INTERMEDIATE CODE: A971007 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120612 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20121113 |