JP2009030167A - Method and apparatus for treating substrate - Google Patents

Method and apparatus for treating substrate Download PDF

Info

Publication number
JP2009030167A
JP2009030167A JP2008170222A JP2008170222A JP2009030167A JP 2009030167 A JP2009030167 A JP 2009030167A JP 2008170222 A JP2008170222 A JP 2008170222A JP 2008170222 A JP2008170222 A JP 2008170222A JP 2009030167 A JP2009030167 A JP 2009030167A
Authority
JP
Japan
Prior art keywords
substrate
plating
plating solution
wiring
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008170222A
Other languages
Japanese (ja)
Inventor
Akira Suzaki
明 須崎
Tsutomu Nakada
勉 中田
Akira Yamamoto
暁 山本
Keiichi Kurashina
敬一 倉科
Hiroyuki Kanda
裕之 神田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ebara Corp
Original Assignee
Ebara Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ebara Corp filed Critical Ebara Corp
Priority to JP2008170222A priority Critical patent/JP2009030167A/en
Priority to US12/216,224 priority patent/US20090020434A1/en
Publication of JP2009030167A publication Critical patent/JP2009030167A/en
Pending legal-status Critical Current

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To enable embedding of a defect-free wiring material in recesses for wiring, such as trenches, by carrying out electroplating directly on a surface of a ruthenium film serving as a barrier layer. <P>SOLUTION: A substrate treating method comprises the steps of: preparing a substrate having the ruthenium film formed on its entire substrate surface including the surfaces of the recesses for wiring; keeping the substrate surface in contact with a plating solution for a prescribed time so that an additive in the plating solution is adsorbed onto the ruthenium film; and subsequently carrying out electroplating to form a conductive film on the surface of the ruthenium film. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、基板処理方法及び基板処理装置に関し、特に半導体ウェハ等の基板の表面（被めっき面）に設けた微細な配線用凹部内に銅や銀等の金属（配線材料）を埋込んで配線を形成するのに使用される基板処理方法及び基板処理装置に関する。   The present invention relates to a substrate processing method and a substrate processing apparatus, and in particular, a metal (wiring material) such as copper or silver is embedded in a fine wiring recess provided on the surface (surface to be plated) of a substrate such as a semiconductor wafer. The present invention relates to a substrate processing method and a substrate processing apparatus used for forming wiring.

電子機器の小型化、高速化及び低消費電力化の進行に伴って、半導体装置内の配線パターンの微細化が進み、配線材料も従来のアルミニウムまたはその合金から銅または銅合金へと移り変わってきている。銅の電気抵抗率は、１．６７μΩｃｍとアルミニウムの電気抵抗率（２．６５μΩcm）よりも約３７％低い。このため、配線に銅を使用することにより、配線による電力の消費を抑えると同時に、アルミニウムと同等の配線抵抗でもその分の微細化が可能であり、さらに配線の低抵抗化により信号遅延も抑えることができる。   As electronic devices become smaller, faster, and consume less power, the wiring patterns in semiconductor devices are becoming finer, and the wiring material has also changed from conventional aluminum or its alloys to copper or copper alloys. Yes. The electrical resistivity of copper is 1.67 μΩcm, which is about 37% lower than that of aluminum (2.65 μΩcm). Therefore, by using copper for the wiring, power consumption by the wiring can be suppressed, and at the same time, the wiring resistance equivalent to that of aluminum can be miniaturized, and the signal delay can be suppressed by reducing the wiring resistance. be able to.

一方で、銅原子は、シリコンや絶縁膜中を容易に移動し、半導体装置の特性を狂わせてしまう。このため、銅配線にあっては、配線の周辺をバリア層と呼ばれる保護層で被覆する必要がある。また配線全体をバリア層で被覆した構造を実現するために、銅配線の形成には、基板の表面に設けたトレンチ等の配線用凹部内に銅（配線材料）を埋込むダマシン法が広く用いられている。これまで、バリア層としては、ＰＶＤ、ＣＶＤまたはＡＬＤで成膜された、Ｔｉ、ＴｉＮ、ＴａまたはＴａＮ等が広く用いられてきた。また、銅の埋込みは、高速で成膜できる電解めっき法で行うのが一般的である。   On the other hand, copper atoms easily move in silicon and the insulating film, and the characteristics of the semiconductor device are upset. For this reason, in the case of copper wiring, it is necessary to cover the periphery of the wiring with a protective layer called a barrier layer. In order to realize a structure in which the entire wiring is covered with a barrier layer, a damascene method in which copper (wiring material) is embedded in a wiring recess such as a trench provided on the surface of the substrate is widely used for the formation of copper wiring. It has been. Until now, Ti, TiN, Ta, TaN, etc., formed by PVD, CVD, or ALD have been widely used as the barrier layer. Copper is generally embedded by an electrolytic plating method capable of forming a film at a high speed.

図１は、従来の一般的な銅配線形成例を工程順に示す。先ず、図１（ａ）に示すように、半導体素子を形成した半導体基材１上の導電層１ａの上にＳｉＯ２やＬｏｗ−Ｋ材からなる絶縁膜（層間絶縁膜）２を堆積し、絶縁膜２の内部に、リソグラフィ・エッチング技術により、配線用凹部としてのビアホール３とトレンチ４を形成する。そして、その上にＴａＮ等からなるバリア層５、更にその上に電解めっきの給電層としてシード層７を形成する。 FIG. 1 shows an example of forming a conventional general copper wiring in the order of steps. First, as shown in FIG. 1A, an insulating film (interlayer insulating film) 2 made of SiO 2 or Low-K material is deposited on a conductive layer 1a on a semiconductor substrate 1 on which a semiconductor element is formed, Via holes 3 and trenches 4 are formed as recesses for wiring inside the insulating film 2 by lithography / etching technology. Then, a barrier layer 5 made of TaN or the like is formed thereon, and a seed layer 7 is formed thereon as a power feeding layer for electrolytic plating.

そして、図１（ｂ）に示すように、基板Ｗの表面に銅めっきを施すことで、ビアホール３及びトレンチ４内に銅を充填するとともに、絶縁膜２上に銅めっき膜６を堆積する。その後、化学的機械的研磨（ＣＭＰ）により、絶縁膜２上の銅めっき膜６、シード層７及びバリア層５を除去して、ビアホール３及びトレンチ４内に充填させた銅めっき膜６の表面と絶縁膜２の表面とをほぼ同一平面にする。これにより、図１（ｃ）に示すように、絶縁膜２の内部に銅めっき膜６からなる配線を形成する。   Then, as shown in FIG. 1B, copper plating is performed on the surface of the substrate W, thereby filling the via hole 3 and the trench 4 with copper and depositing a copper plating film 6 on the insulating film 2. Thereafter, the surface of the copper plating film 6 filled in the via hole 3 and the trench 4 by removing the copper plating film 6, the seed layer 7 and the barrier layer 5 on the insulating film 2 by chemical mechanical polishing (CMP). And the surface of the insulating film 2 are substantially flush. Thereby, as shown in FIG. 1C, a wiring made of the copper plating film 6 is formed inside the insulating film 2.

電解銅めっきでは、硫酸銅を含む酸性のめっき液を用い、基板周辺から銅等からなるシード層７に給電して、シード層７の表面に銅めっき膜６を成長させることが一般に行われている。ここで、例えばＰＶＤにより形成されるシード層７の膜厚は、基板表面では数１０ｎｍあるが、トレンチ４の側壁では数ｎｍ以下となり、このため、酸性の銅めっき液に基板を長時間接触させるとシード層７がめっき液中に容易に溶解してしまう。そこで、例えば、０．２μｍ以下の微細配線化に伴い、実際に電解めっきを行う場合には、図２に示すように、基板をめっき液に接触させる直前に、カソードとなるシード層７と対極（アノード）との間に電圧を印加して、基板をめっき液へ接触させると同時に電解めっきを開始させ、めっき終了後に基板をめっき液から取り出し、洗浄して乾燥させる方法が一般に採られている。   In electrolytic copper plating, an acidic plating solution containing copper sulfate is used to feed power from the periphery of the substrate to the seed layer 7 made of copper or the like to grow a copper plating film 6 on the surface of the seed layer 7. Yes. Here, for example, the film thickness of the seed layer 7 formed by PVD is several tens of nanometers on the substrate surface, but is several nanometers or less on the side wall of the trench 4. For this reason, the substrate is brought into contact with the acidic copper plating solution for a long time. The seed layer 7 is easily dissolved in the plating solution. Therefore, for example, when electrolytic plating is actually performed in accordance with miniaturization of 0.2 μm or less, as shown in FIG. 2, immediately before the substrate is brought into contact with the plating solution, the seed layer 7 serving as the cathode and the counter electrode are counteracted. A method is generally adopted in which a voltage is applied to the anode (anode) to bring the substrate into contact with the plating solution, and at the same time, electroplating is started, and after the plating is finished, the substrate is taken out of the plating solution, washed and dried. .

前述のように、シード層は、一般にＰＶＤで形成されることから、配線内のシード層の膜厚は、基板表面（フィールド部）の膜厚の１０〜２０％程度に薄くなる。配線のより微細化に伴い、配線部の開口を確保するために、基板表面のシード層の膜厚はより薄くなり、また配線内のシード層の膜厚は更に薄くなる。このシード層の薄膜化に対応するため、シード層と対極（アノード）との間に印加する電圧を工夫したり（特許文献１参照）、シード層と対極（アノード）との間にめっき液より抵抗の大きな高抵抗体を挿入することが提案されている（特許文献２参照）。更なる微細化が進んでシード層の膜厚が更に薄くなると、配線内のシード層の膜厚が数μｍになり、シード層の連続性が保つことができなくなると考えられる。   As described above, since the seed layer is generally formed by PVD, the thickness of the seed layer in the wiring is as thin as about 10 to 20% of the thickness of the substrate surface (field portion). As the wiring is further miniaturized, the thickness of the seed layer on the substrate surface becomes thinner and the thickness of the seed layer in the wiring becomes thinner in order to secure the opening of the wiring portion. In order to cope with the thinning of the seed layer, a voltage applied between the seed layer and the counter electrode (anode) is devised (see Patent Document 1), or a plating solution is used between the seed layer and the counter electrode (anode). It has been proposed to insert a high resistance body having a large resistance (see Patent Document 2). If further miniaturization advances and the film thickness of the seed layer further decreases, the film thickness of the seed layer in the wiring becomes several μm, and it is considered that the continuity of the seed layer cannot be maintained.

ここで、基板をめっき液に接触させてから、カソードとなるシード層７と対極（アノード）との間に電圧を印加した場合、トレンチ４の内部への銅の埋込み性が変化することが判っている。つまり、基板をめっき液に接触させてからシード層７と対極（アノード）と間に電圧を印加するまでの時間が長いと、トレンチ内部での該トレンチ底部からの銅めっき膜の優先成長が抑制され、銅めっき膜はトレンチの側壁と底部から等方的に成長するようになる。この場合、成長した銅めっき膜が互いにぶつかり合って、トレンチ内部に埋込まれた銅めっき膜中にシームと呼ばれる空隙が残り、これが銅配線の信頼性を低下させる原因となる。この基板のめっき液への接触から電圧印加までの時間と銅の埋込み性との関係は、めっき液中に含まれる添加剤が表面吸着するまでの時間の影響を受けているものと考えられる。   Here, it is understood that when the voltage is applied between the seed layer 7 serving as the cathode and the counter electrode (anode) after the substrate is brought into contact with the plating solution, the copper embedding property in the trench 4 changes. ing. That is, if the time from when the substrate is brought into contact with the plating solution until the voltage is applied between the seed layer 7 and the counter electrode (anode) is long, the preferential growth of the copper plating film from the bottom of the trench inside the trench is suppressed. Then, the copper plating film grows isotropically from the side wall and bottom of the trench. In this case, the grown copper plating films collide with each other, and a void called a seam remains in the copper plating film embedded in the trench, which causes a decrease in the reliability of the copper wiring. The relationship between the time from contact of the substrate to the plating solution to voltage application and the copper embedding property is considered to be influenced by the time until the surface of the additive contained in the plating solution is adsorbed.

半導体装置のトレンチやビアホールの埋込みめっきに用いられるめっき液には、金属イオン成分、ｐＨ調整成分の他に、埋込み性を改善するために促進剤、抑制剤、平滑化剤といった各種添加剤が一般に含まれている。これらの添加剤は、基板表面に吸着することでそれぞれの効果を示すが、サブミクロンレベルのトレンチ内では表面積に比べてトレンチ中のめっき液量が少なくなるため、基板表面の平坦部と比較して一定量吸着するまでの時間が長くなる。   In addition to metal ion components and pH adjusting components, various additives such as accelerators, inhibitors, and smoothing agents are generally used in plating solutions used for embedding trenches and via holes in semiconductor devices. include. These additives exhibit their respective effects by adsorbing to the substrate surface, but the amount of plating solution in the trench is smaller than the surface area in the sub-micron level trench, so compared with the flat part of the substrate surface. It takes a long time to adsorb a certain amount.

抑制剤は、本来、基板表面の平坦部でのめっき膜の析出を抑制する働きをもつが、基板をめっき液に接触させたまま放置すると、トレンチ内周面への抑制剤の吸着も進行してめっき膜の析出を抑制する。このため、トレンチ内部にあっても、等方的にめっき膜が成長し、結果としてトレンチ内にめっき膜を完全に埋込むことができず、めっき膜の内部にシームやボイドが発生することがある。
特開２００３−１２９２９７号公報 特開２００１−３２３３９８号公報 The inhibitor originally has a function of suppressing the deposition of the plating film on the flat portion of the substrate surface, but if the substrate is left in contact with the plating solution, the adsorption of the inhibitor to the inner peripheral surface of the trench also proceeds. This suppresses the deposition of the plating film. For this reason, the plating film grows isotropically even inside the trench, and as a result, the plating film cannot be completely embedded in the trench, and seams and voids are generated inside the plating film. is there.
JP 2003-129297 A JP 2001-323398 A

バリア層材料として一般に用いられているＴｉ系合金やＴａ系合金の場合、それらの電気抵抗率は、例えばＴａにあっては１２．４５μΩｃｍ、Ｔｉにあっては４２μΩｃｍと銅（配線材料）に比べて1桁以上も高い。そのため電解めっきでトレンチ内に銅を埋込む際には、バリア層表面に給電層としてのシード層を形成する必要がある。シード層としては、ＰＶＤ法により成膜される銅シード層が一般に用いられているが、配線が微細化するに従って、トレンチ表面に銅シード層を形成することが次第に困難になってきている。今後、配線の微細化が更に進むと、配線幅に比べてシード層の膜厚が占める割合が大きくなる。そのため、その後の電解めっき工程ではトレンチ内へのめっき液の浸入が妨げられ、埋込み性が悪化することが懸念される。また、連続したシード層を形成すること自体が次第に困難になってくる。   In the case of Ti-based alloys and Ta-based alloys generally used as barrier layer materials, their electrical resistivity is, for example, 12.45 μΩcm for Ta and 42 μΩcm for Ti, compared to copper (wiring material) More than an order of magnitude higher. Therefore, when copper is buried in the trench by electrolytic plating, it is necessary to form a seed layer as a power feeding layer on the surface of the barrier layer. As the seed layer, a copper seed layer formed by the PVD method is generally used. However, it is becoming increasingly difficult to form a copper seed layer on the trench surface as the wiring becomes finer. If the miniaturization of wiring further progresses in the future, the proportion of the seed layer film thickness will increase compared to the wiring width. Therefore, in the subsequent electrolytic plating process, the penetration of the plating solution into the trench is hindered, and there is a concern that the embedding property may be deteriorated. In addition, it becomes increasingly difficult to form a continuous seed layer itself.

そこで、比較的電気抵抗の低いバリア層を用いて、バリア層の表面に直接電解銅めっきを行う方法（ダイレクトめっき）が検討され始めている。また、バリア層として従来広く用いられているＴａと配線を形成する銅等の配線材料との密着性は一般に低く、配線の信頼性を下げる一因となっている。   Therefore, a method of directly performing electrolytic copper plating on the surface of the barrier layer using a barrier layer having a relatively low electric resistance (direct plating) has begun to be studied. In addition, the adhesion between Ta, which has been widely used as a barrier layer, and a wiring material such as copper forming the wiring is generally low, which is a cause of lowering the reliability of the wiring.

これらの問題を解決するため、バリア層としてＲｕ（ルテニウム）やＷＮＣ（炭窒化タングステン）などを使用することが提案されている。このうちＲｕは、電気抵抗率が７．６μΩｃｍと、Ｔａと比べて電気抵抗が低く、ルテニウム膜の表面へ直接電解めっきを行うことも視野に入れられている。このように、ルテニウムからなるバリア層（ルテニウム膜）の表面に直接電解めっきを行うことができれば、給電層としてのシード層が不要となるため、工程を削減できるだけでなく、不均一なシード層による導通不良や、電解めっき液のトレンチ内への浸入不足に起因するボイドの発生を抑えることもできる。   In order to solve these problems, it has been proposed to use Ru (ruthenium), WNC (tungsten carbonitride) or the like as a barrier layer. Of these, Ru has an electrical resistivity of 7.6 μΩcm, which is lower than that of Ta, and direct electroplating on the surface of the ruthenium film is also under consideration. In this way, if electrolytic plating can be performed directly on the surface of the ruthenium barrier layer (ruthenium film), a seed layer as a power feeding layer becomes unnecessary, so that not only the process can be reduced, but also a non-uniform seed layer is used. It is also possible to suppress the occurrence of voids due to poor continuity and insufficient penetration of the electrolytic plating solution into the trench.

従来のシード層を用いた一般的な電解めっきによる銅の埋込みにあっては、シード層の溶解防止と穴埋め後の欠陥防止の観点から、基板をめっき液へ接触させるのとほぼ同時に、カソードとなるシード層と対極（アノード）との間に電圧を印加して、電解めっきを開始させる必要があった。しかし、バリア層にルテニウムを用い、バリア層としてのルテニウム膜の表面に直接電解銅めっきを行った場合、従来の条件では、トレンチ内に埋込まれた銅めっき膜中にシームやボイドが発生することを見出した。   In copper embedding by general electrolytic plating using a conventional seed layer, from the viewpoint of preventing dissolution of the seed layer and preventing defects after filling the hole, the cathode and the cathode are almost simultaneously contacted with the plating solution. It was necessary to start the electroplating by applying a voltage between the seed layer and the counter electrode (anode). However, when ruthenium is used for the barrier layer and the electrolytic copper plating is directly applied to the surface of the ruthenium film as the barrier layer, seams and voids are generated in the copper plating film embedded in the trench under the conventional conditions. I found out.

本発明は上記事情に鑑みて為されたもので、バリア層としてのルテニウム膜の表面に直接電解めっきを行って、トレンチ等の配線用凹部内に内部に欠陥のない配線材料を埋込むことができるようにした基板処理方法及び基板処理装置を提供することを目的とする。   The present invention has been made in view of the above circumstances, and by directly electroplating the surface of a ruthenium film as a barrier layer, a wiring material having no defects can be embedded in a wiring recess such as a trench. It is an object of the present invention to provide a substrate processing method and a substrate processing apparatus which can be used.

請求項１に記載の発明は、配線用凹部の表面を含む全表面にルテニウム膜を形成した基板を用意し、前記基板表面をめっき液に所定時間接触させてめっき液中の添加剤をルテニウム膜に吸着させ、しかる後、電解めっきによりルテニウム膜の表面に導電膜を成膜すること特徴とする基板処理方法である。   According to the first aspect of the present invention, a substrate having a ruthenium film formed on the entire surface including the surface of the concave portion for wiring is prepared, and the substrate surface is brought into contact with the plating solution for a predetermined time, and the additive in the plating solution is added to the ruthenium film. Then, after that, a conductive film is formed on the surface of the ruthenium film by electrolytic plating.

バリア層としてルテニウム（Ｒｕ）膜を使用し、このルテニウム膜の表面に電解めっきで銅めっき膜を成長させた時における該銅めっき膜の成長過程を追って分析したところ、めっき初期におけるルテニウム膜表面での銅の粒状析出が銅めっき膜内部にボイドが発生する原因と判明し、更にこの粒状析出の発生状況は、基板をめっき液に接触させてから電解めっきを開始するまでの時間に依存することが判った。つまり従来のシード層を用いた埋込み電解めっきとは異なり、めっき液に基板の表面を接触させ、一定時間静置させてめっき液中の添加剤をルテニウム膜に吸着させてから電解めっきを開始することにより、めっき膜内部にボイドが発生することを抑えて、従来のシード層を用いた場合と同等の穴埋め性を確保することができる。   When a ruthenium (Ru) film was used as the barrier layer and the copper plating film was grown on the surface of the ruthenium film by electrolytic plating, the growth process of the copper plating film was analyzed. It turned out that the granular precipitation of copper was the cause of voids inside the copper plating film, and the occurrence of this granular precipitation was dependent on the time from the contact of the substrate with the plating solution to the start of electrolytic plating I understood. In other words, unlike the conventional electroplating using a seed layer, the surface of the substrate is brought into contact with the plating solution and allowed to stand for a certain period of time so that the additive in the plating solution is adsorbed to the ruthenium film before starting the electroplating. Thus, generation of voids in the plating film can be suppressed, and the same hole filling property as that in the case of using a conventional seed layer can be ensured.

請求項２に記載の発明は、前記導電膜は、銅または銅合金からなることを特徴とする請求項１記載の基板処理方法である。
これにより、配線用凹部内に電解めっきによって埋込んだ銅または銅合金からなる配線を形成することができる。 The invention according to claim 2 is the substrate processing method according to claim 1, wherein the conductive film is made of copper or a copper alloy.
As a result, it is possible to form a wiring made of copper or a copper alloy embedded in the wiring recess by electrolytic plating.

請求項３に記載の発明は、前記めっき液は、銅イオン、硫酸イオン及び添加剤を含むことを特徴とする請求項２記載の基板処理方法である。
このように酸性のめっき液を使用して電解めっきを行っても、バリア層としてのルテニウム膜がめっき液中に溶解してしまうことはない。 The invention according to claim 3 is the substrate processing method according to claim 2, wherein the plating solution contains copper ions, sulfate ions and additives.
Thus, even when electrolytic plating is performed using an acidic plating solution, the ruthenium film as the barrier layer does not dissolve in the plating solution.

請求項４に記載の発明は、電解めっきに先立って、基板表面をめっき液に接触させる時間は、０．５秒以上、６０秒以下であることを特徴とする請求項１乃至３のいずれか一項に記載の基板処理方法である。   The invention according to claim 4 is characterized in that, prior to electrolytic plating, the time for contacting the substrate surface with the plating solution is 0.5 second or more and 60 seconds or less. The substrate processing method according to one item.

請求項５に記載の発明は、電解めっきに先立って、基板表面をめっき液に接触させる時間は、０．１秒以上、２０秒以下であることを特徴とする請求項１乃至３のいずれか一項に記載の基板処理方法である。
請求項６に記載の発明は、電解めっきに先立って、基板表面をめっき液に接触させる時間は、０．１秒以上、５秒以下であることを特徴とする請求項1乃至３のいずれか一項に記載の基板処理方法である。 The invention according to claim 5 is characterized in that, prior to electrolytic plating, the time for contacting the substrate surface with the plating solution is 0.1 second or more and 20 seconds or less. The substrate processing method according to one item.
The invention according to claim 6 is characterized in that, prior to electrolytic plating, the time for contacting the substrate surface with the plating solution is 0.1 second or more and 5 seconds or less. The substrate processing method according to one item.

請求項７に記載の発明は、配線用凹部の表面を含む全表面にルテニウム膜を形成した基板を用意し、前記基板表面をめっき液に所定時間接触させてめっき液中の添加剤をルテニウム膜に吸着させた後、第１電解めっきによってルテニウム膜の表面に前記配線用凹部の全表面を覆う初期導電膜を成膜し、基板表面を洗浄し乾燥させ、しかる後、第２電解めっきによって前記初期導電膜の表面に導電膜を更に成長させることを特徴とする基板処理方法である。   According to the seventh aspect of the present invention, a substrate having a ruthenium film formed on the entire surface including the surface of the concave portion for wiring is prepared, and the substrate surface is brought into contact with the plating solution for a predetermined time so that the additive in the plating solution is added to the ruthenium film. Then, an initial conductive film covering the entire surface of the concave portion for wiring is formed on the surface of the ruthenium film by first electrolytic plating, the substrate surface is washed and dried, and then the second electrolytic plating is used to A substrate processing method characterized by further growing a conductive film on the surface of the initial conductive film.

これにより、ルテニウム膜の表面に、配線用凹部の全表面を均一に覆う初期導電膜を第１電解めっきでコンフォーマルに成膜し、しかる後、この初期導電膜をシード層とした第２電解めっきを行うことで、めっき膜内部にボイドが発生することを抑えて、従来のシード層を用いた場合と同等の穴埋め性を確保することができる。第２電解めっきは、基板表面をめっき液に短時間接触させてめっき液中の添加剤を初期導電膜に少量吸着させてから行っても、基板表面をめっき液に接触させるのと同時に行ってもよい。   As a result, an initial conductive film that uniformly covers the entire surface of the concave portion for wiring is formed on the surface of the ruthenium film conformally by the first electrolytic plating, and then the second electrolysis using the initial conductive film as a seed layer. By performing the plating, it is possible to prevent voids from being generated inside the plating film, and to ensure the same hole filling property as when a conventional seed layer is used. Even if the second electrolytic plating is performed after the substrate surface is contacted with the plating solution for a short time and the additive in the plating solution is adsorbed to the initial conductive film in a small amount, it is performed simultaneously with the contact of the substrate surface with the plating solution. Also good.

請求項８に記載の発明は、前記第１めっき処理と前記第２めっき処理を、同一めっき液を使用して行うことを特徴とする請求項７記載の基板処理方法である。
請求項９に記載の発明は、前記第１電解めっきに先立って、基板表面にめっき液を浸漬させる時間は、５秒以上であることを特徴とする請求項７または８記載の基板処理方法である。 The invention according to claim 8 is the substrate processing method according to claim 7, wherein the first plating process and the second plating process are performed using the same plating solution.
The invention according to claim 9 is the substrate processing method according to claim 7 or 8, wherein the time for immersing the plating solution on the surface of the substrate prior to the first electrolytic plating is 5 seconds or more. is there.

請求項１０に記載の発明は、配線用凹部の表面を含む全表面にルテニウム膜を形成した基板表面に電解めっきにより導電膜を成膜する基板処理装置であって、基板表面をめっき液に接触させてからの経過時間を計測する計測部を有することを特徴とする基板処置装置である。   A tenth aspect of the present invention is a substrate processing apparatus for forming a conductive film by electrolytic plating on a substrate surface having a ruthenium film formed on the entire surface including the surface of the concave portion for wiring, and contacting the substrate surface with a plating solution A substrate treatment apparatus having a measuring unit that measures an elapsed time since the start.

請求項１１に記載の発明は、前記計測部は、基板または基板ホルダの位置を検出する位置検出器、または基板とめっき液の接触を検知する接液検出器からなることを特徴とする請求項１０記載の基板処理装置である。
請求項１２に記載の発明は、前記接液検出器は、光センサ、圧力センサ、導電率センサ、温度センサまたは超音波センサ、またはこれらの組合せからなることを特徴とする請求項１１記載の基板処理装置である。 According to an eleventh aspect of the present invention, the measurement unit includes a position detector that detects the position of the substrate or the substrate holder, or a liquid contact detector that detects contact between the substrate and the plating solution. 10. The substrate processing apparatus according to 10.
The invention according to claim 12 is the substrate according to claim 11, wherein the liquid contact detector comprises an optical sensor, a pressure sensor, a conductivity sensor, a temperature sensor, an ultrasonic sensor, or a combination thereof. It is a processing device.

本発明によれば、バリア層として電気抵抗が低いルテニウム膜を用い、その表面に直接電解めっきを行って、内部にボイド等の欠陥のない配線材料、例えば銅をトレンチ等の配線用凹部内に内部に確実に埋込むことができ、これによって、工程を削減しつつ、配線の信頼性を高めることができる。   According to the present invention, a ruthenium film having a low electrical resistance is used as a barrier layer, and the surface thereof is directly subjected to electrolytic plating, so that a wiring material having no defects such as voids inside, for example, copper is placed in a wiring recess such as a trench. Thus, the wiring can be reliably embedded, thereby improving the reliability of the wiring while reducing the number of processes.

以下、本発明の実施の形態を図面を参照して説明する。
図３は、本発明の実施の形態の基板処理装置の全体配置図を示す。図３に示すように、この基板処理装置には、同一設備内に位置して、内部に複数の基板Ｗを収納する２基のロード・アンロード部１０と、電解めっき処理及びその付帯処理を行う２基の電解めっき装置１２と、ロード・アンロード部１０と電解めっき装置１２との間で基板Ｗの受渡しを行う搬送ロボット１４と、めっき液タンク１６を有するめっき液供給設備１８が備えられている。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 3 shows an overall layout of the substrate processing apparatus according to the embodiment of the present invention. As shown in FIG. 3, this substrate processing apparatus includes two load / unload units 10 that are located in the same facility and house a plurality of substrates W therein, and an electroplating process and an incidental process thereof. Two electroplating apparatuses 12 to be performed, a transfer robot 14 for delivering the substrate W between the load / unload unit 10 and the electroplating apparatus 12, and a plating solution supply facility 18 having a plating solution tank 16 are provided. ing.

電解めっき装置１２には、図４に示すように、めっき処理及びその付帯処理を行う基板処理部２０が備えられ、この基板処理部２０に隣接して、めっき液を溜めるめっき液トレー２２が配置されている。また、回転軸２４を中心に揺動する揺動アーム２６の先端に保持されて基板処理部２０とめっき液トレー２２との間を移動する電極ヘッド２８を有する電極アーム部３０が備えられている。更に、基板処理部２０の側方に位置して、めっき液回収アーム３２と、純水やイオン水等の薬液、または気体等を基板に向けて噴射する固定ノズル３４が配置されている。この実施の形態にあっては、３個の固定ノズル３４が備えられ、その内の１個を純水の供給用に用いている。   As shown in FIG. 4, the electrolytic plating apparatus 12 includes a substrate processing unit 20 that performs a plating process and an incidental process, and a plating solution tray 22 that stores a plating solution is disposed adjacent to the substrate processing unit 20. Has been. Further, an electrode arm section 30 having an electrode head 28 that is held at the tip of a swing arm 26 that swings about the rotation shaft 24 and moves between the substrate processing section 20 and the plating solution tray 22 is provided. . Further, a plating solution recovery arm 32 and a fixed nozzle 34 for injecting a chemical solution such as pure water or ionic water, a gas, or the like toward the substrate are disposed on the side of the substrate processing unit 20. In this embodiment, three fixed nozzles 34 are provided, and one of them is used for supplying pure water.

基板処理部２０には、図５に示すように、表面（被めっき面）を上向きにして基板Ｗを保持する基板保持部３６と、この基板保持部３６の上方に該基板保持部３６の周縁部を囲繞するように配置されたカソード部３８が備えられている。更に、基板保持部３６の周囲を囲繞して処理中に用いる各種薬液の飛散を防止する有底略円筒状の飛散防止カップ４０が、エアシリンダ（図示せず）を介して上下動自在に配置されている。   As shown in FIG. 5, the substrate processing unit 20 includes a substrate holding unit 36 that holds the substrate W with the surface (surface to be plated) facing upward, and a peripheral edge of the substrate holding unit 36 above the substrate holding unit 36. A cathode portion 38 is provided so as to surround the portion. Further, a bottomed substantially cylindrical scattering prevention cup 40 that surrounds the periphery of the substrate holding part 36 and prevents the scattering of various chemicals used during processing is arranged to be movable up and down via an air cylinder (not shown). Has been.

ここで、基板保持部３６は、エアシリンダ４４によって、下方の基板受渡し位置Ａと、上方のめっき位置Ｂと、これらの中間の前処理・洗浄位置Ｃとの間を昇降し、図示しない回転モータ及びベルトを介して、任意の加速度及び速度でカソード部３８と一体に回転するように構成されている。この基板受渡し位置Ａに対向して、電解めっき装置１２のフレーム側面の搬送ロボット１４側には、基板搬出入口（図示せず）が設けられ、また基板保持部３６がめっき位置Ｂまで上昇した時に、基板保持部３６で保持された基板Ｗの周縁部に下記のカソード部３８のシール材９０とカソード接点８８が当接する。飛散防止カップ４０は、その上端が基板搬出入口下方に位置し、図５に仮想線で示すように、上昇した時に基板搬出入口を塞いでカソード部３８の上方に達する。   Here, the substrate holding unit 36 is moved up and down between a lower substrate delivery position A, an upper plating position B, and an intermediate pretreatment / cleaning position C by an air cylinder 44, and a rotary motor (not shown). And it is comprised so that it may rotate integrally with the cathode part 38 with arbitrary acceleration and speed | velocity | rate via a belt. Opposite to the substrate delivery position A, a substrate carry-in / out port (not shown) is provided on the side of the transfer robot 14 on the side of the frame of the electroplating apparatus 12, and when the substrate holding part 36 is raised to the plating position B. The sealing material 90 and cathode contact 88 of the cathode part 38 described below abut on the peripheral edge of the substrate W held by the substrate holding part 36. The upper end of the anti-scattering cup 40 is located below the substrate carry-in / out port, and as shown by the phantom line in FIG.

めっき液トレー２２は、めっき処理を実施していない時に、電極アーム部３０の下記の多孔質構造体１１０及びアノード９８をめっき液で湿潤させるためのもので、この多孔質構造体１１０が収容できる大きさに設定され、図示しないめっき液供給口とめっき液排水口を有している。また、光センサがめっき液トレー２２に取付けられており、めっき液トレー２２内のめっき液の満水、即ちオーバーフローと排水の検出が可能になっている。
電極アーム部３０は、図示しないサーボモータからなる上下動モータとボールねじを介して上下動し、旋回モータを介して、めっき液トレー２２と基板処理部２０との間を電極ヘッド２８が移動するように旋回（揺動）する。 The plating solution tray 22 is used to wet the following porous structure 110 and the anode 98 of the electrode arm portion 30 with a plating solution when the plating process is not being performed, and can accommodate the porous structure 110. It is set to a size and has a plating solution supply port and a plating solution drain port (not shown). Further, an optical sensor is attached to the plating solution tray 22 so that the plating solution in the plating solution tray 22 is fully filled, that is, overflow and drainage can be detected.
The electrode arm unit 30 moves up and down via a vertical movement motor and a ball screw, which are not shown, and the electrode head 28 moves between the plating solution tray 22 and the substrate processing unit 20 through a turning motor. Swivel (oscillate).

めっき液回収アーム３２は、図６に示すように、上下方向に延びる支持軸５８の上端に連結されて、ロータリアクチュエータ６０を介して旋回（揺動）し、エアシリンダ（図示せず）を介して上下動するように構成されている。めっき液回収アーム３２には、例えばシリンダポンプまたはアスピレータに接続されて、基板上のめっき液を吸引して回収するめっき液回収ノズル６６が備えられている。   As shown in FIG. 6, the plating solution recovery arm 32 is connected to the upper end of a support shaft 58 extending in the vertical direction, pivots (swings) via a rotary actuator 60, and passes through an air cylinder (not shown). Are configured to move up and down. The plating solution recovery arm 32 is provided with a plating solution recovery nozzle 66 that is connected to, for example, a cylinder pump or an aspirator and sucks and recovers the plating solution on the substrate.

基板保持部３６は、図７乃至図９に示すように、円板状の基板ステージ６８を備え、この基板ステージ６８の周縁部の円周方向に沿った６カ所に、上面に基板Ｗを水平に載置して保持する支持腕７０が立設されている。この支持腕７０の１つの上端には、基板Ｗの端面に当接して位置決めする位置決め板７２が固着され、この位置決め板７２を固着した支持腕７０に対向する支持腕７０の上端には、基板Ｗの端面に当接し回動して基板Ｗを位置決め板７２側に押付ける押付け片７４が回動自在に支承されている。また、他の４個の支持腕７０の上端には、回動して基板Ｗをこの上方から下方に押付けるチャック爪７６が回動自在に支承されている。   As shown in FIGS. 7 to 9, the substrate holding unit 36 includes a disk-shaped substrate stage 68, and the substrate W is horizontally placed on the upper surface at six locations along the circumferential direction of the peripheral portion of the substrate stage 68. A support arm 70 is erected to be placed and held on the head. A positioning plate 72 is fixed to one upper end of the support arm 70 to be positioned in contact with the end surface of the substrate W, and a substrate is fixed to the upper end of the support arm 70 facing the support arm 70 to which the positioning plate 72 is fixed. A pressing piece 74 is pivotally supported so as to be rotated in contact with the end face of W and press the substrate W against the positioning plate 72 side. In addition, chuck claws 76 that pivot and press the substrate W downward from above are rotatably supported at the upper ends of the other four support arms 70.

ここで、押付け片７４及びチャック爪７６の下端は、コイルばね７８を介して下方に付勢した押圧棒８０の上端に連結されて、この押圧棒８０の下動に伴って押付け片７４及びチャック爪７６が内方に回動して閉じるようになっており、基板ステージ６８の下方には、押圧棒８０に下面に当接してこれを上方に押上げる支持板８２が配置されている。   Here, the lower end of the pressing piece 74 and the chuck claw 76 is connected to the upper end of the pressing bar 80 biased downward via the coil spring 78, and the pressing piece 74 and the chuck are moved along with the downward movement of the pressing bar 80. A claw 76 is pivoted inwardly and closed, and a support plate 82 is disposed below the substrate stage 68 so as to abut the lower surface of the pressing rod 80 and push it upward.

これにより、基板保持部３６が図５に示す基板受渡し位置Ａに位置する時、押圧棒８０は支持板８２に当接し上方に押上げられて、押付け片７４及びチャック爪７６が外方に回動して開き、基板ステージ６８を上昇させると、押圧棒８０がコイルばね７８の弾性力で下降して、押付け片７４及びチャック爪７６が内方に回転して閉じる。   As a result, when the substrate holding part 36 is located at the substrate delivery position A shown in FIG. 5, the pressing rod 80 abuts against the support plate 82 and is pushed upward, so that the pressing piece 74 and the chuck pawl 76 rotate outward. When the substrate stage 68 is raised by moving, the pressing rod 80 is lowered by the elastic force of the coil spring 78, and the pressing piece 74 and the chuck pawl 76 are rotated inward and closed.

カソード部３８は、図１０及び図１１に示すように、支持板８２（図９等参照）の周縁部に立設した支柱８４の上端に固着した環状の枠体８６と、この枠体８６の下面に内方に突出させて取付けた、この例では６分割されたカソード接点８８と、このカソード接点８８の上方を覆うように枠体８６の上面に取付けた環状のシール材９０とを有している。シール材９０は、その内周縁部が内方に向け下方に傾斜し、かつ徐々に薄肉となって、内周端部が下方に垂下するように構成されている。   As shown in FIGS. 10 and 11, the cathode portion 38 includes an annular frame 86 fixed to the upper end of a column 84 erected on the peripheral edge of a support plate 82 (see FIG. 9), and the frame 86. In this example, the cathode contact 88 is divided into six parts and attached to the lower surface, and an annular seal member 90 is attached to the upper surface of the frame 86 so as to cover the upper side of the cathode contact 88. ing. The seal member 90 is configured such that an inner peripheral edge thereof is inclined downward inward and gradually becomes thin, and an inner peripheral end portion hangs downward.

これにより、図５に示すように、基板保持部３６がめっき位置Ｂまで上昇した時に、この基板保持部３６で保持した基板Ｗの周縁部にカソード接点８８が押付けられて通電し、同時にシール材９０の内周端部が基板Ｗの周縁部上面に圧接し、ここを水密的にシールして、基板Ｗの上面（被めっき面）に供給されためっき液が基板Ｗの端部から染み出すのを防止するとともに、めっき液がカソード接点８８を汚染することを防止する。
なお、この実施の形態において、カソード部３８は、上下動不能で基板保持部３６と一体に回転するようになっているが、上下動自在で、下降した時にシール材９０が基板Ｗの被めっき面に圧接するように構成してもよい。 As a result, as shown in FIG. 5, when the substrate holding portion 36 is raised to the plating position B, the cathode contact 88 is pressed against the peripheral portion of the substrate W held by the substrate holding portion 36 and energized, and at the same time, the sealing material The inner peripheral end of 90 is in pressure contact with the upper surface of the peripheral edge of the substrate W, and this is sealed in a watertight manner, so that the plating solution supplied to the upper surface (surface to be plated) of the substrate W oozes out from the end of the substrate W. And preventing the plating solution from contaminating the cathode contact 88.
In this embodiment, the cathode portion 38 cannot move up and down and rotates integrally with the substrate holding portion 36. However, the cathode portion 38 is movable up and down, and the seal material 90 is plated on the substrate W when lowered. You may comprise so that it may press-contact to a surface.

前記電極アーム部３０の電極ヘッド２８は、図１２及び図１３に示すように、揺動アーム２６の自由端にボールベアリング９２を介して連結したハウジング９４と、このハウジング９４の下端開口部を塞ぐように配置された多孔質構造体１１０とを有している。すなわち、ハウジング９４は、下方に開口した有底カップ状に形成され、この下部内周面には、凹状部９４ａが、多孔質構造体１１０の上部には、この凹状部９４ａに嵌合するフランジ部１１０ａがそれぞれ設けられ、このフランジ部１１０ａを凹状部９４ａに嵌入することで、ハウジング９４に多孔質構造体１１０が保持されている。これによって、ハウジング９４の内部に中空のめっき液室１００が区画形成されている。   As shown in FIGS. 12 and 13, the electrode head 28 of the electrode arm portion 30 closes the housing 94 connected to the free end of the swing arm 26 via a ball bearing 92 and the lower end opening of the housing 94. The porous structure 110 is arranged as described above. That is, the housing 94 is formed in a bottomed cup shape that opens downward, and a concave portion 94a is formed on the inner peripheral surface of the lower portion, and a flange that fits the concave portion 94a is formed on the upper portion of the porous structure 110. Each portion 110a is provided, and the porous structure 110 is held in the housing 94 by fitting the flange portion 110a into the concave portion 94a. As a result, a hollow plating solution chamber 100 is defined in the housing 94.

この多孔質構造体１１０の内部にめっき液を含有させることで、つまり多孔質構造体１１０自体は絶縁体であるが、この内部にめっき液を複雑に入り込ませ、厚さ方向にかなり長い経路を辿らせることで、めっき液の電気伝導率より小さい電気伝導率を有するように構成されている。   By containing a plating solution inside the porous structure 110, that is, the porous structure 110 itself is an insulator, but the plating solution enters the inside in a complicated manner, and a considerably long path is formed in the thickness direction. By making it trace, it is comprised so that it may have an electrical conductivity smaller than the electrical conductivity of a plating solution.

前記めっき液室１００内には、多孔質構造体１１０の上方に位置して、内部に上下に貫通する多数の通孔９８ｃを有するアノード９８が配置されている。そして、ハウジング９４には、めっき液室１００の内部のめっき液を吸引して排出するめっき液排出口１０３が設けられ、このめっき液排出口１０３は、めっき液供給設備１８（図３参照）から延びるめっき液排出管１０６に接続されている。更に、ハウジング９４の周壁内部には、アノード９８及び多孔質構造体１１０の側方に位置して上下に貫通するめっき液注入部１０４が設けられている。このめっき液注入部１０４は、この例では、下端をノズル形状としたチューブで構成され、めっき液供給設備１８（図３参照）から延びるめっき液供給管１０２に接続されている。   In the plating solution chamber 100, an anode 98 having a large number of through-holes 98c penetrating vertically is disposed above the porous structure 110. The housing 94 is provided with a plating solution discharge port 103 that sucks and discharges the plating solution inside the plating solution chamber 100. The plating solution discharge port 103 is provided from the plating solution supply facility 18 (see FIG. 3). It is connected to the extending plating solution discharge pipe 106. Further, a plating solution injection part 104 is provided inside the peripheral wall of the housing 94 and is located on the side of the anode 98 and the porous structure 110 and penetrates vertically. In this example, the plating solution injection unit 104 is configured by a tube having a nozzle shape at the lower end, and is connected to a plating solution supply pipe 102 extending from the plating solution supply facility 18 (see FIG. 3).

このめっき液注入部１０４は、基板保持部３６がめっき位置Ｂ（図５参照）にある時に、基板保持部３６で保持した基板Ｗと多孔質構造体１１０の隙間が、例えば０．５〜３ｍｍ程度となるまで電極ヘッド２８を下降させ、この状態で、アノード９８及び多孔質構造体１１０の側方から、基板Ｗと多孔質構造体１１０との間の領域にめっき液を注入するためのもので、シール材９０と多孔質構造体１１０に挟まれた領域で下端のノズル部が開口するようになっている。また、多孔質構造体１１０の外周部には、ここを電気的にシールドするゴム製のシールドリング１１２が装着されている。   In the plating solution injection unit 104, when the substrate holding unit 36 is at the plating position B (see FIG. 5), the gap between the substrate W held by the substrate holding unit 36 and the porous structure 110 is, for example, 0.5 to 3 mm. The electrode head 28 is lowered to a certain level, and in this state, a plating solution is injected into the region between the substrate W and the porous structure 110 from the side of the anode 98 and the porous structure 110. Thus, the lower end nozzle portion opens in a region sandwiched between the sealing material 90 and the porous structure 110. In addition, a rubber shield ring 112 that electrically shields the outer periphery of the porous structure 110 is attached.

このめっき液注入時には、めっき液注入部１０４から注入されためっき液は、基板Ｗの表面に沿って一方向に流れ、このめっき液の流れによって、基板Ｗと多孔質構造体１１０との間の領域の空気が外方に押し出されて外部に排出され、この領域がめっき液注入部１０４から注入された新鮮で組成が調整されためっき液で満たされて、基板Ｗとシール材９０で区画された領域に溜められる。   At the time of injecting the plating solution, the plating solution injected from the plating solution injection unit 104 flows in one direction along the surface of the substrate W, and the flow of the plating solution causes a gap between the substrate W and the porous structure 110. The air in the region is pushed outward and discharged to the outside, and this region is filled with the fresh and adjusted plating solution injected from the plating solution injection unit 104 and partitioned by the substrate W and the sealing material 90. Accumulated in the area.

そして、ハウジング９４の側方に位置して、基板保持部３６で保持した基板Ｗの表面にめっき液注入部１０４からめっき液が供給されて該基板Ｗの表面がめっき液に接触したことを検出する、例えば光センサからなる、計測部としての接液検出器１２０が配置されている。つまり、この接液検出器１２０は、基板Ｗの表面がめっき液に接触したことを検出し、更に、この検出した信号を制御部等に入力することで、基板Ｗの表面がめっき液に接触した時からの時間を計測するようになっている。この接液検出器１２０の代わりに、例えば浸漬タイプの電解めっき装置にあっては、基板または基板ホルダの位置を検出する位置検出器を使用し、位置検出器からの検出信号を制御部等に入力するようにしてもよく、また、圧力センサの代わりに、導電率センサ、温度センサまたは超音波センサ、またはこれらの組合せからなるセンサを使用してもよい。   Then, the plating solution is supplied from the plating solution injection unit 104 to the surface of the substrate W held by the substrate holding unit 36, which is located on the side of the housing 94, and it is detected that the surface of the substrate W is in contact with the plating solution. For example, a liquid contact detector 120 as a measuring unit made of, for example, an optical sensor is disposed. That is, the liquid contact detector 120 detects that the surface of the substrate W is in contact with the plating solution, and further inputs the detected signal to the control unit or the like so that the surface of the substrate W contacts the plating solution. It is designed to measure the time from when you did it. In place of the liquid contact detector 120, for example, in an immersion type electroplating apparatus, a position detector that detects the position of the substrate or the substrate holder is used, and a detection signal from the position detector is sent to the control unit or the like. Input may be performed, and instead of the pressure sensor, a conductivity sensor, a temperature sensor, an ultrasonic sensor, or a combination thereof may be used.

ここで、アノード９８は、スライムの生成を抑制するため、含有量が０．０３〜０．０５％のリンを含む銅（含リン銅）で構成されているが、例えば酸化イリジウムで被覆した不溶性アノードを使用するようにしてもよい。そして、アノード９８はめっき電源１１４の陽極に、カソード接点８８はめっき電源１１４の陰極にそれぞれ電気的に接続される。   Here, the anode 98 is composed of copper containing 0.03 to 0.05% phosphorus (phosphorus-containing copper) in order to suppress the formation of slime. For example, the anode 98 is insoluble coated with iridium oxide. An anode may be used. The anode 98 is electrically connected to the anode of the plating power source 114, and the cathode contact 88 is electrically connected to the cathode of the plating power source 114.

そして、基板保持部３６がめっき位置Ｂ（図５参照）にある時に、基板保持部３６で保持した基板Ｗと多孔質構造体１１０との隙間が、例えば０．５〜３ｍｍ程度となるまで電極ヘッド２８を下降させる。この状態で、基板Ｗと多孔質構造体１１０との領域にめっき液注入部１０４からめっき液を注入してめっき液で満たし、このめっき液を基板Ｗとシール材９０で区画された領域に溜めてめっき処理を行う。   Then, when the substrate holding part 36 is at the plating position B (see FIG. 5), the electrode is used until the gap between the substrate W held by the substrate holding part 36 and the porous structure 110 becomes, for example, about 0.5 to 3 mm. The head 28 is lowered. In this state, the plating solution is injected into the region between the substrate W and the porous structure 110 from the plating solution injection unit 104 and filled with the plating solution, and this plating solution is stored in the region partitioned by the substrate W and the sealing material 90. Plating.

次に、基板処理装置を使用した本発明の基板処理方法（めっき方法）について、図１４乃至図１６を更に参照して説明する。
先ず、図１４（ａ）に示すように、半導体素子を形成した半導体基材１上の導電層１ａの上にＳｉＯ２やＬｏｗ−Ｋ材からなる絶縁膜（層間絶縁膜）２を堆積し、絶縁膜２の内部に、リソグラフィ・エッチング技術により、配線用凹部としてのビアホール３とトレンチ４を形成し、その表面にバリア層としてのルテニウム膜５ａを形成した基板Ｗを用意する。 Next, the substrate processing method (plating method) of the present invention using the substrate processing apparatus will be described with further reference to FIGS.
First, as shown in FIG. 14A, an insulating film (interlayer insulating film) 2 made of SiO 2 or Low-K material is deposited on a conductive layer 1a on a semiconductor substrate 1 on which a semiconductor element is formed, A substrate W is prepared in which a via hole 3 and a trench 4 are formed as a wiring recess, and a ruthenium film 5a as a barrier layer is formed on the surface of the insulating film 2 by lithography / etching technique.

そして、先ず、ロード・アンロード部１０からめっき処理前の基板Ｗを搬送ロボット１４で取り出し、表面（被めっき面）を上向きにした状態で、フレームの側面に設けられた基板搬出入口から一方の電解めっき装置１２の内部に搬送する。この時、基板保持部３６は、下方の基板受渡し位置Ａにあり、搬送ロボット１４は、そのハンドが基板ステージ６８の真上に到達した後に、ハンドを下降させることで、基板Ｗを支持腕７０上に載置する。そして、搬送ロボット１４のハンドを、前記基板搬出入口を通って退去させる。   First, the substrate W before plating treatment is taken out from the loading / unloading unit 10 by the transfer robot 14, and one of the substrates (surface to be plated) is turned upward from the substrate loading / unloading port provided on the side surface of the frame. It is conveyed inside the electroplating apparatus 12. At this time, the substrate holding unit 36 is at the lower substrate delivery position A, and the transport robot 14 lowers the hand after the hand reaches just above the substrate stage 68, thereby supporting the substrate W on the support arm 70. Place on top. Then, the hand of the transfer robot 14 is retreated through the substrate carry-in / out entrance.

搬送ロボット１４のハンドの退去が完了した後、飛散防止カップ４０を上昇させ、同時に基板受渡し位置Ａにあった基板保持部３６を前処理・洗浄位置Ｃに上昇させる。この時、この上昇に伴って、支持腕７０上に載置された基板は、位置決め板７２と押付け片７４で位置決めされ、チャック爪７６で確実に把持される。   After the removal of the hand of the transfer robot 14 is completed, the anti-scattering cup 40 is raised, and at the same time, the substrate holding part 36 that was in the substrate delivery position A is raised to the pretreatment / cleaning position C. At this time, with this rise, the substrate placed on the support arm 70 is positioned by the positioning plate 72 and the pressing piece 74 and is securely gripped by the chuck claws 76.

一方、電極アーム部３０の電極ヘッド２８は、この時点ではめっき液トレー２２上の通常位置にあって、多孔質構造体１１０またはアノード９８がめっき液トレー２２内に位置しており、この状態で、飛散防止カップ４０の上昇と同時に、めっき液トレー２２及び電極ヘッド２８にめっき液の供給を開始する。そして、基板のめっき工程に移るまで、新しいめっき液を供給し、併せてめっき液排出管１０６を通じためっき液の吸引を行って、多孔質構造体１１０に含まれるめっき液の交換と泡抜きを行う。なお、飛散防止カップ４０の上昇が完了すると、フレーム側面の基板搬出入口は飛散防止カップ４０で塞がれて閉じ、フレーム内外の雰囲気が遮断状態となる。   On the other hand, the electrode head 28 of the electrode arm unit 30 is at a normal position on the plating solution tray 22 at this point, and the porous structure 110 or the anode 98 is located in the plating solution tray 22. Simultaneously with the rising of the anti-scattering cup 40, supply of the plating solution to the plating solution tray 22 and the electrode head 28 is started. Then, until the substrate plating process is started, a new plating solution is supplied, and at the same time, the plating solution is sucked through the plating solution discharge pipe 106 to replace the plating solution contained in the porous structure 110 and remove bubbles. Do. When the raising of the scattering prevention cup 40 is completed, the substrate carry-in / out entrance on the side of the frame is closed and closed by the scattering prevention cup 40, and the atmosphere inside and outside the frame is cut off.

続いてめっき処理に移る。先ず、基板保持部３６を、この回転を停止、若しくは回転速度をめっき時速度まで低下させた状態で、めっきを施すめっき位置Ｂまで上昇させる。すると、基板Ｗの周縁部は、カソード接点８８に接触して通電可能な状態となり、同時に基板Ｗの周縁部上面にシール材９０が圧接して、基板Ｗの周縁部が水密的にシールされる。   Then, it moves to a plating process. First, the substrate holding unit 36 is raised to the plating position B where plating is performed in a state where the rotation is stopped or the rotation speed is reduced to the plating speed. Then, the peripheral portion of the substrate W comes into contact with the cathode contact 88 and can be energized. At the same time, the sealing material 90 is pressed against the upper surface of the peripheral portion of the substrate W, and the peripheral portion of the substrate W is sealed watertight. .

一方、基板Ｗが搬入されたという信号に基づいて、電極アーム部３０をめっき液トレー２２上方からめっき処理を施す位置の上方に電極ヘッド２８が位置するように水平方向に旋回させ、しかる後、電極ヘッド２８をカソード部３８に向かって下降させる。この時、多孔質構造体１１０を基板Ｗの表面に接触することなく、０．５ｍｍ〜３ｍｍ程度に近接した位置とする。そして、めっき液注入部１０４から基板Ｗと多孔質構造体１１０との間の領域にめっき液を注入して該領域をめっき液で満たす。   On the other hand, based on the signal that the substrate W has been carried in, the electrode arm unit 30 is swung horizontally from above the plating solution tray 22 so that the electrode head 28 is positioned above the position where the plating process is performed, and then, The electrode head 28 is lowered toward the cathode portion 38. At this time, the porous structure 110 is brought into a position close to about 0.5 mm to 3 mm without contacting the surface of the substrate W. Then, the plating solution is injected from the plating solution injection unit 104 into the region between the substrate W and the porous structure 110 to fill the region with the plating solution.

この時、基板Ｗの表面がめっき液に接触したことを接液検出器１２０で検出し、この基板Ｗの表面がめっき液に接触した状態を所定時間維持して、めっき液中の添加剤をルテニウム膜５ａに吸着させる。つまり、図１６に示すように、基板Ｗの表面がめっき液に接触したことを接液検出器１２０で検出した後、この接触時間が所定時間経過したか否かを計測する。この基板表面をめっき液に接触させる時間は、例えば、０．５秒以上、６０秒以下であり、０．１秒以上、２０秒以下であることが好ましく、０．１秒以上、５秒以下であることが更に好ましい。   At this time, it is detected by the liquid contact detector 120 that the surface of the substrate W is in contact with the plating solution, and the state in which the surface of the substrate W is in contact with the plating solution is maintained for a predetermined time. Adsorbed on the ruthenium film 5a. That is, as shown in FIG. 16, after the liquid contact detector 120 detects that the surface of the substrate W is in contact with the plating solution, it is measured whether or not this contact time has elapsed for a predetermined time. The time for contacting the substrate surface with the plating solution is, for example, 0.5 seconds or more and 60 seconds or less, preferably 0.1 seconds or more and 20 seconds or less, and 0.1 seconds or more and 5 seconds or less. More preferably.

そして、この接触時間が所定時間経過した後、カソード接点８８とアノード９８との間に、めっき電源１１４から電圧を印加し、これによって、図１４（ｂ）に示すように、ビアホール３及びトレンチ４内に銅を充填させつつ、ルテニウム膜（バリア層）５ａの表面に銅めっき膜６を成膜する。このように、めっき液にルテニウム膜５ａを接触させ、一定時間静置させてめっき液中の添加剤をルテニウム膜５ａに吸着させてから電解めっきを開始することにより、めっき膜６の内部にボイドが発生することを抑え、しかも、従来と同等の穴埋め性を確保して、ルテニウム膜５ａの表面に銅めっき膜６を成膜することができる。   Then, after a predetermined time has elapsed, a voltage is applied from the plating power source 114 between the cathode contact 88 and the anode 98, and as a result, as shown in FIG. A copper plating film 6 is formed on the surface of the ruthenium film (barrier layer) 5a while being filled with copper. In this way, the ruthenium film 5a is brought into contact with the plating solution and allowed to stand for a certain period of time so that the additive in the plating solution is adsorbed to the ruthenium film 5a, and then electroplating is started. In addition, the copper plating film 6 can be formed on the surface of the ruthenium film 5a while suppressing the occurrence of cavities and ensuring the same hole filling property as that of the prior art.

これにより、バリア層として電気抵抗が低いルテニウム膜５ａを用い、その表面に直接電解めっきを行って、内部にボイド等の欠陥のない銅めっき膜６をトレンチ等の配線用凹部内に内部に確実に埋込むことができ、これによって、工程を削減しつつ、配線の信頼性を高めることができる。しかも、めっき液として、銅イオン、硫酸イオン及び添加剤を含む酸性のめっき液を使用して電解めっきを行っても、バリア層としてのルテニウム膜５ａがめっき液中に溶解してしまうことはない。   As a result, the ruthenium film 5a having a low electrical resistance is used as the barrier layer, and the surface thereof is directly subjected to electroplating, so that the copper plating film 6 having no defects such as voids inside can be reliably formed inside the wiring recess such as a trench. Thus, the reliability of the wiring can be improved while reducing the number of processes. Moreover, even when electrolytic plating is performed using an acidic plating solution containing copper ions, sulfate ions and additives as the plating solution, the ruthenium film 5a as the barrier layer is not dissolved in the plating solution. .

めっき処理が完了すると、電極アーム部３０を上昇させ旋回させてめっき液トレー２２上方へ戻し、通常位置へ下降させる。次に、めっき液回収ノズル６６から基板Ｗ上のめっき液の残液を回収する。この残液の回収が終了した後、基板めっき面のリンスのために、純水用の固定ノズル３４から基板Ｗの中央部に純水を吐出し、同時に基板保持部３６をスピードを増して回転させて基板Ｗの表面のめっき液を純水に置換する。このように、基板Ｗのリンスを行うことで、基板保持部３６をめっき位置Ｂから下降させる際に、めっき液が跳ねて、カソード部３８のカソード接点８８が汚染されることが防止される。   When the plating process is completed, the electrode arm part 30 is raised and turned to return to the upper part of the plating solution tray 22 and lowered to the normal position. Next, the remaining solution of the plating solution on the substrate W is recovered from the plating solution recovery nozzle 66. After the collection of the remaining liquid is completed, pure water is discharged from the fixed nozzle 34 for pure water to the center of the substrate W for rinsing the substrate plating surface, and at the same time, the substrate holder 36 is rotated at an increased speed. Then, the plating solution on the surface of the substrate W is replaced with pure water. Thus, by rinsing the substrate W, when the substrate holding part 36 is lowered from the plating position B, the plating solution is prevented from splashing and the cathode contact 88 of the cathode part 38 is prevented from being contaminated.

リンス終了後に水洗工程に入る。即ち、基板保持部３６をめっき位置Ｂから前処理・洗浄位置Ｃへ下降させ、純水用の固定ノズル３４から純水を供給しつつ基板保持部３６及びカソード部３８を回転させて水洗を実施する。この時、カソード部３８に直接供給した純水、又は基板Ｗの面から飛散した純水によってシール材９０及びカソード接点８８も基板Ｗと同時に洗浄することができる。   After rinsing, the water washing process is started. That is, the substrate holding part 36 is lowered from the plating position B to the pretreatment / cleaning position C, and the substrate holding part 36 and the cathode part 38 are rotated while supplying pure water from the fixed nozzle 34 for pure water, and water washing is performed. To do. At this time, the sealing material 90 and the cathode contact 88 can also be cleaned simultaneously with the substrate W by pure water directly supplied to the cathode portion 38 or pure water scattered from the surface of the substrate W.

水洗完了後にドライ工程に入る。即ち、固定ノズル３４からの純水の供給を停止し、更に基板保持部３６及びカソード部３８の回転スピードを増して、遠心力により基板表面の純水を振り切って乾燥させる。併せて、シール材９０及びカソード接点８８も乾燥される。ドライ工程が完了すると基板保持部３６及びカソード部３８の回転を停止させ、基板保持部３６を基板受渡し位置Ａまで下降させる。すると、チャック爪７６による基板Ｗの把持が解かれ、基板Ｗは、支持腕７０の上面に載置された状態となる。これと同時に、飛散防止カップ４０も下降させる。   After the water washing is completed, the drying process is started. That is, the supply of pure water from the fixed nozzle 34 is stopped, the rotation speed of the substrate holding part 36 and the cathode part 38 is increased, and the pure water on the substrate surface is shaken off by the centrifugal force and dried. At the same time, the sealing material 90 and the cathode contact 88 are also dried. When the drying process is completed, the rotation of the substrate holding part 36 and the cathode part 38 is stopped, and the substrate holding part 36 is lowered to the substrate delivery position A. Then, the grip of the substrate W by the chuck claws 76 is released, and the substrate W is placed on the upper surface of the support arm 70. At the same time, the splash prevention cup 40 is also lowered.

以上でめっき処理及びそれに付帯する前処理や洗浄・乾燥工程の全て工程を終了し、搬送ロボット１４は、そのハンドを基板搬出入口から基板Ｗの下方に挿入し、そのまま上昇させることで、基板保持部３６から処理後の基板Ｗを受取る。そして、搬送ロボット１４は、この基板保持部３６から受取った処理後の基板Ｗをロード・アンロード部１０に戻す。そして、化学的機械的研磨（ＣＭＰ）により、絶縁膜２上の銅めっき膜６及びルテニウム膜（バリア膜）５ａを除去して、図１４（ｃ）に示すように、絶縁膜２の内部に銅めっき膜６からなる配線を形成する。   Thus, the plating process and all the pre-processing and cleaning / drying processes incidental thereto are completed, and the transfer robot 14 inserts the hand into the lower part of the substrate W from the substrate loading / unloading port and lifts the substrate as it is, thereby holding the substrate. The processed substrate W is received from the unit 36. Then, the transfer robot 14 returns the processed substrate W received from the substrate holding unit 36 to the load / unload unit 10. Then, the copper plating film 6 and the ruthenium film (barrier film) 5a on the insulating film 2 are removed by chemical mechanical polishing (CMP), and as shown in FIG. A wiring made of the copper plating film 6 is formed.

次に、上記基板処理装置を使用した本発明の他の基板処理方法（めっき方法）を、図１７を参照して説明する。
先ず、図１７（ａ）に示すように、ＳｉＯ２やＬｏｗ−Ｋ材からなる絶縁膜（層間絶縁膜）２aの内部に、配線用凹部としてのトレンチ４ａを形成し、その表面にバリア層としてのルテニウム膜５ｂを形成した基板Ｗを用意する。 Next, another substrate processing method (plating method) of the present invention using the substrate processing apparatus will be described with reference to FIG.
First, as shown in FIG. 17A, a trench 4a as a wiring recess is formed in an insulating film (interlayer insulating film) 2a made of SiO 2 or Low-K material, and a barrier layer is formed on the surface thereof. A substrate W on which the ruthenium film 5b is formed is prepared.

そして、前述と同様にして、多孔質構造体１１０を基板Ｗの表面に接触することなく、０．５ｍｍ〜３ｍｍ程度に近接した位置とした後、めっき液注入部１０４から基板Ｗと多孔質構造体１１０との間の領域にめっき液を注入して該領域をめっき液で満たす。この時、基板Ｗの表面がめっき液に接触したことを接液検出器１２０で検出し、この基板Ｗの表面がめっき液に接触した状態を所定時間維持して、めっき液中の添加剤をルテニウム膜５ａに吸着させる。この基板表面をめっき液に接触させる時間は、例えば５秒以上、好ましくは２０秒以上であり、例えば３０秒である。   Then, in the same manner as described above, the porous structure 110 is brought into a position close to about 0.5 mm to 3 mm without contacting the surface of the substrate W, and then the substrate W and the porous structure from the plating solution injection part 104. A plating solution is injected into a region between the body 110 and the region is filled with the plating solution. At this time, it is detected by the liquid contact detector 120 that the surface of the substrate W is in contact with the plating solution, and the state in which the surface of the substrate W is in contact with the plating solution is maintained for a predetermined time. Adsorbed on the ruthenium film 5a. The time for contacting the substrate surface with the plating solution is, for example, 5 seconds or longer, preferably 20 seconds or longer, for example 30 seconds.

そして、この接触時間が所定時間経過した後、カソード接点８８とアノード９８との間に、めっき電源１１４から電圧を印加し、これによって、図１７（ｂ）に示すように、ルテニウム膜５ｂの表面に、トレンチ４ａの全表面を均一に覆う初期銅めっき膜６ａをコンフォーマルに成膜する。   Then, after a predetermined time has elapsed, a voltage is applied from the plating power source 114 between the cathode contact 88 and the anode 98, whereby, as shown in FIG. 17B, the surface of the ruthenium film 5b. Then, an initial copper plating film 6a that uniformly covers the entire surface of the trench 4a is formed conformally.

次に、前述と同様にして、基板めっき面を純水でリンス（洗浄）し、更に基板保持部３６及びカソード部３８の回転スピードを増し、例えば１５００ｒｐｍで３０秒のスピンドライを行って乾燥させる。これによって、図１７（ｃ）に示すように、ルテニウム膜５ｂの表面に初期銅めっき膜６ａをコンフォーマルに成膜して乾燥させた基板Ｗを得る。   Next, in the same manner as described above, the substrate plating surface is rinsed (cleaned) with pure water, and the rotation speed of the substrate holding unit 36 and the cathode unit 38 is increased, and spin drying is performed, for example, at 1500 rpm for 30 seconds. . As a result, as shown in FIG. 17C, a substrate W is obtained in which the initial copper plating film 6a is conformally formed on the surface of the ruthenium film 5b and dried.

次に、前記初期銅めっき膜６ａをシード層としためっきを行い、初期銅めっき膜６ａの表面に銅めっき膜を成長させて、図１７（ｄ）に示すように、トレンチ４ａ内に銅めっき膜６を埋込む。つまり、前述と同様にして、多孔質構造体１１０を基板Ｗの表面に接触することなく、０．５ｍｍ〜３ｍｍ程度に近接した位置とした後、カソード接点８８とアノード９８との間にめっき電源１１４から電圧を印加しつつ、めっき液注入部１０４から基板Ｗと多孔質構造体１１０との間の領域にめっき液を注入して該領域をめっき液で満たし、これによって、初期銅めっき膜６ａの表面に銅めっき膜を成長させる。   Next, plating is performed using the initial copper plating film 6a as a seed layer, and a copper plating film is grown on the surface of the initial copper plating film 6a. As shown in FIG. The membrane 6 is embedded. That is, in the same manner as described above, after the porous structure 110 is brought into a position close to about 0.5 mm to 3 mm without contacting the surface of the substrate W, a plating power source is provided between the cathode contact 88 and the anode 98. While applying a voltage from 114, a plating solution is injected from the plating solution injection unit 104 into a region between the substrate W and the porous structure 110 to fill the region with the plating solution, thereby the initial copper plating film 6 a. A copper plating film is grown on the surface.

なお、めっき液注入部１０４から基板Ｗと多孔質構造体１１０との間の領域にめっき液を注入して該領域をめっき液で満たし、短時間そのまま放置して、めっき液中の添加剤を初期銅めっき膜６ａに少量吸着させてから、カソード接点８８とアノード９８との間にめっき電源１１４から電圧を印加するようにしてもよい。
この後の工程は、前述と同様であるので、その説明を省略する。 In addition, the plating solution is injected from the plating solution injection unit 104 into the region between the substrate W and the porous structure 110 to fill the region with the plating solution, and left as it is for a short time to add the additive in the plating solution. A voltage may be applied from the plating power source 114 between the cathode contact 88 and the anode 98 after a small amount is adsorbed on the initial copper plating film 6a.
Since the subsequent steps are the same as described above, the description thereof is omitted.

シリコン基板上にＳｉＯ２を成膜し、その内部に溝状の配線パターン（配線幅０．１μｍ以上）を形成したのち、表面にバリア層としてのルテニウム膜を成膜した試料を用意した。銅めっき液として、半導体装置の配線工程での銅めっき膜の成膜に用いられる硫酸銅系のめっき液に、促進剤、抑制剤及び平滑化剤等の各添加剤を適量加えたものを用いた。アノードには酸化イリジウムで被覆した不溶解アノードを用いた。基板をめっき液に接触させてから電解めっきを開始するまでの時間を変化させたのち、同一条件でめっき液を電解し、トレンチの内部を含むルテニウム膜の表面に銅めっき膜を成長させた。試料の断面を走査型電子顕微鏡で観察し、図１８に示す、トレンチ内の銅めっき膜の膜厚ａ及び基板表面の銅めっき膜の膜厚ｂを測定した。これら銅めっき膜の膜厚ａ，ｂの値から穴埋めの選択比ａ／ｂを算出し、めっき液に基板を接触させてから電解開始までの時間との関係を調べた。図１８にめっき液に基板を接触させてから電解めっき開始までの時間（めっき開始遅れ時間）と穴埋めの選択比（ボトムアップ（ａ／ｂ））との関係を（▲）で示す。 A SiO 2 film was formed on a silicon substrate, a groove-like wiring pattern (wiring width of 0.1 μm or more) was formed therein, and then a sample was prepared in which a ruthenium film as a barrier layer was formed on the surface. As the copper plating solution, a copper sulfate plating solution used for the formation of a copper plating film in the wiring process of a semiconductor device is used by adding appropriate amounts of additives such as accelerators, inhibitors and smoothing agents. It was. An insoluble anode coated with iridium oxide was used as the anode. After changing the time from the contact of the substrate to the plating solution to the start of electrolytic plating, the plating solution was electrolyzed under the same conditions to grow a copper plating film on the surface of the ruthenium film including the inside of the trench. The cross section of the sample was observed with a scanning electron microscope, and the film thickness a of the copper plating film in the trench and the film thickness b of the copper plating film on the substrate surface shown in FIG. 18 were measured. The selection ratio a / b of hole filling was calculated from the values of the film thicknesses a and b of the copper plating films, and the relationship with the time from the start of electrolysis after contacting the substrate to the plating solution was examined. FIG. 18 shows the relationship between the time from contact of the substrate with the plating solution to the start of electroplating (plating start delay time) and the hole filling selectivity (bottom up (a / b)) by (（).

比較対象として、ＰＶＤによって銅シード層を成膜した後、銅シード層の表面に銅めっき膜を形成した時における、前記銅めっき膜の膜厚ａ，ｂの値から穴埋めの選択比ａ／ｂを算出し、めっき液に基板を接触させてから電解開始までの時間との関係を調べた結果を図１８に（○）で示す。これは、配線幅０．２μｍの配線パターンを有するシリコン基板の表面に銅シード層を形成した場合を示す。
このため、これら２つの基板は、配線の構造やアスペクト比が異なり、添加剤の種類やめっき後の膜厚も違っているため、単純な値の比較はできない。 As a comparison object, after forming a copper seed layer by PVD, when a copper plating film is formed on the surface of the copper seed layer, the selection ratio a / b of the hole filling from the values of the film thicknesses a and b of the copper plating film The result of examining the relationship between the time from the contact of the substrate with the plating solution to the start of electrolysis is shown in FIG. This shows a case where a copper seed layer is formed on the surface of a silicon substrate having a wiring pattern with a wiring width of 0.2 μm.
For this reason, these two substrates have different wiring structures and aspect ratios, and different types of additives and different film thicknesses after plating, so that simple values cannot be compared.

図１８から、銅シード層の表面に銅めっきを行った場合、めっき開始遅れ時間（switch on delay time）が長いほど、穴埋めの選択比（ボトムアップ（ａ／ｂ））が小さくなり、穴埋め性が劣化することがわかる。一方、ルテニウム膜の表面に直接銅めっきを行った場合は、めっき開始遅れ時間（switch on delay time）が長い方が穴埋めの選択比（ボトムアップ（ａ／ｂ））が大きくなり、穴埋め性が改善していることが判る。また、断面観察からも、めっき開始遅れ時間が長くなるにつれ、めっき初期に粒子状だっためっき膜が連続膜になることが判った。このことからルテニウム膜の表面に直接銅めっきを行う場合には、めっき液にルテニウム膜を接触させ、一定時間液中に静置してから電解めっきを開始した方が、トレンチ中に埋込まれる銅めっき膜中にボイドやシーム等が発生することを抑えて、配線の信頼性の面からも有利であることが判る。   From FIG. 18, when copper plating is performed on the surface of the copper seed layer, the longer the plating start delay time (switch on delay time), the smaller the filling ratio (bottom-up (a / b)), and the better the filling performance. It turns out that deteriorates. On the other hand, when copper plating is performed directly on the surface of the ruthenium film, the longer the plating start delay time (switch on delay time), the larger the filling ratio (bottom up (a / b)), and the better the filling ability. It turns out that it is improving. Also, from cross-sectional observation, it was found that as the plating start delay time becomes longer, the plated film that was particulate in the initial stage of plating becomes a continuous film. Therefore, when copper plating is performed directly on the surface of the ruthenium film, the one in which the ruthenium film is brought into contact with the plating solution and left in the solution for a certain period of time and then the electrolytic plating is started is buried in the trench. It can be seen that it is advantageous in terms of wiring reliability by suppressing the generation of voids and seams in the copper plating film.

配線深さ０．２５μmで、配線幅０．１μｍ、０．２μｍ及び０．２５μｍの配線パターンをそれぞれ有し、表面に膜厚３ｎｍのルテニウム膜をＣＶＤで成膜した基板を用意した。このルテニウム膜のシート抵抗は、約１５０Ω／ｓｑである。これらの各基板表面に、銅濃度５０ｇ／ｌ、硫酸濃度８０ｇ／ｌ、塩素濃度５０ｐｐｍの銅めっき液に、促進剤、抑制剤及び平滑化剤を添加しためっき液を用いて、電解量として５５ｎｍのめっき量に相当する銅めっきを行った。この時、基板をめっき液に浸漬させてからの電解めっきを開始するまでの時間（めっき開始遅れ時間）を０秒、１秒、２秒及び３秒にそれぞれ設定した。電流密度は５〜４０ｍＡ／ｃｍ２である。配線パターンとして、配線開口部の断面形状が丸まっているものを使用した（図２４及び図２５参照）。 A substrate having a wiring depth of 0.25 μm, wiring widths of 0.1 μm, 0.2 μm, and 0.25 μm and a ruthenium film having a thickness of 3 nm formed on the surface by CVD was prepared. The sheet resistance of this ruthenium film is about 150Ω / sq. On each of these substrates, a plating solution obtained by adding an accelerator, an inhibitor and a smoothing agent to a copper plating solution having a copper concentration of 50 g / l, a sulfuric acid concentration of 80 g / l, and a chlorine concentration of 50 ppm is used. Copper plating corresponding to the amount of plating was performed. At this time, the time (plating start delay time) from when the substrate was immersed in the plating solution until the start of electrolytic plating was set to 0 seconds, 1 second, 2 seconds and 3 seconds, respectively. The current density is 5-40 mA / cm 2 . As the wiring pattern, a wiring pattern having a rounded cross-sectional shape was used (see FIGS. 24 and 25).

図１９に、基板をめっき液に浸漬させてから電解めっきを開始するまでの時間（めっき開始遅れ時間）と前記図１７に示す穴埋め選択比（ボトムアップ（ａ／ｂ））の関係を示す。図１９から、特に配線幅が０．１μmの配線パターンでは、浸漬時間（めっき開始遅れ時間）を長くすると選択比（ボトムアップ（ａ／ｂ））が浸漬時間とともに大きくなることが顕著に現れる。これは、基板がめっき液に浸漬する時間を長くすると、添加剤の1成分である硫黄を含む促進剤が配線内のルテニウム膜の表面に時間とともに吸着され増加していくためと考えられる。   FIG. 19 shows the relationship between the time from when the substrate is immersed in the plating solution until the start of electrolytic plating (plating start delay time) and the hole filling selectivity (bottom up (a / b)) shown in FIG. From FIG. 19, it is noticeable that the selection ratio (bottom-up (a / b)) increases with the immersion time when the immersion time (plating start delay time) is increased, particularly in a wiring pattern with a wiring width of 0.1 μm. This is presumably because when the time during which the substrate is immersed in the plating solution is lengthened, the promoter containing sulfur, which is one component of the additive, is adsorbed and increased over time on the surface of the ruthenium film in the wiring.

図２０は、めっき開始遅れ時間を０秒とした時における各基板の銅めっきの析出状態をＳＥＭ観察した結果を示す。図２１は、めっき開始遅れ時間を１秒とした時における各基板の銅めっきの析出状態をＳＥＭ観察した結果を示す。図２２は、めっき開始遅れ時間を２秒とした時における各基板の銅めっきの析出状態をＳＥＭ観察した結果を示す。図２３は、めっき開始遅れ時間を３秒とした時における各基板の銅めっきの析出状態をＳＥＭ観察した結果を示す。   FIG. 20 shows the result of SEM observation of the deposition state of the copper plating on each substrate when the plating start delay time was 0 second. FIG. 21 shows the result of SEM observation of the deposition state of the copper plating on each substrate when the plating start delay time was 1 second. FIG. 22 shows the result of SEM observation of the copper plating deposition state of each substrate when the plating start delay time was 2 seconds. FIG. 23 shows the result of SEM observation of the deposition state of copper plating on each substrate when the plating start delay time was 3 seconds.

これらの図２０〜図２３から、浸漬時間（めっき開始遅れ時間）が長くなると結晶析出が密になることが判る。これも促進剤の吸着による影響と考えられ、また、結晶析出が密になると配線内のボイドが減少することが予想される。   From FIG. 20 to FIG. 23, it can be seen that the crystal precipitation becomes dense as the immersion time (plating start delay time) increases. This is also considered to be due to the adsorption of the accelerator, and voids in the wiring are expected to decrease as the crystal precipitation becomes dense.

配線深さ０．２５μｍで、配線幅０．０９μm及び０．１５μｍ配線パターンをそれぞれ有し、表面に膜厚３ｎｍのルテニウム膜をＣＶＤで形成した基板を用意した。このルテニウム膜のシート抵抗は、約１５０Ω／ｓｑである。これらの各基板表面に、銅濃度５０ｇ／ｌ、硫酸濃度８０ｇ／ｌ、塩素濃度５０ｐｐｍの銅めっき液に、促進剤、抑制剤及び平滑化剤を添加しためっき液を用いて、電解量として５５ｎｍのめっき量に相当する銅めっきを行った。この時、基板をめっき液に浸漬させてからの電解めっきを開始するまでの時間（めっき開始遅れ時間）を、０秒、３秒、５秒、７秒及び１分にそれぞれ設定した。電流密度は５〜４０ｍＡ／ｃｍ２である。 A substrate having a wiring depth of 0.25 μm, wiring widths of 0.09 μm and 0.15 μm, and a ruthenium film having a thickness of 3 nm formed on the surface by CVD was prepared. The sheet resistance of this ruthenium film is about 150Ω / sq. On each of these substrates, a plating solution obtained by adding an accelerator, an inhibitor and a smoothing agent to a copper plating solution having a copper concentration of 50 g / l, a sulfuric acid concentration of 80 g / l, and a chlorine concentration of 50 ppm is used. Copper plating corresponding to the amount of plating was performed. At this time, the time from the immersion of the substrate in the plating solution to the start of electrolytic plating (plating start delay time) was set to 0 seconds, 3 seconds, 5 seconds, 7 seconds, and 1 minute, respectively. The current density is 5-40 mA / cm 2 .

図２４に、配線幅が０．０９μｍの配線パターンにおける、基板をめっき液に浸漬させてから電解めっきを開始するまでの時間（めっき開始遅れ時間）と配線内のボイドとの関係を示す。図２５に、配線幅が０．１５μｍの配線パターンにおける基板をめっき液に浸漬させてから電解めっきを開始するまでの時間（めっき開始遅れ時間）と配線内のボイドとの関係を示す。   FIG. 24 shows the relationship between the time required to start electrolytic plating after the substrate is immersed in the plating solution (plating start delay time) and the voids in the wiring in the wiring pattern having a wiring width of 0.09 μm. FIG. 25 shows the relationship between the time required to start electrolytic plating after the substrate in the wiring pattern having a wiring width of 0.15 μm is immersed in the plating solution (plating start delay time) and the voids in the wiring.

図２４及び図２５は、絶縁膜（層間絶縁膜）２ｂの内部に形成した表面にルテニウム膜５ｃを形成し、トレンチ４ｂ内に配線となる銅めっき膜６ｂを埋込んだ状態を示している。   24 and 25 show a state in which a ruthenium film 5c is formed on the surface formed inside the insulating film (interlayer insulating film) 2b, and a copper plating film 6b serving as a wiring is buried in the trench 4b.

図２４から、配線幅０．０９μｍの配線パターンでは、浸漬時間（めっき開始遅れ時間）が０秒と１分のときに配線（銅めっき膜）内部にボイドＶの発生が見られた。これは、浸漬時間０秒のときは、添加剤の1成分である硫黄を含む促進剤が配線内のルテニウム膜の表面へ吸着される量が少なすぎるためと考えられる。また浸漬時間が１分のときは、添加剤の１つである抑制剤のルテニウム膜の表面への吸着量が増えめっきが付きにくくなって、配線内部にボイドが発生したものと予想される。これに対して、図２５から、配線幅０．１５μｍの配線パターンでは、いずれの浸漬時間でも、配線内部にボイドの発生は見られなかった。   From FIG. 24, in the wiring pattern with a wiring width of 0.09 μm, generation of voids V was observed inside the wiring (copper plating film) when the immersion time (plating start delay time) was 0 seconds and 1 minute. This is presumably because when the immersion time is 0 seconds, the amount of the sulfur-containing promoter that is one component of the additive is adsorbed on the surface of the ruthenium film in the wiring is too small. When the immersion time is 1 minute, the amount of adsorption of the inhibitor, which is one of the additives, on the surface of the ruthenium film is increased and plating is difficult to occur, and it is expected that voids are generated inside the wiring. On the other hand, from FIG. 25, in the wiring pattern with the wiring width of 0.15 μm, no void was observed in the wiring at any immersion time.

配線幅０．０８μｍ、配線深さ０．２２μmの配線パターンを有し、表面に膜厚２ｎｍのルテニウム膜をＣＶＤで成膜した基板を用意した。このルテニウム膜のシート抵抗は、約２５０Ω／ｓｑである。この基板表面に、銅濃度５０ｇ／ｌ、硫酸濃度８０ｇ／ｌ、塩素濃度５０ｐｐｍの銅めっき液に、促進剤、抑制剤及び平滑化剤を添加しためっき液を用い、電解量として４０ｎｍのめっき量に相当する銅めっきを行った。この時、基板をめっき液に浸漬させてからの電解めっきを開始するまでの時間（めっき開始遅れ時間）を０秒、２秒、５秒、１０秒及び２０秒にそれぞれ設定した。電流密度は５〜４０ｍＡ／ｃｍ２である。配線パターンとして、配線開口部の断面形状が比較的鋭角なものを使用した。 A substrate having a wiring pattern with a wiring width of 0.08 μm and a wiring depth of 0.22 μm and having a ruthenium film with a film thickness of 2 nm formed on the surface by CVD was prepared. The sheet resistance of this ruthenium film is about 250 Ω / sq. On this substrate surface, a plating solution in which an accelerator, an inhibitor and a smoothing agent are added to a copper plating solution having a copper concentration of 50 g / l, a sulfuric acid concentration of 80 g / l, and a chlorine concentration of 50 ppm. Copper plating corresponding to was performed. At this time, the time (plating start delay time) from when the substrate was immersed in the plating solution until the start of electrolytic plating was set to 0 second, 2 seconds, 5 seconds, 10 seconds, and 20 seconds, respectively. The current density is 5-40 mA / cm 2 . As the wiring pattern, a wiring opening having a relatively acute cross-sectional shape was used.

図２６に、基板をめっき液に浸漬させてから電解めっきを開始するまでの時間（めっき開始遅れ時間）と前記図１７に示す穴埋め選択比（ボトムアップ（ａ／ｂ））の関係を示す。穴埋め選択比（ボトムアップ（ａ／ｂ））は、配線幅、配線深さ、電解量により異なるため、同一実験条件での比較が必要となる。   FIG. 26 shows the relationship between the time from when the substrate is immersed in the plating solution until the start of electrolytic plating (plating start delay time) and the hole filling selection ratio (bottom up (a / b)) shown in FIG. Since the hole filling selection ratio (bottom-up (a / b)) varies depending on the wiring width, wiring depth, and amount of electrolysis, comparison under the same experimental conditions is necessary.

この図２６から、めっき開始遅れ時間が０秒から５秒の間で穴埋め選択比（ボトムアップ（ａ／ｂ））の値が大きく、めっき開始遅れ時間が１０秒以後は穴埋め選択比（ボトムアップ（ａ／ｂ））の値が小さくなり、めっき開始遅れ時間が２０秒程度で穴埋め選択比（ボトムアップ（ａ／ｂ））が飽和することが判る。穴埋め選択比（ボトムアップ（ａ／ｂ））の値は、埋込みのための指標となる。このため、この実施例で使用しためっき液に対しては、浸漬時間（めっき開始遅れ時間）を５秒以内とすることが好ましく、より良好な埋め込みをするためには、浸漬時間を２秒以内とすることが望ましいことが判る。これは、添加剤の１つである硫黄を含む促進剤（アクセレレータ）の吸着が、浸漬時間２〜５秒で飽和するのに対して、添加剤の1つである抑制剤（サプレッサー）の吸着は、浸漬時間２０秒で飽和するためである。   From FIG. 26, the value of the hole filling selection ratio (bottom up (a / b)) is large when the plating start delay time is between 0 seconds and 5 seconds, and the hole filling selection ratio (bottom up) after 10 seconds of the plating start delay time. It can be seen that the value of (a / b)) decreases, and the filling ratio (bottom up (a / b)) is saturated when the plating start delay time is about 20 seconds. The value of the hole filling selection ratio (bottom-up (a / b)) is an index for embedding. For this reason, the immersion time (plating start delay time) is preferably within 5 seconds for the plating solution used in this example, and the immersion time is within 2 seconds for better embedding. It turns out that it is desirable. This is because adsorption of an accelerator (accelerator) containing sulfur, which is one of the additives, saturates in an immersion time of 2 to 5 seconds, whereas adsorption of an inhibitor (suppressor), which is one of the additives. This is because it saturates at an immersion time of 20 seconds.

また、浸漬時間２〜５秒では、促進剤の吸着量の増加により、穴埋め選択比（ボトムアップ（ａ／ｂ））の値が大きくなることで、埋込み性が良いめっきとなるが、これに対して、浸漬時間２０秒では抑制剤吸着量の増加により配線内にコンフォーマルなめっきになることが判る。   In addition, when the immersion time is 2 to 5 seconds, the value of the hole filling selection ratio (bottom-up (a / b)) increases due to the increase in the adsorption amount of the accelerator, which results in plating with good embeddability. On the other hand, it can be seen that when the immersion time is 20 seconds, conformal plating is formed in the wiring due to an increase in the amount of adsorption of the inhibitor.

実施例４の結果を基に、コンフォーマルなめっき処理と埋込み性の良いめっき処理を組合せて行い、ボイドのないめっき処理ができるかどうかを確認した。先ず、配線幅０．０８μm、配線深さ０．２２μmの配線パターンを有し、表面に膜厚２ｎｍのルテニウム膜をＣＶＤで成膜した基板を用意した。このルテニウム膜のシート抵抗は、約２５０Ω／ｓｑである。この基板表面に、前記実施例４で使用しためっき液を使用し、浸漬時間（めっき開始待ち時間）を２０秒として、２５ｎｍのめっき量に相当する電解量（電流密度５〜４０ｍＡ／ｃｍ２）の電解めっき処理を行い、コンフォーマルに銅めっき膜を配線パターン内に形成し、その後、水洗・乾燥し（リンス６０秒、スピンドライ１５００ｒｐｍで３０秒）、めっき液を除去した。次に、上記同一のめっき液により、浸漬時間（めっき開始待ち時間）０秒で５００ｎｍ相当する電解量（電流密度５〜４０ｍＡ／ｃｍ２）の電解めっき処理を実施した。断面観察から埋込み性を確認したところ、ボイドのないことが確認された。 Based on the results of Example 4, a conformal plating process and a plating process with good embeddability were performed in combination, and it was confirmed whether or not a void-free plating process was possible. First, a substrate having a wiring pattern with a wiring width of 0.08 μm and a wiring depth of 0.22 μm and having a ruthenium film with a film thickness of 2 nm formed on the surface by CVD was prepared. The sheet resistance of this ruthenium film is about 250 Ω / sq. On this substrate surface, the plating solution used in Example 4 was used, the immersion time (plating start waiting time) was 20 seconds, and the amount of electrolysis corresponding to a plating amount of 25 nm (current density 5 to 40 mA / cm 2 ). The copper plating film was conformally formed in the wiring pattern, then washed with water and dried (rinse 60 seconds, spin dry at 1500 rpm for 30 seconds) to remove the plating solution. Next, with the same plating solution, an electrolytic plating treatment (current density of 5 to 40 mA / cm 2 ) corresponding to 500 nm was performed with an immersion time (plating start waiting time) of 0 second. When embeddability was confirmed by cross-sectional observation, it was confirmed that there was no void.

これまで本発明の実施の形態について説明したが、本発明は上述の実施の形態に限定されず、その技術的思想の範囲内において種々異なる形態にて実施されてよいことは言うまでもない。例えば、配線材料として銅を使用しているが、銅の代わりに銅合金を使用してもよい。   Although the embodiments of the present invention have been described so far, it is needless to say that the present invention is not limited to the above-described embodiments, and may be implemented in various forms within the scope of the technical idea. For example, although copper is used as the wiring material, a copper alloy may be used instead of copper.

従来のめっき処理によって銅配線を形成する例を工程順に示す図である。It is a figure which shows the example which forms a copper wiring by the conventional plating process in order of a process. 従来のめっき処理を示すフロー図である。It is a flowchart which shows the conventional plating process. 本発明の実施の形態の基板処理装置の全体を示す平面図である。It is a top view which shows the whole substrate processing apparatus of embodiment of this invention. 図３に示す電解めっき装置の平面図である。It is a top view of the electroplating apparatus shown in FIG. 図３に示す電解めっき装置の基板保持部及びカソード部の拡大断面図である。It is an expanded sectional view of the board | substrate holding | maintenance part and cathode part of the electroplating apparatus shown in FIG. 図３に示す電解めっき装置のめっき液回収アームを示す正面図である。FIG. 4 is a front view showing a plating solution recovery arm of the electrolytic plating apparatus shown in FIG. 3. 図３に示す電解めっき装置の基板保持部の平面図である。It is a top view of the board | substrate holding part of the electroplating apparatus shown in FIG. 図７のＢ−Ｂ線断面図である。It is the BB sectional view taken on the line of FIG. 図７のＣ−Ｃ線断面図である。It is CC sectional view taken on the line of FIG. 図３に示す電解めっき装置のカソード部の平面図である。It is a top view of the cathode part of the electrolytic plating apparatus shown in FIG. 図１０のＤ−Ｄ線断面図である。It is the DD sectional view taken on the line of FIG. 図３に示す電解めっき装置の電極アーム部の平面図である。It is a top view of the electrode arm part of the electroplating apparatus shown in FIG. 図３に示す電解めっき装置の電極ヘッド及び基板保持部で保持した基板を概略的に示す電解めっき時における断面図である。It is sectional drawing at the time of the electroplating which shows schematically the board | substrate hold | maintained with the electrode head and board | substrate holding part of the electroplating apparatus shown in FIG. 本発明の基板処理方法（めっき方法）によって銅配線を形成する例を工程順に示す図である。It is a figure which shows the example which forms a copper wiring with the board | substrate processing method (plating method) of this invention in order of a process. 本発明の基板処理方法（めっき方法）を示すフロー図である。It is a flowchart which shows the substrate processing method (plating method) of this invention. 本発明の基板処理方法（めっき方法）めっき処理における電解めっき開始までの制御フロー図である。It is a control flow figure until the start of the electroplating in the board | substrate processing method (plating method) plating process of this invention. 本発明の他の基板処理方法（めっき方法）によって銅配線を形成する例を工程順に示す図である。It is a figure which shows the example which forms a copper wiring with the other board | substrate processing method (plating method) of this invention in process order. 実施例１におけるボトムアップとめっき開始遅れ時間との関係を比較対象とともに示すグラフである。It is a graph which shows the relationship between the bottom up in Example 1, and plating start delay time with a comparison object. 実施例２におけるボトムアップとめっき開始遅れ時間との関係を示すグラフである。6 is a graph showing the relationship between bottom-up and plating start delay time in Example 2. 実施例２におけるめっき開始遅れ時間を０秒とした時における各基板の銅めっきの析出状態のＳＥＭ観察した結果を示す図である。It is a figure which shows the result of having observed SEM of the precipitation state of the copper plating of each board | substrate when the plating start delay time in Example 2 was set to 0 second. 実施例２におけるめっき開始遅れ時間を１秒とした時における各基板の銅めっきの析出状態のＳＥＭ観察した結果を示す図である。It is a figure which shows the result of having observed SEM of the precipitation state of the copper plating of each board | substrate when the plating start delay time in Example 2 was 1 second. 実施例２におけるめっき開始遅れ時間を２秒とした時における各基板の銅めっきの析出状態のＳＥＭ観察した結果を示す図である。It is a figure which shows the result of having observed SEM of the precipitation state of the copper plating of each board | substrate when the plating start delay time in Example 2 was 2 second. 実施例２におけるめっき開始遅れ時間を３秒とした時における各基板の銅めっきの析出状態のＳＥＭ観察した結果を示す図である。It is a figure which shows the result of having observed SEM of the precipitation state of the copper plating of each board | substrate when the plating start delay time in Example 2 was 3 second. 実施例３の配線幅が０．０９μｍの配線パターンにおける、めっき開始遅れ時間と配線内のボイドとの関係を示す図である。It is a figure which shows the relationship between the plating start delay time and the void in a wiring in the wiring pattern whose wiring width of Example 3 is 0.09 micrometer. 実施例３の配線幅が０．１５μｍの配線パターンにおける、めっき開始遅れ時間と配線内のボイドとの関係を示す図である。It is a figure which shows the relationship between the metal-plating start delay time and the void in a wiring in the wiring pattern whose wiring width of Example 3 is 0.15 micrometer. 実施例４におけるボトムアップとめっき開始遅れ時間との関係を示すグラフである。It is a graph which shows the relationship between the bottom up and the plating start delay time in Example 4.

符号の説明Explanation of symbols

５ａ，５ｂ，５ｃ ルテニウム膜（バリア層）
６，６ｂ 銅めっき膜
６ａ 初期銅めっき膜
１０ ロード・アンロード部
１２ 電解めっき装置
２０ 基板処理部
２６ 揺動アーム
２８ 電極ヘッド
３６ 基板保持部
３８ カソード部
６８ 基板ステージ
７０ 支持腕
８８ カソード接点
９０ シール材
９４ ハウジング
９８ アノード
１００ めっき液室
１０２ めっき液供給管
１０３ めっき液排出口
１０４ めっき液注入部
１０６ めっき液排出管
１１０ 多孔質構造体
１１２ シールドリング
１１４ 電源
１２０ 接液検出器（計測部） 5a, 5b, 5c Ruthenium film (barrier layer)
6, 6b Copper plating film 6a Initial copper plating film 10 Load / unload unit 12 Electrolytic plating apparatus 20 Substrate processing unit 26 Swing arm 28 Electrode head 36 Substrate holding unit 38 Cathode unit 68 Substrate stage 70 Support arm 88 Cathode contact 90 Seal Material 94 Housing 98 Anode 100 Plating solution chamber 102 Plating solution supply pipe 103 Plating solution discharge port 104 Plating solution injection part 106 Plating solution discharge pipe 110 Porous structure 112 Shield ring 114 Power supply 120 Liquid contact detector (measurement part)

Claims (12)

配線用凹部の表面を含む全表面にルテニウム膜を形成した基板を用意し、
前記基板表面をめっき液に所定時間接触させてめっき液中の添加剤をルテニウム膜に吸着させ、しかる後、
電解めっきによりルテニウム膜の表面に導電膜を成膜すること特徴とする基板処理方法。 Prepare a substrate with a ruthenium film formed on the entire surface including the surface of the wiring recess,
The substrate surface is brought into contact with the plating solution for a predetermined time to adsorb the additive in the plating solution to the ruthenium film, and then
A substrate processing method comprising forming a conductive film on a surface of a ruthenium film by electrolytic plating. 前記導電膜は、銅または銅合金からなることを特徴とする請求項１記載の基板処理方法。   The substrate processing method according to claim 1, wherein the conductive film is made of copper or a copper alloy. 前記めっき液は、銅イオン、硫酸イオン及び添加剤を含むことを特徴とする請求項２記載の基板処理方法。   The substrate processing method according to claim 2, wherein the plating solution contains copper ions, sulfate ions, and additives. 電解めっきに先立って、基板表面をめっき液に接触させる時間は、０．５秒以上、６０秒以下であることを特徴とする請求項１乃至３のいずれか一項に記載の基板処理方法。   4. The substrate processing method according to claim 1, wherein the time for contacting the substrate surface with the plating solution is 0.5 seconds or more and 60 seconds or less prior to the electrolytic plating. 5. 電解めっきに先立って、基板表面をめっき液に接触させる時間は、０．１秒以上、２０秒以下であることを特徴とする請求項１乃至３のいずれか一項に記載の基板処理方法。   The substrate processing method according to any one of claims 1 to 3, wherein the time for contacting the substrate surface with the plating solution prior to the electrolytic plating is 0.1 second or more and 20 seconds or less. 電解めっきに先立って、基板表面をめっき液に接触させる時間は、０．１秒以上、５秒以下であることを特徴とする請求項1乃至３のいずれか一項に記載の基板処理方法。   4. The substrate processing method according to claim 1, wherein the time for contacting the substrate surface with the plating solution prior to the electrolytic plating is 0.1 second or more and 5 seconds or less. 5. 配線用凹部の表面を含む全表面にルテニウム膜を形成した基板を用意し、
前記基板表面をめっき液に所定時間接触させてめっき液中の添加剤をルテニウム膜に吸着させた後、第１電解めっきによってルテニウム膜の表面に前記配線用凹部の全表面を覆う初期導電膜を成膜し、
基板表面を洗浄し乾燥させ、しかる後、
第２電解めっきによって前記初期導電膜の表面に導電膜を更に成長させることを特徴とする基板処理方法。 Prepare a substrate with a ruthenium film formed on the entire surface including the surface of the wiring recess,
After the substrate surface is brought into contact with the plating solution for a predetermined time to adsorb the additive in the plating solution to the ruthenium film, an initial conductive film covering the entire surface of the concave portion for wiring is formed on the surface of the ruthenium film by first electrolytic plating. Deposit,
Clean and dry the substrate surface, then
A substrate processing method, wherein a conductive film is further grown on the surface of the initial conductive film by second electrolytic plating. 前記第１めっき処理と前記第２めっき処理を、同一めっき液を使用して行うことを特徴とする請求項７記載の基板処理方法。   The substrate processing method according to claim 7, wherein the first plating process and the second plating process are performed using the same plating solution. 前記第１電解めっきに先立って、基板表面にめっき液を浸漬させる時間は、５秒以上であることを特徴とする請求項７または８記載の基板処理方法。   9. The substrate processing method according to claim 7, wherein the time for immersing the plating solution on the surface of the substrate prior to the first electrolytic plating is 5 seconds or more. 配線用凹部の表面を含む全表面にルテニウム膜を形成した基板表面に電解めっきにより導電膜を成膜する基板処理装置であって、
基板表面がめっき液に接触してからの経過時間を計測する計測部を有することを特徴とする基板処置装置。 A substrate processing apparatus for forming a conductive film by electrolytic plating on a substrate surface on which a ruthenium film is formed on the entire surface including the surface of a recess for wiring,
A substrate treatment apparatus comprising a measuring unit that measures an elapsed time after the substrate surface contacts the plating solution. 前記計測部は、基板または基板ホルダの位置を検出する位置検出器、または基板とめっき液の接触を検知する接液検出器からなることを特徴とする請求項１０記載の基板処理装置。   The substrate processing apparatus according to claim 10, wherein the measurement unit includes a position detector that detects the position of the substrate or the substrate holder, or a liquid contact detector that detects contact between the substrate and the plating solution. 前記接液検出器は、光センサ、圧力センサ、導電率センサ、温度センサまたは超音波センサ、またはこれらの組合せからなることを特徴とする請求項１１記載の基板処理装置。   The substrate processing apparatus according to claim 11, wherein the liquid contact detector includes an optical sensor, a pressure sensor, a conductivity sensor, a temperature sensor, an ultrasonic sensor, or a combination thereof.
JP2008170222A 2007-07-02 2008-06-30 Method and apparatus for treating substrate Pending JP2009030167A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008170222A JP2009030167A (en) 2007-07-02 2008-06-30 Method and apparatus for treating substrate
US12/216,224 US20090020434A1 (en) 2007-07-02 2008-07-01 Substrate processing method and substrate processing apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007173940 2007-07-02
JP2008170222A JP2009030167A (en) 2007-07-02 2008-06-30 Method and apparatus for treating substrate

Publications (1)

Publication Number Publication Date
JP2009030167A true JP2009030167A (en) 2009-02-12

Family

ID=40400978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008170222A Pending JP2009030167A (en) 2007-07-02 2008-06-30 Method and apparatus for treating substrate

Country Status (1)

Country Link
JP (1) JP2009030167A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016092101A (en) * 2014-10-31 2016-05-23 富士フイルム株式会社 Substrate processing method and semiconductor element manufacturing method
KR20160108784A (en) * 2015-03-06 2016-09-20 에스케이하이닉스 주식회사 Method for forming diffusion barrier film, metal line comprising said diffusion barrier film in semiconductor device and method for manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000345392A (en) * 1999-01-26 2000-12-12 Ebara Corp Copper plating method and device therefor
WO2005008759A1 (en) * 2003-07-08 2005-01-27 Applied Materials, Inc. Multiple-step electrodeposition process for direct copper plating on barrier metals
WO2005123988A1 (en) * 2004-06-10 2005-12-29 Applied Materials, Inc. Method of barrier layer surface treatment to enable direct copper plating on barrier metal
JP2006274369A (en) * 2005-03-29 2006-10-12 Ebara Corp Method and apparatus for forming substrate wiring, and plating suppressing substance transfer stamp
WO2007034117A2 (en) * 2005-09-20 2007-03-29 Alchimer Electroplating method for coating a substrate surface with a metal

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000345392A (en) * 1999-01-26 2000-12-12 Ebara Corp Copper plating method and device therefor
WO2005008759A1 (en) * 2003-07-08 2005-01-27 Applied Materials, Inc. Multiple-step electrodeposition process for direct copper plating on barrier metals
WO2005123988A1 (en) * 2004-06-10 2005-12-29 Applied Materials, Inc. Method of barrier layer surface treatment to enable direct copper plating on barrier metal
JP2006274369A (en) * 2005-03-29 2006-10-12 Ebara Corp Method and apparatus for forming substrate wiring, and plating suppressing substance transfer stamp
WO2007034117A2 (en) * 2005-09-20 2007-03-29 Alchimer Electroplating method for coating a substrate surface with a metal

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016092101A (en) * 2014-10-31 2016-05-23 富士フイルム株式会社 Substrate processing method and semiconductor element manufacturing method
KR20160108784A (en) * 2015-03-06 2016-09-20 에스케이하이닉스 주식회사 Method for forming diffusion barrier film, metal line comprising said diffusion barrier film in semiconductor device and method for manufacturing the same
KR102279757B1 (en) * 2015-03-06 2021-07-21 에스케이하이닉스 주식회사 Method for forming diffusion barrier film, metal line comprising said diffusion barrier film in semiconductor device and method for manufacturing the same

Similar Documents

Publication Publication Date Title
US20040149584A1 (en) Plating method
KR100845566B1 (en) Plating apparatus and method of managing plating liquid composition
US20020020627A1 (en) Plating apparatus and plating method for substrate
KR20040030428A (en) Plating device and method
US20090020434A1 (en) Substrate processing method and substrate processing apparatus
WO2007112768A1 (en) Process for filling recessed features in a dielectric substrate
US20070158202A1 (en) Plating apparatus and method for controlling plating solution
JP2008098449A (en) Substrate processing apparatus and substrate processing method
JP2004083932A (en) Electrolytic treatment apparatus
US7901550B2 (en) Plating apparatus
JP2004218080A (en) Plating method
JP2007149824A (en) Film forming method and film forming device
WO2002099164A2 (en) Electroless-plating solution and semiconductor device
JP4423359B2 (en) Plating method
JP2009030167A (en) Method and apparatus for treating substrate
JP2010007153A (en) Plating apparatus and plating method
US20040248405A1 (en) Method of and apparatus for manufacturing semiconductor device
JP3741682B2 (en) Plating method, plating apparatus, and electronic device manufacturing method
JP3907432B2 (en) Electrolytic solution for electropolishing and electropolishing method
JP2002343797A (en) Wiring forming device and method therefor
US20080132062A1 (en) Method of manufacturing semiconductor device
JP2003306793A (en) Plating apparatus and plating method
US7256120B2 (en) Method to eliminate plating copper defect
JP2007254882A (en) Electroplating device and electroplating method
JP4503401B2 (en) Method for forming metal film and method for forming wiring

Legal Events

Date Code Title Description
A621 Written request for application examination

Effective date: 20100914

Free format text: JAPANESE INTERMEDIATE CODE: A621

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120528

A131 Notification of reasons for refusal

Effective date: 20120619

Free format text: JAPANESE INTERMEDIATE CODE: A131

A02 Decision of refusal

Effective date: 20121106

Free format text: JAPANESE INTERMEDIATE CODE: A02