JP2009027295A - Signal discriminating circuit and optical signal reception discriminating circuit - Google Patents

Signal discriminating circuit and optical signal reception discriminating circuit Download PDF

Info

Publication number
JP2009027295A
JP2009027295A JP2007186487A JP2007186487A JP2009027295A JP 2009027295 A JP2009027295 A JP 2009027295A JP 2007186487 A JP2007186487 A JP 2007186487A JP 2007186487 A JP2007186487 A JP 2007186487A JP 2009027295 A JP2009027295 A JP 2009027295A
Authority
JP
Japan
Prior art keywords
circuit
bit rate
signal
integer
optical signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007186487A
Other languages
Japanese (ja)
Other versions
JP4849635B2 (en
Inventor
Kazutaka Hara
一貴 原
Shunji Kimura
俊二 木村
Kenichi Suzuki
謙一 鈴木
Takashi Yamada
崇史 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP2007186487A priority Critical patent/JP4849635B2/en
Publication of JP2009027295A publication Critical patent/JP2009027295A/en
Application granted granted Critical
Publication of JP4849635B2 publication Critical patent/JP4849635B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)
  • Optical Communication System (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal discriminating circuit capable of suppressing interference between and among a plurality of oscillation circuits causing a problem when one clock data reproducing circuit has the oscillation circuit, and eliminating the necessity of a function of handling a plurality of bit rates not in the relation of a multiple of an integer or a fraction of an integer in a post-stage circuit or device. <P>SOLUTION: The signal discriminating circuit discriminates and identifies signals obtained by time-division multiplexing a plurality bit rate signals all or one part of which are not in the relation of a multiple of an integer or a fraction of an integer, and reproduces the signals. The circuit has corresponding clock data reproducing circuits 5, 6 and 7 per bit rate group or per bit rate in the relation of a multiple of an integer or a fraction of an integer, wherein the time-division multiplexed signals are distributed to all the clock data reproducing circuits 5, 6 and 7, gate circuits 11, 12 and 13 are provided to input terminals of the clock data reproducing circuits 5, 6 and 7, and the opening/closing of the gate circuits 11, 12 and 13 are controlled by a bit rate control signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、複数のビットレートの信号が時分割多重されている信号を取り扱う際に、複数のビットレートの全てもしくは一部が互いに整数倍もしくは整数分の１の関係にない場合に、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、信号を瞬時に弁別する信号弁別回路、およびこれを利用して光信号を弁別して受信する光信号受信弁別回路に関するものである。   When dealing with a signal in which signals of a plurality of bit rates are time-division multiplexed, the present invention provides an integer multiple when all or some of the plurality of bit rates are not in an integer multiple or a fraction of an integer. Alternatively, the present invention relates to a signal discriminating circuit that instantaneously discriminates a signal for each bit rate group or bit rate that has a 1 / integer relationship, and an optical signal reception discriminating circuit that discriminates and receives an optical signal using the signal discriminating circuit. is there.

データ伝送サービスを利用するユーザの要望は時代とともに多様化の一途をたどっており、複数のビットレートのサービスが提供されている。一般に信号を受信する受信回路は、特定のビットレートの信号のみを受信するように設計されているが、設備投資の削減効果を狙って、複数のビットレートの信号を受信可能なマルチレート受信器に対するニーズが顕在化している。   The demands of users who use data transmission services are diversifying with the times, and services with a plurality of bit rates are provided. In general, a receiving circuit that receives a signal is designed to receive only a signal of a specific bit rate, but a multi-rate receiver that can receive a signal of a plurality of bit rates with the aim of reducing capital investment. The need for

これまで、信号のビットレートが時間とともに切り替わる（時分割多重されている）システムを実現するには、主に複数のビットレートの信号を瞬時に切り換え受信可能なバースト受信器を用いて構成する手法が提案されてきた。これは、通常の連続信号用受信器のように、ビットレートの切り換えに対する応答性能が比較的遅い受信装置を用いると、ビットレートが切り換わるたびに受信器の状態が比較的長い時間をかけて変化するため、その間は信号の受信ができなくなり、伝送効率が著しく劣化してしまうからである。   Until now, in order to realize a system in which the bit rate of a signal is switched over time (time-division multiplexed), a method of mainly using a burst receiver capable of instantaneously switching and receiving signals of a plurality of bit rates. Has been proposed. This is because when a receiver that has a relatively slow response performance to bit rate switching is used like a normal continuous signal receiver, the receiver state takes a relatively long time each time the bit rate is switched. This is because the signal cannot be received during that time, and the transmission efficiency is significantly deteriorated.

例えば、特許文献１や特許文献２などでは、データの速度を瞬時に判定し、受信器のクロックを切り替えて受信するシステムが提案されている。これらのシステムに共通して言えることは、取り扱うことのできる複数のビットレートは、各々整数倍もしくは整数分の１の関係にあるものに限られるということである。   For example, Patent Document 1 and Patent Document 2 propose a system for instantaneously determining the data speed and switching the clock of the receiver for reception. What can be said in common in these systems is that the bit rates that can be handled are limited to those having an integer multiple or a fraction of an integer each.

ビットレートの切り換えに対して、受光感度を切り換える必要がない場合には、クロック信号をビットレートに対して瞬時に切り換える機能をクロック再生回路が有していれば良いが、一般に、ＰＬＬを基本とする周波数同期回路は応答性能が遅く、かつ周波数可変範囲が狭いため、逓倍回路や分周回路（特許文献１の１／２分周回路３０８、特許文献２の分周回路４２３）などのクロック周波数を整数倍か整数分の１（厳密には２のべき乗倍もしくは２のべき乗分の１）に変換させる回路を用いる。このため、受信可能なビットレートは発振器の発振周波数の整数倍か整数分の１に限定される。
特開２００２−０５１０３３号公報 特開平８−００８９５４号公報 When it is not necessary to switch the light receiving sensitivity for switching the bit rate, the clock recovery circuit may have a function of instantaneously switching the clock signal with respect to the bit rate. Since the frequency synchronization circuit to be used has a slow response performance and a narrow frequency variable range, a clock frequency of a multiplier circuit, a frequency divider circuit (1/2 frequency divider circuit 308 of Patent Document 1, and frequency divider circuit 423 of Patent Document 2), etc. Is converted into an integer multiple or a fraction of an integer (strictly, a power of 2 or 1 of a power of 2). For this reason, the receivable bit rate is limited to an integer multiple or a fraction of an integer of the oscillation frequency of the oscillator.
JP 2002-051033 A JP-A-8-008954

上記に述べたように、従来技術では、複数のビットレートを扱う場合に、ビットレート間に整数倍もしくは整数分の１の関係が成立しなければ救うことができない。整数倍もしくは整数分の１の関係に無い複数のビットレートを扱う場合、クロック・データ再生回路内部のクロック再生回路をビットレート毎に設けて、入力される信号のビットレートに対応して瞬時に切り換える機能が必要になるが、一般に発振回路を有するクロック再生回路を複数設けた場合、電磁界的な結合による発振回路間の干渉などが生じるため、発振回路間の遮蔽が必要になるなどの課題があった。   As described above, according to the conventional technique, when a plurality of bit rates are handled, it cannot be saved unless an integer multiple or a fraction of an integer is established between the bit rates. When handling multiple bit rates that are not an integer multiple or a fraction of an integer, a clock recovery circuit inside the clock / data recovery circuit is provided for each bit rate, and instantaneously corresponding to the bit rate of the input signal A switching function is required, but in general, when multiple clock recovery circuits having an oscillation circuit are provided, interference between the oscillation circuits may occur due to electromagnetic coupling, which may require shielding between the oscillation circuits. was there.

さらに、特許文献１や特許文歓２の受信装置は、異なるビットレートの受信信号を同一の出力端子から出力する構成となっている。このため、仮に受信器が整数倍もしくは整数分の１の関係にないビットレートを受信できたとしても、受信器の後段に接続される回路および装置も同様に、整数倍もしくは整数分の１の関係にない複数のビットレートに対応可能でなければならないという課題がある。   Further, the receiving devices of Patent Document 1 and Patent Literature 2 are configured to output received signals of different bit rates from the same output terminal. For this reason, even if the receiver can receive a bit rate that is not an integer multiple or a fraction of an integer, the circuit and device connected to the subsequent stage of the receiver are also an integer multiple or a fraction of an integer. There is a problem that it is necessary to be able to cope with a plurality of unrelated bit rates.

本発明の目的は、１つのクロック・データ再生回路が複数の発振回路を有する場合に問題となる発振回路間の干渉を抑えることができ、また、後段の回路及び装置には整数倍もしくは整数分の１の関係にない複数のビットレートを取り扱う機能を必要としない、信号弁別回路および光信号受信弁別回路を提供することである。   It is an object of the present invention to suppress interference between oscillation circuits, which is a problem when one clock / data recovery circuit has a plurality of oscillation circuits. It is an object of the present invention to provide a signal discriminating circuit and an optical signal receiving discriminating circuit that do not require a function for handling a plurality of bit rates that are not related to one of the above.

上記目的を達成するために、請求項１にかかる発明の信号弁別回路は、全てもしくは一部が互いに整数倍もしくは整数分の１の関係にない複数のビットレートの信号を時分割多重した信号を弁別して識別再生する信号弁別回路であって、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、対応したクロック・データ再生回路を有し、前記時分割多重された信号を全てのクロック・データ再生回路に分配し、該クロック・データ再生回路の入力端子部もしくは内部にゲート回路を設け、該ゲート回路の開閉をビットレート制御信号で制御することで、前記時分割多重された信号を、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、弁別して出力することを特徴とする。
請求項２にかかる発明の信号弁別回路は、全てもしくは一部が互いに整数倍もしくは整数分の１の関係にない複数のビットレートの信号を時分割多重した信号を弁別して識別再生する信号弁別回路であって、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、対応したクロック・データ再生回路を有し、１つの信号入力端子と全ての前記クロック・データ再生回路の入力端子の間に方路切換回路を接続し、該方路切換回路をビットレート制御信号により制御することで、前記時分割多重された信号を、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、弁別して出力することを特徴とする。
請求項３にかかる発明の光信号受信弁別回路は、複数のビットレートの信号を時分割多重した光信号を、光電気変換素子を用いて電流信号に変換し、該電流信号をインピータンス変換増幅回路で電圧信号に変換増幅し、後置増幅回路を用いて一定振幅の電圧信号に増幅した後に、クロック・データ再生回路で識別再生する光信号受信弁別回路であって、
該クロック・データ再生回路の代わりに、請求項１もしくは請求項２に記載の信号弁別回路を具備し、前記時分割多重された光信号を電圧信号に変換し、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、弁別して出力することを特徴とする。
請求項４にかかる発明は、請求項３に記載の光信号受信弁別回路において、前記インピーダンス変換増幅回路として並列帰還並列注入型増幅回路を用い、該並列帰還並列注入型増幅回路の並列帰還抵抗の抵抗値を前記ビットレート制御信号により制御可能な可変抵抗とすることを特徴とする。
請求項５にかかる発明は、請求項３に記載の光信号受信弁別回路において、前記インピーダンス変換増幅回路の出力端子と前記後置増幅回路の入力端子の間に、ビットレート制御信号により帯域を制御可能な帯域可変低域通過フィルタ回路を挿入したことを特徴とする。
請求項６にかかる発明の光信号受信弁別回路は、全てもしくは一部が互いに整数倍もしくは整数分の１の関係にない複数のビットレートの信号を時分割多重した光信号を、光電気変換素子を用いて電流信号に変換し、該電流信号をインピーダンス変換増幅回路で電圧信号に変換増幅し、後置増幅回路を用いて一定振幅の電圧信号に増幅した後に、クロック・データ再生回路で識別再生する光信号受信弁別回路であって、前記後置増幅回路として、前記整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、対応した複数の後置増幅回路を有し、前記インピーダンス変換増幅回路の出力信号を全ての前記後置増幅回路に分配し、前記複数の後置増幅回路の出力信号を各々対応したクロック・データ再生回路で識別再生するとともに、前記整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、前記後置増幅回路の入力端子部もしくは内部、もしくは前記クロック・データ再生回路の入力端子部もしくは内部にゲート回路を設け、該ゲート回路の開閉をビットレート制御信号で制御することで、前記時分割多重された光信号を電圧信号に変換し、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、弁別して出力することを特徴とする。
請求項７にかかる発明の光信号受信弁別回路は、全てもしくは一部が互いに整数倍もしくは整数分の１の関係にない複数のビットレートの信号を時分割多重した光信号を、光電気変換素子を用いて電流信号に変換し、該電流信号をインピーダンス変換増幅回路で電圧信号に変換増幅し、後置増幅回路を用いて一定振幅の電圧信号に増幅した後に、クロック・データ再生回路で識別再生する光信号受信弁別回路であって、前記整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、対応した複数の後置増幅回路を有し、前記インピーダンス変換増幅回路の出力端子と全ての前記後置増幅回路の入力端子の間に方路切換回路を接続し、前記複数の後置増幅回路の出力信号を各々対応したクロック・データ再生回路で識別再生するともに、ビットレート制御信号により前記方路切換回路を制御することで、前記時分割多重された光信号を電圧信号に変換し、整数倍もしくは整数分の１の関係にあるヒットレート群毎もしくはビットレート毎に、弁別して出力することを特徴とする。
請求項８にかかる発明は、請求項６に記載の光信号受信弁別回路において、前記インピーダンス変換増幅回路の出力端子と前記複数の後置増幅回路の内の少なくとも１つの後置増幅回路の入力端子との間に、低域通過フィルタ回路もしくはビットレート制御信号により帯域を制御可能な帯域可変低域通過フィルタ回路を挿入したことを特徴とする。
請求項９にかかる発明は、請求項７に記載の光信号受信弁別回路において、前記方路切換回路の出力端子と前記複数の後置増幅回路の内の少なくとも１つの後置増幅回路の入力端子との間に、低域通過フィルタ回路もしくはビットレート制御信号により帯域を制御可能な帯域可変低域通過フィルタ回路を挿入したことを特徴とする。 In order to achieve the above object, the signal discrimination circuit according to the first aspect of the present invention provides a signal obtained by time-division-multiplexing a plurality of bit rate signals, all or part of which are not in an integer multiple or a fraction of an integer. A signal discriminating circuit for discriminating and recognizing and having a clock / data recovery circuit corresponding to each bit rate group or each bit rate having an integer multiple or a fraction of an integer, and said time division multiplexed The signal is distributed to all the clock and data recovery circuits, and a gate circuit is provided in or inside the clock and data recovery circuit, and the opening and closing of the gate circuit is controlled by a bit rate control signal. The multiplexed signals are distinguished and output for each bit rate group or each bit rate having an integer multiple or a fraction of an integer.
The signal discriminating circuit of the invention according to claim 2 is a signal discriminating circuit for discriminating and regenerating a signal obtained by time-division-multiplexing a plurality of bit rate signals, all or part of which are not integral multiples or a fraction of an integer. A clock / data recovery circuit corresponding to each bit rate group or each bit rate having an integer multiple or a fraction of an integer, and one signal input terminal and all the clock / data recovery circuits By connecting a route switching circuit between the input terminals of the, and controlling the route switching circuit with a bit rate control signal, the time-division multiplexed signal has an integer multiple or a fraction of an integer relationship. Discriminating and outputting for each bit rate group or for each bit rate.
An optical signal reception discriminating circuit according to a third aspect of the present invention converts an optical signal obtained by time-division multiplexing a plurality of bit rate signals into a current signal using a photoelectric conversion element, and the current signal is amplified by impedance conversion amplification. An optical signal reception discriminating circuit that performs conversion amplification into a voltage signal by a circuit, amplifies it to a voltage signal having a constant amplitude using a post-amplifier circuit, and discriminates and reproduces it by a clock data reproduction circuit,
A signal discriminating circuit according to claim 1 or 2 is provided instead of the clock and data recovery circuit, and the time-division multiplexed optical signal is converted into a voltage signal. It is characterized by discriminating and outputting each bit rate group or bit rate concerned.
According to a fourth aspect of the present invention, in the optical signal receiving discrimination circuit according to the third aspect, a parallel feedback parallel injection type amplifier circuit is used as the impedance conversion amplifier circuit, and the parallel feedback resistance of the parallel feedback parallel injection type amplifier circuit is reduced. The resistance value is a variable resistance that can be controlled by the bit rate control signal.
According to a fifth aspect of the present invention, in the optical signal receiving discrimination circuit according to the third aspect, a band is controlled by a bit rate control signal between the output terminal of the impedance conversion amplifier circuit and the input terminal of the post-amplifier circuit. A possible band variable low-pass filter circuit is inserted.
An optical signal receiving and discriminating circuit according to a sixth aspect of the present invention provides an optical / electrical conversion element for optical signals obtained by time-division-multiplexing a plurality of bit rate signals, all or a part of which are not integral multiples or a fraction of an integer. The current signal is converted into a voltage signal by an impedance conversion amplifier circuit, amplified to a voltage signal having a constant amplitude by a post-amplifier circuit, and then identified and reproduced by a clock / data recovery circuit. An optical signal reception discriminating circuit having a plurality of post-amplifier circuits corresponding to each bit rate group or each bit rate having a relation of an integral multiple or a fraction of an integer as the post-amplifier circuit The output signal of the impedance conversion amplifier circuit is distributed to all the post-amplifier circuits, and the output signals of the plurality of post-amplifier circuits are identified by the corresponding clock / data recovery circuits. For each bit rate group or bit rate that is in an integral multiple or a fraction of an integer, or an input terminal portion or an internal portion of the post-amplifier circuit, or an input terminal portion of the clock / data recovery circuit, or A gate circuit is provided inside, and the opening and closing of the gate circuit is controlled by a bit rate control signal, thereby converting the time-division multiplexed optical signal into a voltage signal, and a bit having an integer multiple or a fraction of an integer relationship. Discriminating and outputting for each rate group or bit rate.
An optical signal receiving and discriminating circuit according to a seventh aspect of the present invention provides an optical / electrical conversion element comprising an optical signal obtained by time-division-multiplexing a plurality of bit rate signals, all or part of which are not integral multiples or a fraction of an integer. The current signal is converted into a voltage signal by an impedance conversion amplifier circuit, amplified to a voltage signal having a constant amplitude by a post-amplifier circuit, and then identified and reproduced by a clock / data recovery circuit. An optical signal reception discriminating circuit having a plurality of post-amplifier circuits corresponding to each bit rate group or each bit rate having a relation of an integral multiple or a fraction of an integer. A path switching circuit is connected between the output terminal and the input terminals of all the post-amplifier circuits, and the output signals of the plurality of post-amplifier circuits are respectively associated with clock / data recovery circuits. In addition to reproducing separately, the route switching circuit is controlled by a bit rate control signal to convert the time-division multiplexed optical signal into a voltage signal, and a hit rate group having an integer multiple or a fraction of an integer relationship It is characterized in that the output is discriminated at every bit rate or every bit rate.
The invention according to claim 8 is the optical signal reception discriminating circuit according to claim 6, wherein the output terminal of the impedance conversion amplifier circuit and the input terminal of at least one post-amplifier circuit among the plurality of post-amplifier circuits. Between the two, a low-pass filter circuit or a band-variable low-pass filter circuit whose band can be controlled by a bit rate control signal is inserted.
The invention according to claim 9 is the optical signal reception discriminating circuit according to claim 7, wherein an output terminal of the route switching circuit and an input terminal of at least one post-amplifier circuit among the plurality of post-amplifier circuits. Between the two, a low-pass filter circuit or a band-variable low-pass filter circuit whose band can be controlled by a bit rate control signal is inserted.

本発明によれば、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、クロック・データ再生回路を有することで、１つのクロック・データ再生回路が複数の発振回路を有する場合に問題となる発振回路間の干渉を抑えることができる。また、入力端子部に設けられたゲート回路の開閉選択もしくは方路切換回路の切り換えによって、各クロック・データ再生回路が有しているクロック再生回路の発振周波数と同一もしくは整数分の１のビットレートの信号のみを識別再生することで、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、個々の出力端子から出力させることができるので、後段の回路及び装置には整数倍もしくは整数分の１の関係にない複数のビットレートを取り扱う機能を必要としない。   According to the present invention, a clock / data recovery circuit is provided for each bit rate group or for each bit rate having an integer multiple or a fraction of an integer, so that one clock / data recovery circuit includes a plurality of oscillation circuits. It is possible to suppress interference between the oscillation circuits, which becomes a problem when it is provided. Also, the bit rate equal to or a fraction of an integer of the oscillation frequency of the clock recovery circuit included in each clock / data recovery circuit can be selected by opening / closing the gate circuit provided in the input terminal section or switching the route switching circuit. Can be output from each output terminal for each bit rate group or bit rate having a relation of an integer multiple or a fraction of an integer. A function for handling a plurality of bit rates not having an integer multiple or a fraction of an integer is not required.

＜実施例１＞
図１に本発明の実施例１の信号弁別回路を示す。図中、１は信号入力端子、２は第１の信号出力端子、３は第２の信号出力端子、４は第３の信号出力端子、５は第１のクロック・データ再生回路（ＣＤＲ回路）、６は第２のクロック・データ再生回路、７は第３のクロック・データ再生回路、８は第１のビットレート制御信号入力端子、９は第２のビットレート制御信号入力端子、１０は第３のビットレート制御信号入力端子、１１は第１のゲート回路、１２は第２のゲート回路、１３は第３のゲート回路、を示す。クロック・データ再生回路５，６，７は、それぞれ整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、設けられる。 <Example 1>
FIG. 1 shows a signal discrimination circuit according to the first embodiment of the present invention. In the figure, 1 is a signal input terminal, 2 is a first signal output terminal, 3 is a second signal output terminal, 4 is a third signal output terminal, and 5 is a first clock / data recovery circuit (CDR circuit). , 6 is a second clock and data recovery circuit, 7 is a third clock and data recovery circuit, 8 is a first bit rate control signal input terminal, 9 is a second bit rate control signal input terminal, and 10 is a first bit rate control signal input terminal. 3 is a bit rate control signal input terminal, 11 is a first gate circuit, 12 is a second gate circuit, and 13 is a third gate circuit. The clock / data recovery circuits 5, 6, and 7 are provided for each bit rate group or each bit rate having an integer multiple or a fraction of an integer.

本発明の全ての信号弁別回路（もしくはその信号弁別回路を利用した後記する光信号受信弁別回路）に入力される信号のビットレートの切り換えタイミングは、信号を送信する回路の送信タイミングを制御する制御回路や、別途設けられるビットレート判定手段などからビットレート制御信号として与えられるものとする。   The bit rate switching timing of the signal input to all the signal discriminating circuits of the present invention (or an optical signal receiving discriminating circuit which will be described later using the signal discriminating circuit) is a control for controlling the transmission timing of the circuit that transmits the signal. It is assumed that it is given as a bit rate control signal from a circuit or a bit rate determination means provided separately.

本実施例から明らかなように、本発明の信号弁別回路では、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、クロック・データ再生回路５，６，７を有しているので、１つのクロック・データ再生回路が複数の発振回路を有する場合に問題となる発振回路間の干渉を抑制し易い。   As is clear from the present embodiment, the signal discrimination circuit of the present invention has clock / data recovery circuits 5, 6, and 7 for each bit rate group or bit rate that have an integer multiple or a fraction of an integer. Therefore, it is easy to suppress the interference between the oscillation circuits, which is a problem when one clock / data recovery circuit has a plurality of oscillation circuits.

また、入力端子１の側に設けられたゲート回路１１，１２，１３の開閉を選択することで、各クロック・データ再生回路５，６，７が有しているクロック再生回路の発振周波数と同一もしくは整数分の１のビットレートの信号のみを識別再生することができるとともに、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、個々の出力端子２，３，４から出力することができるので、後段の回路及び装置には、整数倍もしくは整数分の１の関係にない複数のビットレートを取り扱う機能を必要としない。   Further, by selecting the opening and closing of the gate circuits 11, 12, 13 provided on the input terminal 1 side, the oscillation frequency of the clock recovery circuit included in each clock / data recovery circuit 5, 6, 7 is the same. Alternatively, only a signal with a bit rate of 1 / integer can be identified and reproduced, and each output terminal 2, 3, 4 for each bit rate group or bit rate having an integer multiple or 1 / integer relationship. Therefore, the circuit and device in the subsequent stage do not need a function for handling a plurality of bit rates not having an integer multiple or a fraction of an integer relationship.

＜実施例２＞
図２に本発明の実施例２の信号弁別回路を示す。実施例１と同じものには同じ符号を付けた。５Ａは第１のゲート回路内蔵クロック・データ再生回路、５Ｂは第２のゲート回路内蔵クロック・データ再生回路、５Ｃは第３のゲート回路内蔵クロック・データ再生回路、を示す。 <Example 2>
FIG. 2 shows a signal discrimination circuit according to the second embodiment of the present invention. The same components as those in Example 1 are denoted by the same reference numerals. Reference numeral 5A denotes a first clock / data recovery circuit with a built-in gate circuit, 5B denotes a second clock / data recovery circuit with a built-in gate circuit, and 5C denotes a third clock / data recovery circuit with a built-in gate circuit.

本実施例は、実施例１のゲート回路１１，１２，１３をクロック・データ再生回路５，６，７の内部に設けた例であり、ビットレート制御信号入力端子８，９，１０がクロック・データ再生回路５Ａ，６Ａ，７Ａに直接設けられている。機能に関しては実施例１と変わらないので、同様の効果が得られる。   The present embodiment is an example in which the gate circuits 11, 12, 13 of the first embodiment are provided in the clock / data recovery circuits 5, 6, 7 and the bit rate control signal input terminals 8, 9, 10 are connected to the clock It is directly provided in the data reproduction circuits 5A, 6A, 7A. Since the function is not different from that of the first embodiment, the same effect can be obtained.

＜実施例３＞
図３に本発明の実施例３の信号弁別回路を示す。実施例１と同じものには同じ符号を付けた。１７は方路切換回路を示す。実施例１においては、ゲート回路１１，１２，１３の開閉を選択することで、また実施例２においてはゲート回路内蔵クロック・データ再生回路５Ａ，６Ａ，７Ａ内のゲート回路の開閉を選択することで、各クロック・データ再生回路が有しているクロック再生回路の発振周波数と同一もしくは整数分の１のビットレートの信号のみを識別再生する機能を実現しているが、本実施例では方路切換回路１７のスイッチを用いて、入力信号のビットレートに対応したクロック・データ再生回路にのみ信号を伝達することで、同一の機能を提供している。 <Example 3>
FIG. 3 shows a signal discrimination circuit according to the third embodiment of the present invention. The same components as those in Example 1 are denoted by the same reference numerals. Reference numeral 17 denotes a route switching circuit. In the first embodiment, the opening / closing of the gate circuits 11, 12, 13 is selected, and in the second embodiment, the opening / closing of the gate circuits in the built-in clock / data recovery circuits 5A, 6A, 7A is selected. In this embodiment, the function of recognizing and reproducing only a signal having a bit rate equal to or a fraction of an integer of the oscillation frequency of the clock recovery circuit included in each clock / data recovery circuit is realized. The same function is provided by transmitting the signal only to the clock / data recovery circuit corresponding to the bit rate of the input signal using the switch of the switching circuit 17.

本実施例は、実施例１，２のように信号を分配するのに比べ、挿入損失の小さな方路切換回路１７を用いることで、分配による信号電力の損失を抑えることができるので、クロック・データ再生回路の識別感度を上げることができる。   In the present embodiment, the loss of signal power due to the distribution can be suppressed by using the path switching circuit 17 having a small insertion loss compared to the case of distributing the signal as in the first and second embodiments. The identification sensitivity of the data reproduction circuit can be increased.

＜実施例４＞
図４に本発明の実施例４の光信号受信弁別回路を示す。実施例１と同じものには同じ符号を付けた。１８は光電気変換素子、１９はインピーダンス変換増幅回路、２０は後置増幅回路、２１は図１で説明した信号弁別回路、２２は電源もしくは接地、を示す。 <Example 4>
FIG. 4 shows an optical signal receiving discrimination circuit according to the fourth embodiment of the present invention. The same components as those in Example 1 are denoted by the same reference numerals. Reference numeral 18 denotes a photoelectric conversion element, 19 denotes an impedance conversion amplifier circuit, 20 denotes a post-amplifier circuit, 21 denotes a signal discrimination circuit described with reference to FIG. 1, and 22 denotes a power source or ground.

本実施例は実施例１で示した信号弁別回路を光信号受信弁別回路に応用した例であり、複数のビットレートの信号を時分割多重した光信号を受信し弁別することができる。   The present embodiment is an example in which the signal discrimination circuit shown in the first embodiment is applied to an optical signal reception discrimination circuit, and can receive and discriminate an optical signal obtained by time-division multiplexing a plurality of bit rate signals.

なお、本実施例では、信号弁別回路２１に実施例１の構成を用いているが、実施例１，２，３のいずれの信号弁別回路を用いても同様の効果が得られる。また、インピーダンス変換増幅回路１９に並列帰還並列注入型増幅回路を用いたが、光電気変換素子１８の出力電流信号を電圧信号に変換増幅する機能を有していれば、回路構成に拘わらず同様の効果が得られる。   In the present embodiment, the configuration of the first embodiment is used for the signal discriminating circuit 21, but the same effect can be obtained by using any of the signal discriminating circuits of the first, second, and third embodiments. Further, although the parallel feedback parallel injection type amplifier circuit is used for the impedance conversion amplifier circuit 19, the same applies to any circuit as long as it has a function of converting and amplifying the output current signal of the photoelectric conversion element 18 into a voltage signal. The effect is obtained.

＜実施例５＞
図５に本発明の実施例５の光信号受信弁別回路を示す。実施例４と同じものには同じ符号を付けた。図中、２３は可変抵抗器、２４は抵抗値制御端子、を示す。文献（T.Yoshida et al.,"New 156M/2.5Gbit/s multi-rate SPF transceiver with automatic sensitivity switching",The 10th Optolectronics and Communications Conference(OECC2005),Jul.2005,paper 6B4-3.)にあるように、インピーダンス変換増幅回路に並列帰還並列注入型増幅回路の構成を用いた場合、帰還抵抗の値を変化させると光受信器の受光感度が変化する。帰還抵抗が大きければ大きいほど受光感度は改善するが、同時に回路の帯域は減少してしまう。 <Example 5>
FIG. 5 shows an optical signal receiving discrimination circuit according to the fifth embodiment of the present invention. The same components as those in Example 4 are denoted by the same reference numerals. In the figure, reference numeral 23 denotes a variable resistor, and 24 denotes a resistance value control terminal. In literature (T. Yoshida et al., "New 156M / 2.5Gbit / s multi-rate SPF transceiver with automatic sensitivity switching", The 10th Optolectronics and Communications Conference (OECC2005), Jul. 2005, paper 6B4-3.) As described above, when the configuration of the parallel feedback parallel injection type amplifier circuit is used for the impedance conversion amplifier circuit, the light receiving sensitivity of the optical receiver changes when the value of the feedback resistor is changed. The greater the feedback resistance, the better the light receiving sensitivity, but at the same time the circuit bandwidth decreases.

信号を等化増幅するには、ビットレート×０．７Ｈｚ以上の帯域が必要であるため、ビットレートに併せて帰還抵抗の値を最適化できれば、受光感度をビットレート毎に最適化することができる。本実施例は並列帰還抵抗に可変抵抗２３を用い、抵抗値制御端子２４への制御信号入力によってその値を変化させることができるので、受信する光信号のビットレートに応じて受光感度を最適化させることができる。   In order to equalize and amplify the signal, a band of bit rate x 0.7 Hz or more is required. Therefore, if the value of the feedback resistor can be optimized in accordance with the bit rate, the light receiving sensitivity can be optimized for each bit rate. it can. In this embodiment, the variable feedback resistor 23 is used as the parallel feedback resistor, and the value can be changed by inputting the control signal to the resistance value control terminal 24. Therefore, the light receiving sensitivity is optimized according to the bit rate of the received optical signal. Can be made.

なお、図５中では図４同様に、信号弁別回路２１に実施例１の構成を用いているが、実施例１，２，３のいずれの信号弁別回路を用いても同様の効果が得られる。   In FIG. 5, the configuration of the first embodiment is used for the signal discrimination circuit 21 as in FIG. 4, but the same effect can be obtained by using any of the signal discrimination circuits of the first, second, and third embodiments. .

＜実施例６＞
図６に本発明の第６の実施例の光信号受信弁別回路を示す。実施例４と同じものには同じ符号を付けた。２５は帯域可変低域通過フィルタ回路、２６は帯域制御端子、を示す。本実施例はインピーダンス変換増幅回路１９の帰還抵抗を変化させるかわりに、インピーダンス変換増幅回路１９と後置増幅回路２０の間に帯域可変低域通過フィルタ回路２５を挿入し、帯域制御端子２６にビットレート制御信号を入力することで、雑音帯域をビットレート毎に最適化するので、一定の受光感度改善効果が得られる。 <Example 6>
FIG. 6 shows an optical signal receiving discrimination circuit according to a sixth embodiment of the present invention. The same components as those in Example 4 are denoted by the same reference numerals. Reference numeral 25 denotes a band variable low-pass filter circuit, and 26 denotes a band control terminal. In this embodiment, instead of changing the feedback resistance of the impedance conversion amplifier circuit 19, a band-variable low-pass filter circuit 25 is inserted between the impedance conversion amplifier circuit 19 and the post-amplifier circuit 20, and a bit is connected to the band control terminal 26. By inputting the rate control signal, the noise band is optimized for each bit rate, so that a certain light receiving sensitivity improvement effect can be obtained.

＜実施例７＞
図７に本発明の実施例７の光信号受信弁別回路を示す。実施例４と同じものには同じ符号を付けた。２７は第１の後置増幅回路、２８は第２の後置増幅回路、２９は第３の後置増幅回路、を示す。本実施例では信号の分配をインピーダンス変換増幅回路１９の後段で行っており、機能的には実施例４と同様の効果が得られる。さらに後置増幅回路２７，２８，２９が、それらの後置増幅回路の後段に接続されるクロック・データ再生回路５，６，７の扱うビットレートのうち、最も高いビットレートの信号に対して最適化された帯域を有している場合には、ビットレート群毎に最適化された受光感度を得ることができる。 <Example 7>
FIG. 7 shows an optical signal receiving discrimination circuit according to the seventh embodiment of the present invention. The same components as those in Example 4 are denoted by the same reference numerals. Reference numeral 27 denotes a first post-amplifier circuit, 28 denotes a second post-amplifier circuit, and 29 denotes a third post-amplifier circuit. In the present embodiment, signal distribution is performed in the subsequent stage of the impedance conversion amplifier circuit 19, and the same effects as those of the fourth embodiment can be obtained in terms of function. Further, the post-amplifier circuits 27, 28, and 29 operate on the signal having the highest bit rate among the bit rates handled by the clock / data recovery circuits 5, 6, and 7 connected to the subsequent stage of the post-amplifier circuits. In the case of having an optimized band, the light receiving sensitivity optimized for each bit rate group can be obtained.

＜実施例８＞
図８に本発明の実施例８の光信号受信弁別回路を示す。実施例７と同じものには同じ符号を付けた。図から明らかなように、弁別機能を実現するゲート回路１１，１２，１３の位置を、後置増幅回路２７，２８，２９とクロック・データ再生回路５，６，７の間に設けた例であり、実施例７と同様の効果が得られる。 <Example 8>
FIG. 8 shows an optical signal receiving discrimination circuit according to the eighth embodiment of the present invention. The same components as those in Example 7 are denoted by the same reference numerals. As is apparent from the figure, in the example in which the positions of the gate circuits 11, 12, and 13 that realize the discrimination function are provided between the post-amplifier circuits 27, 28, and 29 and the clock / data recovery circuits 5, 6, and 7, respectively. Yes, the same effect as in Example 7 can be obtained.

＜実施例９＞
図９に本発明の実施例９の光信号受信弁別回路を示す。実施例７と同じものには同じ符号を付けた。本実施例は、弁別機能を実現するゲート回路を後置増幅回路の内部に設けた例であり、ビットレート制御信号入力端子８，９，１０がゲート回路内蔵後置増幅回路２７Ａ，２８Ａ，２９Ａに直接設けられている。本実施例でも、実施例７、８と同様の効果が得られる。 <Example 9>
FIG. 9 shows an optical signal receiving discrimination circuit according to the ninth embodiment of the present invention. The same components as those in Example 7 are denoted by the same reference numerals. This embodiment is an example in which a gate circuit that realizes a discrimination function is provided in the post-amplifier circuit, and the bit rate control signal input terminals 8, 9, and 10 have post-amplifier circuits 27A, 28A, and 29A with built-in gate circuits. Is provided directly. Also in this embodiment, the same effects as those of Embodiments 7 and 8 can be obtained.

＜実施例１０＞
図１０に本発明の実施例１０の光信号受信弁別回路を示す。実施例７と同じものには同じ符号を付けた。本実施例は、弁別機能を実現するゲート回路をクロック・データ再生回路の内部に設けた例であり、ビットレート制御信号入力端子８，９，１０がゲート回路内蔵クロック・データ再生回路５Ａ，６Ａ，７Ａに直接設けられている。本実施例でも、実施例７、８、９と同様の効果が得られる。 <Example 10>
FIG. 10 shows an optical signal receiving discrimination circuit according to the tenth embodiment of the present invention. The same components as those in Example 7 are denoted by the same reference numerals. The present embodiment is an example in which a gate circuit for realizing a discrimination function is provided in the clock / data recovery circuit, and the bit rate control signal input terminals 8, 9, and 10 are provided with the clock / data recovery circuits 5A and 6A with a built-in gate circuit. , 7A. In this embodiment, the same effects as those of Embodiments 7, 8, and 9 can be obtained.

＜実施例１１＞
図１１に本発明の実施例１１の光信号受信弁別回路を示す。実施例３および実施例７と同じものには同じ符号を付けた。本実施例は、実施例７〜１０の信号弁別機能を実施例３と同様に方路切換回路１７を用いて実現した例である。本実施例では、実施例１，２に対する実施例３の効果と同様の効果が、実施例７〜１０に対して得られる。 <Example 11>
FIG. 11 shows an optical signal receiving discrimination circuit according to the eleventh embodiment of the present invention. The same reference numerals are assigned to the same components as those in the third and seventh embodiments. The present embodiment is an example in which the signal discrimination function of the seventh to tenth embodiments is realized by using the route switching circuit 17 as in the third embodiment. In the present embodiment, the same effects as those of the third embodiment with respect to the first and second embodiments can be obtained with respect to the seventh to tenth embodiments.

＜実施例１２＞
図１２に本発明の実施例１２の光信号受信弁別回路を示す。実施例６および実施例７と同じものには同じ符号を付けた。本実施例では帯域可変低域通過フィルタ回路２５が第１の後置増幅回路２７を含む分岐回路の先頭に挿入されている。 <Example 12>
FIG. 12 shows an optical signal receiving discrimination circuit according to the twelfth embodiment of the present invention. The same components as those in Example 6 and Example 7 are denoted by the same reference numerals. In this embodiment, a variable band low-pass filter circuit 25 is inserted at the head of the branch circuit including the first post-amplifier circuit 27.

この分岐回路が、第１のクロック・データ再生回路５の有するクロック再生回路の発振周波数と同一のビットレートだけでなく、整数分の１のビットレートをも取り扱う場合、ビットレートに応じて帯域制御端子２６にビットレート制御信号を入力することで、雑音帯域をビットレート毎に最適化することかできるので、受光感度改善効果が得られる。   When this branch circuit handles not only the same bit rate as the oscillation frequency of the clock recovery circuit included in the first clock / data recovery circuit 5, but also a bit rate of 1 / integer, bandwidth control is performed according to the bit rate. By inputting a bit rate control signal to the terminal 26, it is possible to optimize the noise band for each bit rate, so that an effect of improving the light receiving sensitivity can be obtained.

なお、本実施例では便宜上、帯域可変低域通過フィルタ回路２５を用いた例を示したが、帯域の広い後置増幅回路を用いざるを得ない場合には、固定の低域通過フィルタ回路を用いて帯域を最適化することで、実施例７〜１０と同程度の効果が得られる。また、本実施例ではゲート回路の前段に当該低域通過フィルタ回路を挿入した例を示したが、後置増幅回路の前段であれば、ゲート回路の後段であっても同様の効果が得られる。また、本実施例では便宜上、第１の後置増幅回路２７を含む分岐回路にフィルタ回路を挿入した例を示したが、複数の分岐回路に設けても良いし、全ての分岐回路に設けても良い。また、本実施例では実施例７をベースにフィルタ回路を挿入した例を示したが、実施例７〜１０のどの実施例に対して適用しても同様の効果が得られる。   In this embodiment, for convenience, the example using the band variable low-pass filter circuit 25 is shown. However, when a post-amplifier circuit having a wide band must be used, a fixed low-pass filter circuit is used. By using and optimizing the band, the same effects as those of Examples 7 to 10 can be obtained. Further, in this embodiment, an example in which the low-pass filter circuit is inserted before the gate circuit is shown. However, the same effect can be obtained even when the gate circuit is subsequent to the post-amplifier circuit. . Further, in this embodiment, for the sake of convenience, an example in which a filter circuit is inserted into the branch circuit including the first post-amplifier circuit 27 is shown, but it may be provided in a plurality of branch circuits or in all branch circuits. Also good. In the present embodiment, an example in which a filter circuit is inserted on the basis of the seventh embodiment has been described. However, the same effect can be obtained when applied to any of the seventh to tenth embodiments.

＜実施例１３＞
図１３に本発明の実施例１３の光信号受信弁別回路を示す。実施例１１および実施例１２と同じものには同じ符号を付けた。本実施例は、実施例１２の信号弁別機能を実施例３と同様に方路切換回路１７を用いて実現した例で、実施例１、２に対する実施例３の効果と同様の効果が実施例１２に対して得られる。 <Example 13>
FIG. 13 shows an optical signal receiving discrimination circuit according to the thirteenth embodiment of the present invention. The same reference numerals are assigned to the same components as those in Example 11 and Example 12. The present embodiment is an example in which the signal discrimination function of the twelfth embodiment is realized by using the route switching circuit 17 as in the third embodiment, and the same effect as the third embodiment with respect to the first and second embodiments is obtained. 12 is obtained.

本実施例では便宜上、帯域可変低域通過フィルタ回路２５を用いた例を示したが、帯域の広い後置増幅回路を用いざるを得ない場合には、固定の低域通過フィルタ回路を用いて帯域を最適化することで、実施例１１と同程度の効果が得られる。また、本実施例では便宜上、第１の後置増幅回路を含む分岐回路にフィルタ回路を挿入した例を示したが、複数の分岐回路に設けても良いし、全ての分岐回路に設けても良い。   In the present embodiment, an example using the band variable low-pass filter circuit 25 is shown for convenience. However, when a post-amplifier circuit having a wide band must be used, a fixed low-pass filter circuit is used. By optimizing the bandwidth, the same effect as in the eleventh embodiment can be obtained. Further, in this embodiment, for the sake of convenience, an example in which a filter circuit is inserted into the branch circuit including the first post-amplifier circuit has been shown. However, the filter circuit may be provided in a plurality of branch circuits or in all branch circuits. good.

＜他の実施例＞
以上の実施例では、便宜上３つのクロック・データ再生回路５，６，７（あるいは５Ａ，６Ａ，７Ａ）を有している例を示したが、整数倍もしくは整数分の１の関係にあるビットレート群の数、もしくはビットレートの種類と同数のクロック・データ再生回路を有していれば良い。また、信号結線をシングルエンド型の表記で示したが、信号結線の全てもしくは一部を差動型接続にしても同様の効果が得られる。図１，２，４，５，６，７，８，９，１０，１２の実施例では、便宜上分岐部を結線の分岐で示したが、分配回路やその他の分配手段をもって分配しても同様の効果が得られる。さらに本発明の実施例に用いられている全てのゲート回路は、制御信号によって信号を通過もしくは遮断する機能を有していれば、内部の材料や回路構成によらない。 <Other embodiments>
In the above embodiment, an example in which three clock / data recovery circuits 5, 6, and 7 (or 5A, 6A, and 7A) are provided for convenience is shown. It is only necessary to have the same number of clock data recovery circuits as the number of rate groups or types of bit rates. Further, although the signal connection is shown by a single-end type notation, the same effect can be obtained even if all or a part of the signal connection is a differential type connection. In the embodiments of FIGS. 1, 2, 4, 5, 6, 7, 8, 9, 10, and 12, the branching portion is shown as a branch of connection for convenience, but the same applies even if distribution is performed using a distribution circuit or other distribution means. The effect is obtained. Furthermore, all the gate circuits used in the embodiments of the present invention do not depend on internal materials or circuit configurations as long as they have a function of passing or blocking signals according to control signals.

以上、説明したとおり、本実施例のように、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、クロック・データ再生回路を有することで、１つのクロック・データ再生回路が複数の発振回路を有する場合に問題となる発振回路間の干渉を抑えることができ、入力端子部に設けられたゲート回路の開閉選択もしくは方路切換回路の切り換えによって、各クロック・データ再生回路が有しているクロック再生回路の発振周波数と同一もしくは整数分の１のビットレートの信号のみを識別再生することができるとともに、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、個々の出力端子から出力させることができるので、後段の回路及び装置には整数倍もしくは整数分の１の関係にない複数のビットレートを取り扱う機能を必要としない。   As described above, as in the present embodiment, one clock / data recovery circuit is provided by having a clock / data recovery circuit for each bit rate group or each bit rate having an integer multiple or a fraction of an integer relationship. Interference between oscillation circuits, which is a problem when the circuit has a plurality of oscillation circuits, can be suppressed, and each clock and data can be regenerated by selecting the open / close of the gate circuit provided at the input terminal or switching the route switching circuit. Only a signal having a bit rate equal to or a fraction of an integer of the oscillation frequency of the clock regeneration circuit included in the circuit can be identified and reproduced, and each bit rate group having an integer multiple or a fraction of an integer relationship or Since each bit rate can be output from an individual output terminal, the subsequent circuits and devices have an integral multiple or a fraction of an integer. It does not require the ability to handle multiple bit rates no relationship.

本発明の実施例１の信号弁別回路のブロック図である。It is a block diagram of the signal discrimination circuit of Example 1 of this invention. 本発明の実施例２の信号弁別回路のブロック図である。It is a block diagram of the signal discrimination circuit of Example 2 of the present invention. 本発明の実施例３の信号弁別回路のブロック図である。It is a block diagram of the signal discrimination circuit of Example 3 of the present invention. 本発明の実施例４の光信号受信弁別回路のブロック図である。It is a block diagram of the optical signal reception discrimination circuit of Example 4 of this invention. 本発明の実施例５の光信号受信弁別回路のブロック図である。It is a block diagram of the optical signal reception discrimination circuit of Example 5 of this invention. 本発明の実施例６の光信号受信弁別回路のブロック図である。It is a block diagram of the optical signal reception discrimination circuit of Example 6 of this invention. 本発明の実施例７の光信号受信弁別回路のブロック図である。It is a block diagram of the optical signal reception discrimination circuit of Example 7 of this invention. 本発明の実施例８の光信号受信弁別回路のブロック図である。It is a block diagram of the optical signal reception discrimination circuit of Example 8 of this invention. 本発明の実施例９の光信号受信弁別回路のブロック図である。It is a block diagram of the optical signal reception discrimination circuit of Example 9 of this invention. 本発明の実施例１０の光信号受信弁別回路のブロック図である。It is a block diagram of the optical signal reception discrimination circuit of Example 10 of this invention. 本発明の実施例１１の光信号受信弁別回路のブロック図である。It is a block diagram of the optical signal reception discrimination circuit of Example 11 of this invention. 本発明の実施例１２の光信号受信弁別回路のブロック図である。It is a block diagram of the optical signal reception discrimination circuit of Example 12 of this invention. 本発明の実施例１３の光信号受信弁別回路のブロック図である。It is a block diagram of the optical signal receiving discrimination circuit of Example 13 of this invention.

符号の説明Explanation of symbols

１：信号入力端子
２，３，４：信号出力端子
５，６，７：クロック・データ再生回路
５Ａ，６Ａ，７Ａ：ゲート回路内蔵クロック・データ再生回路
８〜１０：ビットレート制御信号入力端子
１１，１２，１３：ゲート回路
１７：方路切換回
１８：光電気変換素子
１９：インピーダンス変換増幅回路
２０：後置増幅回路
２１：信号弁別回路
２２：電源もしくは接地
２３：可変抵抗器
２４：抵抗制御御端子
２５：帯域可変低域通過フィルタ回路
２６：帯域制御端子
２７，２８，２９：後置増幅回路
２７Ａ，２８Ａ，２９Ａ：ゲート回路内蔵後置増幅回路 1: Signal input terminal 2, 3, 4: Signal output terminal 5, 6, 7: Clock / data recovery circuit 5A, 6A, 7A: Clock / data recovery circuit with built-in gate circuit 8-10: Bit rate control signal input terminal 11 , 12, 13: Gate circuit 17: Path switching circuit 18: Photoelectric conversion element 19: Impedance conversion amplifier circuit 20: Post-amplifier circuit 21: Signal discrimination circuit 22: Power supply or ground 23: Variable resistor 24: Resistance control Control terminal 25: Band variable low-pass filter circuit 26: Band control terminal 27, 28, 29: Post-amplifier circuit 27A, 28A, 29A: Post-amplifier circuit with built-in gate circuit

Claims (9)

全てもしくは一部が互いに整数倍もしくは整数分の１の関係にない複数のビットレートの信号を時分割多重した信号を弁別して識別再生する信号弁別回路であって、
整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、対応したクロック・データ再生回路を有し、
前記時分割多重された信号を全てのクロック・データ再生回路に分配し、
該クロック・データ再生回路の入力端子部もしくは内部にゲート回路を設け、該ゲート回路の開閉をビットレート制御信号で制御することで、前記時分割多重された信号を、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、弁別して出力することを特徴とする信号弁別回路。 A signal discriminating circuit for discriminating and regenerating a signal obtained by time-division-multiplexing a plurality of bit rate signals, all or part of which are not integral multiples or a fraction of an integer,
A clock / data recovery circuit corresponding to each bit rate group or each bit rate having a relation of an integer multiple or a fraction of an integer,
Distributing the time-division multiplexed signal to all clock and data recovery circuits;
A gate circuit is provided inside or inside the clock / data recovery circuit, and the gate circuit is controlled by a bit rate control signal so that the time-division multiplexed signal is an integer multiple or a fraction of an integer. A signal discriminating circuit that discriminates and outputs each bit rate group or each bit rate in the relationship of 全てもしくは一部が互いに整数倍もしくは整数分の１の関係にない複数のビットレートの信号を時分割多重した信号を弁別して識別再生する信号弁別回路であって、
整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、対応したクロック・データ再生回路を有し、
１つの信号入力端子と全ての前記クロック・データ再生回路の入力端子の間に方路切換回路を接続し、
該方路切換回路をビットレート制御信号により制御することで、前記時分割多重された信号を、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、弁別して出力することを特徴とする信号弁別回路。 A signal discriminating circuit for discriminating and regenerating a signal obtained by time-division-multiplexing a plurality of bit rate signals, all or part of which are not integral multiples or a fraction of an integer,
A clock / data recovery circuit corresponding to each bit rate group or each bit rate having a relation of an integer multiple or a fraction of an integer,
A route switching circuit is connected between one signal input terminal and input terminals of all the clock / data recovery circuits,
By controlling the route switching circuit with a bit rate control signal, the time-division multiplexed signal is discriminated and output for each bit rate group or bit rate having an integer multiple or a fraction of an integer relationship. A signal discrimination circuit characterized by that. 複数のビットレートの信号を時分割多重した光信号を、光電気変換素子を用いて電流信号に変換し、該電流信号をインピータンス変換増幅回路で電圧信号に変換増幅し、後置増幅回路を用いて一定振幅の電圧信号に増幅した後に、クロック・データ再生回路で識別再生する光信号受信弁別回路であって、
該クロック・データ再生回路の代わりに、請求項１もしくは請求項２に記載の信号弁別回路を具備し、前記時分割多重された光信号を電圧信号に変換し、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、弁別して出力することを特徴とする光信号受信弁別回路。 An optical signal obtained by time-division-multiplexing a plurality of bit rate signals is converted into a current signal using a photoelectric conversion element, and the current signal is converted and amplified into a voltage signal by an impedance conversion amplifier circuit. An optical signal reception discriminating circuit for performing identification and reproduction by a clock and data reproduction circuit after being amplified to a voltage signal having a constant amplitude using,
A signal discriminating circuit according to claim 1 or 2 is provided instead of the clock and data recovery circuit, and the time-division multiplexed optical signal is converted into a voltage signal. An optical signal reception discriminating circuit which discriminates and outputs each bit rate group or bit rate concerned. 請求項３に記載の光信号受信弁別回路において、
前記インピーダンス変換増幅回路として並列帰還並列注入型増幅回路を用い、該並列帰還並列注入型増幅回路の並列帰還抵抗の抵抗値を前記ビットレート制御信号により制御可能な可変抵抗とすることを特徴とする光信号受信弁別回路。 In the optical signal reception discrimination circuit according to claim 3,
A parallel feedback parallel injection amplifier circuit is used as the impedance conversion amplifier circuit, and the resistance value of the parallel feedback resistor of the parallel feedback parallel injection amplifier circuit is a variable resistor that can be controlled by the bit rate control signal. Optical signal reception discrimination circuit. 請求項３に記載の光信号受信弁別回路において、
前記インピーダンス変換増幅回路の出力端子と前記後置増幅回路の入力端子の間に、ビットレート制御信号により帯域を制御可能な帯域可変低域通過フィルタ回路を挿入したことを特徴とする光信号受信弁別回路。 In the optical signal reception discrimination circuit according to claim 3,
An optical signal receiving discrimination characterized in that a band-variable low-pass filter circuit capable of controlling a band by a bit rate control signal is inserted between an output terminal of the impedance conversion amplifier circuit and an input terminal of the post-amplifier circuit. circuit. 全てもしくは一部が互いに整数倍もしくは整数分の１の関係にない複数のビットレートの信号を時分割多重した光信号を、光電気変換素子を用いて電流信号に変換し、該電流信号をインピーダンス変換増幅回路で電圧信号に変換増幅し、後置増幅回路を用いて一定振幅の電圧信号に増幅した後に、クロック・データ再生回路で識別再生する光信号受信弁別回路であって、
前記後置増幅回路として、前記整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、対応した複数の後置増幅回路を有し、
前記インピーダンス変換増幅回路の出力信号を全ての前記後置増幅回路に分配し、
前記複数の後置増幅回路の出力信号を各々対応したクロック・データ再生回路で識別再生するとともに、前記整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、前記後置増幅回路の入力端子部もしくは内部、もしくは前記クロック・データ再生回路の入力端子部もしくは内部にゲート回路を設け、
該ゲート回路の開閉をビットレート制御信号で制御することで、前記時分割多重された光信号を電圧信号に変換し、整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、弁別して出力することを特徴とする光信号受信弁別回路。 An optical signal obtained by time-division-multiplexing a plurality of bit rate signals, all or part of which is not an integer multiple or a fraction of an integer, is converted into a current signal using a photoelectric conversion element, and the current signal is converted into an impedance. An optical signal reception discriminating circuit that converts and amplifies to a voltage signal by a conversion amplifier circuit, amplifies it to a voltage signal having a constant amplitude using a post-amplifier circuit, and performs identification and reproduction by a clock and data recovery circuit,
The post-amplifier circuit has a plurality of post-amplifier circuits corresponding to each bit rate group or each bit rate in the integer multiple or a fraction of an integer,
Distributing the output signal of the impedance conversion amplifier circuit to all the post-amplifier circuits;
The output signals of the plurality of post-amplifier circuits are discriminated and reproduced by corresponding clock / data reproduction circuits, and the post-position is provided for each bit rate group or bit rate having a relation of the integral multiple or the integral fraction. A gate circuit is provided in the input terminal part or inside of the amplifier circuit, or in the input terminal part or inside of the clock / data recovery circuit,
By controlling the opening and closing of the gate circuit with a bit rate control signal, the time-division multiplexed optical signal is converted into a voltage signal, and each bit rate group or bit rate having an integer multiple or a fraction of an integer relationship. And an optical signal receiving discrimination circuit characterized in that the discrimination signal is outputted after discrimination. 全てもしくは一部が互いに整数倍もしくは整数分の１の関係にない複数のビットレートの信号を時分割多重した光信号を、光電気変換素子を用いて電流信号に変換し、該電流信号をインピーダンス変換増幅回路で電圧信号に変換増幅し、後置増幅回路を用いて一定振幅の電圧信号に増幅した後に、クロック・データ再生回路で識別再生する光信号受信弁別回路であって、
前記整数倍もしくは整数分の１の関係にあるビットレート群毎もしくはビットレート毎に、対応した複数の後置増幅回路を有し、
前記インピーダンス変換増幅回路の出力端子と全ての前記後置増幅回路の入力端子の間に方路切換回路を接続し、
前記複数の後置増幅回路の出力信号を各々対応したクロック・データ再生回路で識別再生するともに、ビットレート制御信号により前記方路切換回路を制御することで、前記時分割多重された光信号を電圧信号に変換し、整数倍もしくは整数分の１の関係にあるヒットレート群毎もしくはビットレート毎に、弁別して出力することを特徴とする光信号受信弁別回路。 An optical signal obtained by time-division-multiplexing a plurality of bit rate signals, all or part of which is not an integer multiple or a fraction of an integer, is converted into a current signal using a photoelectric conversion element, and the current signal is converted into an impedance. An optical signal reception discriminating circuit that converts and amplifies to a voltage signal by a conversion amplifier circuit, amplifies it to a voltage signal having a constant amplitude using a post-amplifier circuit, and performs identification and reproduction by a clock and data recovery circuit,
A plurality of post-amplifier circuits corresponding to each bit rate group or each bit rate in a relation of the integer multiple or a fraction of an integer,
A path switching circuit is connected between the output terminal of the impedance conversion amplifier circuit and the input terminals of all the post-amplifier circuits,
The output signals of the plurality of post-amplifier circuits are discriminated and reproduced by corresponding clock / data reproduction circuits, and the route switching circuit is controlled by a bit rate control signal, whereby the time-division multiplexed optical signal is converted. An optical signal reception discriminating circuit which converts to a voltage signal and discriminates and outputs it for each hit rate group or bit rate which have an integer multiple or a fraction of an integer relationship. 請求項６に記載の光信号受信弁別回路において、
前記インピーダンス変換増幅回路の出力端子と前記複数の後置増幅回路の内の少なくとも１つの後置増幅回路の入力端子との間に、低域通過フィルタ回路もしくはビットレート制御信号により帯域を制御可能な帯域可変低域通過フィルタ回路を挿入したことを特徴とする光信号受信弁別回路。 In the optical signal reception discrimination circuit according to claim 6,
A band can be controlled by a low-pass filter circuit or a bit rate control signal between an output terminal of the impedance conversion amplifier circuit and an input terminal of at least one of the plurality of post-amplifier circuits. An optical signal reception discriminating circuit, wherein a band-variable low-pass filter circuit is inserted. 請求項７に記載の光信号受信弁別回路において、
前記方路切換回路の出力端子と前記複数の後置増幅回路の内の少なくとも１つの後置増幅回路の入力端子との間に、低域通過フィルタ回路もしくはビットレート制御信号により帯域を制御可能な帯域可変低域通過フィルタ回路を挿入したことを特徴とする光信号受信弁別回路。 The optical signal reception discrimination circuit according to claim 7,
A band can be controlled by a low-pass filter circuit or a bit rate control signal between the output terminal of the route switching circuit and the input terminal of at least one post-amplifier circuit among the plurality of post-amplifier circuits. An optical signal reception discriminating circuit, wherein a band-variable low-pass filter circuit is inserted.
JP2007186487A 2007-07-18 2007-07-18 Signal discrimination circuit and optical signal reception discrimination circuit Active JP4849635B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007186487A JP4849635B2 (en) 2007-07-18 2007-07-18 Signal discrimination circuit and optical signal reception discrimination circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007186487A JP4849635B2 (en) 2007-07-18 2007-07-18 Signal discrimination circuit and optical signal reception discrimination circuit

Publications (2)

Publication Number Publication Date
JP2009027295A true JP2009027295A (en) 2009-02-05
JP4849635B2 JP4849635B2 (en) 2012-01-11

Family

ID=40398717

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007186487A Active JP4849635B2 (en) 2007-07-18 2007-07-18 Signal discrimination circuit and optical signal reception discrimination circuit

Country Status (1)

Country Link
JP (1) JP4849635B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011160054A (en) * 2010-01-29 2011-08-18 Nippon Telegr & Teleph Corp <Ntt> Dual rate amplitude limiting amplifier circuit
JP2011199559A (en) * 2010-03-19 2011-10-06 Nippon Telegr & Teleph Corp <Ntt> Dual rate receiving circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH088954A (en) * 1994-06-21 1996-01-12 Nec Corp Increase system for service capacity in point-multi-point optical transmission system
JP2005033537A (en) * 2003-07-14 2005-02-03 Hitachi Communication Technologies Ltd Passive optical network data transmission method and terminating device
JP2005197881A (en) * 2004-01-05 2005-07-21 Nippon Telegr & Teleph Corp <Ntt> Multiple speed burst optical signal receiver optimizing reception sensitivity
JP2006352329A (en) * 2005-06-14 2006-12-28 Sumitomo Electric Ind Ltd Optical communication system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH088954A (en) * 1994-06-21 1996-01-12 Nec Corp Increase system for service capacity in point-multi-point optical transmission system
JP2005033537A (en) * 2003-07-14 2005-02-03 Hitachi Communication Technologies Ltd Passive optical network data transmission method and terminating device
JP2005197881A (en) * 2004-01-05 2005-07-21 Nippon Telegr & Teleph Corp <Ntt> Multiple speed burst optical signal receiver optimizing reception sensitivity
JP2006352329A (en) * 2005-06-14 2006-12-28 Sumitomo Electric Ind Ltd Optical communication system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011160054A (en) * 2010-01-29 2011-08-18 Nippon Telegr & Teleph Corp <Ntt> Dual rate amplitude limiting amplifier circuit
JP2011199559A (en) * 2010-03-19 2011-10-06 Nippon Telegr & Teleph Corp <Ntt> Dual rate receiving circuit

Also Published As

Publication number Publication date
JP4849635B2 (en) 2012-01-11

Similar Documents

Publication Publication Date Title
JP4409446B2 (en) Optical receiver and optical transmission system
CA2244385C (en) Optical node system for a ring architecture and method thereof
JP4584257B2 (en) Optical performance monitoring method and system
EP1379042B1 (en) Multiplexer
US20040013429A1 (en) Power equalization in optical switches
JP3437532B2 (en) Transmission speed independent optical receiver
JP6251269B2 (en) System and method for 400G signal generation and coherent detection
JP2007502085A6 (en) Optical performance monitoring method and system
US6396607B1 (en) Multi-wavelength all-optical regenerators (MARS)
JP3833655B2 (en) Optical communication system
JP2013009193A (en) Optical packet exchange device
JP4849635B2 (en) Signal discrimination circuit and optical signal reception discrimination circuit
WO2019160838A1 (en) Multi-rate optical network
JP5399932B2 (en) Optical receiver and optical transmitter / receiver
US20090220249A1 (en) Demodulation circuit
JP3498839B2 (en) Optical communication receiver
JP2007208747A (en) Optical access network system
US10291970B2 (en) Trunk and drop RFOG architecture
JP2010157911A (en) Optical receiver
JP2003198463A (en) Common clock optical fiber transmission system
JP4555348B2 (en) System and method for mitigating dispersion slope in optical communication system
JP4888488B2 (en) Communication terminal device and signal receiving method
US10727971B1 (en) Methods and apparatus for separating the wavelength switching function from the channel equalization function in a reconfigurable optical add/drop multiplexer (ROADM)
JP2010178257A (en) Amplifier corresponding to a plurality of speeds
Nakagawa et al. 10.3 Gb/s burst-mode 3R receiver incorporating full AGC optical receiver and 82.5 GS/s sampling CDR for 10G-EPON systems

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090715

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20111007

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20111012

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20111014

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4849635

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20141028

Year of fee payment: 3

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350