JP2009026960A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2009026960A
JP2009026960A JP2007188634A JP2007188634A JP2009026960A JP 2009026960 A JP2009026960 A JP 2009026960A JP 2007188634 A JP2007188634 A JP 2007188634A JP 2007188634 A JP2007188634 A JP 2007188634A JP 2009026960 A JP2009026960 A JP 2009026960A
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insulating resin
plate electrode
gap
temperature range
semiconductor device
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Seiki Hiramatsu
星紀 平松
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having high reliability for the junction of a semiconductor element mounted on a parallel plate electrode and the parallel plate electrode. <P>SOLUTION: The semiconductor device includes the parallel plate electrode formed of two plates separated in parallel so as to form a predetermined gap; the semiconductor elements arranged in the gap and mounted on the two plates; a first insulating resin which is filled in the gap and is cured at a first curing temperature; a second insulating resin which covers an outer circumference of the parallel plate electrode and is cured at a second curing temperature which is lower than the first curing temperature. The sum of the thermal stresses generated in the first insulating resin and the thermal stresses generated in the second insulating resin is applied on the two plates so that the gap is narrowed in the range of the operating temperature. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

この発明は、互いに平行な２枚の平板電極を含む半導体装置に関するものである。   The present invention relates to a semiconductor device including two plate electrodes parallel to each other.

半導体素子の高性能化に伴い、半導体装置は高速化の一途を辿っている。また、半導体素子は、小型化、高集積化の傾向にあるため、半導体装置内の配線密度は急速に増えている。この結果、半導体装置内のインダクタンスが大きくなったり、放熱性能が低下したり、十分な絶縁信頼性を得ることができなかったり、半導体装置を組み込んだ電気システム装置の高機能化、高性能化を妨げる要因のひとつになっている。
そのような半導体装置の問題を解決するひとつの手段として、互いに平行な２枚の平板で構成された平行平板電極を設置し、半導体素子から平行平板電極に配線し回路のインダクタンスを低減したり、平行平板電極間に半導体素子を搭載して放熱性を向上させたりする方法が提案されている（例えば、特許文献１、特許文献２参照）。 As the performance of semiconductor elements increases, the speed of semiconductor devices continues to increase. Further, since semiconductor elements tend to be miniaturized and highly integrated, the wiring density in the semiconductor device is rapidly increasing. As a result, the inductance in the semiconductor device increases, the heat dissipation performance deteriorates, sufficient insulation reliability cannot be obtained, and the functionality and performance of the electrical system device incorporating the semiconductor device is improved. It is one of the obstacles.
As one means for solving the problem of such a semiconductor device, a parallel plate electrode composed of two flat plates parallel to each other is installed, and wiring from the semiconductor element to the parallel plate electrode reduces the inductance of the circuit. A method of mounting a semiconductor element between parallel plate electrodes to improve heat dissipation has been proposed (for example, see Patent Document 1 and Patent Document 2).

特開平０５−２１６７４号公報Japanese Patent Laid-Open No. 05-21474 特開２００４−１９３４７６号公報JP 2004-193476 A

しかしながら、従来の方法では、半導体装置のヒートサイクル試験時に、内部を封止する樹脂の膨張により平行平板電極の間が開いてしまい、半導体素子との接合が破断したり、半導体素子に亀裂が入ったりして半導体装置が動作しなくなるという問題や、電極と絶縁性樹脂の界面が剥離したり、絶縁性樹脂に亀裂が入ったりして半導体装置の絶縁性が損なわれたりする問題がある。   However, in the conventional method, during the heat cycle test of the semiconductor device, the parallel plate electrodes are opened due to the expansion of the resin that seals the inside, and the junction with the semiconductor element is broken or the semiconductor element is cracked. There is a problem that the semiconductor device does not operate, and an interface between the electrode and the insulating resin is peeled off, or the insulating resin is cracked and the insulating property of the semiconductor device is impaired.

この発明の目的は、平行平板電極の上に搭載した半導体素子と平行平板電極との接合の信頼性の高い半導体装置を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device with high reliability of bonding between a semiconductor element mounted on a parallel plate electrode and the parallel plate electrode.

この発明に係る半導体装置は、所定の隙間を形成するよう平行に離間する２枚の平板からなる平行平板電極と、上記隙間に配置されるとともに上記２枚の平板に実装される半導体素子と、上記隙間を埋めるとともに第１の硬化温度で硬化される第１の絶縁性樹脂と、上記平行平板電極の外周を包むとともに上記第１の硬化温度未満の第２の硬化温度で硬化される第２の絶縁性樹脂と、を有し、使用温度範囲において上記隙間が狭くなるよう上記２枚の平板に上記第１の絶縁性樹脂に発生する熱応力と上記第２の絶縁性樹脂に発生する熱応力との和が加わる。   A semiconductor device according to the present invention includes a parallel plate electrode composed of two flat plates spaced in parallel to form a predetermined gap, a semiconductor element disposed in the gap and mounted on the two flat plates, A first insulating resin that fills the gap and is cured at a first curing temperature, and a second that wraps around the outer periphery of the parallel plate electrode and is cured at a second curing temperature lower than the first curing temperature. Thermal stress generated in the first insulating resin and heat generated in the second insulating resin on the two flat plates so that the gap is narrowed in the operating temperature range. The sum with stress is added.

この発明に係る半導体装置の効果は、使用温度範囲において隙間が狭くなるよう２枚の平板に第１の絶縁性樹脂および第２の絶縁性樹脂の熱応力の和が加わるので、半導体素子が平板電極に押し付けられる力が加わり接続の信頼性が向上する。   The effect of the semiconductor device according to the present invention is that the sum of the thermal stresses of the first insulating resin and the second insulating resin is applied to the two flat plates so that the gap is narrowed in the operating temperature range. The force pressed against the electrode is added to improve the connection reliability.

実施の形態１．
図１は、この発明の実施の形態１に係る半導体装置の断面図である。
この発明の実施の形態１に係る半導体装置は、互いに平行で所定の隙間だけ離間し平行平板電極１を構成する第１の平板電極１ａおよび第２の平板電極１ｂ、第１の平板電極１ａと第２の平板電極１ｂとの間の中間に配置される中間電極２、および、第１の平板電極１ａと中間電極２との間および第２の平板電極１ｂと中間電極２との間に配設される半導体素子３を有する。 Embodiment 1 FIG.
FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention.
The semiconductor device according to the first embodiment of the present invention includes a first flat plate electrode 1a, a second flat plate electrode 1b, and a first flat plate electrode 1a, which are parallel to each other and spaced apart from each other by a predetermined gap. An intermediate electrode 2 disposed in the middle between the second flat plate electrode 1b, and between the first flat plate electrode 1a and the intermediate electrode 2 and between the second flat plate electrode 1b and the intermediate electrode 2. The semiconductor element 3 is provided.

また、この発明の実施の形態１に係る半導体装置は、半導体素子３を第１の平板電極、第２の平板電極および中間電極２に接合する接合材４、外部端子５、半導体素子３の図示しない電極と外部端子５とを接続する配線６、および、平行平板電極１を囲むケース７を有する。
また、この発明の実施の形態１に係る半導体装置は、第１の平板電極１ａと第２の平板電極１ｂとの間に充填される第１の絶縁性樹脂８、および、第１の絶縁性樹脂８が充填された平行平板電極１の内側を除くケース７内に充填される第２の絶縁性樹脂９を有する。
なお、外部端子５および配線６は、一般的なものなので説明は省略する。 Further, in the semiconductor device according to the first embodiment of the present invention, the semiconductor element 3 is bonded to the first flat plate electrode, the second flat plate electrode, and the intermediate electrode 2, the bonding material 4, the external terminal 5, and the semiconductor element 3 illustrated. A wiring 6 for connecting the electrode not to be connected to the external terminal 5, and a case 7 surrounding the parallel plate electrode 1.
In addition, the semiconductor device according to the first embodiment of the present invention includes the first insulating resin 8 filled between the first flat plate electrode 1a and the second flat plate electrode 1b, and the first insulating property. A second insulating resin 9 is filled in the case 7 except for the inside of the parallel plate electrode 1 filled with the resin 8.
Note that the external terminals 5 and the wiring 6 are general and will not be described.

第１の平板電極１ａ、第２の平板電極１ｂおよび中間電極２は、半導体素子３に電力を供給したり、半導体素子３からの電気信号を伝達したりする配線路である。
また、第１の平板電極１ａ、第２の平板電極１ｂおよび中間電極２は、銅が用いられているが、第１の平板電極１ａ、第２の平板電極１ｂおよび中間電極２は、銅に限定するものではなく、銀、アルミニウム、金など導電性を有する金属であれば良い。
なお、第１の平板電極１ａ、第２の平板電極１ｂおよび中間電極２の表面に防錆のため金、ニッケルなどのめっきを施しても良いし、第１の絶縁性樹脂８および第２の絶縁性樹脂９と接する部分の表面に凹凸を設けて接着性を向上させても良い。
また、第１の平板電極１ａ、第２の平板電極１ｂおよび中間電極２は、エッチングにより作製するが、この方法に限定されるものではなく、打ち抜き加工で作製しても良く、所定の形状に加工できる方法であればいずれの方法でも良い。 The first plate electrode 1 a, the second plate electrode 1 b, and the intermediate electrode 2 are wiring paths that supply power to the semiconductor element 3 and transmit electric signals from the semiconductor element 3.
The first flat plate electrode 1a, the second flat plate electrode 1b, and the intermediate electrode 2 are made of copper, but the first flat plate electrode 1a, the second flat plate electrode 1b, and the intermediate electrode 2 are made of copper. It is not limited, and any metal having conductivity such as silver, aluminum, or gold may be used.
The first plate electrode 1a, the second plate electrode 1b, and the intermediate electrode 2 may be plated with gold, nickel or the like for rust prevention, or the first insulating resin 8 and the second plate 2 The surface of the portion in contact with the insulating resin 9 may be provided with unevenness to improve the adhesion.
In addition, the first plate electrode 1a, the second plate electrode 1b, and the intermediate electrode 2 are manufactured by etching. However, the present invention is not limited to this method, and may be manufactured by punching and has a predetermined shape. Any method may be used as long as it can be processed.

半導体素子３は、電気信号の切換、増幅などを行うシリコンからなる半導体素子であるが、半導体素子３としては、半導体特性を示すものであればシリコンに限定するものではなく、例えばガリウム砒素、インジウム燐、炭化シリコンなどの化合物半導体を用いた素子でも良い。なお、図１中では半導体素子３が４個しか搭載されていないが、半導体素子３の数は４個に限るものではない。   The semiconductor element 3 is a semiconductor element made of silicon that performs switching, amplification, and the like of an electric signal. However, the semiconductor element 3 is not limited to silicon as long as it exhibits semiconductor characteristics. For example, gallium arsenide, indium An element using a compound semiconductor such as phosphorus or silicon carbide may be used. Although only four semiconductor elements 3 are mounted in FIG. 1, the number of semiconductor elements 3 is not limited to four.

接合材４は、はんだであるが、接合材４としてははんだに限るものではなく、ボール状の金属を使用しても良く、金属の柱をはんだで固定しても良い。
また、銀や銅などの導電性の微粒子を樹脂中に分散させた導電性ペーストを使用しても良く、半導体素子３に必要な電流密度が得られる接続方法ならば構わない。
また、図２に示すように、バネ１１を利用して押圧力で第１の平板電極１ａ、第２の平板電極１ｂおよび中間電極２に電気的に接続し固定しても良い。 The bonding material 4 is solder, but the bonding material 4 is not limited to solder, and a ball-shaped metal may be used, and a metal column may be fixed with solder.
Further, a conductive paste in which conductive fine particles such as silver and copper are dispersed in a resin may be used, and any connection method that can obtain a current density necessary for the semiconductor element 3 may be used.
Further, as shown in FIG. 2, a spring 11 may be used to electrically connect and fix the first flat plate electrode 1 a, the second flat plate electrode 1 b, and the intermediate electrode 2 with a pressing force.

ケース７は、第１の平板電極１ａ、第２の平板電極１ｂ、中間電極２、および、外部端子５を固定し、半導体装置の外形を形成する絶縁性の樹脂であり、エポキシ樹脂中にアルミナ、シリカ、ボロンナイトライド（以下、「ＢＮ」と称す）、アルミニウムナイトライド（以下、「ＡｌＮ」と称す）などのセラミック微粒子を充填させたものを用いるが、ケース７の材質はこれに限定するものではない。微粒子は、ダイヤモンドや樹脂でも良く、絶縁性の樹脂は、シリコーン樹脂、アクリル樹脂、ウレタン樹脂、ポリフェニレンサルファイド樹脂（以下、「ＰＰＳ樹脂」と称す）、ポリエステル樹脂など整形できる樹脂であれば良い。微粒子の粒子形状は通常球状粒子を用いるがこれに限定するものではなく、破砕状、りん片状などを用いても良い。   The case 7 is an insulating resin that fixes the first flat plate electrode 1a, the second flat plate electrode 1b, the intermediate electrode 2, and the external terminal 5, and forms the outer shape of the semiconductor device. A material filled with ceramic fine particles such as silica, boron nitride (hereinafter referred to as “BN”), aluminum nitride (hereinafter referred to as “AlN”) is used, but the material of the case 7 is limited to this. It is not a thing. The fine particles may be diamond or resin, and the insulating resin may be any resin that can be shaped, such as silicone resin, acrylic resin, urethane resin, polyphenylene sulfide resin (hereinafter referred to as “PPS resin”), and polyester resin. The particle shape of the fine particles is usually a spherical particle, but is not limited to this, and a crushed shape, a flake shape and the like may be used.

第１の絶縁性樹脂８は、シリコーン樹脂にアルミナの絶縁性の粒子を充填した樹脂が用いられるがこれに限定するものではなく、絶縁性の樹脂としてはアクリル樹脂、ウレタン樹脂、エポキシ樹脂などの熱硬化性樹脂やＰＰＳ樹脂、ポリエチレン樹脂、ポリエチレンテレフタレート樹脂（以下、「ＰＥＴ樹脂」と称す）などの熱可塑性樹脂でも良く、絶縁性で成形できるものであれば構わない。
また、絶縁性の粒子もアルミナに限定するものではなく、シリカ、ＢＮ、ダイヤモンド、シリコーンゴムなどの粒子を用いても良い。
粒子形状は通常球状粒子を用いるがこれに限定するものではなく、破砕状、りん片状などを用いても良い。 As the first insulating resin 8, a resin in which alumina insulating particles are filled in a silicone resin is used. However, the insulating resin is not limited to this, and examples of the insulating resin include an acrylic resin, a urethane resin, and an epoxy resin. A thermoplastic resin such as a thermosetting resin, PPS resin, polyethylene resin, or polyethylene terephthalate resin (hereinafter referred to as “PET resin”) may be used as long as it can be molded in an insulating manner.
Also, the insulating particles are not limited to alumina, and particles such as silica, BN, diamond, and silicone rubber may be used.
The particle shape is usually a spherical particle, but is not limited to this, and a crushed shape, a flake shape, or the like may be used.

第２の絶縁性樹脂９は、シリコーン樹脂にアルミナの絶縁性の粒子を充填した樹脂が用いられるがこれに限定するものではなく、絶縁性の樹脂としてはアクリル樹脂、ウレタン樹脂、エポキシ樹脂などの熱硬化性樹脂やＰＰＳ樹脂、ポリエチレン樹脂、ＰＥＴ樹脂などの熱可塑性樹脂でも良く、絶縁性で成形できるものであれば構わない。
また、絶縁性の粒子もアルミナに限定するものではなく、シリカ、ＢＮ、ダイヤモンド、シリコーンゴムなどの粒子を用いても良い。
粒子形状は通常球状粒子を用いるがこれに限定するものではなく、破砕状、りん片状などを用いても良い。 As the second insulating resin 9, a resin in which alumina insulating particles are filled in a silicone resin is used. However, the insulating resin is not limited to this, and examples of the insulating resin include acrylic resin, urethane resin, and epoxy resin. A thermoplastic resin such as a thermosetting resin, PPS resin, polyethylene resin, or PET resin may be used as long as it can be molded insulatively.
Also, the insulating particles are not limited to alumina, and particles such as silica, BN, diamond, and silicone rubber may be used.
The particle shape is usually a spherical particle, but is not limited to this, and a crushed shape, a flake shape, or the like may be used.

次に、この発明の実施の形態１に係る半導体装置の製造方法を説明する。
第１の平板電極１ａ、第２の平板電極１ｂおよび中間電極２に銅、ケース７にＰＰＳ樹脂、接合材４にはんだ、半導体素子３にＳｉＣを使用した半導体装置で、図３に示すように、半導体素子３を平行平板電極１に実装する。
次に、第１の絶縁性樹脂８として信越化学工業製一液型シリコーンゴムコンパウンドＫＥ１８３３を、平行平板電極１の内側に注入し、硬化温度１２０℃で６０分間硬化する。
次に、第２の絶縁性樹脂９として信越化学工業製二液付加型シリコーンゴムコンパウンドＫＥ１０３をケース７内に充填し、硬化温度２３℃で７２時間硬化する。 Next, a method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described.
As shown in FIG. 3, a semiconductor device using copper for the first plate electrode 1a, the second plate electrode 1b and the intermediate electrode 2, PPS resin for the case 7, solder for the bonding material 4, and SiC for the semiconductor element 3 The semiconductor element 3 is mounted on the parallel plate electrode 1.
Next, one-part silicone rubber compound KE1833 manufactured by Shin-Etsu Chemical Co., Ltd. is injected as the first insulating resin 8 into the parallel plate electrode 1 and cured at a curing temperature of 120 ° C. for 60 minutes.
Next, a two-component addition type silicone rubber compound KE103 manufactured by Shin-Etsu Chemical Co., Ltd. is filled in the case 7 as the second insulating resin 9, and cured at a curing temperature of 23 ° C. for 72 hours.

次に、第１の平板電極１ａと第２の平板電極１ｂとに加わる力について説明する。
第１の平板電極１ａ、第２の平板電極１ｂおよび中間電極２は銅、接合材４ははんだ、半導体素子３はＳｉＣからできているので、熱膨張係数が樹脂に比べて一桁小さく周囲温度の変化による熱膨張収縮を無視できる。そこで、第１の平板電極１ａと第２の平板電極１ｂとに加わる熱応力は、第１の絶縁性樹脂８および第２の絶縁性樹脂９に発生する熱応力である。 Next, the force applied to the first flat plate electrode 1a and the second flat plate electrode 1b will be described.
Since the first plate electrode 1a, the second plate electrode 1b and the intermediate electrode 2 are made of copper, the bonding material 4 is made of solder, and the semiconductor element 3 is made of SiC, the thermal expansion coefficient is an order of magnitude smaller than that of the resin and the ambient temperature. The thermal expansion and contraction due to the change of can be ignored. Therefore, the thermal stress applied to the first flat plate electrode 1a and the second flat plate electrode 1b is a thermal stress generated in the first insulating resin 8 and the second insulating resin 9.

熱硬化性樹脂に発生する熱応力は、樹脂の硬化温度で最小になり、硬化温度を超えると樹脂の膨張方向に、硬化温度未満だと樹脂の収縮方向に発生する。図４に示すように、内部に充填された第１の絶縁性樹脂８は硬化温度１２０℃で硬化されているので、第１の絶縁性樹脂８が１２０℃で熱応力は最小になり、１２０℃未満で第１の絶縁性樹脂８を収縮するように熱応力が働き、１２０℃を超えると第１の絶縁性樹脂８を膨張するように熱応力が働く。一方、平行平板電極１の外部を封止する第２の絶縁性樹脂９は硬化温度２３℃で硬化されているので、第２の絶縁性樹脂９が２３℃で熱応力は最小になり、２３℃未満で第２の絶縁性樹脂９を収縮するように熱応力が働き、２３℃を超えると第２の絶縁性樹脂９を膨張するように熱応力が働く。   The thermal stress generated in the thermosetting resin is minimized at the curing temperature of the resin. When the curing temperature is exceeded, the thermal stress is generated in the expansion direction of the resin. As shown in FIG. 4, since the first insulating resin 8 filled therein is cured at a curing temperature of 120 ° C., the first insulating resin 8 is 120 ° C., and the thermal stress is minimized. Thermal stress acts to shrink the first insulating resin 8 at a temperature below 120 ° C., and thermal stress acts to expand the first insulating resin 8 at a temperature above 120 ° C. On the other hand, since the second insulating resin 9 that seals the outside of the parallel plate electrode 1 is cured at a curing temperature of 23 ° C., the thermal stress is minimized at 23 ° C. Thermal stress acts to shrink the second insulating resin 9 at a temperature below 23 ° C., and thermal stress acts to expand the second insulating resin 9 at a temperature above 23 ° C.

平行平板電極１の外部に何もない状態を想定すると外からは力が作用しないので、第１の絶縁性樹脂８が収縮すると、第１の平板電極１ａと第２の平板電極１ｂとに応力が加わり、第１の平板電極１ａと第２の平板電極１ｂとの隙間が狭められる。逆に、第１の絶縁性樹脂８が膨張すると、第１の平板電極１ａと第２の平板電極１ｂとに応力が加わり、第１の平板電極１ａと第２の平板電極１ｂとの隙間が拡げられる。   Assuming a state where there is nothing outside the parallel plate electrode 1, no force is applied from the outside. Therefore, when the first insulating resin 8 contracts, stress is applied to the first plate electrode 1 a and the second plate electrode 1 b. Is added to narrow the gap between the first plate electrode 1a and the second plate electrode 1b. Conversely, when the first insulating resin 8 expands, stress is applied to the first plate electrode 1a and the second plate electrode 1b, and the gap between the first plate electrode 1a and the second plate electrode 1b becomes larger. Can be expanded.

一方、内側に平行平板電極１がない状態を想定すると内側から力が作用しないので、第２の絶縁性樹脂９が収縮すると、内側に存在する空間の容積が膨張する。そして、第２の絶縁性樹脂９の内周面に第１の平板電極１ａと第２の平板電極１ｂとが固定されると、第１の平板電極１ａと第２の平板電極１ｂとの隙間が拡げられる。逆に、第２の絶縁性樹脂９が膨張すると、内側に存在する空間の容積が収縮する。そして、第２の絶縁性樹脂９の内周面に第１の平板電極１ａと第２の平板電極１ｂとが固定されると、第１の平板電極１ａと第２の平板電極１ｂとの隙間が狭められる。   On the other hand, assuming that there is no parallel plate electrode 1 on the inner side, no force is applied from the inner side. Therefore, when the second insulating resin 9 contracts, the volume of the space existing on the inner side expands. And when the 1st flat plate electrode 1a and the 2nd flat plate electrode 1b are fixed to the internal peripheral surface of the 2nd insulating resin 9, the clearance gap between the 1st flat plate electrode 1a and the 2nd flat plate electrode 1b Is expanded. Conversely, when the second insulating resin 9 expands, the volume of the space existing inside contracts. And when the 1st flat plate electrode 1a and the 2nd flat plate electrode 1b are fixed to the internal peripheral surface of the 2nd insulating resin 9, the clearance gap between the 1st flat plate electrode 1a and the 2nd flat plate electrode 1b Is narrowed.

そこで、使用温度範囲の下限を第２の硬化温度、上限を第１の硬化温度とすれば、使用温度範囲内において第１の絶縁性樹脂８が収縮し、第２の絶縁性樹脂９が膨張しているので、第１の平板電極１ａと第２の平板電極１ｂとの隙間が狭められる。   Therefore, if the lower limit of the operating temperature range is the second curing temperature and the upper limit is the first curing temperature, the first insulating resin 8 contracts and the second insulating resin 9 expands within the operating temperature range. Therefore, the gap between the first flat plate electrode 1a and the second flat plate electrode 1b is narrowed.

このように平行平板電極１の内側が硬化温度１２０℃で硬化する第１の絶縁性樹脂８で充填され、平行平板電極１の外側が硬化温度２３℃で硬化する第２の絶縁性樹脂９で充填されているので、半導体装置が周囲温度２３℃から１２０℃の間に置かれていると、第１の絶縁性樹脂８に収縮方向の応力が働き、第２の絶縁性樹脂９に膨張方向の熱応力が働く。その結果、平行平板電極１は半導体素子３の接合に押圧力を加えることが出来るため、接合部分の破壊やクラックを防ぐ事ができ、半導体素子３の信頼性が向上する。   Thus, the inside of the parallel plate electrode 1 is filled with the first insulating resin 8 that cures at a curing temperature of 120 ° C., and the outside of the parallel plate electrode 1 is the second insulating resin 9 that cures at a curing temperature of 23 ° C. Since it is filled, when the semiconductor device is placed between 23 ° C. and 120 ° C., the stress in the shrinking direction acts on the first insulating resin 8 and the expansion direction of the second insulating resin 9. The thermal stress of works. As a result, since the parallel plate electrode 1 can apply a pressing force to the bonding of the semiconductor element 3, it is possible to prevent breakage and cracking of the bonded portion and improve the reliability of the semiconductor element 3.

実施の形態２．
この発明の実施の形態１に係る半導体装置では使用温度範囲の下限を第２の硬化温度、上限を第１の硬化温度としているが、この発明の実施の形態２に係る半導体装置では使用温度範囲の下限または上限が第１の硬化温度または第２の硬化温度と異なっている。すなわち、この発明の実施の形態２に係る半導体装置の構成は第１の絶縁性樹脂または第２の絶縁性樹脂の特性を除けば図１に示す半導体装置の構成と同様である。 Embodiment 2. FIG.
In the semiconductor device according to the first embodiment of the present invention, the lower limit of the operating temperature range is the second curing temperature, and the upper limit is the first curing temperature. In the semiconductor device according to the second embodiment of the present invention, the operating temperature range is Is lower than the first curing temperature or the second curing temperature. That is, the configuration of the semiconductor device according to the second embodiment of the present invention is the same as the configuration of the semiconductor device shown in FIG. 1 except for the characteristics of the first insulating resin or the second insulating resin.

以下の説明において用いる第１の絶縁性樹脂８および第２の絶縁性樹脂９の特性を以下のように定義する。
第１の絶縁性樹脂８の第１の硬化温度Ｔ１未満での線膨張率をα１１、第１の硬化温度Ｔ１以上での線膨張率をα１２、第１の硬化温度Ｔ１未満での弾性率をＥ１１、第１の硬化温度Ｔ１以上での弾性率をＥ１２とする。
第２の絶縁性樹脂９の第２の硬化温度Ｔ２未満での線膨張率をα２１、第２の硬化温度Ｔ２以上での線膨張率をα２２、第２の硬化温度Ｔ２未満での弾性率をＥ２１、第２の硬化温度Ｔ２以上での弾性率をＥ２２とする。
また、使用温度範囲の下限をＴ３、上限をＴ４とする。 The characteristics of the first insulating resin 8 and the second insulating resin 9 used in the following description are defined as follows.
The linear expansion coefficient of the first insulating resin 8 below the first curing temperature T 1 is α 11 , the linear expansion coefficient at the first curing temperature T 1 or higher is α 12 , and is less than the first curing temperature T 1. The elastic modulus at E 11 is E 11 , and the elastic modulus at the first curing temperature T 1 or higher is E 12 .
The linear expansion coefficient of the second insulating resin 9 below the second curing temperature T 2 is α 21 , the linear expansion coefficient at the second curing temperature T 2 or higher is α 22 , and is less than the second curing temperature T 2. The elastic modulus at E 21 is E 21 , and the elastic modulus at the second curing temperature T 2 or higher is E 22 .
The lower limit of the operating temperature range is T 3 and the upper limit is T 4 .

熱硬化性樹脂に発生する熱応力は、樹脂の硬化温度で最小になり、硬化温度を超えると樹脂の膨張方向に、硬化温度未満だと樹脂の収縮方向に発生する。
そして、第１の絶縁性樹脂８および第２の絶縁性樹脂９の硬化温度と半導体装置の使用温度範囲により、５つの条件に分類される。
（１）第１の硬化温度Ｔ１が使用温度範囲以下、（２）第１の硬化温度Ｔ１が使用温度範囲内且つ第２の硬化温度Ｔ２が使用温度範囲以下、（３）第１の硬化温度Ｔ１が使用温度範囲の上限Ｔ４未満且つ第２の硬化温度Ｔ２が使用温度範囲の下限Ｔ３を超える、（４）第２の硬化温度Ｔ２が使用温度範囲内且つ第１の硬化温度Ｔ１が使用温度範囲以上、（５）第２の硬化温度Ｔ２が使用温度範囲以上のときの５つの条件である。 The thermal stress generated in the thermosetting resin is minimized at the curing temperature of the resin. When the curing temperature is exceeded, the thermal stress is generated in the expansion direction of the resin.
And it classify | categorizes into five conditions by the curing temperature of the 1st insulating resin 8 and the 2nd insulating resin 9, and the use temperature range of a semiconductor device.
(1) first curing temperature T 1 is temperature range below (2) first curing temperature T 1 is the curing temperature T 2 of the temperature range within and second use temperature range below (3) first the curing temperature T 1 is less than the upper limit T 4 of the operating temperature range and a second curing temperature T 2 exceeds the lower limit T 3 operating temperature range, (4) and first in the second curing temperature T 2 is the operating temperature range 1 of the curing temperature T 1 is temperature range above, (5) second curing temperature T 2 is a five conditions when the above temperature range.

（１）第１の硬化温度Ｔ１が使用温度範囲以下のときについて説明する。第１の硬化温度Ｔ１が使用温度範囲以下であるので、第２の硬化温度Ｔ２も使用温度範囲未満であり、図５に示すように、使用温度範囲内においては第１の絶縁性樹脂８および第２の絶縁性樹脂９の膨張方向に熱応力が発生する。そして、第１の平板電極１ａと第２の平板電極１ｂとに対して、第１の絶縁性樹脂８で発生する熱応力は隙間を拡げるように作用し、第２の絶縁性樹脂９で発生する熱応力は隙間を狭めるように作用する。このとき使用温度範囲内で第１の絶縁性樹脂８で発生する熱応力σ１３４は線膨張率α１２と弾性率Ｅ１２とを用いて式（１）から求められる。また、使用温度範囲内で第２の絶縁性樹脂９で発生する熱応力σ２３４は線膨張率α２２と弾性率Ｅ２２とを用いて式（２）から求められる。 (1) first curing temperature T 1 is explained when the following temperature range. Since the first curing temperature T 1 is equal to or less than the operating temperature range, the second curing temperature T 2 was less than the operating temperature range, as shown in FIG. 5, in the temperature range the first insulating resin Thermal stress is generated in the expansion direction of the 8 and the second insulating resin 9. The thermal stress generated in the first insulating resin 8 acts on the first flat plate electrode 1a and the second flat plate electrode 1b so as to widen the gap and is generated in the second insulating resin 9. The thermal stress that acts acts to narrow the gap. At this time, the thermal stress σ 134 generated in the first insulating resin 8 within the operating temperature range is obtained from the equation (1) using the linear expansion coefficient α 12 and the elastic modulus E 12 . Further, the thermal stress σ 234 generated in the second insulating resin 9 within the operating temperature range is obtained from the equation (2) using the linear expansion coefficient α 22 and the elastic modulus E 22 .

Figure 2009026960
Figure 2009026960

そして、第１の絶縁性樹脂８で発生する熱応力σ１３４と第２の絶縁性樹脂９で発生する熱応力σ２３４は逆方向に働くので、第１の平板電極１ａと第２の平板電極１ｂとに応力が加わって第１の平板電極１ａと第２の平板電極１ｂとの隙間が狭まるときは、第２の絶縁性樹脂９で発生する熱応力σ２３４が第１の絶縁性樹脂８で発生する熱応力σ１３４を超えているときである。 Since the thermal stress σ 134 generated in the first insulating resin 8 and the thermal stress σ 234 generated in the second insulating resin 9 work in opposite directions, the first plate electrode 1a and the second plate electrode When stress is applied to 1b and the gap between the first plate electrode 1a and the second plate electrode 1b is narrowed, the thermal stress σ 234 generated in the second insulating resin 9 becomes the first insulating resin 8. This is when the thermal stress σ 134 generated in the above is exceeded.

（２）第１の硬化温度Ｔ１が使用温度範囲内且つ第２の硬化温度Ｔ２が使用温度範囲以下のときについて説明する。第１の硬化温度Ｔ１が使用温度範囲内であるので、図６に示すように、使用温度範囲の温度Ｔ３〜温度Ｔ１で第１の絶縁性樹脂８の収縮方向、温度Ｔ１〜Ｔ４で第１の絶縁性樹脂８の膨張方向に熱応力が発生する。また、使用温度範囲においては第２の絶縁性樹脂９の膨張方向に熱応力が発生する。 (2) first curing temperature T 1 is operating temperature range and a second curing temperature T 2 will be described when the following temperature range. Since the first curing temperature T 1 is within the operating temperature range, as shown in FIG. 6, shrinkage direction of the first insulating resin 8 at a temperature T 3 ~ temperature T 1 of the temperature range, temperatures T 1 ~ thermal stress is generated in the direction of expansion of the first insulating resin 8 at T 4. Further, thermal stress is generated in the expansion direction of the second insulating resin 9 in the operating temperature range.

そして、使用温度範囲の温度Ｔ３〜温度Ｔ１で第１の平板電極１ａと第２の平板電極１ｂとに対して、第１の絶縁性樹脂および第２の絶縁性樹脂９で発生する熱応力はともに隙間を狭めるように作用する。ゆえに、第１の平板電極１ａと第２の平板電極１ｂとの隙間が狭まり、第１の平板電極１ａと第２の平板電極１ｂとは半導体素子３を押圧する。このように第１の絶縁性樹脂および第２の絶縁性樹脂９で発生する熱応力はともに隙間を狭めるように作用するときは、絶縁特性も向上する。 The heat generated in the first insulating resin and the second insulating resin 9 with respect to the first flat plate electrode 1a and the second flat plate electrode 1b at the temperature T 3 to the temperature T 1 in the operating temperature range. Both stresses act to narrow the gap. Therefore, the gap between the first plate electrode 1 a and the second plate electrode 1 b is narrowed, and the first plate electrode 1 a and the second plate electrode 1 b press the semiconductor element 3. Thus, when both the thermal stress generated in the first insulating resin and the second insulating resin 9 acts to narrow the gap, the insulating characteristics are also improved.

一方、使用温度範囲の温度Ｔ１〜温度Ｔ４で第１の平板電極１ａと第２の平板電極１ｂとに対して、第１の絶縁性樹脂８で発生する熱応力σ１１４は隙間を拡げるように作用し、第２の絶縁性樹脂９で発生する熱応力σ２１４は隙間を狭めるように作用する。このとき使用温度範囲内で第１の絶縁性樹脂８で発生する熱応力σ１１４は線膨張率α１２と弾性率Ｅ１２とを用いて式（３）から求められる。また、使用温度範囲内で第２の絶縁性樹脂９で発生する熱応力σ２１４は線膨張率α２２と弾性率Ｅ２２とを用いて式（４）から求められる。 On the other hand, with respect to the first plate electrode 1a at a temperature T 1 ~ temperature T 4 of the temperature range and the second plate electrode 1b, the thermal stress sigma 114 generated in the first insulating resin 8 is spread the gap The thermal stress σ 214 generated in the second insulating resin 9 acts to narrow the gap. At this time, the thermal stress σ 114 generated in the first insulating resin 8 within the operating temperature range is obtained from the equation (3) using the linear expansion coefficient α 12 and the elastic modulus E 12 . Further, the thermal stress σ 214 generated in the second insulating resin 9 within the operating temperature range is obtained from the equation (4) using the linear expansion coefficient α 22 and the elastic modulus E 22 .

Figure 2009026960
Figure 2009026960

そして、第１の絶縁性樹脂８で発生する熱応力σ１１４と第２の絶縁性樹脂９で発生する熱応力σ２１４は逆方向に働くので、第１の平板電極１ａと第２の平板電極１ｂとに応力が加わって第１の平板電極１ａと第２の平板電極１ｂとの隙間が狭まるときは、第２の絶縁性樹脂９で発生する熱応力σ２１４が第１の絶縁性樹脂８で発生する熱応力σ１１４を超えているときである。 Since the thermal stress σ 114 generated in the first insulating resin 8 and the thermal stress σ 214 generated in the second insulating resin 9 work in opposite directions, the first plate electrode 1a and the second plate electrode When stress is applied to 1b and the gap between the first plate electrode 1a and the second plate electrode 1b is narrowed, the thermal stress σ 214 generated in the second insulating resin 9 becomes the first insulating resin 8. This is when the thermal stress σ 114 generated in the above is exceeded.

（３）第１の硬化温度Ｔ１が使用温度範囲の上限Ｔ４未満且つ第２の硬化温度Ｔ２が使用温度範囲の下限Ｔ３を超えるときについて説明する。第１の硬化温度Ｔ１が使用温度範囲内であるので、図７に示すように、使用温度範囲の温度Ｔ３〜温度Ｔ１で第１の絶縁性樹脂８の収縮方向、温度Ｔ１〜Ｔ４で第１の絶縁性樹脂８の膨張方向に熱応力が発生する。また、第２の硬化温度Ｔ２が使用温度範囲内であるので、図７に示すように、使用温度範囲の温度Ｔ３〜温度Ｔ２で第２の絶縁性樹脂９の収縮方向、温度Ｔ２〜Ｔ４で第２の絶縁性樹脂９の膨張方向に熱応力が発生する。 (3) will be described when the upper limit T 4 and less than the second curing temperature T 2 of the first curing temperature T 1 is temperature range exceeds the lower limit T 3 of the operating temperature range. Since the first curing temperature T 1 is within the operating temperature range, as shown in FIG. 7, shrinkage direction of the first insulating resin 8 at a temperature T 3 ~ temperature T 1 of the temperature range, temperatures T 1 ~ thermal stress is generated in the direction of expansion of the first insulating resin 8 at T 4. Further, since the second hardening temperature T 2 is within the operating temperature range, as shown in FIG. 7, shrinkage direction of the second insulating resin 9 at a temperature T 3 ~ temperature T 2 of the temperature range, the temperature T thermal stress is generated in the 2 through T 4 to the expansion direction of the second insulating resin 9.

そして、使用温度範囲の温度Ｔ２〜温度Ｔ１で第１の平板電極１ａと第２の平板電極１ｂとに対して、第１の絶縁性樹脂８および第２の絶縁性樹脂９で発生する熱応力はともに隙間を狭めるように作用する。ゆえに、第１の平板電極１ａと第２の平板電極１ｂとの隙間が狭まり、第１の平板電極１ａと第２の平板電極１ｂとは半導体素子３を押圧する。このように第１の絶縁性樹脂８および第２の絶縁性樹脂９で発生する熱応力はともに隙間を狭めるように作用するときは、絶縁特性も向上する。 Then, with respect to the first plate electrode 1a at a temperature T 2 ~ temperature T 1 of the temperature range and the second plate electrode 1b, is generated in the first insulating resin 8 and the second insulating resin 9 Both thermal stresses act to narrow the gap. Therefore, the gap between the first plate electrode 1 a and the second plate electrode 1 b is narrowed, and the first plate electrode 1 a and the second plate electrode 1 b press the semiconductor element 3. Thus, when both the thermal stresses generated in the first insulating resin 8 and the second insulating resin 9 act to narrow the gap, the insulating characteristics are also improved.

一方、使用温度範囲の温度Ｔ３〜温度Ｔ２で第１の平板電極１ａと第２の平板電極１ｂとに対して、第１の絶縁性樹脂８で発生する熱応力は隙間を狭めるように作用し、第２の絶縁性樹脂９で発生する熱応力は隙間を拡げるように作用する。このとき温度Ｔ３〜Ｔ２で第１の絶縁性樹脂８で発生する熱応力σ１３２は線膨張率α１１と弾性率Ｅ１１とを用いて式（５）から求められる。また、温度Ｔ３〜温度Ｔ２で第２の絶縁性樹脂９で発生する熱応力σ２３２は線膨張率α２１と弾性率Ｅ２１とを用いて式（６）から求められる。 On the other hand, with respect to the first plate electrode 1a at a temperature T 3 ~ temperature T 2 of the temperature range and the second plate electrode 1b, the thermal stress generated in the first insulating resin 8 so as to narrow the gap The thermal stress generated in the second insulating resin 9 acts to widen the gap. At this time, the thermal stress σ 132 generated in the first insulating resin 8 at temperatures T 3 to T 2 is obtained from the equation (5) using the linear expansion coefficient α 11 and the elastic modulus E 11 . Further, the thermal stress σ 232 generated in the second insulating resin 9 at the temperature T 3 to the temperature T 2 is obtained from the equation (6) using the linear expansion coefficient α 21 and the elastic modulus E 21 .

Figure 2009026960
Figure 2009026960

そして、第１の絶縁性樹脂８で発生する熱応力σ１３２と第２の絶縁性樹脂９で発生する熱応力σ２３２は逆方向に働くので、第１の平板電極１ａと第２の平板電極１ｂとに応力が加わって第１の平板電極１ａと第２の平板電極１ｂとの隙間が狭まるときは、第１の絶縁性樹脂８で発生する熱応力σ１３１が第２の絶縁性樹脂９で発生する熱応力σ２３２を超えているときである。 Since the thermal stress σ 132 generated in the first insulating resin 8 and the thermal stress σ 232 generated in the second insulating resin 9 work in opposite directions, the first plate electrode 1a and the second plate electrode When stress is applied to 1b and the gap between the first flat plate electrode 1a and the second flat plate electrode 1b is narrowed, the thermal stress σ 131 generated in the first insulating resin 8 becomes the second insulating resin 9. This is when the thermal stress σ 232 generated in the above is exceeded.

他方、使用温度範囲の温度Ｔ１〜温度Ｔ４で第１の平板電極１ａと第２の平板電極１ｂとに対して、第１の絶縁性樹脂８で発生する熱応力σ１１４は隙間を拡げるように作用し、第２の絶縁性樹脂９で発生する熱応力σ２１４は隙間を狭めるように作用する。このとき温度Ｔ１〜温度Ｔ４で第１の絶縁性樹脂８で発生する熱応力σ１１４は線膨張率α１２と弾性率Ｅ１２とを用いて式（３）から求められる。また、温度Ｔ１〜温度Ｔ４で第２の絶縁性樹脂９で発生する熱応力σ２１４は線膨張率α２２と弾性率Ｅ２２とを用いて式（４）から求められる。 On the other hand, the thermal stress σ 114 generated in the first insulating resin 8 expands the gap with respect to the first flat plate electrode 1a and the second flat plate electrode 1b in the temperature T 1 to the temperature T 4 in the operating temperature range. The thermal stress σ 214 generated in the second insulating resin 9 acts to narrow the gap. At this time, the thermal stress σ 114 generated in the first insulating resin 8 at the temperature T 1 to the temperature T 4 is obtained from the equation (3) using the linear expansion coefficient α 12 and the elastic modulus E 12 . Further, the thermal stress σ 214 generated in the second insulating resin 9 at the temperature T 1 to the temperature T 4 is obtained from the equation (4) using the linear expansion coefficient α 22 and the elastic modulus E 22 .

そして、第１の絶縁性樹脂８で発生する熱応力σ１１４と第２の絶縁性樹脂９で発生する熱応力σ２１４は逆方向に働くので、第１の平板電極１ａと第２の平板電極１ｂとに応力が加わって第１の平板電極１ａと第２の平板電極１ｂとの隙間が狭まるときは、第２の絶縁性樹脂９で発生する熱応力σ２１４が第１の絶縁性樹脂８で発生する熱応力σ１１４を超えているときである。 Since the thermal stress σ 114 generated in the first insulating resin 8 and the thermal stress σ 214 generated in the second insulating resin 9 work in opposite directions, the first plate electrode 1a and the second plate electrode When stress is applied to 1b and the gap between the first plate electrode 1a and the second plate electrode 1b is narrowed, the thermal stress σ 214 generated in the second insulating resin 9 becomes the first insulating resin 8. This is when the thermal stress σ 114 generated in the above is exceeded.

（４）第２の硬化温度Ｔ２が使用温度範囲内且つ第１の硬化温度Ｔ１が使用温度範囲以上のときについて説明する。第２の硬化温度Ｔ２が使用温度範囲内であるので、図８に示すように、使用温度範囲の温度Ｔ３〜Ｔ２で第２の絶縁性樹脂９の収縮方向、温度Ｔ２〜Ｔ４で第２の絶縁性樹脂９の膨張方向に熱応力が発生する。また、使用温度範囲においては第１の絶縁性樹脂８の収縮方向に熱応力が発生する。 (4) a second curing temperature T 2 is operating temperature range and a first curing temperature T 1 is explained when the above temperature range. Since the second curing temperature T 2 is within the operating temperature range, as shown in FIG. 8, shrinkage direction of the second insulating resin 9 at a temperature T 3 through T 2 of the operating temperature range, temperature T 2 through T 4 , thermal stress is generated in the expansion direction of the second insulating resin 9. Further, thermal stress is generated in the shrinking direction of the first insulating resin 8 in the operating temperature range.

使用温度範囲の温度Ｔ３〜温度Ｔ２で第１の平板電極１ａと第２の平板電極１ｂとに対して、第１の絶縁性樹脂８で発生する熱応力σ１３２は隙間を狭めるように作用し、第２の絶縁性樹脂９で発生する熱応力σ２３２は隙間を拡げるように作用する。このとき使用温度範囲内で第１の絶縁性樹脂８で発生する熱応力σ１３２は線膨張率α１１と弾性率Ｅ１１とを用いて式（５）から求められる。また、使用温度範囲内で第２の絶縁性樹脂９で発生する熱応力σ２３２は線膨張率α２１と弾性率Ｅ２１とを用いて式（６）から求められる。 The thermal stress σ 132 generated in the first insulating resin 8 narrows the gap with respect to the first flat plate electrode 1a and the second flat plate electrode 1b at temperatures T 3 to T 2 in the operating temperature range. The thermal stress σ 232 generated in the second insulating resin 9 acts to widen the gap. At this time, the thermal stress σ 132 generated in the first insulating resin 8 within the operating temperature range is obtained from the equation (5) using the linear expansion coefficient α 11 and the elastic modulus E 11 . Further, the thermal stress σ 232 generated in the second insulating resin 9 within the operating temperature range is obtained from the equation (6) using the linear expansion coefficient α 21 and the elastic modulus E 21 .

そして、第１の絶縁性樹脂８で発生する熱応力σ１３２と第２の絶縁性樹脂９で発生する熱応力σ２３２は逆方向に働くので、第１の平板電極１ａと第２の平板電極１ｂとに応力が加わって第１の平板電極１ａと第２の平板電極１ｂとの隙間が狭まるときは、第１の絶縁性樹脂８で発生する熱応力σ１３２が第２の絶縁性樹脂９で発生する熱応力σ２３２を超えているときである。 Since the thermal stress σ 132 generated in the first insulating resin 8 and the thermal stress σ 232 generated in the second insulating resin 9 work in opposite directions, the first plate electrode 1a and the second plate electrode When stress is applied to 1b and the gap between the first plate electrode 1a and the second plate electrode 1b is narrowed, the thermal stress σ 132 generated in the first insulating resin 8 becomes the second insulating resin 9. This is when the thermal stress σ 232 generated in the above is exceeded.

一方、使用温度範囲の温度Ｔ２〜温度Ｔ４で第１の平板電極１ａと第２の平板電極１ｂとに対して、第１の絶縁性樹脂８および第２の絶縁性樹脂９で発生する熱応力はともに隙間を狭めるように作用する。ゆえに、第１の平板電極１ａと第２の平板電極１ｂとの隙間が狭まり、第１の平板電極１ａと第２の平板電極１ｂとは半導体素子３を押圧する。このように第１の絶縁性樹脂および第２の絶縁性樹脂９で発生する熱応力はともに隙間を狭めるように作用するときは、絶縁特性も向上する。 On the other hand, with respect to the first plate electrode 1a at a temperature T 2 ~ temperature T 4 of the temperature range and the second plate electrode 1b, is generated in the first insulating resin 8 and the second insulating resin 9 Both thermal stresses act to narrow the gap. Therefore, the gap between the first plate electrode 1 a and the second plate electrode 1 b is narrowed, and the first plate electrode 1 a and the second plate electrode 1 b press the semiconductor element 3. Thus, when both the thermal stress generated in the first insulating resin and the second insulating resin 9 acts to narrow the gap, the insulating characteristics are also improved.

（５）第２の硬化温度Ｔ２が使用温度範囲以上のときについて説明する。第２の硬化温度Ｔ２が使用温度範囲以上であるので、第１の硬化温度Ｔ１も使用温度範囲を超えていて、図９に示すように、使用温度範囲内においては第１の絶縁性樹脂８および第２の絶縁性樹脂９の収縮方向に熱応力が発生する。そして、第１の平板電極１ａと第２の平板電極１ｂとに対して、第１の絶縁性樹脂８で発生する熱応力σ’１３４は隙間を狭めるように作用し、第２の絶縁性樹脂９で発生する熱応力σ’２３４は隙間を拡げるように作用する。このとき使用温度範囲内で第１の絶縁性樹脂８で発生する熱応力σ’１３４は線膨張率α１１と弾性率Ｅ１１とを用いて式（７）から求められる。また、使用温度範囲内で第２の絶縁性樹脂９で発生する熱応力σ’２３４は線膨張率α２１と弾性率Ｅ２１とを用いて式（８）から求められる。 (5) second curing temperature T 2 will be described when the above temperature range. Since the second curing temperature T 2 is at operating temperature range of the first curing temperature T 1 of even exceeds the temperature range, as shown in FIG. 9, the first insulating in the temperature range Thermal stress is generated in the shrinking direction of the resin 8 and the second insulating resin 9. The thermal stress σ ′ 134 generated in the first insulating resin 8 acts on the first plate electrode 1a and the second plate electrode 1b so as to narrow the gap, and the second insulating resin. The thermal stress σ ′ 234 generated at 9 acts to widen the gap. At this time, the thermal stress σ ′ 134 generated in the first insulating resin 8 within the operating temperature range is obtained from the equation (7) using the linear expansion coefficient α 11 and the elastic modulus E 11 . Further, the thermal stress σ ′ 234 generated in the second insulating resin 9 within the operating temperature range is obtained from the equation (8) using the linear expansion coefficient α 21 and the elastic modulus E 21 .

Figure 2009026960
Figure 2009026960

そして、第１の絶縁性樹脂８で発生する熱応力σ’１３２と第２の絶縁性樹脂９で発生する熱応力σ’２３２は逆方向に働くので、第１の平板電極１ａと第２の平板電極１ｂとに応力が加わって第１の平板電極１ａと第２の平板電極１ｂとの隙間が狭まるときは、第１の絶縁性樹脂８で発生する熱応力σ’１３４が第２の絶縁性樹脂９で発生する熱応力σ’２３４を超えているときである。 Since the thermal stress σ ′ 132 generated in the first insulating resin 8 and the thermal stress σ ′ 232 generated in the second insulating resin 9 work in opposite directions, the first plate electrode 1a and the second When stress is applied to the flat plate electrode 1b and the gap between the first flat plate electrode 1a and the second flat plate electrode 1b is narrowed, the thermal stress σ ′ 134 generated in the first insulating resin 8 is the second insulation. This is when the thermal stress σ ′ 234 generated in the conductive resin 9 is exceeded.

次に、この発明の実施の形態２に係る半導体装置の実施例を５つの条件毎に１つ示す。
図１０は、実施例の半導体装置の第１の絶縁性樹脂８および第２の絶縁性樹脂９に使用する樹脂の一覧表である。 Next, one example of the semiconductor device according to the second embodiment of the present invention is shown for every five conditions.
FIG. 10 is a list of resins used for the first insulating resin 8 and the second insulating resin 9 of the semiconductor device of the example.

第１の硬化温度Ｔ１が図１１に示すように使用温度範囲以下のときの具体例を示す。
使用温度範囲の下限Ｔ３を１００℃、上限Ｔ４を１４０℃とし、第１の硬化温度Ｔ１が１００℃の第１の絶縁性樹脂８としてのＳＥ１８８６と第２の硬化温度Ｔ２が８０℃の第２の絶縁性樹脂９としてのＥＣＲ−９９００Ｋを用いて半導体装置を封止する。使用温度範囲１００℃〜１４０℃の間で発生する応力は、ＳＥ１８８６のとき７５Ｐａ・℃、ＥＣＲ−９９００Ｋのとき０．６２ＭＰａ・℃であることから、第１の絶縁性樹脂８に発生する熱応力より第２の絶縁性樹脂９に発生する熱応力が大きいので、平行平板電極１の内側方向に押す圧力を加えることができる。 First curing temperature T 1 is show an embodiment of the following temperature range as shown in FIG. 11.
The lower limit T 3 of the operating temperature range is 100 ° C., the upper limit T 4 is 140 ° C., SE 1886 as the first insulating resin 8 with the first curing temperature T 1 being 100 ° C., and the second curing temperature T 2 is 80 ° C. The semiconductor device is sealed using ECR-9900K as the second insulating resin 9 at ° C. Since the stress generated in the operating temperature range of 100 ° C. to 140 ° C. is 75 Pa · ° C. for SE1886 and 0.62 MPa · ° C. for ECR-9900K, the thermal stress generated in the first insulating resin 8 Further, since the thermal stress generated in the second insulating resin 9 is larger, it is possible to apply a pressure that pushes in the inner direction of the parallel plate electrode 1.

第１の硬化温度Ｔ１が図１２に示すように使用温度範囲内且つ第２の硬化温度Ｔ２が使用温度範囲以下のときの具体的な例を示す。
使用温度範囲の下限Ｔ３を１００℃、上限Ｔ４を１４０℃とし、第１の硬化温度Ｔ１が１２０℃の第１の絶縁性樹脂８としてのＫＥ１８３３と第２の硬化温度Ｔ２が８０℃の第２の絶縁性樹脂９としてのＥＣＲ−９９００Ｋを用いて半導体装置を封止する。温度１００℃〜１２０℃の間で発生する熱応力はともに平行平板電極１の内側方向に押す熱応力なので半導体素子３を押圧する力が働き接続の信頼性が向上するとともに、部分放電開始電圧が４．０ｋＶに向上する。
温度１２０℃〜１４０℃の間で発生する応力は、ＫＥ１８３３のとき８．９ＫＰａ・℃、ＥＣＲ−９９００Ｋのとき９３．９ＫＰａ・℃であることから、第１の絶縁性樹脂８に発生する熱応力より第２の絶縁性樹脂９に発生する熱応力が大きいので、平行平板電極１の内側方向に押す圧力を加えることができる。このときの部分放電開始電圧が３．５ｋＶである。 First curing temperature T 1 is shows a specific example when using a temperature range and a second curing temperature T 2 is below operating temperature range as shown in FIG. 12.
The lower limit T 3 of the operating temperature range is 100 ° C., the upper limit T 4 is 140 ° C., KE 1833 as the first insulating resin 8 with the first curing temperature T 1 being 120 ° C., and the second curing temperature T 2 is 80 The semiconductor device is sealed using ECR-9900K as the second insulating resin 9 at ° C. Since the thermal stress generated between the temperatures of 100 ° C. and 120 ° C. is a thermal stress that pushes inward of the parallel plate electrode 1, the force that presses the semiconductor element 3 works to improve the connection reliability and the partial discharge start voltage. Increase to 4.0 kV.
The stress generated between 120 ° C. and 140 ° C. is 8.9 KPa · ° C. when KE1833, and 93.9 KPa · ° C. when ECR-9900K. Therefore, the thermal stress generated in the first insulating resin 8. Further, since the thermal stress generated in the second insulating resin 9 is larger, it is possible to apply a pressure that pushes in the inner direction of the parallel plate electrode 1. The partial discharge start voltage at this time is 3.5 kV.

第１の硬化温度Ｔ１が図１３に示すように使用温度範囲の上限Ｔ４未満且つ第２の硬化温度Ｔ２が使用温度範囲の下限Ｔ３を超えるときの具体的な例を示す。
使用温度範囲の下限Ｔ３を−４０℃、上限Ｔ４を１２５℃とし、第１の硬化温度Ｔ１が１２０℃の第１の絶縁性樹脂８としてのＫＥ１８３３と第２の硬化温度Ｔ２が２３℃の第２の絶縁性樹脂９としてのＫＥ１０３を用いて半導体装置を封止する。
温度−４０℃〜２３℃の間で発生する応力は、ＫＥ１８３３のとき８７ＫＰａ・℃、ＫＥ１０３のとき７２ＫＰａ・℃であることから、第２の絶縁性樹脂９に発生する熱応力より第１の絶縁性樹脂８に発生する熱応力が大きいので、平行平板電極１の内側方向に押す圧力を加えることができる。このときの部分放電開始電圧が３．５ｋＶである。
温度２３℃〜１２０℃の間で発生する熱応力はともに平行平板電極１の内側方向に押すので半導体素子３を押圧する力が働き接続の信頼性が向上するとともに、部分放電開始電圧が４．０ｋＶに向上する。
温度１２０℃〜１２５℃の間で発生する応力は、ＫＥ１８３３のとき２．３ＫＰａ・℃、ＫＥ１０３のとき１２ＫＰａ・℃であることから、第１の絶縁性樹脂８に発生する熱応力より第２の絶縁性樹脂９に発生する熱応力が大きいので、平行平板電極１の内側方向に押す圧力を加えることができる。このときの部分放電開始電圧が３．５ｋＶである。 First curing temperature T 1 is showing a specific example of when the temperature range curing temperature T 2 and the second less than the upper limit T 4 of, as shown in FIG. 13 exceeds the lower limit T 3 of the operating temperature range.
The lower limit T 3 of the operating temperature range is −40 ° C., the upper limit T 4 is 125 ° C., the first curing temperature T 1 is 120 ° C., and KE1833 as the first insulating resin 8 and the second curing temperature T 2 are The semiconductor device is sealed using KE103 as the second insulating resin 9 at 23 ° C.
The stress generated between −40 ° C. and 23 ° C. is 87 KPa · ° C. for KE1833 and 72 KPa · ° C. for KE103. Therefore, the first insulation is greater than the thermal stress generated in the second insulating resin 9. Since the thermal stress generated in the conductive resin 8 is large, it is possible to apply a pressure to push the parallel plate electrode 1 in the inner direction. The partial discharge start voltage at this time is 3.5 kV.
Both the thermal stresses generated between the temperatures of 23 ° C. and 120 ° C. are pushed inward of the parallel plate electrode 1, so that the force of pressing the semiconductor element 3 works to improve the connection reliability and the partial discharge start voltage is 4. Improve to 0 kV.
The stress generated between the temperatures of 120 ° C. and 125 ° C. is 2.3 KPa · ° C. for KE1833 and 12 KPa · ° C. for KE103. Therefore, the second stress is higher than the thermal stress generated in the first insulating resin 8. Since the thermal stress generated in the insulating resin 9 is large, it is possible to apply a pressure that pushes inward of the parallel plate electrode 1. The partial discharge start voltage at this time is 3.5 kV.

第２の硬化温度Ｔ２が図１４に示すように使用温度範囲内且つ第１の硬化温度Ｔ１が使用温度範囲以上のときの具体的な例を示す。
使用温度範囲の下限Ｔ３を１００℃、上限Ｔ４を１４０℃とし、第１の硬化温度Ｔ１が１５０℃の第１の絶縁性樹脂８としてのＥＸ５５０／Ｈ５５０と第２の硬化温度Ｔ２が１２０℃の第２の絶縁性樹脂９としてのＫＥ１８３３を用いて半導体装置を封止する。
温度１００℃〜１２０℃の間で発生する応力は、ＥＸ５５０／Ｈ５５０のとき３．９ＭＰａ・℃、ＫＥ１８３３のとき９．５ＫＰａ・℃であることから、第２の絶縁性樹脂９に発生する熱応力より第１の絶縁性樹脂８に発生する熱応力が大きいので、平行平板電極１の内側方向に押す圧力を加えることができる。このときの部分放電開始電圧が３．５ｋＶである。
温度１２０℃〜１４０℃の間で発生する熱応力はともに平行平板電極１の内側方向に押す熱応力なので半導体素子３を押圧する力が働き接続の信頼性が向上するとともに、部分放電開始電圧が４．０ｋＶに向上する。 Second curing temperature T 2 shows a specific example when using a temperature range and a first curing temperature T 1 is greater than the operating temperature range as shown in FIG. 14.
The lower limit T 3 to 100 ° C. in the temperature range, the upper limit T 4 was a 140 ° C., a first curing temperature T 1 is hardened temperature T 2 and EX550 / H550 of the second as the first insulating resin 8 of 0.99 ° C. The semiconductor device is sealed using KE1833 as the second insulating resin 9 having a temperature of 120.degree.
The stress generated between the temperatures of 100 ° C. and 120 ° C. is 3.9 MPa · ° C. when EX550 / H550 and 9.5 KPa · ° C. when KE1833. Therefore, the thermal stress generated in the second insulating resin 9 Further, since the thermal stress generated in the first insulating resin 8 is larger, it is possible to apply a pressure that pushes in the inner direction of the parallel plate electrode 1. The partial discharge start voltage at this time is 3.5 kV.
Since the thermal stress generated between the temperatures of 120 ° C. and 140 ° C. is a thermal stress that pushes inward of the parallel plate electrode 1, the force that presses the semiconductor element 3 works to improve the connection reliability and the partial discharge start voltage. Increase to 4.0 kV.

第２の硬化温度Ｔ２が図１５に示すように使用温度範囲以上のときの具体的な例を示す。
使用温度範囲の下限Ｔ３を１００℃、上限Ｔ４を１４０℃とし、第１の硬化温度Ｔ１が１５０℃の第１の絶縁性樹脂８としてのＥＸ５５０／Ｈ５５０と第２の硬化温度Ｔ２が１４０℃の第２の絶縁性樹脂９としてのＲＣ６２９５／ＲＨ６２９６を用いて半導体装置を封止する。
使用温度範囲１００℃〜１４０℃の間で発生する応力は、ＥＸ５５０／Ｈ５５０のとき７．４ＭＰａ・℃、ＲＣ６２９５／ＲＨ６２９６のとき５．２ＭＰａ・℃であることから、第２の絶縁性樹脂９に発生する熱応力より第１の絶縁性樹脂８に発生する熱応力が大きいので、平行平板電極１の内側方向に押す圧力を加えることができる。 Second curing temperature T 2 shows a specific example of when the above temperature range, as shown in FIG. 15.
The lower limit T 3 to 100 ° C. in the temperature range, the upper limit T 4 was a 140 ° C., a first curing temperature T 1 is hardened temperature T 2 and EX550 / H550 of the second as the first insulating resin 8 of 0.99 ° C. The semiconductor device is sealed using RC6295 / RH6296 as the second insulating resin 9 at 140 ° C.
The stress generated in the operating temperature range of 100 ° C. to 140 ° C. is 7.4 MPa · ° C. for EX550 / H550 and 5.2 MPa · ° C. for RC6295 / RH6296. Since the thermal stress generated in the first insulating resin 8 is larger than the generated thermal stress, it is possible to apply a pressure that pushes in the inner direction of the parallel plate electrode 1.

実施の形態３．
図１６は、この発明の実施の形態３に係る半導体装置の断面図である。
この発明の実施の形態３に係る半導体装置は、この発明の実施の形態１に係る半導体装置に平行平板電極１の間に設けられる壁１２を追加したことが異なっており、それ以外は同様であるので、同様な部分に同じ符号を付記し説明は省略する。 Embodiment 3 FIG.
FIG. 16 is a cross-sectional view of a semiconductor device according to Embodiment 3 of the present invention.
The semiconductor device according to the third embodiment of the present invention is different from the semiconductor device according to the first embodiment of the present invention in that a wall 12 provided between the parallel plate electrodes 1 is added. Therefore, the same reference numerals are attached to the same parts, and the description is omitted.

壁１２は、平行平板電極１の一側端部に設けられ、第１の平板電極１ａ、第２の平板電極１ｂおよび中間電極２と密着する絶縁性のシリコーン樹脂からできている。
なお、壁１２の材質は、シリコーン樹脂に限るものではなく、密着性と絶縁性とを有する樹脂であれば良く、例えば、エポキシ樹脂、アクリル樹脂、ウレタン樹脂などの熱硬化性樹脂、ＰＰＳ、ポリエチレン、ＰＥＴなどの熱可塑性樹脂を用いても良い。
また、シリカ、アルミナなどのセラミック粒子を充填して、線膨張率や弾性率を調節しても良い。 The wall 12 is provided at one end of the parallel plate electrode 1 and is made of an insulating silicone resin that is in close contact with the first plate electrode 1 a, the second plate electrode 1 b, and the intermediate electrode 2.
The material of the wall 12 is not limited to a silicone resin, and may be any resin having adhesion and insulating properties. For example, thermosetting resin such as epoxy resin, acrylic resin, urethane resin, PPS, polyethylene, etc. A thermoplastic resin such as PET may be used.
In addition, ceramic particles such as silica and alumina may be filled to adjust the linear expansion coefficient and elastic modulus.

また、この発明の実施の形態３に係る半導体装置では、平行平板電極１の間に２箇所の壁１２を設けているが、これに限定するものではなく、平行平板電極１の間であれば幾つ設けても良い。
また、この発明の実施の形態３に係る半導体装置では、平行平板電極１の一側端部に壁１２を設けているが、複数の壁を設けるときには、平行平板電極１の内側と外側とを隔てる箇所に設けていれば、何処に壁１２を設けても構わない。
図１６では、壁の断面形状は矩形の形状をしているが、この形状に限定するものではなく、断面形状が円形、楕円形、多曲線から成る形状でもよく、平行平板電極の内部と外部を隔てる構造であれば構わない。 Further, in the semiconductor device according to the third embodiment of the present invention, the two walls 12 are provided between the parallel plate electrodes 1, but the present invention is not limited to this. Any number may be provided.
In the semiconductor device according to the third embodiment of the present invention, the wall 12 is provided at one end of the parallel plate electrode 1. However, when a plurality of walls are provided, the inner side and the outer side of the parallel plate electrode 1 are provided. The wall 12 may be provided anywhere as long as the wall 12 is provided at a separated location.
In FIG. 16, the cross-sectional shape of the wall is a rectangular shape, but the wall shape is not limited to this shape, and the cross-sectional shape may be a circle, an ellipse, or a multi-curve shape. Any structure can be used as long as they are separated.

次に、この発明の実施の形態３に係る半導体装置の製造方法を説明する。
第１の平板電極１ａ、第２の平板電極１ｂおよび中間電極２に銅、ケース７にＰＰＳ、接合材４にはんだ、半導体素子３にＳｉＣを使用した半導体装置で、図１６に示すように、半導体素子３を平行平板電極１に実装を行った後に、信越化学工業製一液型シリコーンゴムコンパウンドＫＥ１８３３を注射器より塗出して、平行平板電極１の一側端部に壁状に形成し、硬化温度１２０℃で６０分間硬化して平行平板電極１の一側端部に壁１２を設ける。
このとき、壁１２の断面形状は、多曲線から囲まれた形状で形成されるが、平行平板電極の内部と外部を隔てる形状であれば構わない。壁１２を設けた後に、平行平板電極１の内側に第１の絶縁性樹脂８となる信越化学工業製一液型シリコーンゴムコンパウンドＫＥ１８３３を注入、脱泡し、硬化温度１２０℃で６０分間硬化し、その後、平行平板電極１の外側でケース７により囲まれた空間に第２の絶縁性樹脂９となる信越化学工業製二液付加型シリコーンゴムコンパウンドＫＥ１０３を注入、脱泡し、硬化温度２３℃で７２時間硬化して半導体装置を作成する。 Next, a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described.
A semiconductor device using copper for the first plate electrode 1a, second plate electrode 1b and intermediate electrode 2, PPS for the case 7, solder for the bonding material 4, and SiC for the semiconductor element 3, as shown in FIG. After mounting the semiconductor element 3 on the parallel plate electrode 1, a one-part silicone rubber compound KE1833 manufactured by Shin-Etsu Chemical Co., Ltd. is applied from a syringe to form a wall at one end of the parallel plate electrode 1 and cured. The wall 12 is provided at one end of the parallel plate electrode 1 by curing at a temperature of 120 ° C. for 60 minutes.
At this time, the cross-sectional shape of the wall 12 is formed in a shape surrounded by a multi-curve, but any shape that separates the inside and the outside of the parallel plate electrode may be used. After the wall 12 is provided, a one-part silicone rubber compound KE1833 manufactured by Shin-Etsu Chemical Co., Ltd., which becomes the first insulating resin 8, is injected inside the parallel plate electrode 1, defoamed, and cured at a curing temperature of 120 ° C. for 60 minutes. Thereafter, the two-component addition type silicone rubber compound KE103 manufactured by Shin-Etsu Chemical Co., which becomes the second insulating resin 9 is injected into the space surrounded by the case 7 outside the parallel plate electrode 1, defoamed, and the curing temperature is 23 ° C. To cure for 72 hours to make a semiconductor device.

この発明の実施の形態３に係る半導体装置では、平行平板電極１の間に所定の高さの壁１２を設けているために、平行平板電極１の外部を封止する第２の絶縁性樹脂９に亀裂が入っても、内部を封止する第１の絶縁性樹脂８に影響を及ぼすことがないため、半導体装置の信頼性が向上する。
また、壁１２により第１の絶縁性樹脂８と第２の絶縁性樹脂９を隔離することで、第２の絶縁性樹脂９が吸湿してもその水分が第１の絶縁性樹脂８に拡散することを防げるため、半導体装置の絶縁信頼性が向上する。
また、平行平板電極１の間に所定の高さの壁１２を設けることで、封止を行う際も容易に別々の樹脂を注入することができ、半導体装置を製造する工程を減らすことができる。 In the semiconductor device according to the third embodiment of the present invention, since the wall 12 having a predetermined height is provided between the parallel plate electrodes 1, the second insulating resin that seals the outside of the parallel plate electrode 1 is used. Even if a crack is generated in 9, the first insulating resin 8 that seals the inside is not affected, so that the reliability of the semiconductor device is improved.
In addition, by separating the first insulating resin 8 and the second insulating resin 9 by the wall 12, even if the second insulating resin 9 absorbs moisture, the moisture diffuses into the first insulating resin 8. Therefore, the insulation reliability of the semiconductor device is improved.
Further, by providing the wall 12 having a predetermined height between the parallel plate electrodes 1, it is possible to easily inject different resins even when sealing, and the number of steps for manufacturing the semiconductor device can be reduced. .

実施の形態４．
図１７は、この発明の実施の形態４に係る半導体装置の断面図である。
この発明の実施の形態４に係る半導体装置は、この発明の実施の形態１に係る半導体装置に平行平板電極１の外周に設けられる補強板１３を追加したことが異なっており、それ以外は同様であるので、同様な部分に同じ符号を付記し説明は省略する。 Embodiment 4 FIG.
FIG. 17 is a cross-sectional view of a semiconductor device according to Embodiment 4 of the present invention.
The semiconductor device according to the fourth embodiment of the present invention is different from the semiconductor device according to the first embodiment of the present invention in that a reinforcing plate 13 provided on the outer periphery of the parallel plate electrode 1 is added. Therefore, the same reference numerals are added to the same parts, and the description is omitted.

平行平板電極の外周部に設ける補強板１３は、電極と密着する絶縁性の樹脂でできており、エポキシ樹脂を用いるが、これに限定するものではなく、シリコーン樹脂、アクリル樹脂、ウレタン樹脂など熱硬化性樹脂を用いても良く、ＰＰＳ、ポリエチレン、ＰＥＴなどの熱可塑性樹脂を用いても良く、絶縁性を持つ樹脂であれば構わない。
また、ポリイミドテープなどテープによって補強板１３を構成しても良い。
また、絶縁性の樹脂には、シリカ、アルミナなどのセラミック粒子を充填して、線膨張率や弾性率を調節しても良く、密着性と絶縁性が確保できる樹脂であれば構わない。 The reinforcing plate 13 provided on the outer peripheral portion of the parallel plate electrode is made of an insulating resin that is in close contact with the electrode and uses an epoxy resin, but is not limited to this, and heat such as a silicone resin, an acrylic resin, or a urethane resin is used. A curable resin may be used, a thermoplastic resin such as PPS, polyethylene, or PET may be used, and any resin having an insulating property may be used.
Moreover, you may comprise the reinforcement board 13 with tapes, such as a polyimide tape.
Further, the insulating resin may be filled with ceramic particles such as silica and alumina to adjust the linear expansion coefficient and the elastic modulus, and any resin can be used as long as adhesion and insulation can be ensured.

なお、この発明の実施の形態４に係る半導体装置では、平行平板電極１の外周に１箇所の補強板１３を設けているが、これに限定するものではなく、平行平板電極１の外周であれば、いくつ補強板１３を設けても良い。
また、図１７では、補強板１３の断面形状は矩形の形状をしているが、この形状に限定するものではなく、断面形状が円形、楕円形、多曲線から成る形状でもよく、電極外周部と密着できる構造であれば構わない。 In the semiconductor device according to the fourth embodiment of the present invention, one reinforcing plate 13 is provided on the outer periphery of the parallel plate electrode 1. However, the present invention is not limited to this. Any number of reinforcing plates 13 may be provided.
In FIG. 17, the cross-sectional shape of the reinforcing plate 13 is a rectangular shape, but the shape is not limited to this shape, and the cross-sectional shape may be a circular shape, an elliptical shape, or a multi-curve shape. Any structure can be used as long as it can be closely attached.

次に、この発明の実施の形態４に係る半導体装置の製造方法を説明する。
第１の平板電極１ａ、第２の平板電極１ｂおよび中間電極２に銅、ケース７にＰＰＳ、接合材４にはんだ、半導体素子３にＳｉＣを使用した半導体装置で、図１７に示すように、半導体素子３を平行平板電極１に実装を行った後に、厚さ０．０７ｍｍのポリイミドテープ（３Ｍ社製５４１９）を使用して電極外周部を補強して補強板１３とする。このように補強板１３で平行平板電極１の一端部を固定することにより第１の絶縁性樹脂８を内側に注入しても平行平板電極１が拡がらずに固定される。
次に、平行平板電極１の内側に第１の絶縁性樹脂８となる信越化学工業製一液型シリコーンゴムコンパウンドＫＥ１８３３を注入、脱泡し、硬化温度１２０℃で６０分間硬化し、その後、平行平板電極１の外側でケース７により囲まれた空間に第２の絶縁性樹脂９となる信越化学工業製二液付加型シリコーンゴムコンパウンドＫＥ１０３を注入、脱泡し、硬化温度２３℃で７２時間硬化して半導体装置を作成する。 Next, a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention will be described.
A semiconductor device using copper for the first plate electrode 1a, second plate electrode 1b and intermediate electrode 2, PPS for the case 7, solder for the bonding material 4, and SiC for the semiconductor element 3, as shown in FIG. After mounting the semiconductor element 3 on the parallel plate electrode 1, the outer periphery of the electrode is reinforced by using a polyimide tape (5419 manufactured by 3M) with a thickness of 0.07 mm to obtain the reinforcing plate 13. In this way, by fixing one end of the parallel plate electrode 1 with the reinforcing plate 13, the parallel plate electrode 1 is fixed without expanding even if the first insulating resin 8 is injected inside.
Next, a one-part silicone rubber compound KE1833 manufactured by Shin-Etsu Chemical Co., Ltd., which becomes the first insulating resin 8, is injected inside the parallel plate electrode 1, defoamed, cured at 120 ° C. for 60 minutes, and then parallel A two-component addition type silicone rubber compound KE103 manufactured by Shin-Etsu Chemical Co., Ltd., which becomes the second insulating resin 9, is injected into the space surrounded by the case 7 outside the plate electrode 1, defoamed, and cured at a curing temperature of 23 ° C. for 72 hours. Thus, a semiconductor device is produced.

この発明の実施の形態４に係る半導体装置では、平行平板電極１の外周部分を補強板１３で囲うことで、ヒートサイクル試験などの環境下でも平行平板電極１の間隔が広がることが無く、半導体装置の信頼性がさらに向上する。
また、補強板１３を設けているので、平行平板電極１の外部を封止する樹脂に亀裂が入っても、内部を封止する樹脂に影響を及ぼすことがないため、半導体装置の信頼性が向上する。
また、平行平板電極１の内部を封止する第１の絶縁性樹脂８と外部を封止する絶縁性樹脂９を隔離することで、第２の絶縁性樹脂９の水分吸湿が、第１の絶縁性樹脂に拡散することを防げるため、半導体装置の絶縁信頼性が向上する。
また、平行平板電極１の外周部に補強板１３が設けられているので、封止を行う際も容易に別々の樹脂を注入することができ、半導体装置を製造する工程を減らすことができる。 In the semiconductor device according to the fourth embodiment of the present invention, by surrounding the outer peripheral portion of the parallel plate electrode 1 with the reinforcing plate 13, the interval between the parallel plate electrodes 1 does not increase even under an environment such as a heat cycle test. The reliability of the device is further improved.
In addition, since the reinforcing plate 13 is provided, even if a crack occurs in the resin that seals the outside of the parallel plate electrode 1, the resin that seals the inside is not affected. improves.
Further, by isolating the first insulating resin 8 that seals the inside of the parallel plate electrode 1 from the insulating resin 9 that seals the outside, the moisture absorption of the second insulating resin 9 Since the diffusion to the insulating resin can be prevented, the insulation reliability of the semiconductor device is improved.
In addition, since the reinforcing plate 13 is provided on the outer peripheral portion of the parallel plate electrode 1, it is possible to easily inject different resins even when sealing, and the number of steps for manufacturing the semiconductor device can be reduced.

この発明の実施の形態１に係る半導体装置の一例の断面図である。It is sectional drawing of an example of the semiconductor device which concerns on Embodiment 1 of this invention. この発明の実施の形態１に係る半導体装置の他の例の断面図である。It is sectional drawing of the other example of the semiconductor device which concerns on Embodiment 1 of this invention. この発明の実施の形態１に係る平行平板電極に加わる応力の様子を示す断面図である。It is sectional drawing which shows the mode of the stress added to the parallel plate electrode which concerns on Embodiment 1 of this invention. この発明の実施の形態１に係る第１の絶縁性樹脂および第２の絶縁性樹脂に発生する熱応力の向きを周囲温度をパラメータとして表した線図である。It is the diagram which represented the direction of the thermal stress which generate | occur | produces in the 1st insulating resin and 2nd insulating resin which concern on Embodiment 1 of this invention as a parameter of ambient temperature. この発明の実施の形態２に係る半導体装置の条件１での第１の絶縁性樹脂および第２の絶縁性樹脂に発生する熱応力の向きを周囲温度をパラメータとして表した線図である。It is the diagram which represented the direction of the thermal stress which generate | occur | produces in the 1st insulating resin and the 2nd insulating resin in the conditions 1 of the semiconductor device concerning Embodiment 2 of this invention as a parameter of ambient temperature. この発明の実施の形態２に係る半導体装置の条件２での第１の絶縁性樹脂および第２の絶縁性樹脂に発生する熱応力の向きを周囲温度をパラメータとして表した線図である。It is the diagram which represented the direction of the thermal stress which generate | occur | produces in the 1st insulating resin and the 2nd insulating resin on condition 2 of the semiconductor device which concerns on Embodiment 2 of this invention as a parameter of ambient temperature. この発明の実施の形態２に係る半導体装置の条件３での第１の絶縁性樹脂および第２の絶縁性樹脂に発生する熱応力の向きを周囲温度をパラメータとして表した線図である。It is the diagram which represented the direction of the thermal stress which generate | occur | produces in the 1st insulating resin and the 2nd insulating resin in the conditions 3 of the semiconductor device concerning Embodiment 2 of this invention as a parameter of ambient temperature. この発明の実施の形態２に係る半導体装置の条件４での第１の絶縁性樹脂および第２の絶縁性樹脂に発生する熱応力の向きを周囲温度をパラメータとして表した線図である。It is the diagram which represented the direction of the thermal stress which generate | occur | produces in the 1st insulating resin and the 2nd insulating resin on condition 4 of the semiconductor device which concerns on Embodiment 2 of this invention as a parameter of ambient temperature. この発明の実施の形態２に係る半導体装置の条件５での第１の絶縁性樹脂および第２の絶縁性樹脂に発生する熱応力の向きを周囲温度をパラメータとして表した線図である。It is the diagram which represented the direction of the thermal stress which generate | occur | produces in the 1st insulating resin and the 2nd insulating resin on condition 5 of the semiconductor device which concerns on Embodiment 2 of this invention as a parameter of ambient temperature. この発明の実施の形態２に係る半導体装置の実施例で第１の絶縁性樹脂および第２の絶縁性樹脂に使用する樹脂の一覧表である。It is a list of resin used for the 1st insulating resin and the 2nd insulating resin in the example of the semiconductor device concerning Embodiment 2 of this invention. この発明の実施の形態２に係る半導体装置の実施例１で平行平板電極に加わる力の向きと熱応力とを表した線図である。It is the diagram showing the direction of the force added to a parallel plate electrode, and the thermal stress in Example 1 of the semiconductor device which concerns on Embodiment 2 of this invention. この発明の実施の形態２に係る半導体装置の実施例２で平行平板電極に加わる力の向きと熱応力とを表した線図である。It is the diagram showing the direction of the force added to a parallel plate electrode, and the thermal stress in Example 2 of the semiconductor device which concerns on Embodiment 2 of this invention. この発明の実施の形態２に係る半導体装置の実施例３で平行平板電極に加わる力の向きと熱応力とを表した線図である。It is the diagram showing the direction of the force added to a parallel plate electrode, and the thermal stress in Example 3 of the semiconductor device which concerns on Embodiment 2 of this invention. この発明の実施の形態２に係る半導体装置の実施例４で平行平板電極に加わる力の向きと熱応力とを表した線図である。It is the diagram showing the direction of the force added to a parallel plate electrode, and the thermal stress in Example 4 of the semiconductor device which concerns on Embodiment 2 of this invention. この発明の実施の形態２に係る半導体装置の実施例５で平行平板電極に加わる力の向きと熱応力とを表した線図である。It is the diagram showing the direction of the force added to a parallel plate electrode, and the thermal stress in Example 5 of the semiconductor device which concerns on Embodiment 2 of this invention. この発明の実施の形態３に係る半導体装置の一例の断面図である。It is sectional drawing of an example of the semiconductor device which concerns on Embodiment 3 of this invention. この発明の実施の形態４に係る半導体装置の一例の断面図である。It is sectional drawing of an example of the semiconductor device which concerns on Embodiment 4 of this invention.

符号の説明Explanation of symbols

１ 平行平板電極、１ａ 第１の平板電極、１ｂ 第２の平板電極、２ 中間電極、３ 半導体素子、４ 接合材、５ 外部端子、６ 配線、７ ケース、８ 第１の絶縁性樹脂、９ 第２の絶縁性樹脂、１１ バネ、１２ 壁、１３ 補強板。   DESCRIPTION OF SYMBOLS 1 Parallel plate electrode, 1a 1st plate electrode, 1b 2nd plate electrode, 2 Intermediate electrode, 3 Semiconductor element, 4 Bonding material, 5 External terminal, 6 Wiring, 7 Case, 8 1st insulating resin, 9 Second insulating resin, 11 spring, 12 wall, 13 reinforcing plate.

Claims (5)

所定の隙間を形成するよう平行に離間する２枚の平板からなる平行平板電極と、
上記隙間に配置されるとともに上記２枚の平板に実装される半導体素子と、
上記隙間を埋めるとともに第１の硬化温度で硬化される第１の絶縁性樹脂と、
上記平行平板電極の外周を包むとともに上記第１の硬化温度未満の第２の硬化温度で硬化される第２の絶縁性樹脂と、
を有し、
使用温度範囲において上記隙間が狭くなるよう上記２枚の平板に上記第１の絶縁性樹脂に発生する熱応力と上記第２の絶縁性樹脂に発生する熱応力との和が加わることを特徴とする半導体装置。 A parallel plate electrode composed of two flat plates spaced in parallel to form a predetermined gap;
A semiconductor element disposed in the gap and mounted on the two flat plates;
A first insulating resin that fills the gap and is cured at a first curing temperature;
A second insulating resin that wraps around the outer periphery of the parallel plate electrode and is cured at a second curing temperature lower than the first curing temperature;
Have
The sum of the thermal stress generated in the first insulating resin and the thermal stress generated in the second insulating resin is applied to the two flat plates so that the gap becomes narrow in the operating temperature range. Semiconductor device. 上記第１の硬化温度が上記使用温度範囲以上且つ上記第２の硬化温度が上記使用温度範囲以下であることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the first curing temperature is not less than the use temperature range and the second cure temperature is not more than the use temperature range. 上記第１の硬化温度が上記使用温度範囲以下または上記第１の硬化温度が上記使用温度範囲内且つ上記第２の硬化温度が上記使用温度範囲以下のとき、上記第１の絶縁性樹脂に外力が加わっていない場合に上記第１の絶縁性樹脂が熱膨張することにより上記隙間が拡がる分を元に戻せる力を超える力で上記第２の絶縁性樹脂が熱膨張することにより上記隙間を狭め、
上記第２の硬化温度が上記使用温度範囲内且つ上記第１の硬化温度が上記使用温度範囲以上または上記第２の硬化温度が上記使用温度範囲以上のとき、上記第２の絶縁性樹脂に外力が加わっていない場合に上記第２の絶縁性樹脂が熱収縮することにより上記隙間が拡がる分を元に戻せる力を超える力で上記第１の絶縁性樹脂が熱収縮することにより上記隙間を狭め、
上記第１の硬化温度が上記使用温度範囲の上限未満且つ上記第２の硬化温度が上記使用温度範囲の下限を超えるとき、上記第１の絶縁性樹脂に外力が加わっていない場合に上記第１の絶縁性樹脂が熱膨張することにより上記隙間が拡がる分を元に戻せる力を超える力で上記第２の絶縁性樹脂が熱膨張することにより上記隙間を狭め、また、上記第２の絶縁性樹脂に外力が加わっていない場合に上記第２の絶縁性樹脂が熱収縮することにより上記隙間が拡がる分を元に戻せる力を超える力で上記第１の絶縁性樹脂が熱収縮することにより上記隙間を狭めることを特徴とする請求項１に記載の半導体装置。 When the first curing temperature is equal to or lower than the use temperature range, or the first cure temperature is within the use temperature range and the second cure temperature is equal to or less than the use temperature range, an external force is applied to the first insulating resin. When the first insulating resin is not expanded, the second insulating resin is thermally expanded with a force exceeding the force that can restore the expansion of the gap due to thermal expansion of the first insulating resin, thereby narrowing the gap. ,
When the second curing temperature is within the use temperature range and the first cure temperature is not less than the use temperature range or the second cure temperature is not less than the use temperature range, an external force is applied to the second insulating resin. When the second insulating resin is not shrunk, the first insulating resin is thermally contracted by a force that exceeds the force by which the amount of expansion of the gap due to the thermal contraction of the second insulating resin can be reduced. ,
When the first curing temperature is less than the upper limit of the operating temperature range and the second curing temperature exceeds the lower limit of the operating temperature range, the first insulating resin is not applied with an external force. The second insulating resin thermally expands with a force that exceeds the force that can restore the amount of expansion of the gap due to thermal expansion of the insulating resin, and the second insulating resin narrows the gap. When the external insulation force is not applied to the resin, the first insulating resin is thermally contracted with a force that exceeds the force that can restore the amount that the gap expands due to the thermal contraction of the second insulating resin. The semiconductor device according to claim 1, wherein the gap is narrowed. 上記隙間の外縁部に設けられた壁を有することを特徴とする請求項１乃至３のいずれか一項に記載の半導体装置。   The semiconductor device according to claim 1, further comprising a wall provided at an outer edge of the gap. 上記平行平板電極の外周部に設けられた補強板を有することを特徴とする請求項１乃至３のいずれか一項に記載の半導体装置。   4. The semiconductor device according to claim 1, further comprising a reinforcing plate provided on an outer peripheral portion of the parallel plate electrode.
JP2007188634A 2007-07-19 2007-07-19 Semiconductor device Pending JP2009026960A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012009569A (en) * 2010-06-23 2012-01-12 Denso Corp Semiconductor module manufacturing method
JP2012009568A (en) * 2010-06-23 2012-01-12 Denso Corp Semiconductor module
JP2016115870A (en) * 2014-12-17 2016-06-23 新光電気工業株式会社 Semiconductor device and manufacturing method of the same
WO2019038906A1 (en) * 2017-08-25 2019-02-28 三菱電機株式会社 Power semiconductor device and method for manufacturing power semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012009569A (en) * 2010-06-23 2012-01-12 Denso Corp Semiconductor module manufacturing method
JP2012009568A (en) * 2010-06-23 2012-01-12 Denso Corp Semiconductor module
JP2016115870A (en) * 2014-12-17 2016-06-23 新光電気工業株式会社 Semiconductor device and manufacturing method of the same
WO2019038906A1 (en) * 2017-08-25 2019-02-28 三菱電機株式会社 Power semiconductor device and method for manufacturing power semiconductor device
JPWO2019038906A1 (en) * 2017-08-25 2019-11-07 三菱電機株式会社 Power semiconductor device and method for manufacturing power semiconductor device

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