JP2009021530A - Insulating resin film and power module - Google Patents

Insulating resin film and power module Download PDF

Info

Publication number
JP2009021530A
JP2009021530A JP2007185016A JP2007185016A JP2009021530A JP 2009021530 A JP2009021530 A JP 2009021530A JP 2007185016 A JP2007185016 A JP 2007185016A JP 2007185016 A JP2007185016 A JP 2007185016A JP 2009021530 A JP2009021530 A JP 2009021530A
Authority
JP
Japan
Prior art keywords
adhesive
resin film
adhesive layer
insulating resin
filler
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007185016A
Other languages
Japanese (ja)
Inventor
Takuji Kozu
卓司 神頭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2007185016A priority Critical patent/JP2009021530A/en
Publication of JP2009021530A publication Critical patent/JP2009021530A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4846Connecting portions with multiple bonds on the same bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13062Junction field-effect transistor [JFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Abstract

<P>PROBLEM TO BE SOLVED: To provide a filler structure that is suitable for being mixed in an adhesive at a high filling factor, and provide an adhesive layer using the same and a power module. <P>SOLUTION: A power module 10 is provided with a semiconductor chip 11, a heat sink 21, a metal wiring 23, an insulating resin film 26 provided between the metal wiring 23 and the heat sink 21, and a solder layer 14. The insulating resin film 26 has a first adhesive layer 26a formed by mixing a filler F in the adhesive E, and a second adhesive layer 26b provided on the upper and lower surfaces of the first adhesive layer 26a and substantially comprising only an adhesive. By the second adhesive layer 26b, the adhesive strength between the first adhesive layer 26a with the comparatively low adhesive strength due to the filler F and the adherend surface is enhanced. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、無機絶縁性材料からなるフィラーを混入した絶縁性樹脂膜およびパワーモジュールに関する。   The present invention relates to an insulating resin film and a power module mixed with a filler made of an inorganic insulating material.

図10は、従来のIGBTチップを搭載したパワーモジュールの構造を示す断面図である。同図に示すように、CuMo等により構成されている放熱基板101の主面側には、放熱基板101に、半田層102により固定されたAl板104と、Al板104の主面にAlろうによって固定されたAlN板106と、AlN板106の主面にAlろうによって固定されたAl配線108と、Al配線108の上に、半田層109により固定された半導体チップ120とを備えている。また、放熱基板101の裏面側には、グリース112によりフィン付きのヒートシンク113が取り付けられている。上記Al板104,AlN板106およびAl配線108は、DBA基板として一体的に用いられている。   FIG. 10 is a cross-sectional view showing the structure of a power module on which a conventional IGBT chip is mounted. As shown in the figure, on the main surface side of the heat radiating substrate 101 made of CuMo or the like, an Al plate 104 fixed to the heat radiating substrate 101 by a solder layer 102 and an Al solder on the main surface of the Al plate 104. The AlN plate 106 fixed by the above, the Al wiring 108 fixed to the main surface of the AlN plate 106 by Al solder, and the semiconductor chip 120 fixed by the solder layer 109 on the Al wiring 108 are provided. Further, a heat sink 113 with fins is attached to the rear surface side of the heat dissipation substrate 101 with grease 112. The Al plate 104, AlN plate 106, and Al wiring 108 are integrally used as a DBA substrate.

このように、Al板104,AlN板106およびAl配線108をDBA基板(絶縁層を含む配線部材)として用いたパワーモジュールの構造は、たとえば、特許文献1に記載されている(同文献の図5参照)。同図には、チップ直下の半田層(同図の符号122)には、液相点が300℃〜330℃の高融点半田(Sn−90%Pb)を用い、下方の半田層(同図の符号125)には、液相点が216℃程度の低融点半田(Sn−50%Pb)を用いている例が開示されている。なお、本明細書においては、組成割合を表す「%」は、重量%を示すものとする。
特開2001−168256号公報
As described above, the structure of a power module using the Al plate 104, the AlN plate 106, and the Al wiring 108 as a DBA substrate (wiring member including an insulating layer) is described in, for example, Patent Document 1 (FIG. 1). 5). In the figure, a high melting point solder (Sn-90% Pb) having a liquidus point of 300 ° C. to 330 ° C. is used for a solder layer (reference numeral 122 in the figure) immediately below the chip, and a lower solder layer (same figure). 125) discloses an example in which a low melting point solder (Sn-50% Pb) having a liquidus point of about 216 ° C. is used. In the present specification, “%” representing the composition ratio represents weight%.
JP 2001-168256 A

上記図10に開示される構造では、互いに融点が異なる2つの半田層102,109が設けられている。一般に、コストの上昇を回避したい場合には、できるだけ高融点のろう材(たとえば、特許文献1に記載されているような,融点が600℃程度のAl−11%Si−2%Mg)の使用を避けて、リフロー炉を利用できる半田を用いる。そこで、図10に示す下方の半田層102には、たとえば特許文献1における低融点半田(Sn−50%Pb)や、液相点が183℃程度の共晶半田(Sn−37%Pb)を用い、上方の半田層109には、たとえば液相点が300℃〜330℃の高融点半田(Sn−90%Pbなど)を用いるのが一般的である。すなわち、先の半田付け工程では高融点半田を用い、後の半田付け工程では、先の工程で形成された半田層がリフロー炉内で融解しないように、低融点半田を用いるのである。   In the structure disclosed in FIG. 10, two solder layers 102 and 109 having different melting points are provided. Generally, when it is desired to avoid an increase in cost, the use of a solder having a melting point as high as possible (for example, Al-11% Si-2% Mg having a melting point of about 600 ° C. as described in Patent Document 1) Use solder that can use a reflow oven. Therefore, for example, low melting point solder (Sn-50% Pb) in Patent Document 1 or eutectic solder (Sn-37% Pb) having a liquidus point of about 183 ° C. is used for the lower solder layer 102 shown in FIG. As the upper solder layer 109, for example, a high melting point solder (Sn-90% Pb or the like) having a liquidus point of 300 ° C. to 330 ° C. is generally used. That is, high melting point solder is used in the previous soldering process, and low melting point solder is used in the subsequent soldering process so that the solder layer formed in the previous process does not melt in the reflow furnace.

しかしながら、上記従来のパワーモジュールのように、2つの半田層を設けると、半田材料のコストと、2回のリフロー工程を行うことによる製造コストとによって、パワーモジュールのコストが多大となる。   However, when two solder layers are provided as in the above-described conventional power module, the cost of the power module increases due to the cost of the solder material and the manufacturing cost of performing the reflow process twice.

そこで、一方の半田層に代えて、接着剤を用いることが考えられる。その場合、熱抵抗を小さく維持するためには、熱伝導率の高いフィラーを接着剤に混入する必要があるが、フィラーを高充填率で接着剤に混入すると、接着強度が低下して、剥がれなどを生じるおそれがある。   Thus, it is conceivable to use an adhesive instead of one solder layer. In that case, in order to keep the thermal resistance small, it is necessary to mix a filler with high thermal conductivity into the adhesive. However, if the filler is mixed into the adhesive at a high filling rate, the adhesive strength is lowered and peeling occurs. This may cause

本発明の目的は、フィラーを高充填率で接着剤に混入した接着剤層を備えつつ接着強度の高い絶縁性樹脂膜、およびこれを用いたパワーモジュールを提供することにある。   An object of the present invention is to provide an insulating resin film having high adhesive strength while including an adhesive layer in which a filler is mixed in an adhesive at a high filling rate, and a power module using the same.

本発明の絶縁性樹脂膜は、無機絶縁性材料からなるフィラーおよび接着剤を含む第1の接着剤層と、実質的に接着剤のみからなる第2の接着剤層とを積層したものである。
ここで、「実質的に接着剤のみによって構成されている」とは、接着剤としての機能に必要な各種添加物や粘度調整のためのフィラーは含んでいてもよいが、熱伝導率向上のためのフィラーは含まないことを意味する。
The insulating resin film of the present invention is obtained by laminating a first adhesive layer containing a filler and an adhesive made of an inorganic insulating material, and a second adhesive layer consisting essentially of an adhesive. .
Here, “substantially composed only of an adhesive” may include various additives necessary for the function as an adhesive and fillers for viscosity adjustment. Means no filler.

これにより、第1の接着剤層の表面にフィラーが露出しても、第1の接着剤層と被接着面との間に第2の接着剤層が介在するので、接着強度が維持されて、剥がれなどの発生を抑制することができる。   As a result, even if the filler is exposed on the surface of the first adhesive layer, the second adhesive layer is interposed between the first adhesive layer and the adherend surface, so that the adhesive strength is maintained. The occurrence of peeling or the like can be suppressed.

第1の接着剤層が、固体シート状に形成されていることにより、各種機器中の接着剤層を形成するために便利な接着剤シートが得られる。また、第1の接着剤層中に気泡が存在している場合には、熱抵抗の増大を招くおそれがあるが、接着剤シートの状態で気泡の有無を予め検査しておくことにより、熱抵抗の増大を招く接着剤シートの使用を回避することができる。   By forming the first adhesive layer in the form of a solid sheet, an adhesive sheet convenient for forming the adhesive layer in various devices can be obtained. In addition, when air bubbles are present in the first adhesive layer, there is a risk of increasing the thermal resistance. However, by inspecting the presence or absence of air bubbles in the state of the adhesive sheet in advance, The use of an adhesive sheet that causes an increase in resistance can be avoided.

本発明のパワーモジュールは、半導体チップ用の配線部材と支持基材との間に、本発明の絶縁性樹脂膜を介在させたものである。   The power module of the present invention is obtained by interposing the insulating resin film of the present invention between a wiring member for a semiconductor chip and a support base material.

これにより、半田層に代えて絶縁性樹脂膜を利用することで、半田層を形成する工程が低減される。したがって、製造コストの削減を図りつつ、接着剤層中のフィラーの充填率を高め、放熱性能の高いパワーモジュールを得ることができる。   Thereby, the process of forming a solder layer is reduced by using an insulating resin film instead of the solder layer. Therefore, it is possible to obtain a power module with high heat dissipation performance by increasing the filling rate of the filler in the adhesive layer while reducing the manufacturing cost.

特に、支持部材が、フィンを有するヒートシンク部材であることにより、構造が簡素化されてコストの低減を図ることができるとともに、半導体チップから熱交換媒体に至る経路の熱抵抗が小さくなるので、放熱性能がより高くなる。   In particular, since the support member is a heat sink member having fins, the structure can be simplified and the cost can be reduced, and the thermal resistance of the path from the semiconductor chip to the heat exchange medium is reduced, so that heat is dissipated. Higher performance.

本発明の絶縁性樹脂膜によると、無機絶縁性材料からなるフィラーの充填率を高めつつ、被接着面との接着強度を維持することができ、この絶縁性樹脂膜を用いたパワーモジュールにより、放熱性能の向上を図ることができる。   According to the insulating resin film of the present invention, it is possible to maintain the adhesive strength with the adherend surface while increasing the filling rate of the filler made of the inorganic insulating material, and the power module using this insulating resin film, The heat dissipation performance can be improved.

−パワーモジュールの構造−
図1は、実施の形態に係るパワーモジュールセットの構造を示す斜視図である。同図に示すように、本実施形態のパワーモジュールセットは、放熱器50の上に、複数のパワーモジュール10を取り付けて構成されている。放熱器50は、天板50aと天板50aに接合された容器50bとからなり、天板50aには、パワーモジュール10を組み込むための多数の矩形状貫通穴が設けられている。本実施形態においては、矩形状貫通穴が多数設けられているが、1つだけでもよい。放熱器50を構成する天板50aと容器50bとは、アルミニウムまたはアルミニウム合金からなり、ダイキャスト,押し出し,鍛造,鋳造,機械加工等によって組み立てることができる。
-Power module structure-
FIG. 1 is a perspective view showing a structure of a power module set according to the embodiment. As shown in the figure, the power module set of the present embodiment is configured by attaching a plurality of power modules 10 on a radiator 50. The radiator 50 includes a top plate 50a and a container 50b joined to the top plate 50a. The top plate 50a is provided with a number of rectangular through holes for incorporating the power module 10 therein. In the present embodiment, a large number of rectangular through holes are provided, but only one may be provided. The top plate 50a and the container 50b constituting the radiator 50 are made of aluminum or an aluminum alloy, and can be assembled by die casting, extrusion, forging, casting, machining, or the like.

本実施の形態では、放熱器50は天板50aと容器50bとを個別に形成してから両者を接合しているが、天板と容器とを一体に形成してもよい。その場合、たとえば一体型を用いたダイキャストにより放熱器を形成することができる。   In the present embodiment, the radiator 50 is formed by individually forming the top plate 50a and the container 50b and then joining the two. However, the top plate and the container may be integrally formed. In that case, the radiator can be formed, for example, by die casting using an integral type.

図2は、実施の形態に係るパワーモジュールセットのII-II線における断面図である。ただし、図2において配線構造の図示は省略されている。図3は、図2の一部を拡大して示す断面図である。図2および図3に示すように、本実施の形態のパワーモジュールセットにおいて、放熱器50の天板50aと容器50bとの間の空間51には、熱交換媒体としての冷却水が図2の紙面に直交する方向に流れている。パワーモジュール10は、Oリング25により気密を保持しつつボルト54により天板50aにネジ止めされている。また、パワーモジュール10は、主要部材として、IGBTなどの半導体素子が形成された半導体チップ11と、半導体チップ11内の半導体素子と外部部材とを電気的に接続するための金属配線23と、金属配線23と半導体チップ11とを接合する,Pbフリー半田を含む半田層14と、半導体チップ11で発生した熱を外方に放出するためのヒートシンク21と、金属配線23をヒートシンク21に固着する絶縁性樹脂膜26とを備えている。図3に示すように、半導体チップ11の上面および下面には、それぞれ、IGBTなどの半導体素子の活性領域に接続される上面電極12および裏面電極13が設けられている。そして、半導体チップ11の裏面電極13が、半田層14によって、金属配線23に導通状態で接合されている。   FIG. 2 is a cross-sectional view taken along line II-II of the power module set according to the embodiment. However, the illustration of the wiring structure is omitted in FIG. FIG. 3 is an enlarged cross-sectional view of a part of FIG. As shown in FIGS. 2 and 3, in the power module set of the present embodiment, cooling water as a heat exchange medium is shown in FIG. 2 in the space 51 between the top plate 50a and the container 50b of the radiator 50. It flows in the direction perpendicular to the paper surface. The power module 10 is screwed to the top plate 50 a by bolts 54 while being kept airtight by the O-ring 25. The power module 10 includes, as main members, a semiconductor chip 11 on which a semiconductor element such as an IGBT is formed, a metal wiring 23 for electrically connecting the semiconductor element in the semiconductor chip 11 and an external member, a metal A solder layer 14 containing Pb-free solder for joining the wiring 23 and the semiconductor chip 11, a heat sink 21 for releasing heat generated in the semiconductor chip 11 to the outside, and an insulation for fixing the metal wiring 23 to the heat sink 21. The resin film 26 is provided. As shown in FIG. 3, an upper surface electrode 12 and a back surface electrode 13 connected to an active region of a semiconductor element such as an IGBT are provided on the upper surface and the lower surface of the semiconductor chip 11, respectively. The back electrode 13 of the semiconductor chip 11 is joined to the metal wiring 23 in a conductive state by the solder layer 14.

ヒートシンク21は、平板部21aと、平板部21aの裏面側から突出するフィン部21bとからなり、平板部21aは、金属配線23を支持する支持部材として機能している。そして、フィン部21bは、熱交換媒体である冷却水にさらされて、熱交換効率を高めるように構成されている。ただし、フィン部21bは必ずしも必要ではなく、また、フィン部21bに代えて、他の放熱構造体を備えていてもよい。   The heat sink 21 includes a flat plate portion 21 a and fin portions 21 b protruding from the back surface side of the flat plate portion 21 a, and the flat plate portion 21 a functions as a support member that supports the metal wiring 23. And the fin part 21b is exposed to the cooling water which is a heat exchange medium, and is comprised so that heat exchange efficiency may be improved. However, the fin part 21b is not necessarily required, and may be provided with another heat dissipation structure instead of the fin part 21b.

また、放熱器50の天板50a上に、半導体チップ11等を囲むモジュール樹脂枠53が設けられていて、モジュール樹脂枠53がボルト54によって天板50aに固定されている。モジュール樹脂枠53の内部および外表面には電極端子層56が形成されている。この電極端子層56と金属配線23とは、大電流用配線18によって接続されており、電極端子層56と半導体チップ11の上面電極12の一部とは、信号配線17によって接続されている。これによって、パワーモジュール10と外部機器との電気的な接続が可能になっている。また、モジュール樹脂枠53の内方には、シリコンゲルからなるゲル層40が設けられていて、ヒートシンク21の上面側で半導体チップ11,信号配線17,大電流用配線18,金属配線23,半田層14,絶縁性樹脂膜26などの部材がゲル層40内に埋設されている。   A module resin frame 53 surrounding the semiconductor chip 11 and the like is provided on the top plate 50 a of the radiator 50, and the module resin frame 53 is fixed to the top plate 50 a by bolts 54. Electrode terminal layers 56 are formed on the inner and outer surfaces of the module resin frame 53. The electrode terminal layer 56 and the metal wiring 23 are connected by a large current wiring 18, and the electrode terminal layer 56 and a part of the upper surface electrode 12 of the semiconductor chip 11 are connected by a signal wiring 17. As a result, the power module 10 and the external device can be electrically connected. Further, a gel layer 40 made of silicon gel is provided on the inner side of the module resin frame 53, and the semiconductor chip 11, the signal wiring 17, the high current wiring 18, the metal wiring 23, the solder on the upper surface side of the heat sink 21. Members such as the layer 14 and the insulating resin film 26 are embedded in the gel layer 40.

ここで、図3の拡大部分に示すように、絶縁性樹脂膜26は、第1の接着剤層26aと、第1の接着剤層26aの上面および下面の上に形成された第2の接着剤層26bとを備えている。第1の接着剤層26aは、接着剤Eに無機絶縁性材料からなるフィラーFを混入して構成され、厚みが100〜200μmである。一方、第2の接着剤層26bは、実質的に接着剤のみによって構成され、厚みは10μm程度である。「実質的に接着剤のみによって構成されている」とは、接着剤としての機能に必要な各種添加物や粘度調整のためのフィラーは含んでいてもよいが、熱伝導率向上のためのフィラーは含まないことを意味する。   Here, as shown in the enlarged portion of FIG. 3, the insulating resin film 26 includes a first adhesive layer 26a and a second adhesive formed on the upper and lower surfaces of the first adhesive layer 26a. And an agent layer 26b. The first adhesive layer 26a is configured by mixing the filler F made of an inorganic insulating material into the adhesive E, and has a thickness of 100 to 200 μm. On the other hand, the 2nd adhesive bond layer 26b is substantially comprised only with the adhesive agent, and thickness is about 10 micrometers. “Substantially composed only of an adhesive” may contain various additives necessary for the function as an adhesive and a filler for viscosity adjustment, but a filler for improving thermal conductivity. Means not included.

第1の接着剤層26a中のフィラーFの材質は、高硬度の無機絶縁性材料であって、たとえばAlN,SiC,Al,BN,窒化珪素,ダイヤモンドなどが好ましい。高硬度の無機絶縁性材料は、熱伝導率が高いので、第1の接着剤層26aの熱抵抗、ひいては絶縁性樹脂膜26全体の熱抵抗を小さくすることができる。たとえばAlNの熱伝導率は約200(W/m・K)であり、SiCの熱伝導率は約200〜500(W/m・K)であり、Alの熱伝導率は約17(W/m・K)であり、BNの熱伝導率は約60〜200(W/m・K)であり、窒化珪素の熱伝導率は約80(W/m・K)であり、ダイヤモンドの熱伝導率は最大2000(W/m・K)である。 The material of the filler F in the first adhesive layer 26a is a high-hardness inorganic insulating material, and for example, AlN, SiC, Al 2 O 3 , BN, silicon nitride, diamond and the like are preferable. Since the high-hardness inorganic insulating material has high thermal conductivity, the thermal resistance of the first adhesive layer 26a, and hence the thermal resistance of the entire insulating resin film 26, can be reduced. For example, the thermal conductivity of AlN is about 200 (W / m · K), the thermal conductivity of SiC is about 200 to 500 (W / m · K), and the thermal conductivity of Al 2 O 3 is about 17 (W / m · K), the thermal conductivity of BN is about 60 to 200 (W / m · K), the thermal conductivity of silicon nitride is about 80 (W / m · K), diamond The maximum thermal conductivity is 2000 (W / m · K).

一方、絶縁性樹脂膜26中の接着剤Eには、エポキシ樹脂が用いられているが、エポキシ樹脂以外の熱硬化性接着剤や熱可塑性接着剤を用いることができる。   On the other hand, an epoxy resin is used for the adhesive E in the insulating resin film 26, but a thermosetting adhesive or a thermoplastic adhesive other than the epoxy resin can be used.

フィラーFを混入した第1の接着剤層26aの表面には、ところどころにフィラーFの一部が露出している。フィラーFの充填率が高い場合には、露出場所の割合も高い。したがって、第1の接着剤層26aだけを、ヒートシンク21と金属配線23との間に介在させた場合、ヒートシンク21および金属配線23との界面において、フィラーFの露出部分から剥がれが進行するおそれがある。それに対し、本実施の形態では、第1の接着剤層26aの上面および下面の上に、第2の接着剤層26bが設けられているので、絶縁性樹脂膜26と、ヒートシンク21および金属配線23との接着強度が高く維持され、剥がれなどのおそれを回避することができる。   On the surface of the first adhesive layer 26a mixed with the filler F, a part of the filler F is exposed in some places. When the filling rate of the filler F is high, the ratio of exposed locations is also high. Therefore, when only the first adhesive layer 26 a is interposed between the heat sink 21 and the metal wiring 23, there is a possibility that peeling will proceed from the exposed portion of the filler F at the interface between the heat sink 21 and the metal wiring 23. is there. In contrast, in the present embodiment, since the second adhesive layer 26b is provided on the upper and lower surfaces of the first adhesive layer 26a, the insulating resin film 26, the heat sink 21, and the metal wiring are provided. The adhesive strength with 23 is maintained high, and the possibility of peeling or the like can be avoided.

絶縁性樹脂膜26全体の厚みは、0.4mm以下であることが好ましく、0.1mm〜0.25mmであることがより好ましい。絶縁性樹脂膜26の熱抵抗は、熱伝導率と厚みに依存して定まるが、厚みが薄いほど熱抵抗が小さくなる。したがって、厚みが0.4mm以下であることにより、放熱性能が高くなることになる。   The total thickness of the insulating resin film 26 is preferably 0.4 mm or less, and more preferably 0.1 mm to 0.25 mm. The thermal resistance of the insulating resin film 26 is determined depending on the thermal conductivity and thickness, but the thermal resistance decreases as the thickness decreases. Therefore, heat dissipation performance will become high because thickness is 0.4 mm or less.

(変形例)
次に、実施の形態の変形例について説明する。本変形例においても、パワーモジュールセットの構成は、図1及び図2に示す構成と同じであって、絶縁性樹脂膜26の構造だけが異なる。図4は、変形例に係る図2の一部を拡大して示す断面図である。ここで、図4の拡大部分に示すように、絶縁性樹脂膜26は、接着剤Eに充填剤を混入して構成されている。充填剤は、大径表面コートフィラーCF1と、小径表面コートフィラーCF2とに区分けされている。同図に示すように、各表面コートフィラーCF1,CF2は、無機絶縁性材料からなるフィラーFと、フィラーFの表面を覆う樹脂皮膜Lとからなり、全体の外形が実質的に球面体である。「実質的に球面体である」とは、製造工程などにおいて生じうる,真球面からの誤差を有するものは、球面体とする意味である。なお、1つの表面コートフィラーCF1,CF2中に複数のフィラーFが含まれていてもよい。
(Modification)
Next, a modification of the embodiment will be described. Also in this modification, the configuration of the power module set is the same as the configuration shown in FIGS. 1 and 2, and only the structure of the insulating resin film 26 is different. 4 is an enlarged cross-sectional view of a part of FIG. 2 according to the modification. Here, as shown in the enlarged portion of FIG. 4, the insulating resin film 26 is configured by mixing a filler in the adhesive E. The filler is divided into a large diameter surface coat filler CF1 and a small diameter surface coat filler CF2. As shown in the figure, each of the surface coat fillers CF1 and CF2 includes a filler F made of an inorganic insulating material and a resin film L covering the surface of the filler F, and the entire outer shape is substantially a spherical body. . The phrase “substantially spherical body” means that a spherical body is an object having an error from a true spherical surface that may occur in a manufacturing process or the like. A plurality of fillers F may be contained in one surface coat filler CF1, CF2.

そして、絶縁性樹脂膜26内において、大径表面コートフィラーCF1同士の間隙に小径表面コートフィラーCF2が入り込んでいる。本実施の形態においては、大径表面コートフィラーCF1の径(最大部)は、所定範囲(30〜60μm)内にあり、小径表面コートフィラーCF2の径は、大径表面コートフィラーCF1の径の約0.2倍程度(6〜12μm)である。たとえば、大径表面コートフィラーCF1の径が40±10μmであり、小径表面コートフィラーCF2の径が、8±3μmである。また、小径表面コートフィラーCF2よりもさらに径の小さい微細表面コートフィラー(図示せず)を加えることにより、大径表面コートフィラーCF1と小径表面コートフィラーCF2との間隙に微細表面コートフィラーを入り込ませて、フィラーの充填率をさらに向上させることができる。   In the insulating resin film 26, the small-diameter surface coat filler CF2 enters the gap between the large-diameter surface coat fillers CF1. In the present embodiment, the diameter (maximum part) of the large-diameter surface coat filler CF1 is within a predetermined range (30 to 60 μm), and the small-diameter surface coat filler CF2 has a diameter equal to that of the large-diameter surface coat filler CF1. It is about 0.2 times (6 to 12 μm). For example, the large-diameter surface coat filler CF1 has a diameter of 40 ± 10 μm, and the small-diameter surface coat filler CF2 has a diameter of 8 ± 3 μm. Further, by adding a fine surface coat filler (not shown) having a diameter smaller than that of the small diameter surface coat filler CF2, the fine surface coat filler enters the gap between the large diameter surface coat filler CF1 and the small diameter surface coat filler CF2. Thus, the filler filling rate can be further improved.

以上のような整列状態は、たとえば、稠密六方構造や面心立方構造などの単結晶構造に類似した積み重ね状態である。そして、充填剤を混入した接着剤をスクリーン印刷などによって、塗布する際に圧力を印加することによって、各表面コートフィラーCF1,CF2が最小の体積を占めるように移動する結果、実現される。ただし、部分的な整列状態の乱れはあっても、全体としての充填率がそれほど低下するわけではないので、ここにいう整列状態に含まれる。   The aligned state as described above is a stacked state similar to a single crystal structure such as a dense hexagonal structure or a face-centered cubic structure. Then, by applying pressure when applying the adhesive mixed with the filler by screen printing or the like, the surface coat fillers CF1 and CF2 move so as to occupy the minimum volume, which is realized. However, even if there is a partial disturbance in the alignment state, the filling rate as a whole does not decrease so much, so it is included in this alignment state.

特に、高硬度の無機絶縁性材料は、現実的な製造コストを維持しうる加工では、表面を滑らかにして球状に近づけることが困難で、表面が細かな凹凸を有している。そのため、フィラーを高充填率(たとえば60〜70%)で混入した接着剤は、極めて高粘度状態になって、上記実施の形態に示す第1の接着剤層26aをスクリーン印刷などで塗布することが困難である。   In particular, a high-hardness inorganic insulating material has a rough surface with fine irregularities because it is difficult to make the surface smooth and close to a sphere by processing that can maintain realistic manufacturing costs. Therefore, the adhesive mixed with the filler at a high filling rate (for example, 60 to 70%) is in a very high viscosity state, and the first adhesive layer 26a shown in the above embodiment is applied by screen printing or the like. Is difficult.

それに対し、本変形例の表面コートフィラーCF1,CF2は、表面の凹凸の大きいフィラーFであっても、その表面を樹脂被膜Lで被覆して、全体の外形を実質的に球面体にしているので、表面コートフィラーCF1,CF2を混入しても、接着剤の粘度上昇を抑制することができる。その結果、本発明の表面コートフィラーCF1,CF2を混入した接着剤を、スクリーン印刷などで、塗布することが可能になる。   On the other hand, the surface coat fillers CF1 and CF2 of this modified example have a substantially spherical surface as a whole by covering the surface with the resin coating L even if the filler F has large irregularities on the surface. Therefore, even if the surface coat fillers CF1 and CF2 are mixed, an increase in the viscosity of the adhesive can be suppressed. As a result, the adhesive mixed with the surface coat fillers CF1 and CF2 of the present invention can be applied by screen printing or the like.

ただし、表面コートフィラーCF1,CF2の外形は必ずしも球状である必要はない。表面コートフィラーCF1,CF2の外形が曲面体であれば、スクリーン印刷などが可能な程度に粘度を小さく抑えることはできる。特に、表面の任意の部分が凸であれば(言い換えると、曲率半径が正の値であれば)、接着剤の中で表面コートフィラーCF1,CF2がスムーズに移動可能であるので、接着剤の粘度低減という本発明の効果を確実に発揮することができる。曲面体の例としては、球面体以外に、ラグビーボールのような2軸方向で径が異なる楕円体、3軸方向で径が異なる楕円体、多面体の表面を滑らかにしたもの、などがある。   However, the outer shape of the surface coat fillers CF1 and CF2 is not necessarily spherical. If the outer shape of the surface coat fillers CF1 and CF2 is a curved body, the viscosity can be suppressed to a level that allows screen printing and the like. In particular, if any part of the surface is convex (in other words, if the radius of curvature is a positive value), the surface coat fillers CF1 and CF2 can move smoothly in the adhesive. The effect of the present invention of reducing the viscosity can be surely exhibited. Examples of the curved body include a spherical body, an ellipsoid having a different diameter in two axes, such as a rugby ball, an ellipsoid having a diameter different in three axes, and a smooth surface of a polyhedron.

本変形例では、大径表面コートフィラーCF1の径が所定範囲に収まっているので、大径表面コートフィラーCF1が整列することで、フィラーの充填率を高めることができる。さらに、小径表面コートフィラーCF2が大径表面コートフィラーCF1の間隙に入り込む寸法に収まっていることで、より充填率を高めることができる。   In the present modification, the diameter of the large-diameter surface coat filler CF1 is within a predetermined range. Therefore, the filler filling rate can be increased by aligning the large-diameter surface coat filler CF1. Furthermore, since the small diameter surface coat filler CF2 is accommodated in the size of entering the gap between the large diameter surface coat filler CF1, the filling rate can be further increased.

ただし、表面コートフィラーCFの径がランダムに分布していても、表面コートフィラーCFの外形が任意の部分で凸状の曲面体であれば、表面コートフィラーCFが接着剤層中で自由に移動できるので、接着剤層をスクリーン印刷などによって塗布する際に、接着剤層に加わる圧力によって、各表面コートフィラーCFが最小の体積を占めるように移動する結果、一定の充填率の向上効果を発揮することができる。   However, even if the diameter of the surface coat filler CF is randomly distributed, the surface coat filler CF moves freely in the adhesive layer if the outer shape of the surface coat filler CF is a convex curved surface at an arbitrary portion. As a result, when applying the adhesive layer by screen printing, etc., the pressure applied to the adhesive layer moves so that each surface coat filler CF occupies the smallest volume, and as a result, a certain filling rate is improved. can do.

本変形例の表面コートフィラーCF1,CF2の樹脂被膜Lは、エポキシ樹脂であり、接着剤に混入される前に、エポキシ樹脂は硬化されている。ただし、エポキシ樹脂を硬化前の熱可塑性状態で接着剤に混入してもよい。また、樹脂皮膜Lの材料が、エポキシ樹脂以外の熱硬化型樹脂や熱可塑性樹脂であってもよい。   The resin coating L of the surface coat fillers CF1 and CF2 of this modification is an epoxy resin, and the epoxy resin is cured before being mixed into the adhesive. However, you may mix an epoxy resin in an adhesive agent in the thermoplastic state before hardening. The material of the resin film L may be a thermosetting resin or a thermoplastic resin other than the epoxy resin.

本変形例においても、絶縁性樹脂膜26中の接着剤Eには、エポキシ樹脂が用いられているが、エポキシ樹脂以外の熱硬化性接着剤や熱可塑性接着剤を用いることができる。   Also in this modification, an epoxy resin is used as the adhesive E in the insulating resin film 26, but a thermosetting adhesive or a thermoplastic adhesive other than the epoxy resin can be used.

−絶縁性樹脂膜の作成方法−
図5(a)〜(c)は、絶縁性樹脂膜26の形成手順の一例を示す断面図である。図5(a)に示す工程で、スクリーン印刷等により、下地部材であるヒートシンク21の上に、厚み10μm程度の第2の接着剤層26bを形成する。
-Method of making insulating resin film-
FIGS. 5A to 5C are cross-sectional views illustrating an example of a procedure for forming the insulating resin film 26. In the step shown in FIG. 5A, a second adhesive layer 26b having a thickness of about 10 μm is formed on the heat sink 21 as a base member by screen printing or the like.

次に、図5(b)に示す工程で、第2の接着剤層26bの上に、厚み100〜200μmの第1の接着剤層26aを形成する。このとき、上記実施の形態における第1の接着剤層26aの構造(図3参照)の場合は、フィラーFの充填率が高くなると、粘性の増大によってスクリーン印刷などは困難となる。したがって、たとえば、平板状の型内に接着剤EおよびフィラーFを充填して、固化させて固体シート状の第1の接着剤層26aを第2の接着剤層26bの上に貼り付ける方法を採ることができる。また、ポリテトラフルオロエチレン等のフッ素樹脂など、剥離性のよい材料からなる1対の平板間に、接着剤EおよびフィラーFを挟んで硬化させた後、平板を剥離する方法を採ることもできる。   Next, in the step shown in FIG. 5B, a first adhesive layer 26a having a thickness of 100 to 200 μm is formed on the second adhesive layer 26b. At this time, in the case of the structure of the first adhesive layer 26a in the above-described embodiment (see FIG. 3), if the filling rate of the filler F is high, screen printing or the like becomes difficult due to an increase in viscosity. Therefore, for example, a method of filling the first adhesive layer 26a in the form of a solid sheet on the second adhesive layer 26b by filling the adhesive E and the filler F into a flat plate mold and solidifying it. Can be taken. Further, a method of peeling the flat plate after the adhesive E and the filler F are sandwiched between a pair of flat plates made of a material having good peelability, such as a fluororesin such as polytetrafluoroethylene, may be employed. .

このとき、接着剤としてエポキシ樹脂を用いる場合には、貼り付け前に硬化させておいてもよいが、半硬化状態(熱可塑性)にしておいて、表面にシランカップリング剤などの界面活性剤を表面に塗布しておくことが好ましい。表面にシランカップリング剤等を塗布することにより、エポキシ樹脂の表面が粘着性をもつので、取り扱い上の利便性が高まる。   At this time, when an epoxy resin is used as an adhesive, it may be cured before being attached, but it is in a semi-cured state (thermoplastic) and has a surface active agent such as a silane coupling agent on the surface. Is preferably applied to the surface. By applying a silane coupling agent or the like to the surface, the surface of the epoxy resin is sticky, so that convenience in handling is increased.

一方、変形例における第1の接着剤層26aの構造(図4参照)の場合は、第1の接着剤層26aをスクリーン印刷で塗布することもできるし、予め、固体シート状の第1の接着剤層26a(エポキシシート)を形成しておいて、それを第2の接着剤層26bの上に貼り付けてもよい。予めエポキシシートにしておくことにより、目視によって気泡がないことを確認することができる。気泡が存在すると、絶縁性樹脂膜26の熱抵抗が増大するおそれがあるが、エポキシシートにしておくことにより、絶縁性樹脂膜26の熱抵抗が気泡によって増大するのを未然に防止することができる。第2の接着剤層26bについても、同様である。   On the other hand, in the case of the structure of the first adhesive layer 26a in the modification (see FIG. 4), the first adhesive layer 26a can be applied by screen printing, or the solid sheet-like first An adhesive layer 26a (epoxy sheet) may be formed and pasted on the second adhesive layer 26b. By using an epoxy sheet in advance, it can be confirmed visually that there are no bubbles. If bubbles exist, the thermal resistance of the insulating resin film 26 may increase. However, by using an epoxy sheet, it is possible to prevent the thermal resistance of the insulating resin film 26 from increasing due to the bubbles. it can. The same applies to the second adhesive layer 26b.

変形例の場合、表面コートフィラーCF1,CF2の作製は、フィラーFを樹脂皮膜Lの融液に浸漬した後、取り出して、相対向する平板間で転動させる、などの方法によって行うことができる。転動させる際に、エポキシ樹脂等が硬化していてもよいし、熱可塑性状態であってもよい。熱可塑性状態のものを転動させて球面体にする場合、球面体にしてから硬化させてもよいし、硬化させないままで接着剤に混入してもよい。なお、フィラーFの径を所定範囲内に収める場合には、メッシュなどで予め粒度を区分けしておく。   In the case of the modification, the surface coat fillers CF1 and CF2 can be produced by a method in which the filler F is immersed in the melt of the resin film L and then taken out and rolled between the opposing flat plates. . When rolling, the epoxy resin or the like may be cured, or may be in a thermoplastic state. In the case where a thermoplastic material is rolled into a spherical body, it may be cured after it is made into a spherical body, or may be mixed in the adhesive without being cured. In addition, when the diameter of the filler F falls within a predetermined range, the particle size is divided in advance with a mesh or the like.

図6は、絶縁性樹脂膜26の形成方法の他の例を示す断面図である。この方法では、第1の接着剤層26aを、1対の第2の接着剤層26bで挟んで固体サンドイッチ構造の絶縁性樹脂膜26を予め形成しておいて、絶縁性樹脂膜26をヒートシンク21の上に貼り付けることになる。ただし、下側の第2の接着剤層26bおよび第1の接着剤層26aを固体シート状に形成しておいて、それをヒートシンク21上に貼り付けた後、さらに上側の第2の接着剤層26bをスクリーン印刷などによって形成してもよい。また、上側の第2の接着剤層26bおよび第1の接着剤層26aを固体シート状に形成しておいて、下側の第2の接着剤層26bをスクリーン印刷などによって形成した後、固体シート状の上側の第2の接着剤層26bおよび第1の接着剤層26aを、下側の第2の接着剤層26bの上に貼り付けてもよい。   FIG. 6 is a cross-sectional view showing another example of the method for forming the insulating resin film 26. In this method, an insulating resin film 26 having a solid sandwich structure is formed in advance by sandwiching the first adhesive layer 26a between a pair of second adhesive layers 26b, and the insulating resin film 26 is then heat sinked. It will be pasted on 21. However, after the lower second adhesive layer 26b and the first adhesive layer 26a are formed in a solid sheet shape and are attached onto the heat sink 21, the second adhesive layer on the upper side is further formed. The layer 26b may be formed by screen printing or the like. In addition, the upper second adhesive layer 26b and the first adhesive layer 26a are formed in a solid sheet shape, and the lower second adhesive layer 26b is formed by screen printing or the like. The sheet-like upper second adhesive layer 26b and the first adhesive layer 26a may be attached on the lower second adhesive layer 26b.

エポキシ樹脂の場合、固体シート状のものを貼り付けるよりも、液状の接着剤をスクリーン印刷などで塗布した後、硬化させる方が接着強度が高い。したがって、絶縁性樹脂膜26によって接着される上下の部材のうち、接着強度が低い材料(たとえばCu)に対しては、第2の接着剤層26bをスクリーン印刷などで塗布した後、硬化させる方法が好ましい。   In the case of an epoxy resin, the adhesive strength is higher when a liquid adhesive is applied by screen printing or the like and then cured than when a solid sheet is attached. Therefore, among the upper and lower members bonded by the insulating resin film 26, a method of curing the material having a low adhesive strength (for example, Cu) after applying the second adhesive layer 26b by screen printing or the like. Is preferred.

−絶縁性樹脂膜以外の部材の材質−
本実施の形態および変形例では、半田層14は、Pbフリー半田を用いて形成されている。一般に、Pbフリー半田には、以下のものがある。たとえば、Sn(液相点232℃),Sn−3.5%Ag(液相点221℃),Sn−3.0%Ag(液相点222℃),Sn−3.5%Ag−0.55%Cu(液相点220℃),Sn−3.0%Ag−0.5%Cu(液相点220℃),Sn−1.5%Ag−0.85%Cu−2.0Bi(液相点223℃),Sn−2.5%Ag−0.5%Cu−1.0Bi(液相点219℃),Sn−5.8Bi(液相点138℃),Sn−0.55%Cu(液相点226℃),Sn−0.55%Cu−その他(液相点226℃),Sn−0.55%Cu−0.3%Ag(液相点226℃),Sn−5.0%Cu(液相点358℃),Sn−3.0%Cu−0.3%Ag(液相点312℃),Sn−3.5%Ag−0.5%Bi−3.0In(液相点216℃),Sn−3.5%Ag−0.5%Bi−4.0In(液相点211℃),Sn−3.5%Ag−0.5%Bi−8.0In(液相点208℃),Sn−8.0%Zn−3.0%Bi(液相点197℃)等がある。本実施の形態では、液相点が250℃以下の低融点のPbフリー半田、たとえば、Sn−3.0%Ag−0.5%Cu(液相点220℃)を用いているが、これに限定されるものではない。
-Materials of members other than insulating resin film-
In the present embodiment and modifications, the solder layer 14 is formed using Pb-free solder. In general, Pb-free solder includes the following. For example, Sn (liquid phase point 232 ° C.), Sn-3.5% Ag (liquid phase point 221 ° C.), Sn-3.0% Ag (liquid phase point 222 ° C.), Sn-3.5% Ag−0.55% Cu (liquid phase point) 220 ° C.), Sn-3.0% Ag-0.5% Cu (liquid phase point 220 ° C.), Sn-1.5% Ag-0.85% Cu-2.0 Bi (liquid phase point 223 ° C.), Sn-2.5% Ag-0.5% Cu -1.0Bi (liquid phase point 219 ° C), Sn-5.8Bi (liquid phase point 138 ° C), Sn-0.55% Cu (liquid phase point 226 ° C), Sn-0.55% Cu-others (liquid phase point 226 ° C) , Sn-0.55% Cu-0.3% Ag (liquid phase point 226 ° C), Sn-5.0% Cu (liquid phase point 358 ° C), Sn-3.0% Cu-0.3% Ag (liquid phase point 312 ° C), Sn- 3.5% Ag-0.5% Bi-3.0In (liquid phase point 216 ° C), Sn-3.5% Ag-0.5% Bi-4.0In (liquid phase point 211 ° C), Sn-3.5% Ag-0.5% Bi-8.0In (Liquid phase point 208 ° C), Sn-8.0% Zn 3.0% Bi (liquidus point 197 ° C.), and the like. In this embodiment, a low-melting point Pb-free solder having a liquidus point of 250 ° C. or lower, for example, Sn-3.0% Ag-0.5% Cu (liquidus point 220 ° C.) is used. It is not a thing.

本実施の形態では、絶縁性樹脂膜26中の、接着剤Eおよび樹脂皮膜Lとして、エポキシ樹脂を用い、Pbフリー半田の液相点よりも高いものを用いている。したがって、後述するパワーモジュールの組み立て工程において、絶縁性樹脂膜26を形成した後で、Pbフリー半田のリフロー工程を行うことが可能になる。本実施の形態によると、従来用いられていた2つの半田層に代えて、1つの半田層14と、樹脂接着剤からなる絶縁性樹脂膜26とを用いているので、工程の先後に応じて低融点のPbフリー半田と高融点のPbフリー半田とを用いる必要はなく、低融点のPbフリー半田だけで済むことになる。したがって、本実施の形態により、半田層14をPbフリー化して、接続信頼性を確保しつつ、Pbフリー化を図ることができる利点もある。   In the present embodiment, as the adhesive E and the resin film L in the insulating resin film 26, an epoxy resin is used, which is higher than the liquid phase point of Pb-free solder. Therefore, it becomes possible to perform a Pb-free solder reflow process after the insulating resin film 26 is formed in the power module assembly process described later. According to the present embodiment, instead of the conventionally used two solder layers, one solder layer 14 and the insulating resin film 26 made of a resin adhesive are used. It is not necessary to use a low melting point Pb-free solder and a high melting point Pb free solder, and only a low melting point Pb free solder is required. Therefore, according to the present embodiment, there is an advantage that the solder layer 14 can be made Pb-free and Pb-free can be achieved while ensuring connection reliability.

本実施の形態では、ヒートシンク21の材料として、焼結アルミニウム(焼結Al)を用いているが、これに限定されるものではない。たとえば、Al,Al合金,Cu,Cu合金などの他の金属、AlN,SiN,BN,SiC,WCなどのセラミックス、或いは、Al−SiC,Cu−W,Cu−Moなどの複合材料を用いてもよい。   In the present embodiment, sintered aluminum (sintered Al) is used as the material of the heat sink 21, but the material is not limited to this. For example, using other metals such as Al, Al alloy, Cu, Cu alloy, ceramics such as AlN, SiN, BN, SiC, WC, or composite materials such as Al—SiC, Cu—W, Cu—Mo. Also good.

本実施の形態では、金属配線23の材料として、CuまたはCu合金を用いているが、これに限定されるものではない。たとえば、Al,Al合金,DBA基板,DBC基板や、Al−SiC,Cu−W,Cu−Moなどの複合材料を用いてもよい。ただし、DBA基板やDBC基板を用いると、製造コストが高くつく。本発明では、DBA基板やDBC基板を用いなくても接合の信頼性を維持することができるので、金属配線23をCuやCu合金などの金属板単体構造とすることにより、製造コストの削減を図ることができる。   In the present embodiment, Cu or Cu alloy is used as the material of the metal wiring 23, but the material is not limited to this. For example, a composite material such as Al, Al alloy, DBA substrate, DBC substrate, Al—SiC, Cu—W, or Cu—Mo may be used. However, using a DBA substrate or a DBC substrate increases the manufacturing cost. In the present invention, since the reliability of bonding can be maintained without using a DBA substrate or a DBC substrate, manufacturing costs can be reduced by making the metal wiring 23 a single metal plate structure such as Cu or Cu alloy. Can be planned.

−パワーモジュールの製造工程−
次に、図7(a)〜(d),図8(a)〜(d)および図9(a)〜(c)を参照しながら、本実施の形態のパワーモジュールの製造方法について説明する。図7(a)〜(d)は、本実施の形態の製造工程における,樹脂接着剤の塗布からモジュール樹脂枠の取付までの工程を示す断面図である。図8(a)〜(d)は、本実施の形態の製造工程における,チップマウントからポッティングまでの工程を示す断面図である。図9(a)〜(c)は、本実施の形態の製造工程における,Oリングの設置からボルトの締結までの工程を示す断面図である。
-Power module manufacturing process-
Next, a method for manufacturing the power module of the present embodiment will be described with reference to FIGS. 7A to 7D, FIGS. 8A to 8D, and FIGS. 9A to 9C. . FIGS. 7A to 7D are cross-sectional views showing steps from application of the resin adhesive to attachment of the module resin frame in the manufacturing process of the present embodiment. 8A to 8D are cross-sectional views showing steps from chip mounting to potting in the manufacturing process of the present embodiment. FIGS. 9A to 9C are cross-sectional views showing steps from installation of an O-ring to fastening of a bolt in the manufacturing process of the present embodiment.

まず、図7(a)に示す工程で、焼結Alからなり、平板部21aとフィン部21bとを有するヒートシンク21を準備する。そして、ヒートシンク21の平板部21aの上面上に、上記図5(a)〜(c)または図6に示す方法で、厚みがたとえば100〜200μmの絶縁性樹脂膜26を形成する。   First, in the step shown in FIG. 7A, a heat sink 21 made of sintered Al and having a flat plate portion 21a and fin portions 21b is prepared. Then, an insulating resin film 26 having a thickness of, for example, 100 to 200 μm is formed on the upper surface of the flat plate portion 21a of the heat sink 21 by the method shown in FIGS. 5A to 5C or FIG.

次に、図7(b)に示す工程で、所定形状にパターニングされた金属配線23を絶縁性樹脂膜26の上にマウントし、図7(c)に示す工程で、絶縁性樹脂膜26により、金属配線23をヒートシンク21の平板部21の上面に固着する。   Next, in the step shown in FIG. 7B, the metal wiring 23 patterned in a predetermined shape is mounted on the insulating resin film 26, and in the step shown in FIG. The metal wiring 23 is fixed to the upper surface of the flat plate portion 21 of the heat sink 21.

次に、図7(d)に示す工程で、ヒートシンク21の平板部21aの上に、モジュール樹脂枠53を取り付ける。モジュール樹脂枠53の内部および外表面には、電極端子層56が一体成形により形成されている。そして、モジュール樹脂枠53の内側には、電極端子層56の一部が露出している。   Next, in the step shown in FIG. 7D, the module resin frame 53 is attached on the flat plate portion 21 a of the heat sink 21. Electrode terminal layers 56 are integrally formed on the inner and outer surfaces of the module resin frame 53. A part of the electrode terminal layer 56 is exposed inside the module resin frame 53.

次に、図8(a)に示す工程で、金属配線23の上に、Pbフリー半田を吐出または印刷し、Pbフリー半田の上に、半導体チップ11をマウントする。半導体チップ11には、パワーデバイスとして機能するIGBT、あるいはダイオードが形成されている。さらに、図8(b)に示す工程で、パワーモジュールをリフロー炉に投入し、半導体チップ11と金属配線23とを接合する半田層14を形成する。このときのリフロー炉の雰囲気は不活性ガス雰囲気または還元性雰囲気で、炉内の最高温度は260℃である。その後、フラックス洗浄を行なって、フラックス残渣を除去する。   Next, in a step shown in FIG. 8A, Pb-free solder is discharged or printed on the metal wiring 23, and the semiconductor chip 11 is mounted on the Pb-free solder. The semiconductor chip 11 is formed with an IGBT or a diode that functions as a power device. Further, in the step shown in FIG. 8B, the power module is put into a reflow furnace, and the solder layer 14 for joining the semiconductor chip 11 and the metal wiring 23 is formed. The atmosphere of the reflow furnace at this time is an inert gas atmosphere or a reducing atmosphere, and the maximum temperature in the furnace is 260 ° C. Thereafter, flux cleaning is performed to remove the flux residue.

次に、図8(c)に示す工程で、比較的大径(たとえば400μm径)のAlワイヤを用いたワイヤボンディングを行う。そして、半導体チップ11の上面電極12(図3参照)同士や、上面電極12と金属配線23との間、金属配線23と電極端子層56との間を接続する大電流用配線18を形成する。その後、小径(たとえば125μm径)のAlワイヤを用いたワイヤボンディングを行なって、半導体チップ11の上面電極12と電極端子層56との間を接続する信号配線17を形成する。   Next, in the step shown in FIG. 8C, wire bonding using a relatively large diameter (for example, 400 μm diameter) Al wire is performed. Then, the large current wiring 18 is formed to connect the upper surface electrodes 12 (see FIG. 3) of the semiconductor chip 11, between the upper surface electrode 12 and the metal wiring 23, and between the metal wiring 23 and the electrode terminal layer 56. . Thereafter, wire bonding using an Al wire having a small diameter (for example, 125 μm diameter) is performed to form the signal wiring 17 that connects the upper surface electrode 12 of the semiconductor chip 11 and the electrode terminal layer 56.

次に、図8(d)に示す工程で、シリコンゲルを用いたポッティングにより、モジュール樹脂枠53の内方を埋めるゲル層40を形成する。これにより、ヒートシンク21の上面に設けられている、半導体チップ11,信号配線17,大電流用配線18,金属配線23,半田層14,絶縁性樹脂膜26などの部材が、ゲル層40内に埋め込まれる。   Next, in the step shown in FIG. 8D, the gel layer 40 that fills the inside of the module resin frame 53 is formed by potting using silicon gel. Thereby, members such as the semiconductor chip 11, the signal wiring 17, the large current wiring 18, the metal wiring 23, the solder layer 14, and the insulating resin film 26 provided on the upper surface of the heat sink 21 are placed in the gel layer 40. Embedded.

次に、図9(a)に示す工程で、準備されている天板50aの矩形状貫通穴の周縁部に設けられた環状溝にOリング25を設置する。   Next, in the step shown in FIG. 9A, the O-ring 25 is installed in an annular groove provided at the peripheral edge of the rectangular through hole of the prepared top plate 50a.

次に、図9(b)に示す工程で、天板50aの矩形状貫通穴にヒートシンク21のフィン部21bを挿通させて、パワーモジュール10を放熱器50にマウントし、図9(c)に示す工程で、ボルト54により、パワーモジュール10を天板50aに固定する。同様にして、複数のパワーモジュールを、放熱器50の複数の矩形状貫通穴に、それぞれ取り付ける。   Next, in the step shown in FIG. 9 (b), the fin portion 21b of the heat sink 21 is inserted into the rectangular through hole of the top plate 50a, and the power module 10 is mounted on the radiator 50. In the illustrated process, the power module 10 is fixed to the top board 50a by the bolt 54. Similarly, the plurality of power modules are respectively attached to the plurality of rectangular through holes of the radiator 50.

上述の工程により、放熱器50の天板50aにパワーモジュール10が実装された後、天板50aが容器50bに接合される(図1および図2参照)。この接合は、機械かしめ等によって行なってもよい。これより、パワーモジュールセットが形成される。なお、先に天板50aと容器50bとを接合してから、天板50aに各パワーモジュール10を取り付けてもよい。   After the power module 10 is mounted on the top plate 50a of the radiator 50 by the above-described steps, the top plate 50a is joined to the container 50b (see FIGS. 1 and 2). This joining may be performed by mechanical caulking or the like. Thus, a power module set is formed. In addition, after joining the top plate 50a and the container 50b previously, you may attach each power module 10 to the top plate 50a.

本実施の形態のパワーモジュールの製造方法によると、先に、樹脂接着剤を用いて絶縁性樹脂膜26を形成してから、Pbフリー半田を用いて半田層14を形成しているので、下方の部材の固着から上方の部材の固着までを、順次、効率よく行うことができる。すなわち、絶縁性樹脂膜26の形成時には、金属配線23のみを把持して樹脂接着剤の上に載置すればよく、半田層14の形成時には、半導体チップ11のみを把持してPbフリー半田の上に載置すればよいので、先に半田層14を形成して半導体チップ11および金属配線23をヒートシンク21上に載置するのに比べ、組立作業のための装置が簡素化され、作業能率も高くなる。よって、製造コストの低減を図ることができる。
しかも、本発明の絶縁性樹脂膜を用いることにより、被接着部材であるヒートシンク21と金属配線23との間の熱抵抗を、第2の接着剤層26bに高充填率で混入されたフィラーによって低減しつつ、第1の接着剤層26aにより、接続の信頼性を高く維持することができる。
According to the method for manufacturing the power module of the present embodiment, the insulating resin film 26 is first formed using a resin adhesive, and then the solder layer 14 is formed using Pb-free solder. From the fixing of the member to the fixing of the upper member can be performed sequentially and efficiently. That is, when the insulating resin film 26 is formed, only the metal wiring 23 is gripped and placed on the resin adhesive, and when the solder layer 14 is formed, only the semiconductor chip 11 is gripped and Pb-free solder is formed. As compared with the case where the solder layer 14 is first formed and the semiconductor chip 11 and the metal wiring 23 are placed on the heat sink 21, the apparatus for the assembly work is simplified and the work efficiency is improved. Also gets higher. Therefore, the manufacturing cost can be reduced.
Moreover, by using the insulating resin film of the present invention, the thermal resistance between the heat sink 21 and the metal wiring 23, which are members to be bonded, is reduced by the filler mixed in the second adhesive layer 26b at a high filling rate. While being reduced, the first adhesive layer 26a can maintain high connection reliability.

(他の実施の形態)
本発明のパワーモジュールに配置される半導体素子は、ワイドバンドギャップ半導体(SiC,GaNなど)を用いたパワーデバイスでもよいし、Siを用いたパワーデバイスでもよい。
(Other embodiments)
The semiconductor element disposed in the power module of the present invention may be a power device using a wide band gap semiconductor (SiC, GaN, etc.) or a power device using Si.

上記実施の形態では、半導体チップ11に、IGBTが形成されているが、MOSFET,ダイオード,JFETなどが形成された半導体チップを用いてもよい。   In the above embodiment, the IGBT is formed on the semiconductor chip 11, but a semiconductor chip on which a MOSFET, a diode, a JFET, or the like is formed may be used.

上記実施の形態では、天板50aに多数のパワーモジュール10を取り付ける構造を採ったが、天板を兼ねる単一のヒートシンク上に多数の半導体チップを搭載してもよい。   In the above embodiment, a structure in which a large number of power modules 10 are attached to the top plate 50a is adopted. However, a large number of semiconductor chips may be mounted on a single heat sink that also serves as the top plate.

ヒートシンク21との熱交換を行う熱交換媒体は、冷却能やコストを考慮すると、フロリナートや水などの液体であることが好ましい。ただし、ヘリウム,アルゴン,窒素,空気などの気体であってもよい。   The heat exchange medium for exchanging heat with the heat sink 21 is preferably a liquid such as fluorinate or water in consideration of cooling ability and cost. However, it may be a gas such as helium, argon, nitrogen or air.

上記開示された本発明の実施の形態の構造は、あくまで例示であって、本発明の範囲はこれらの記載の範囲に限定されるものではない。本発明の範囲は、特許請求の範囲の記載によって示され、さらに特許請求の範囲の記載と均等の意味及び範囲内でのすべての変更を含むものである。   The structure of the embodiment of the present invention disclosed above is merely an example, and the scope of the present invention is not limited to the scope of these descriptions. The scope of the present invention is indicated by the description of the scope of claims, and further includes meanings equivalent to the description of the scope of claims and all modifications within the scope.

本発明のパワーモジュールは、MOSFET,IGBT,ダイオード,JFET等を搭載した各種機器に利用することができ、本発明の絶縁性樹脂膜はこのようなパワーモジュールの要素として利用することができる。   The power module of the present invention can be used for various devices equipped with MOSFETs, IGBTs, diodes, JFETs, etc., and the insulating resin film of the present invention can be used as an element of such a power module.

実施の形態に係るパワーモジュールセットの構造を示す斜視図である。It is a perspective view which shows the structure of the power module set which concerns on embodiment. 実施の形態に係るパワーモジュールセットのII-II線における断面図である。It is sectional drawing in the II-II line of the power module set which concerns on embodiment. 図2の一部を拡大して示す断面図である。It is sectional drawing which expands and shows a part of FIG. 変形例に係る図2の一部を拡大して示す断面図である。It is sectional drawing which expands and shows a part of FIG. 2 which concerns on a modification. (a)〜(c)は、絶縁性樹脂膜の形成手順の一例を示す断面図である。(A)-(c) is sectional drawing which shows an example of the formation procedure of an insulating resin film. 絶縁性樹脂膜の形成方法の他の例を示す断面図である。It is sectional drawing which shows the other example of the formation method of an insulating resin film. (a)〜(d)は、実施の形態の製造工程における,樹脂接着剤の塗布からモジュール樹脂枠の取付までの工程を示す断面図である。(A)-(d) is sectional drawing which shows the process from application | coating of a resin adhesive to attachment of a module resin frame in the manufacturing process of embodiment. (a)〜(d)は、実施の形態の製造工程における,チップマウントからポッティングまでの工程を示す断面図である。(A)-(d) is sectional drawing which shows the process from the chip mounting to potting in the manufacturing process of embodiment. (a)〜(c)は、本実施の形態の製造工程における,Oリングの設置からボルトの締結までの工程を示す断面図である。(A)-(c) is sectional drawing which shows the process from installation of an O-ring to the fastening of a volt | bolt in the manufacturing process of this Embodiment. 従来のIGBTチップを搭載したパワーモジュールの構造を示す断面図である。It is sectional drawing which shows the structure of the power module carrying the conventional IGBT chip | tip.

符号の説明Explanation of symbols

CF1 大径表面コートフィラー
CF2 小径表面コートフィラー
E 接着剤
F フィラー
L 樹脂皮膜
10 パワーモジュール
11 半導体チップ
12 上面電極
13 裏面電極
14 半田層
17 信号配線
18 大電流用配線
21 ヒートシンク
21a 平板部
21b フィン部
23 金属配線
25 Oリング
26 絶縁性樹脂膜
26a 第1の接着剤層
26b 第2の接着剤層
40 ゲル層
50 放熱器
50a 天板
50b 容器
53 モジュール樹脂枠
56 電極端子層
CF1 Large diameter surface coat filler CF2 Small diameter surface coat filler E Adhesive F Filler L Resin film 10 Power module 11 Semiconductor chip 12 Top electrode 13 Back electrode 14 Solder layer 17 Signal wiring 18 High current wiring 21 Heat sink 21a Flat plate portion 21b Fin portion 23 Metal wiring 25 O-ring 26 Insulating resin film 26a First adhesive layer 26b Second adhesive layer 40 Gel layer 50 Radiator 50a Top plate 50b Container 53 Module resin frame 56 Electrode terminal layer

Claims (5)

無機絶縁性材料からなるフィラーおよび接着剤を含む第1の接着剤層と、
前記第1の接着剤層の上面および下面のうち少なくとも一方の面上に形成され、実質的に接着剤のみからなる第2の接着剤層と、
を備えている絶縁性樹脂膜。
A first adhesive layer comprising a filler and an adhesive made of an inorganic insulating material;
A second adhesive layer that is formed on at least one of the upper surface and the lower surface of the first adhesive layer and substantially consists of an adhesive; and
Insulating resin film.
請求項1記載の絶縁性樹脂膜において、
前記第1の接着剤層は、固体シート状に形成されている、絶縁性樹脂膜。
The insulating resin film according to claim 1,
The first adhesive layer is an insulating resin film formed in a solid sheet shape.
請求項2記載の絶縁性樹脂膜において、
前記第2の接着剤層は、熱可塑性の状態で固化されて固体シート状に形成されている、絶縁性樹脂膜。
The insulating resin film according to claim 2,
The second adhesive layer is an insulating resin film that is solidified in a thermoplastic state and formed into a solid sheet.
半導体チップ内の半導体素子と外部とを電気的に接続するための配線部材と、
前記配線部材を支持する支持部材と、
前記配線部材と前記支持部材との間に介在する,請求項1〜3のうちいずれか1つに記載の絶縁性樹脂膜と、
を備えているパワーモジュール。
A wiring member for electrically connecting a semiconductor element in the semiconductor chip and the outside;
A support member for supporting the wiring member;
The insulating resin film according to any one of claims 1 to 3, interposed between the wiring member and the support member,
Power module equipped with.
請求項4記載のパワーモジュールにおいて、
前記支持部材は、フィンを有するヒートシンク部材である、パワーモジュール。
The power module according to claim 4, wherein
The power module is a power module, wherein the support member is a heat sink member having fins.
JP2007185016A 2007-07-13 2007-07-13 Insulating resin film and power module Pending JP2009021530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007185016A JP2009021530A (en) 2007-07-13 2007-07-13 Insulating resin film and power module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007185016A JP2009021530A (en) 2007-07-13 2007-07-13 Insulating resin film and power module

Publications (1)

Publication Number Publication Date
JP2009021530A true JP2009021530A (en) 2009-01-29

Family

ID=40360883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007185016A Pending JP2009021530A (en) 2007-07-13 2007-07-13 Insulating resin film and power module

Country Status (1)

Country Link
JP (1) JP2009021530A (en)

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010267663A (en) * 2009-05-12 2010-11-25 Toyota Motor Corp Method of manufacturing power module, power module manufactured by the method, and power module manufacturing device
JP2011023380A (en) * 2009-07-13 2011-02-03 Sumitomo Osaka Cement Co Ltd Heat conduction structure and method of manufacturing the same
JP2011035267A (en) * 2009-08-04 2011-02-17 Mitsubishi Electric Corp Semiconductor module
JP2011040565A (en) * 2009-08-11 2011-02-24 Fuji Electric Systems Co Ltd Thermal conductive sheet, semiconductor device using the same, and method of manufacturing the same
JP2011253891A (en) * 2010-06-01 2011-12-15 Jtekt Corp Method of manufacturing multilayer circuit board
JP2012004218A (en) * 2010-06-15 2012-01-05 Mitsubishi Electric Corp Semiconductor device
CN102349151A (en) * 2009-05-05 2012-02-08 派克汉尼芬公司 Thermally conductive foam product
WO2012046814A1 (en) 2010-10-06 2012-04-12 日立化成工業株式会社 Multilayer resin sheet and process for production thereof, resin sheet laminate and process for production thereof, cured multilayer resin sheet, metal-foil-cladded multilayer resin sheet, and semiconductor device
WO2012132691A1 (en) 2011-03-28 2012-10-04 日立化成工業株式会社 Multilayer resin sheet, resin sheet laminate, cured multilayer resin sheet and method for producing same, multilayer resin sheet with metal foil, and semiconductor device
JP2012199596A (en) * 2012-07-25 2012-10-18 Mitsubishi Electric Corp Semiconductor module
JP2013098459A (en) * 2011-11-04 2013-05-20 Toyota Motor Corp Reactor
JP2013229535A (en) * 2012-04-27 2013-11-07 Mitsubishi Electric Corp Semiconductor device
JP2013229534A (en) * 2012-04-27 2013-11-07 Mitsubishi Electric Corp Semiconductor device
JP2014504334A (en) * 2010-12-13 2014-02-20 ジーケーエヌ シンター メタルズ、エル・エル・シー Aluminum alloy powder metal with high thermal conductivity
JP2014096463A (en) * 2012-11-08 2014-05-22 Auto Network Gijutsu Kenkyusho:Kk Reactor, converter, power conversion device, and method of manufacturing reactor
JP2014512678A (en) * 2011-03-29 2014-05-22 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Electronic module and manufacturing method thereof
EP2613350A4 (en) * 2010-09-02 2016-04-13 Toyota Motor Co Ltd Semiconductor module
WO2019116910A1 (en) * 2017-12-13 2019-06-20 三菱電機株式会社 Semiconductor device and method for producing semiconductor device
WO2021230326A1 (en) * 2020-05-14 2021-11-18 昭和電工マテリアルズ株式会社 Primer, substrate equipped with primer layer, method for producing substrate equipped with primer layer, semiconductor device, and method for producing semiconductor device

Cited By (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102349151A (en) * 2009-05-05 2012-02-08 派克汉尼芬公司 Thermally conductive foam product
JP2012526397A (en) * 2009-05-05 2012-10-25 パーカー.ハニフィン.コーポレイション Thermally conductive foam product
JP2010267663A (en) * 2009-05-12 2010-11-25 Toyota Motor Corp Method of manufacturing power module, power module manufactured by the method, and power module manufacturing device
JP2011023380A (en) * 2009-07-13 2011-02-03 Sumitomo Osaka Cement Co Ltd Heat conduction structure and method of manufacturing the same
JP2011035267A (en) * 2009-08-04 2011-02-17 Mitsubishi Electric Corp Semiconductor module
JP2011040565A (en) * 2009-08-11 2011-02-24 Fuji Electric Systems Co Ltd Thermal conductive sheet, semiconductor device using the same, and method of manufacturing the same
JP2011253891A (en) * 2010-06-01 2011-12-15 Jtekt Corp Method of manufacturing multilayer circuit board
JP2012004218A (en) * 2010-06-15 2012-01-05 Mitsubishi Electric Corp Semiconductor device
US8637979B2 (en) 2010-06-15 2014-01-28 Mitsubishi Electric Corporation Semiconductor device
EP2613350A4 (en) * 2010-09-02 2016-04-13 Toyota Motor Co Ltd Semiconductor module
WO2012046814A1 (en) 2010-10-06 2012-04-12 日立化成工業株式会社 Multilayer resin sheet and process for production thereof, resin sheet laminate and process for production thereof, cured multilayer resin sheet, metal-foil-cladded multilayer resin sheet, and semiconductor device
TWI462831B (en) * 2010-10-06 2014-12-01 Hitachi Chemical Co Ltd Multilayered resin sheet and method for producing the same, resin sheet laminate and method for producing the same, harded resin sheet, multilayered resin sheet with metal foil, and semiconductor device
JP2013048257A (en) * 2010-10-06 2013-03-07 Hitachi Chemical Co Ltd Semiconductor device
US10058916B2 (en) 2010-12-13 2018-08-28 Gkn Sinter Metals, Llc Aluminum alloy powder metal with high thermal conductivity
JP2014504334A (en) * 2010-12-13 2014-02-20 ジーケーエヌ シンター メタルズ、エル・エル・シー Aluminum alloy powder metal with high thermal conductivity
KR101936449B1 (en) 2011-03-28 2019-01-08 히타치가세이가부시끼가이샤 Multilayer resin sheet, resin sheet laminate, cured multilayer resin sheet and method for producing same, multilayer resin sheet with metal foil, and semiconductor device
WO2012132691A1 (en) 2011-03-28 2012-10-04 日立化成工業株式会社 Multilayer resin sheet, resin sheet laminate, cured multilayer resin sheet and method for producing same, multilayer resin sheet with metal foil, and semiconductor device
CN103459149A (en) * 2011-03-28 2013-12-18 日立化成株式会社 Multilayer resin sheet, resin sheet laminate, cured multilayer resin sheet and method for producing same, multilayer resin sheet with metal foil, and semiconductor device
JP2019014261A (en) * 2011-03-28 2019-01-31 日立化成株式会社 Multilayer resin sheet, resin sheet laminate, cured multilayer resin sheet and method for producing same, multilayer resin sheet with metal foil, and semiconductor device
JP2013039834A (en) * 2011-03-28 2013-02-28 Hitachi Chemical Co Ltd Multilayer resin sheet, resin sheet laminate, cured multilayer resin sheet and method for manufacturing the same, multilayer resin sheet with metal foil, and semiconductor device
TWI462836B (en) * 2011-03-28 2014-12-01 Hitachi Chemical Co Ltd Multilayer resin sheet, resin sheet laminate, cured multilayer resin sheet and method of producing the same, multilayer resin sheet having metal foil, and semiconductor device
JP5141853B2 (en) * 2011-03-28 2013-02-13 日立化成工業株式会社 Multilayer resin sheet, resin sheet laminate, cured multilayer resin sheet and method for producing the same, multilayer resin sheet with metal foil, and semiconductor device
JP2017019291A (en) * 2011-03-28 2017-01-26 日立化成株式会社 Multilayer resin sheet, resin sheet laminate, multilayer resin sheet cured product and method for producing the same, multilayer resin sheet with metal foil, and semiconductor device
JP2014512678A (en) * 2011-03-29 2014-05-22 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Electronic module and manufacturing method thereof
JP2013098459A (en) * 2011-11-04 2013-05-20 Toyota Motor Corp Reactor
JP2013229535A (en) * 2012-04-27 2013-11-07 Mitsubishi Electric Corp Semiconductor device
JP2013229534A (en) * 2012-04-27 2013-11-07 Mitsubishi Electric Corp Semiconductor device
JP2012199596A (en) * 2012-07-25 2012-10-18 Mitsubishi Electric Corp Semiconductor module
JP2014096463A (en) * 2012-11-08 2014-05-22 Auto Network Gijutsu Kenkyusho:Kk Reactor, converter, power conversion device, and method of manufacturing reactor
WO2019116910A1 (en) * 2017-12-13 2019-06-20 三菱電機株式会社 Semiconductor device and method for producing semiconductor device
CN111433910A (en) * 2017-12-13 2020-07-17 三菱电机株式会社 Semiconductor device and method for manufacturing semiconductor device
JPWO2019116910A1 (en) * 2017-12-13 2020-11-26 三菱電機株式会社 Semiconductor devices and methods for manufacturing semiconductor devices
US11398447B2 (en) 2017-12-13 2022-07-26 Mitsubishi Electric Corporation Semiconductor device and method for producing semiconductor device
CN111433910B (en) * 2017-12-13 2023-10-10 三菱电机株式会社 Semiconductor device and method for manufacturing semiconductor device
WO2021230326A1 (en) * 2020-05-14 2021-11-18 昭和電工マテリアルズ株式会社 Primer, substrate equipped with primer layer, method for producing substrate equipped with primer layer, semiconductor device, and method for producing semiconductor device
KR20230011975A (en) 2020-05-14 2023-01-25 쇼와덴코머티리얼즈가부시끼가이샤 A primer, a substrate with a primer layer, a method for manufacturing a substrate with a primer layer, a semiconductor device, and a method for manufacturing a semiconductor device

Similar Documents

Publication Publication Date Title
JP2009021530A (en) Insulating resin film and power module
EP2234155B1 (en) Method of fabricating a semiconductor device
US20170092611A1 (en) Porous metallic film as die attach and interconnect
CN103035601B (en) Include the semiconductor devices of Diffusion Welding layer on sintering silver layer
US7435622B2 (en) High performance reworkable heatsink and packaging structure with solder release layer and method of making
JP6044097B2 (en) Power module substrate with heat sink, power module substrate with cooler, and power module
US20060267218A1 (en) Electronic part mounting method, semiconductor module, and semiconductor device
US20050224955A1 (en) Method and apparatus for establishing improved thermal communication between a die and a heatspreader in a semiconductor package
JP2002203932A (en) Heat radiation substrate for semiconductor power device and its conductor plate, heat sink material, and brazing material
US10403594B2 (en) Hybrid bonding materials comprising ball grid arrays and metal inverse opal bonding layers, and power electronics assemblies incorporating the same
JP2008300379A (en) Power module
JP2010098057A (en) Substrate for power module with heat sink, power module with heat sink and substrate for power module with buffer layer
JP2009019182A (en) Surface-coated filler, composite adhesive and power module
JPWO2016079881A1 (en) Semiconductor power module, method for manufacturing the same, and moving body
JP2005332874A (en) Circuit board and semiconductor device employing it
CN106132909B (en) Ceramics-the manufacturing method of aluminium conjugant, the manufacturing method of power module substrate and ceramics-aluminium conjugant, power module substrate
JP5141061B2 (en) Power module
JP2009158715A (en) Heat dissipator and power module
JP2009032996A (en) Manufacturing method of heat radiation structure
JP2008218814A (en) Power module
JP2008243878A (en) Heat dissipation structure, its manufacturing method and power module
JP6843503B2 (en) Semiconductor devices and mobiles
JP2010098058A (en) Substrate for power module with heat sink, power module with heat sink and method of manufacturing substrate for power module with heat sink
JP2008218940A (en) Power module and method of manufacturing the same
JP2014147966A (en) Joining material, joining method, joining structure, and semiconductor device

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20091222